drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/gfp.h>
  24 #include <asm/unaligned.h>
  25
  26 #include "xhci.h"
  27
  28 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  29 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  30                          PORT_RC | PORT_PLC | PORT_PE)
  31
  32 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  33 static u8 usb_bos_descriptor [] = {
  34         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  35         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  36         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  37         0x1,                            /*  __u8 bNumDeviceCaps */
  38         /* First device capability */
  39         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  40         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  41         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  42         0x00,                           /* bmAttributes, LTM off by default */
  43         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  44         0x03,                           /* bFunctionalitySupport,
  45                                            USB 3.0 speed only */
  46         0x00,                           /* bU1DevExitLat, set later. */
  47         0x00, 0x00                      /* __le16 bU2DevExitLat, set later. */
  48 };
  49
  50
  51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  52                 struct usb_hub_descriptor *desc, int ports)
  53 {
  54         u16 temp;
  55
  56         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  57         desc->bHubContrCurrent = 0;
  58
  59         desc->bNbrPorts = ports;
  60         temp = 0;
  61         /* Bits 1:0 - support per-port power switching, or power always on */
  62         if (HCC_PPC(xhci->hcc_params))
  63                 temp |= HUB_CHAR_INDV_PORT_LPSM;
  64         else
  65                 temp |= HUB_CHAR_NO_LPSM;
  66         /* Bit  2 - root hubs are not part of a compound device */
  67         /* Bits 4:3 - individual port over current protection */
  68         temp |= HUB_CHAR_INDV_PORT_OCPM;
  69         /* Bits 6:5 - no TTs in root ports */
  70         /* Bit  7 - no port indicators */
  71         desc->wHubCharacteristics = cpu_to_le16(temp);
  72 }
  73
  74 /* Fill in the USB 2.0 roothub descriptor */
  75 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  76                 struct usb_hub_descriptor *desc)
  77 {
  78         int ports;
  79         u16 temp;
  80         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  81         u32 portsc;
  82         unsigned int i;
  83
  84         ports = xhci->num_usb2_ports;
  85
  86         xhci_common_hub_descriptor(xhci, desc, ports);
  87         desc->bDescriptorType = USB_DT_HUB;
  88         temp = 1 + (ports / 8);
  89         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  90
  91         /* The Device Removable bits are reported on a byte granularity.
  92          * If the port doesn't exist within that byte, the bit is set to 0.
  93          */
  94         memset(port_removable, 0, sizeof(port_removable));
  95         for (i = 0; i < ports; i++) {
  96                 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  97                 /* If a device is removable, PORTSC reports a 0, same as in the
  98                  * hub descriptor DeviceRemovable bits.
  99                  */
 100                 if (portsc & PORT_DEV_REMOVE)
 101                         /* This math is hairy because bit 0 of DeviceRemovable
 102                          * is reserved, and bit 1 is for port 1, etc.
 103                          */
 104                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 105         }
 106
 107         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 108          * ports on it.  The USB 2.0 specification says that there are two
 109          * variable length fields at the end of the hub descriptor:
 110          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 111          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 112          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 113          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 114          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 115          * set of ports that actually exist.
 116          */
 117         memset(desc->u.hs.DeviceRemovable, 0xff,
 118                         sizeof(desc->u.hs.DeviceRemovable));
 119         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 120                         sizeof(desc->u.hs.PortPwrCtrlMask));
 121
 122         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 123                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 124                                 sizeof(__u8));
 125 }
 126
 127 /* Fill in the USB 3.0 roothub descriptor */
 128 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 129                 struct usb_hub_descriptor *desc)
 130 {
 131         int ports;
 132         u16 port_removable;
 133         u32 portsc;
 134         unsigned int i;
 135
 136         ports = xhci->num_usb3_ports;
 137         xhci_common_hub_descriptor(xhci, desc, ports);
 138         desc->bDescriptorType = USB_DT_SS_HUB;
 139         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 140
 141         /* header decode latency should be zero for roothubs,
 142          * see section 4.23.5.2.
 143          */
 144         desc->u.ss.bHubHdrDecLat = 0;
 145         desc->u.ss.wHubDelay = 0;
 146
 147         port_removable = 0;
 148         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 149         for (i = 0; i < ports; i++) {
 150                 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
 151                 if (portsc & PORT_DEV_REMOVE)
 152                         port_removable |= 1 << (i + 1);
 153         }
 154
 155         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 156 }
 157
 158 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 159                 struct usb_hub_descriptor *desc)
 160 {
 161
 162         if (hcd->speed == HCD_USB3)
 163                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 164         else
 165                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 166
 167 }
 168
 169 static unsigned int xhci_port_speed(unsigned int port_status)
 170 {
 171         if (DEV_LOWSPEED(port_status))
 172                 return USB_PORT_STAT_LOW_SPEED;
 173         if (DEV_HIGHSPEED(port_status))
 174                 return USB_PORT_STAT_HIGH_SPEED;
 175         /*
 176          * FIXME: Yes, we should check for full speed, but the core uses that as
 177          * a default in portspeed() in usb/core/hub.c (which is the only place
 178          * USB_PORT_STAT_*_SPEED is used).
 179          */
 180         return 0;
 181 }
 182
 183 /*
 184  * These bits are Read Only (RO) and should be saved and written to the
 185  * registers: 0, 3, 10:13, 30
 186  * connect status, over-current status, port speed, and device removable.
 187  * connect status and port speed are also sticky - meaning they're in
 188  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 189  */
 190 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 191 /*
 192  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 193  * bits 5:8, 9, 14:15, 25:27
 194  * link state, port power, port indicator state, "wake on" enable state
 195  */
 196 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 197 /*
 198  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 199  * bit 4 (port reset)
 200  */
 201 #define XHCI_PORT_RW1S  ((1<<4))
 202 /*
 203  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 204  * bits 1, 17, 18, 19, 20, 21, 22, 23
 205  * port enable/disable, and
 206  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 207  * over-current, reset, link state, and L1 change
 208  */
 209 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 210 /*
 211  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 212  * latched in
 213  */
 214 #define XHCI_PORT_RW    ((1<<16))
 215 /*
 216  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 217  * bits 2, 24, 28:31
 218  */
 219 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 220
 221 /*
 222  * Given a port state, this function returns a value that would result in the
 223  * port being in the same state, if the value was written to the port status
 224  * control register.
 225  * Save Read Only (RO) bits and save read/write bits where
 226  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 227  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 228  */
 229 u32 xhci_port_state_to_neutral(u32 state)
 230 {
 231         /* Save read-only status and port state */
 232         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 233 }
 234
 235 /*
 236  * find slot id based on port number.
 237  * @port: The one-based port number from one of the two split roothubs.
 238  */
 239 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 240                 u16 port)
 241 {
 242         int slot_id;
 243         int i;
 244         enum usb_device_speed speed;
 245
 246         slot_id = 0;
 247         for (i = 0; i < MAX_HC_SLOTS; i++) {
 248                 if (!xhci->devs[i])
 249                         continue;
 250                 speed = xhci->devs[i]->udev->speed;
 251                 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
 252                                 && xhci->devs[i]->fake_port == port) {
 253                         slot_id = i;
 254                         break;
 255                 }
 256         }
 257
 258         return slot_id;
 259 }
 260
 261 /*
 262  * Stop device
 263  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 264  * to complete.
 265  * suspend will set to 1, if suspend bit need to set in command.
 266  */
 267 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 268 {
 269         struct xhci_virt_device *virt_dev;
 270         struct xhci_command *cmd;
 271         unsigned long flags;
 272         int timeleft;
 273         int ret;
 274         int i;
 275
 276         ret = 0;
 277         virt_dev = xhci->devs[slot_id];
 278         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 279         if (!cmd) {
 280                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 281                 return -ENOMEM;
 282         }
 283
 284         spin_lock_irqsave(&xhci->lock, flags);
 285         for (i = LAST_EP_INDEX; i > 0; i--) {
 286                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
 287                         xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
 288         }
 289         cmd->command_trb = xhci->cmd_ring->enqueue;
 290         list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
 291         xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
 292         xhci_ring_cmd_db(xhci);
 293         spin_unlock_irqrestore(&xhci->lock, flags);
 294
 295         /* Wait for last stop endpoint command to finish */
 296         timeleft = wait_for_completion_interruptible_timeout(
 297                         cmd->completion,
 298                         USB_CTRL_SET_TIMEOUT);
 299         if (timeleft <= 0) {
 300                 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
 301                                 timeleft == 0 ? "Timeout" : "Signal");
 302                 spin_lock_irqsave(&xhci->lock, flags);
 303                 /* The timeout might have raced with the event ring handler, so
 304                  * only delete from the list if the item isn't poisoned.
 305                  */
 306                 if (cmd->cmd_list.next != LIST_POISON1)
 307                         list_del(&cmd->cmd_list);
 308                 spin_unlock_irqrestore(&xhci->lock, flags);
 309                 ret = -ETIME;
 310                 goto command_cleanup;
 311         }
 312
 313 command_cleanup:
 314         xhci_free_command(xhci, cmd);
 315         return ret;
 316 }
 317
 318 /*
 319  * Ring device, it rings the all doorbells unconditionally.
 320  */
 321 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 322 {
 323         int i;
 324
 325         for (i = 0; i < LAST_EP_INDEX + 1; i++)
 326                 if (xhci->devs[slot_id]->eps[i].ring &&
 327                     xhci->devs[slot_id]->eps[i].ring->dequeue)
 328                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 329
 330         return;
 331 }
 332
 333 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 334                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 335 {
 336         /* Don't allow the USB core to disable SuperSpeed ports. */
 337         if (hcd->speed == HCD_USB3) {
 338                 xhci_dbg(xhci, "Ignoring request to disable "
 339                                 "SuperSpeed port.\n");
 340                 return;
 341         }
 342
 343         /* Write 1 to disable the port */
 344         xhci_writel(xhci, port_status | PORT_PE, addr);
 345         port_status = xhci_readl(xhci, addr);
 346         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 347                         wIndex, port_status);
 348 }
 349
 350 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 351                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 352 {
 353         char *port_change_bit;
 354         u32 status;
 355
 356         switch (wValue) {
 357         case USB_PORT_FEAT_C_RESET:
 358                 status = PORT_RC;
 359                 port_change_bit = "reset";
 360                 break;
 361         case USB_PORT_FEAT_C_BH_PORT_RESET:
 362                 status = PORT_WRC;
 363                 port_change_bit = "warm(BH) reset";
 364                 break;
 365         case USB_PORT_FEAT_C_CONNECTION:
 366                 status = PORT_CSC;
 367                 port_change_bit = "connect";
 368                 break;
 369         case USB_PORT_FEAT_C_OVER_CURRENT:
 370                 status = PORT_OCC;
 371                 port_change_bit = "over-current";
 372                 break;
 373         case USB_PORT_FEAT_C_ENABLE:
 374                 status = PORT_PEC;
 375                 port_change_bit = "enable/disable";
 376                 break;
 377         case USB_PORT_FEAT_C_SUSPEND:
 378                 status = PORT_PLC;
 379                 port_change_bit = "suspend/resume";
 380                 break;
 381         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 382                 status = PORT_PLC;
 383                 port_change_bit = "link state";
 384                 break;
 385         default:
 386                 /* Should never happen */
 387                 return;
 388         }
 389         /* Change bits are all write 1 to clear */
 390         xhci_writel(xhci, port_status | status, addr);
 391         port_status = xhci_readl(xhci, addr);
 392         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 393                         port_change_bit, wIndex, port_status);
 394 }
 395
 396 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 397 {
 398         int max_ports;
 399         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 400
 401         if (hcd->speed == HCD_USB3) {
 402                 max_ports = xhci->num_usb3_ports;
 403                 *port_array = xhci->usb3_ports;
 404         } else {
 405                 max_ports = xhci->num_usb2_ports;
 406                 *port_array = xhci->usb2_ports;
 407         }
 408
 409         return max_ports;
 410 }
 411
 412 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 413                                 int port_id, u32 link_state)
 414 {
 415         u32 temp;
 416
 417         temp = xhci_readl(xhci, port_array[port_id]);
 418         temp = xhci_port_state_to_neutral(temp);
 419         temp &= ~PORT_PLS_MASK;
 420         temp |= PORT_LINK_STROBE | link_state;
 421         xhci_writel(xhci, temp, port_array[port_id]);
 422 }
 423
 424 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 425                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 426 {
 427         u32 temp;
 428
 429         temp = xhci_readl(xhci, port_array[port_id]);
 430         temp = xhci_port_state_to_neutral(temp);
 431
 432         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 433                 temp |= PORT_WKCONN_E;
 434         else
 435                 temp &= ~PORT_WKCONN_E;
 436
 437         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 438                 temp |= PORT_WKDISC_E;
 439         else
 440                 temp &= ~PORT_WKDISC_E;
 441
 442         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 443                 temp |= PORT_WKOC_E;
 444         else
 445                 temp &= ~PORT_WKOC_E;
 446
 447         xhci_writel(xhci, temp, port_array[port_id]);
 448 }
 449
 450 /* Test and clear port RWC bit */
 451 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 452                                 int port_id, u32 port_bit)
 453 {
 454         u32 temp;
 455
 456         temp = xhci_readl(xhci, port_array[port_id]);
 457         if (temp & port_bit) {
 458                 temp = xhci_port_state_to_neutral(temp);
 459                 temp |= port_bit;
 460                 xhci_writel(xhci, temp, port_array[port_id]);
 461         }
 462 }
 463
 464 /* Updates Link Status for super Speed port */
 465 static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
 466 {
 467         u32 pls = status_reg & PORT_PLS_MASK;
 468
 469         /* resume state is a xHCI internal state.
 470          * Do not report it to usb core.
 471          */
 472         if (pls == XDEV_RESUME)
 473                 return;
 474
 475         /* When the CAS bit is set then warm reset
 476          * should be performed on port
 477          */
 478         if (status_reg & PORT_CAS) {
 479                 /* The CAS bit can be set while the port is
 480                  * in any link state.
 481                  * Only roothubs have CAS bit, so we
 482                  * pretend to be in compliance mode
 483                  * unless we're already in compliance
 484                  * or the inactive state.
 485                  */
 486                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 487                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 488                         pls = USB_SS_PORT_LS_COMP_MOD;
 489                 }
 490                 /* Return also connection bit -
 491                  * hub state machine resets port
 492                  * when this bit is set.
 493                  */
 494                 pls |= USB_PORT_STAT_CONNECTION;
 495         } else {
 496                 /*
 497                  * If CAS bit isn't set but the Port is already at
 498                  * Compliance Mode, fake a connection so the USB core
 499                  * notices the Compliance state and resets the port.
 500                  * This resolves an issue generated by the SN65LVPE502CP
 501                  * in which sometimes the port enters compliance mode
 502                  * caused by a delay on the host-device negotiation.
 503                  */
 504                 if (pls == USB_SS_PORT_LS_COMP_MOD)
 505                         pls |= USB_PORT_STAT_CONNECTION;
 506         }
 507
 508         /* update status field */
 509         *status |= pls;
 510 }
 511
 512 /*
 513  * Function for Compliance Mode Quirk.
 514  *
 515  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 516  * the compliance mode timer is deleted. A port won't enter
 517  * compliance mode if it has previously entered U0.
 518  */
 519 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
 520 {
 521         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 522         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 523
 524         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 525                 return;
 526
 527         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 528                 xhci->port_status_u0 |= 1 << wIndex;
 529                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 530                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 531                         xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
 532                         xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
 533                 }
 534         }
 535 }
 536
 537 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 538                 u16 wIndex, char *buf, u16 wLength)
 539 {
 540         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 541         int max_ports;
 542         unsigned long flags;
 543         u32 temp, status;
 544         int retval = 0;
 545         __le32 __iomem **port_array;
 546         int slot_id;
 547         struct xhci_bus_state *bus_state;
 548         u16 link_state = 0;
 549         u16 wake_mask = 0;
 550         u16 timeout = 0;
 551
 552         max_ports = xhci_get_ports(hcd, &port_array);
 553         bus_state = &xhci->bus_state[hcd_index(hcd)];
 554
 555         spin_lock_irqsave(&xhci->lock, flags);
 556         switch (typeReq) {
 557         case GetHubStatus:
 558                 /* No power source, over-current reported per port */
 559                 memset(buf, 0, 4);
 560                 break;
 561         case GetHubDescriptor:
 562                 /* Check to make sure userspace is asking for the USB 3.0 hub
 563                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 564                  * endpoint, like external hubs do.
 565                  */
 566                 if (hcd->speed == HCD_USB3 &&
 567                                 (wLength < USB_DT_SS_HUB_SIZE ||
 568                                  wValue != (USB_DT_SS_HUB << 8))) {
 569                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 570                                         "USB 3.0 roothub.\n");
 571                         goto error;
 572                 }
 573                 xhci_hub_descriptor(hcd, xhci,
 574                                 (struct usb_hub_descriptor *) buf);
 575                 break;
 576         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 577                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 578                         goto error;
 579
 580                 if (hcd->speed != HCD_USB3)
 581                         goto error;
 582
 583                 /* Set the U1 and U2 exit latencies. */
 584                 memcpy(buf, &usb_bos_descriptor,
 585                                 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
 586                 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
 587                 buf[12] = HCS_U1_LATENCY(temp);
 588                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 589
 590                 /* Indicate whether the host has LTM support. */
 591                 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
 592                 if (HCC_LTC(temp))
 593                         buf[8] |= USB_LTM_SUPPORT;
 594
 595                 spin_unlock_irqrestore(&xhci->lock, flags);
 596                 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 597         case GetPortStatus:
 598                 if (!wIndex || wIndex > max_ports)
 599                         goto error;
 600                 wIndex--;
 601                 status = 0;
 602                 temp = xhci_readl(xhci, port_array[wIndex]);
 603                 if (temp == 0xffffffff) {
 604                         retval = -ENODEV;
 605                         break;
 606                 }
 607                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n", wIndex, temp);
 608
 609                 /* wPortChange bits */
 610                 if (temp & PORT_CSC)
 611                         status |= USB_PORT_STAT_C_CONNECTION << 16;
 612                 if (temp & PORT_PEC)
 613                         status |= USB_PORT_STAT_C_ENABLE << 16;
 614                 if ((temp & PORT_OCC))
 615                         status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 616                 if ((temp & PORT_RC))
 617                         status |= USB_PORT_STAT_C_RESET << 16;
 618                 /* USB3.0 only */
 619                 if (hcd->speed == HCD_USB3) {
 620                         if ((temp & PORT_PLC))
 621                                 status |= USB_PORT_STAT_C_LINK_STATE << 16;
 622                         if ((temp & PORT_WRC))
 623                                 status |= USB_PORT_STAT_C_BH_RESET << 16;
 624                 }
 625
 626                 if (hcd->speed != HCD_USB3) {
 627                         if ((temp & PORT_PLS_MASK) == XDEV_U3
 628                                         && (temp & PORT_POWER))
 629                                 status |= USB_PORT_STAT_SUSPEND;
 630                 }
 631                 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
 632                                 !DEV_SUPERSPEED(temp)) {
 633                         if ((temp & PORT_RESET) || !(temp & PORT_PE))
 634                                 goto error;
 635                         if (time_after_eq(jiffies,
 636                                         bus_state->resume_done[wIndex])) {
 637                                 xhci_dbg(xhci, "Resume USB2 port %d\n",
 638                                         wIndex + 1);
 639                                 bus_state->resume_done[wIndex] = 0;
 640                                 clear_bit(wIndex, &bus_state->resuming_ports);
 641                                 xhci_set_link_state(xhci, port_array, wIndex,
 642                                                         XDEV_U0);
 643                                 xhci_dbg(xhci, "set port %d resume\n",
 644                                         wIndex + 1);
 645                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 646                                                                  wIndex + 1);
 647                                 if (!slot_id) {
 648                                         xhci_dbg(xhci, "slot_id is zero\n");
 649                                         goto error;
 650                                 }
 651                                 xhci_ring_device(xhci, slot_id);
 652                                 bus_state->port_c_suspend |= 1 << wIndex;
 653                                 bus_state->suspended_ports &= ~(1 << wIndex);
 654                         } else {
 655                                 /*
 656                                  * The resume has been signaling for less than
 657                                  * 20ms. Report the port status as SUSPEND,
 658                                  * let the usbcore check port status again
 659                                  * and clear resume signaling later.
 660                                  */
 661                                 status |= USB_PORT_STAT_SUSPEND;
 662                         }
 663                 }
 664                 if ((temp & PORT_PLS_MASK) == XDEV_U0
 665                         && (temp & PORT_POWER)
 666                         && (bus_state->suspended_ports & (1 << wIndex))) {
 667                         bus_state->suspended_ports &= ~(1 << wIndex);
 668                         if (hcd->speed != HCD_USB3)
 669                                 bus_state->port_c_suspend |= 1 << wIndex;
 670                 }
 671                 if (temp & PORT_CONNECT) {
 672                         status |= USB_PORT_STAT_CONNECTION;
 673                         status |= xhci_port_speed(temp);
 674                 }
 675                 if (temp & PORT_PE)
 676                         status |= USB_PORT_STAT_ENABLE;
 677                 if (temp & PORT_OC)
 678                         status |= USB_PORT_STAT_OVERCURRENT;
 679                 if (temp & PORT_RESET)
 680                         status |= USB_PORT_STAT_RESET;
 681                 if (temp & PORT_POWER) {
 682                         if (hcd->speed == HCD_USB3)
 683                                 status |= USB_SS_PORT_STAT_POWER;
 684                         else
 685                                 status |= USB_PORT_STAT_POWER;
 686                 }
 687                 /* Update Port Link State for super speed ports*/
 688                 if (hcd->speed == HCD_USB3) {
 689                         xhci_hub_report_link_state(&status, temp);
 690                         /*
 691                          * Verify if all USB3 Ports Have entered U0 already.
 692                          * Delete Compliance Mode Timer if so.
 693                          */
 694                         xhci_del_comp_mod_timer(xhci, temp, wIndex);
 695                 }
 696                 if (bus_state->port_c_suspend & (1 << wIndex))
 697                         status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 698                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 699                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 700                 break;
 701         case SetPortFeature:
 702                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 703                         link_state = (wIndex & 0xff00) >> 3;
 704                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 705                         wake_mask = wIndex & 0xff00;
 706                 /* The MSB of wIndex is the U1/U2 timeout */
 707                 timeout = (wIndex & 0xff00) >> 8;
 708                 wIndex &= 0xff;
 709                 if (!wIndex || wIndex > max_ports)
 710                         goto error;
 711                 wIndex--;
 712                 temp = xhci_readl(xhci, port_array[wIndex]);
 713                 if (temp == 0xffffffff) {
 714                         retval = -ENODEV;
 715                         break;
 716                 }
 717                 temp = xhci_port_state_to_neutral(temp);
 718                 /* FIXME: What new port features do we need to support? */
 719                 switch (wValue) {
 720                 case USB_PORT_FEAT_SUSPEND:
 721                         temp = xhci_readl(xhci, port_array[wIndex]);
 722                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 723                                 /* Resume the port to U0 first */
 724                                 xhci_set_link_state(xhci, port_array, wIndex,
 725                                                         XDEV_U0);
 726                                 spin_unlock_irqrestore(&xhci->lock, flags);
 727                                 msleep(10);
 728                                 spin_lock_irqsave(&xhci->lock, flags);
 729                         }
 730                         /* In spec software should not attempt to suspend
 731                          * a port unless the port reports that it is in the
 732                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 733                          */
 734                         temp = xhci_readl(xhci, port_array[wIndex]);
 735                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 736                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 737                                 xhci_warn(xhci, "USB core suspending device "
 738                                           "not in U0/U1/U2.\n");
 739                                 goto error;
 740                         }
 741
 742                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 743                                         wIndex + 1);
 744                         if (!slot_id) {
 745                                 xhci_warn(xhci, "slot_id is zero\n");
 746                                 goto error;
 747                         }
 748                         /* unlock to execute stop endpoint commands */
 749                         spin_unlock_irqrestore(&xhci->lock, flags);
 750                         xhci_stop_device(xhci, slot_id, 1);
 751                         spin_lock_irqsave(&xhci->lock, flags);
 752
 753                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
 754
 755                         spin_unlock_irqrestore(&xhci->lock, flags);
 756                         msleep(10); /* wait device to enter */
 757                         spin_lock_irqsave(&xhci->lock, flags);
 758
 759                         temp = xhci_readl(xhci, port_array[wIndex]);
 760                         bus_state->suspended_ports |= 1 << wIndex;
 761                         break;
 762                 case USB_PORT_FEAT_LINK_STATE:
 763                         temp = xhci_readl(xhci, port_array[wIndex]);
 764                         /* Software should not attempt to set
 765                          * port link state above '5' (Rx.Detect) and the port
 766                          * must be enabled.
 767                          */
 768                         if ((temp & PORT_PE) == 0 ||
 769                                 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
 770                                 xhci_warn(xhci, "Cannot set link state.\n");
 771                                 goto error;
 772                         }
 773
 774                         if (link_state == USB_SS_PORT_LS_U3) {
 775                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 776                                                 wIndex + 1);
 777                                 if (slot_id) {
 778                                         /* unlock to execute stop endpoint
 779                                          * commands */
 780                                         spin_unlock_irqrestore(&xhci->lock,
 781                                                                 flags);
 782                                         xhci_stop_device(xhci, slot_id, 1);
 783                                         spin_lock_irqsave(&xhci->lock, flags);
 784                                 }
 785                         }
 786
 787                         xhci_set_link_state(xhci, port_array, wIndex,
 788                                                 link_state);
 789
 790                         spin_unlock_irqrestore(&xhci->lock, flags);
 791                         msleep(20); /* wait device to enter */
 792                         spin_lock_irqsave(&xhci->lock, flags);
 793
 794                         temp = xhci_readl(xhci, port_array[wIndex]);
 795                         if (link_state == USB_SS_PORT_LS_U3)
 796                                 bus_state->suspended_ports |= 1 << wIndex;
 797                         break;
 798                 case USB_PORT_FEAT_POWER:
 799                         /*
 800                          * Turn on ports, even if there isn't per-port switching.
 801                          * HC will report connect events even before this is set.
 802                          * However, khubd will ignore the roothub events until
 803                          * the roothub is registered.
 804                          */
 805                         xhci_writel(xhci, temp | PORT_POWER,
 806                                         port_array[wIndex]);
 807
 808                         temp = xhci_readl(xhci, port_array[wIndex]);
 809                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 810
 811                         spin_unlock_irqrestore(&xhci->lock, flags);
 812                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 813                                         wIndex);
 814                         if (temp)
 815                                 usb_acpi_set_power_state(hcd->self.root_hub,
 816                                                 wIndex, true);
 817                         spin_lock_irqsave(&xhci->lock, flags);
 818                         break;
 819                 case USB_PORT_FEAT_RESET:
 820                         temp = (temp | PORT_RESET);
 821                         xhci_writel(xhci, temp, port_array[wIndex]);
 822
 823                         temp = xhci_readl(xhci, port_array[wIndex]);
 824                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 825                         break;
 826                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
 827                         xhci_set_remote_wake_mask(xhci, port_array,
 828                                         wIndex, wake_mask);
 829                         temp = xhci_readl(xhci, port_array[wIndex]);
 830                         xhci_dbg(xhci, "set port remote wake mask, "
 831                                         "actual port %d status  = 0x%x\n",
 832                                         wIndex, temp);
 833                         break;
 834                 case USB_PORT_FEAT_BH_PORT_RESET:
 835                         temp |= PORT_WR;
 836                         xhci_writel(xhci, temp, port_array[wIndex]);
 837
 838                         temp = xhci_readl(xhci, port_array[wIndex]);
 839                         break;
 840                 case USB_PORT_FEAT_U1_TIMEOUT:
 841                         if (hcd->speed != HCD_USB3)
 842                                 goto error;
 843                         temp = xhci_readl(xhci, port_array[wIndex] + 1);
 844                         temp &= ~PORT_U1_TIMEOUT_MASK;
 845                         temp |= PORT_U1_TIMEOUT(timeout);
 846                         xhci_writel(xhci, temp, port_array[wIndex] + 1);
 847                         break;
 848                 case USB_PORT_FEAT_U2_TIMEOUT:
 849                         if (hcd->speed != HCD_USB3)
 850                                 goto error;
 851                         temp = xhci_readl(xhci, port_array[wIndex] + 1);
 852                         temp &= ~PORT_U2_TIMEOUT_MASK;
 853                         temp |= PORT_U2_TIMEOUT(timeout);
 854                         xhci_writel(xhci, temp, port_array[wIndex] + 1);
 855                         break;
 856                 default:
 857                         goto error;
 858                 }
 859                 /* unblock any posted writes */
 860                 temp = xhci_readl(xhci, port_array[wIndex]);
 861                 break;
 862         case ClearPortFeature:
 863                 if (!wIndex || wIndex > max_ports)
 864                         goto error;
 865                 wIndex--;
 866                 temp = xhci_readl(xhci, port_array[wIndex]);
 867                 if (temp == 0xffffffff) {
 868                         retval = -ENODEV;
 869                         break;
 870                 }
 871                 /* FIXME: What new port features do we need to support? */
 872                 temp = xhci_port_state_to_neutral(temp);
 873                 switch (wValue) {
 874                 case USB_PORT_FEAT_SUSPEND:
 875                         temp = xhci_readl(xhci, port_array[wIndex]);
 876                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
 877                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
 878                         if (temp & PORT_RESET)
 879                                 goto error;
 880                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
 881                                 if ((temp & PORT_PE) == 0)
 882                                         goto error;
 883
 884                                 xhci_set_link_state(xhci, port_array, wIndex,
 885                                                         XDEV_RESUME);
 886                                 spin_unlock_irqrestore(&xhci->lock, flags);
 887                                 msleep(20);
 888                                 spin_lock_irqsave(&xhci->lock, flags);
 889                                 xhci_set_link_state(xhci, port_array, wIndex,
 890                                                         XDEV_U0);
 891                         }
 892                         bus_state->port_c_suspend |= 1 << wIndex;
 893
 894                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 895                                         wIndex + 1);
 896                         if (!slot_id) {
 897                                 xhci_dbg(xhci, "slot_id is zero\n");
 898                                 goto error;
 899                         }
 900                         xhci_ring_device(xhci, slot_id);
 901                         break;
 902                 case USB_PORT_FEAT_C_SUSPEND:
 903                         bus_state->port_c_suspend &= ~(1 << wIndex);
 904                 case USB_PORT_FEAT_C_RESET:
 905                 case USB_PORT_FEAT_C_BH_PORT_RESET:
 906                 case USB_PORT_FEAT_C_CONNECTION:
 907                 case USB_PORT_FEAT_C_OVER_CURRENT:
 908                 case USB_PORT_FEAT_C_ENABLE:
 909                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
 910                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
 911                                         port_array[wIndex], temp);
 912                         break;
 913                 case USB_PORT_FEAT_ENABLE:
 914                         xhci_disable_port(hcd, xhci, wIndex,
 915                                         port_array[wIndex], temp);
 916                         break;
 917                 case USB_PORT_FEAT_POWER:
 918                         xhci_writel(xhci, temp & ~PORT_POWER,
 919                                 port_array[wIndex]);
 920
 921                         spin_unlock_irqrestore(&xhci->lock, flags);
 922                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 923                                         wIndex);
 924                         if (temp)
 925                                 usb_acpi_set_power_state(hcd->self.root_hub,
 926                                                 wIndex, false);
 927                         spin_lock_irqsave(&xhci->lock, flags);
 928                         break;
 929                 default:
 930                         goto error;
 931                 }
 932                 break;
 933         default:
 934 error:
 935                 /* "stall" on error */
 936                 retval = -EPIPE;
 937         }
 938         spin_unlock_irqrestore(&xhci->lock, flags);
 939         return retval;
 940 }
 941
 942 /*
 943  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
 944  * Ports are 0-indexed from the HCD point of view,
 945  * and 1-indexed from the USB core pointer of view.
 946  *
 947  * Note that the status change bits will be cleared as soon as a port status
 948  * change event is generated, so we use the saved status from that event.
 949  */
 950 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
 951 {
 952         unsigned long flags;
 953         u32 temp, status;
 954         u32 mask;
 955         int i, retval;
 956         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 957         int max_ports;
 958         __le32 __iomem **port_array;
 959         struct xhci_bus_state *bus_state;
 960
 961         max_ports = xhci_get_ports(hcd, &port_array);
 962         bus_state = &xhci->bus_state[hcd_index(hcd)];
 963
 964         /* Initial status is no changes */
 965         retval = (max_ports + 8) / 8;
 966         memset(buf, 0, retval);
 967
 968         /*
 969          * Inform the usbcore about resume-in-progress by returning
 970          * a non-zero value even if there are no status changes.
 971          */
 972         status = bus_state->resuming_ports;
 973
 974         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
 975
 976         spin_lock_irqsave(&xhci->lock, flags);
 977         /* For each port, did anything change?  If so, set that bit in buf. */
 978         for (i = 0; i < max_ports; i++) {
 979                 temp = xhci_readl(xhci, port_array[i]);
 980                 if (temp == 0xffffffff) {
 981                         retval = -ENODEV;
 982                         break;
 983                 }
 984                 if ((temp & mask) != 0 ||
 985                         (bus_state->port_c_suspend & 1 << i) ||
 986                         (bus_state->resume_done[i] && time_after_eq(
 987                             jiffies, bus_state->resume_done[i]))) {
 988                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
 989                         status = 1;
 990                 }
 991         }
 992         spin_unlock_irqrestore(&xhci->lock, flags);
 993         return status ? retval : 0;
 994 }
 995
 996 #ifdef CONFIG_PM
 997
 998 int xhci_bus_suspend(struct usb_hcd *hcd)
 999 {
1000         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1001         int max_ports, port_index;
1002         __le32 __iomem **port_array;
1003         struct xhci_bus_state *bus_state;
1004         unsigned long flags;
1005
1006         max_ports = xhci_get_ports(hcd, &port_array);
1007         bus_state = &xhci->bus_state[hcd_index(hcd)];
1008
1009         spin_lock_irqsave(&xhci->lock, flags);
1010
1011         if (hcd->self.root_hub->do_remote_wakeup) {
1012                 if (bus_state->resuming_ports) {
1013                         spin_unlock_irqrestore(&xhci->lock, flags);
1014                         xhci_dbg(xhci, "suspend failed because "
1015                                                 "a port is resuming\n");
1016                         return -EBUSY;
1017                 }
1018         }
1019
1020         port_index = max_ports;
1021         bus_state->bus_suspended = 0;
1022         while (port_index--) {
1023                 /* suspend the port if the port is not suspended */
1024                 u32 t1, t2;
1025                 int slot_id;
1026
1027                 t1 = xhci_readl(xhci, port_array[port_index]);
1028                 t2 = xhci_port_state_to_neutral(t1);
1029
1030                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1031                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1032                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1033                                         port_index + 1);
1034                         if (slot_id) {
1035                                 spin_unlock_irqrestore(&xhci->lock, flags);
1036                                 xhci_stop_device(xhci, slot_id, 1);
1037                                 spin_lock_irqsave(&xhci->lock, flags);
1038                         }
1039                         t2 &= ~PORT_PLS_MASK;
1040                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1041                         set_bit(port_index, &bus_state->bus_suspended);
1042                 }
1043                 /* USB core sets remote wake mask for USB 3.0 hubs,
1044                  * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
1045                  * is enabled, so also enable remote wake here.
1046                  */
1047                 if (hcd->self.root_hub->do_remote_wakeup) {
1048                         if (t1 & PORT_CONNECT) {
1049                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1050                                 t2 &= ~PORT_WKCONN_E;
1051                         } else {
1052                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1053                                 t2 &= ~PORT_WKDISC_E;
1054                         }
1055                 } else
1056                         t2 &= ~PORT_WAKE_BITS;
1057
1058                 t1 = xhci_port_state_to_neutral(t1);
1059                 if (t1 != t2)
1060                         xhci_writel(xhci, t2, port_array[port_index]);
1061
1062                 if (hcd->speed != HCD_USB3) {
1063                         /* enable remote wake up for USB 2.0 */
1064                         __le32 __iomem *addr;
1065                         u32 tmp;
1066
1067                         /* Add one to the port status register address to get
1068                          * the port power control register address.
1069                          */
1070                         addr = port_array[port_index] + 1;
1071                         tmp = xhci_readl(xhci, addr);
1072                         tmp |= PORT_RWE;
1073                         xhci_writel(xhci, tmp, addr);
1074                 }
1075         }
1076         hcd->state = HC_STATE_SUSPENDED;
1077         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1078         spin_unlock_irqrestore(&xhci->lock, flags);
1079         return 0;
1080 }
1081
1082 int xhci_bus_resume(struct usb_hcd *hcd)
1083 {
1084         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1085         int max_ports, port_index;
1086         __le32 __iomem **port_array;
1087         struct xhci_bus_state *bus_state;
1088         u32 temp;
1089         unsigned long flags;
1090
1091         max_ports = xhci_get_ports(hcd, &port_array);
1092         bus_state = &xhci->bus_state[hcd_index(hcd)];
1093
1094         if (time_before(jiffies, bus_state->next_statechange))
1095                 msleep(5);
1096
1097         spin_lock_irqsave(&xhci->lock, flags);
1098         if (!HCD_HW_ACCESSIBLE(hcd)) {
1099                 spin_unlock_irqrestore(&xhci->lock, flags);
1100                 return -ESHUTDOWN;
1101         }
1102
1103         /* delay the irqs */
1104         temp = xhci_readl(xhci, &xhci->op_regs->command);
1105         temp &= ~CMD_EIE;
1106         xhci_writel(xhci, temp, &xhci->op_regs->command);
1107
1108         port_index = max_ports;
1109         while (port_index--) {
1110                 /* Check whether need resume ports. If needed
1111                    resume port and disable remote wakeup */
1112                 u32 temp;
1113                 int slot_id;
1114
1115                 temp = xhci_readl(xhci, port_array[port_index]);
1116                 if (DEV_SUPERSPEED(temp))
1117                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1118                 else
1119                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1120                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1121                     (temp & PORT_PLS_MASK)) {
1122                         if (DEV_SUPERSPEED(temp)) {
1123                                 xhci_set_link_state(xhci, port_array,
1124                                                         port_index, XDEV_U0);
1125                         } else {
1126                                 xhci_set_link_state(xhci, port_array,
1127                                                 port_index, XDEV_RESUME);
1128
1129                                 spin_unlock_irqrestore(&xhci->lock, flags);
1130                                 msleep(20);
1131                                 spin_lock_irqsave(&xhci->lock, flags);
1132
1133                                 xhci_set_link_state(xhci, port_array,
1134                                                         port_index, XDEV_U0);
1135                         }
1136                         /* wait for the port to enter U0 and report port link
1137                          * state change.
1138                          */
1139                         spin_unlock_irqrestore(&xhci->lock, flags);
1140                         msleep(20);
1141                         spin_lock_irqsave(&xhci->lock, flags);
1142
1143                         /* Clear PLC */
1144                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1145                                                 PORT_PLC);
1146
1147                         slot_id = xhci_find_slot_id_by_port(hcd,
1148                                         xhci, port_index + 1);
1149                         if (slot_id)
1150                                 xhci_ring_device(xhci, slot_id);
1151                 } else
1152                         xhci_writel(xhci, temp, port_array[port_index]);
1153
1154                 if (hcd->speed != HCD_USB3) {
1155                         /* disable remote wake up for USB 2.0 */
1156                         __le32 __iomem *addr;
1157                         u32 tmp;
1158
1159                         /* Add one to the port status register address to get
1160                          * the port power control register address.
1161                          */
1162                         addr = port_array[port_index] + 1;
1163                         tmp = xhci_readl(xhci, addr);
1164                         tmp &= ~PORT_RWE;
1165                         xhci_writel(xhci, tmp, addr);
1166                 }
1167         }
1168
1169         (void) xhci_readl(xhci, &xhci->op_regs->command);
1170
1171         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1172         /* re-enable irqs */
1173         temp = xhci_readl(xhci, &xhci->op_regs->command);
1174         temp |= CMD_EIE;
1175         xhci_writel(xhci, temp, &xhci->op_regs->command);
1176         temp = xhci_readl(xhci, &xhci->op_regs->command);
1177
1178         spin_unlock_irqrestore(&xhci->lock, flags);
1179         return 0;
1180 }
1181
1182 #endif  /* CONFIG_PM */