drivers/usb/host/ohci-hcd.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * Open Host Controller Interface (OHCI) driver for USB.
   4  *
   5  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   6  *
   7  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   8  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   9  *
  10  * [ Initialisation is based on Linus'  ]
  11  * [ uhci code and gregs ohci fragments ]
  12  * [ (C) Copyright 1999 Linus Torvalds  ]
  13  * [ (C) Copyright 1999 Gregory P. Smith]
  14  *
  15  *
  16  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  17  * interfaces (though some non-x86 Intel chips use it).  It supports
  18  * smarter hardware than UHCI.  A download link for the spec available
  19  * through the http://www.usb.org website.
  20  *
  21  * This file is licenced under the GPL.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/pci.h>
  27 #include <linux/kernel.h>
  28 #include <linux/delay.h>
  29 #include <linux/ioport.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <linux/errno.h>
  33 #include <linux/init.h>
  34 #include <linux/timer.h>
  35 #include <linux/list.h>
  36 #include <linux/usb.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/usb/hcd.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/dmapool.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/debugfs.h>
  43 #include <linux/genalloc.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/unaligned.h>
  48 #include <asm/byteorder.h>
  49
  50
  51 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  52 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  53
  54 /*-------------------------------------------------------------------------*/
  55
  56 /* For initializing controller (mask in an HCFS mode too) */
  57 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  58 #define OHCI_INTR_INIT \
  59                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  60                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  61
  62 #ifdef __hppa__
  63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  64 #define IR_DISABLE
  65 #endif
  66
  67 #ifdef CONFIG_ARCH_OMAP
  68 /* OMAP doesn't support IR (no SMM; not needed) */
  69 #define IR_DISABLE
  70 #endif
  71
  72 /*-------------------------------------------------------------------------*/
  73
  74 static const char       hcd_name [] = "ohci_hcd";
  75
  76 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  77 #define IO_WATCHDOG_DELAY       msecs_to_jiffies(275)
  78 #define IO_WATCHDOG_OFF         0xffffff00
  79
  80 #include "ohci.h"
  81 #include "pci-quirks.h"
  82
  83 static void ohci_dump(struct ohci_hcd *ohci);
  84 static void ohci_stop(struct usb_hcd *hcd);
  85 static void io_watchdog_func(struct timer_list *t);
  86
  87 #include "ohci-hub.c"
  88 #include "ohci-dbg.c"
  89 #include "ohci-mem.c"
  90 #include "ohci-q.c"
  91
  92
  93 /*
  94  * On architectures with edge-triggered interrupts we must never return
  95  * IRQ_NONE.
  96  */
  97 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
  98 #define IRQ_NOTMINE     IRQ_HANDLED
  99 #else
 100 #define IRQ_NOTMINE     IRQ_NONE
 101 #endif
 102
 103
 104 /* Some boards misreport power switching/overcurrent */
 105 static bool distrust_firmware = true;
 106 module_param (distrust_firmware, bool, 0);
 107 MODULE_PARM_DESC (distrust_firmware,
 108         "true to distrust firmware power/overcurrent setup");
 109
 110 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 111 static bool no_handshake;
 112 module_param (no_handshake, bool, 0);
 113 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 114
 115 /*-------------------------------------------------------------------------*/
 116
 117 static int number_of_tds(struct urb *urb)
 118 {
 119         int                     len, i, num, this_sg_len;
 120         struct scatterlist      *sg;
 121
 122         len = urb->transfer_buffer_length;
 123         i = urb->num_mapped_sgs;
 124
 125         if (len > 0 && i > 0) {         /* Scatter-gather transfer */
 126                 num = 0;
 127                 sg = urb->sg;
 128                 for (;;) {
 129                         this_sg_len = min_t(int, sg_dma_len(sg), len);
 130                         num += DIV_ROUND_UP(this_sg_len, 4096);
 131                         len -= this_sg_len;
 132                         if (--i <= 0 || len <= 0)
 133                                 break;
 134                         sg = sg_next(sg);
 135                 }
 136
 137         } else {                        /* Non-SG transfer */
 138                 /* one TD for every 4096 Bytes (could be up to 8K) */
 139                 num = DIV_ROUND_UP(len, 4096);
 140         }
 141         return num;
 142 }
 143
 144 /*
 145  * queue up an urb for anything except the root hub
 146  */
 147 static int ohci_urb_enqueue (
 148         struct usb_hcd  *hcd,
 149         struct urb      *urb,
 150         gfp_t           mem_flags
 151 ) {
 152         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 153         struct ed       *ed;
 154         urb_priv_t      *urb_priv;
 155         unsigned int    pipe = urb->pipe;
 156         int             i, size = 0;
 157         unsigned long   flags;
 158         int             retval = 0;
 159
 160         /* every endpoint has a ed, locate and maybe (re)initialize it */
 161         ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
 162         if (! ed)
 163                 return -ENOMEM;
 164
 165         /* for the private part of the URB we need the number of TDs (size) */
 166         switch (ed->type) {
 167                 case PIPE_CONTROL:
 168                         /* td_submit_urb() doesn't yet handle these */
 169                         if (urb->transfer_buffer_length > 4096)
 170                                 return -EMSGSIZE;
 171
 172                         /* 1 TD for setup, 1 for ACK, plus ... */
 173                         size = 2;
 174                         /* FALLTHROUGH */
 175                 // case PIPE_INTERRUPT:
 176                 // case PIPE_BULK:
 177                 default:
 178                         size += number_of_tds(urb);
 179                         /* maybe a zero-length packet to wrap it up */
 180                         if (size == 0)
 181                                 size++;
 182                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 183                                 && (urb->transfer_buffer_length
 184                                         % usb_maxpacket (urb->dev, pipe,
 185                                                 usb_pipeout (pipe))) == 0)
 186                                 size++;
 187                         break;
 188                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 189                         size = urb->number_of_packets;
 190                         break;
 191         }
 192
 193         /* allocate the private part of the URB */
 194         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 195                         mem_flags);
 196         if (!urb_priv)
 197                 return -ENOMEM;
 198         INIT_LIST_HEAD (&urb_priv->pending);
 199         urb_priv->length = size;
 200         urb_priv->ed = ed;
 201
 202         /* allocate the TDs (deferring hash chain updates) */
 203         for (i = 0; i < size; i++) {
 204                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 205                 if (!urb_priv->td [i]) {
 206                         urb_priv->length = i;
 207                         urb_free_priv (ohci, urb_priv);
 208                         return -ENOMEM;
 209                 }
 210         }
 211
 212         spin_lock_irqsave (&ohci->lock, flags);
 213
 214         /* don't submit to a dead HC */
 215         if (!HCD_HW_ACCESSIBLE(hcd)) {
 216                 retval = -ENODEV;
 217                 goto fail;
 218         }
 219         if (ohci->rh_state != OHCI_RH_RUNNING) {
 220                 retval = -ENODEV;
 221                 goto fail;
 222         }
 223         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 224         if (retval)
 225                 goto fail;
 226
 227         /* schedule the ed if needed */
 228         if (ed->state == ED_IDLE) {
 229                 retval = ed_schedule (ohci, ed);
 230                 if (retval < 0) {
 231                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 232                         goto fail;
 233                 }
 234
 235                 /* Start up the I/O watchdog timer, if it's not running */
 236                 if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
 237                                 list_empty(&ohci->eds_in_use) &&
 238                                 !(ohci->flags & OHCI_QUIRK_QEMU)) {
 239                         ohci->prev_frame_no = ohci_frame_no(ohci);
 240                         mod_timer(&ohci->io_watchdog,
 241                                         jiffies + IO_WATCHDOG_DELAY);
 242                 }
 243                 list_add(&ed->in_use_list, &ohci->eds_in_use);
 244
 245                 if (ed->type == PIPE_ISOCHRONOUS) {
 246                         u16     frame = ohci_frame_no(ohci);
 247
 248                         /* delay a few frames before the first TD */
 249                         frame += max_t (u16, 8, ed->interval);
 250                         frame &= ~(ed->interval - 1);
 251                         frame |= ed->branch;
 252                         urb->start_frame = frame;
 253                         ed->last_iso = frame + ed->interval * (size - 1);
 254                 }
 255         } else if (ed->type == PIPE_ISOCHRONOUS) {
 256                 u16     next = ohci_frame_no(ohci) + 1;
 257                 u16     frame = ed->last_iso + ed->interval;
 258                 u16     length = ed->interval * (size - 1);
 259
 260                 /* Behind the scheduling threshold? */
 261                 if (unlikely(tick_before(frame, next))) {
 262
 263                         /* URB_ISO_ASAP: Round up to the first available slot */
 264                         if (urb->transfer_flags & URB_ISO_ASAP) {
 265                                 frame += (next - frame + ed->interval - 1) &
 266                                                 -ed->interval;
 267
 268                         /*
 269                          * Not ASAP: Use the next slot in the stream,
 270                          * no matter what.
 271                          */
 272                         } else {
 273                                 /*
 274                                  * Some OHCI hardware doesn't handle late TDs
 275                                  * correctly.  After retiring them it proceeds
 276                                  * to the next ED instead of the next TD.
 277                                  * Therefore we have to omit the late TDs
 278                                  * entirely.
 279                                  */
 280                                 urb_priv->td_cnt = DIV_ROUND_UP(
 281                                                 (u16) (next - frame),
 282                                                 ed->interval);
 283                                 if (urb_priv->td_cnt >= urb_priv->length) {
 284                                         ++urb_priv->td_cnt;     /* Mark it */
 285                                         ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
 286                                                         urb, frame, length,
 287                                                         next);
 288                                 }
 289                         }
 290                 }
 291                 urb->start_frame = frame;
 292                 ed->last_iso = frame + length;
 293         }
 294
 295         /* fill the TDs and link them to the ed; and
 296          * enable that part of the schedule, if needed
 297          * and update count of queued periodic urbs
 298          */
 299         urb->hcpriv = urb_priv;
 300         td_submit_urb (ohci, urb);
 301
 302 fail:
 303         if (retval)
 304                 urb_free_priv (ohci, urb_priv);
 305         spin_unlock_irqrestore (&ohci->lock, flags);
 306         return retval;
 307 }
 308
 309 /*
 310  * decouple the URB from the HC queues (TDs, urb_priv).
 311  * reporting is always done
 312  * asynchronously, and we might be dealing with an urb that's
 313  * partially transferred, or an ED with other urbs being unlinked.
 314  */
 315 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 316 {
 317         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 318         unsigned long           flags;
 319         int                     rc;
 320         urb_priv_t              *urb_priv;
 321
 322         spin_lock_irqsave (&ohci->lock, flags);
 323         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 324         if (rc == 0) {
 325
 326                 /* Unless an IRQ completed the unlink while it was being
 327                  * handed to us, flag it for unlink and giveback, and force
 328                  * some upcoming INTR_SF to call finish_unlinks()
 329                  */
 330                 urb_priv = urb->hcpriv;
 331                 if (urb_priv->ed->state == ED_OPER)
 332                         start_ed_unlink(ohci, urb_priv->ed);
 333
 334                 if (ohci->rh_state != OHCI_RH_RUNNING) {
 335                         /* With HC dead, we can clean up right away */
 336                         ohci_work(ohci);
 337                 }
 338         }
 339         spin_unlock_irqrestore (&ohci->lock, flags);
 340         return rc;
 341 }
 342
 343 /*-------------------------------------------------------------------------*/
 344
 345 /* frees config/altsetting state for endpoints,
 346  * including ED memory, dummy TD, and bulk/intr data toggle
 347  */
 348
 349 static void
 350 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 351 {
 352         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 353         unsigned long           flags;
 354         struct ed               *ed = ep->hcpriv;
 355         unsigned                limit = 1000;
 356
 357         /* ASSERT:  any requests/urbs are being unlinked */
 358         /* ASSERT:  nobody can be submitting urbs for this any more */
 359
 360         if (!ed)
 361                 return;
 362
 363 rescan:
 364         spin_lock_irqsave (&ohci->lock, flags);
 365
 366         if (ohci->rh_state != OHCI_RH_RUNNING) {
 367 sanitize:
 368                 ed->state = ED_IDLE;
 369                 ohci_work(ohci);
 370         }
 371
 372         switch (ed->state) {
 373         case ED_UNLINK:         /* wait for hw to finish? */
 374                 /* major IRQ delivery trouble loses INTR_SF too... */
 375                 if (limit-- == 0) {
 376                         ohci_warn(ohci, "ED unlink timeout\n");
 377                         goto sanitize;
 378                 }
 379                 spin_unlock_irqrestore (&ohci->lock, flags);
 380                 schedule_timeout_uninterruptible(1);
 381                 goto rescan;
 382         case ED_IDLE:           /* fully unlinked */
 383                 if (list_empty (&ed->td_list)) {
 384                         td_free (ohci, ed->dummy);
 385                         ed_free (ohci, ed);
 386                         break;
 387                 }
 388                 /* fall through */
 389         default:
 390                 /* caller was supposed to have unlinked any requests;
 391                  * that's not our job.  can't recover; must leak ed.
 392                  */
 393                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 394                         ed, ep->desc.bEndpointAddress, ed->state,
 395                         list_empty (&ed->td_list) ? "" : " (has tds)");
 396                 td_free (ohci, ed->dummy);
 397                 break;
 398         }
 399         ep->hcpriv = NULL;
 400         spin_unlock_irqrestore (&ohci->lock, flags);
 401 }
 402
 403 static int ohci_get_frame (struct usb_hcd *hcd)
 404 {
 405         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 406
 407         return ohci_frame_no(ohci);
 408 }
 409
 410 static void ohci_usb_reset (struct ohci_hcd *ohci)
 411 {
 412         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 413         ohci->hc_control &= OHCI_CTRL_RWC;
 414         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 415         ohci->rh_state = OHCI_RH_HALTED;
 416 }
 417
 418 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 419  * other cases where the next software may expect clean state from the
 420  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 421  */
 422 static void _ohci_shutdown(struct usb_hcd *hcd)
 423 {
 424         struct ohci_hcd *ohci;
 425
 426         ohci = hcd_to_ohci (hcd);
 427         ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
 428
 429         /* Software reset, after which the controller goes into SUSPEND */
 430         ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
 431         ohci_readl(ohci, &ohci->regs->cmdstatus);       /* flush the writes */
 432         udelay(10);
 433
 434         ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
 435         ohci->rh_state = OHCI_RH_HALTED;
 436 }
 437
 438 static void ohci_shutdown(struct usb_hcd *hcd)
 439 {
 440         struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 441         unsigned long flags;
 442
 443         spin_lock_irqsave(&ohci->lock, flags);
 444         _ohci_shutdown(hcd);
 445         spin_unlock_irqrestore(&ohci->lock, flags);
 446 }
 447
 448 /*-------------------------------------------------------------------------*
 449  * HC functions
 450  *-------------------------------------------------------------------------*/
 451
 452 /* init memory, and kick BIOS/SMM off */
 453
 454 static int ohci_init (struct ohci_hcd *ohci)
 455 {
 456         int ret;
 457         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 458
 459         /* Accept arbitrarily long scatter-gather lists */
 460         if (!hcd->localmem_pool)
 461                 hcd->self.sg_tablesize = ~0;
 462
 463         if (distrust_firmware)
 464                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 465
 466         ohci->rh_state = OHCI_RH_HALTED;
 467         ohci->regs = hcd->regs;
 468
 469         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 470          * was never needed for most non-PCI systems ... remove the code?
 471          */
 472
 473 #ifndef IR_DISABLE
 474         /* SMM owns the HC?  not for long! */
 475         if (!no_handshake && ohci_readl (ohci,
 476                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 477                 u32 temp;
 478
 479                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 480
 481                 /* this timeout is arbitrary.  we make it long, so systems
 482                  * depending on usb keyboards may be usable even if the
 483                  * BIOS/SMM code seems pretty broken.
 484                  */
 485                 temp = 500;     /* arbitrary: five seconds */
 486
 487                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 488                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 489                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 490                         msleep (10);
 491                         if (--temp == 0) {
 492                                 ohci_err (ohci, "USB HC takeover failed!"
 493                                         "  (BIOS/SMM bug)\n");
 494                                 return -EBUSY;
 495                         }
 496                 }
 497                 ohci_usb_reset (ohci);
 498         }
 499 #endif
 500
 501         /* Disable HC interrupts */
 502         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 503
 504         /* flush the writes, and save key bits like RWC */
 505         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 506                 ohci->hc_control |= OHCI_CTRL_RWC;
 507
 508         /* Read the number of ports unless overridden */
 509         if (ohci->num_ports == 0)
 510                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 511
 512         if (ohci->hcca)
 513                 return 0;
 514
 515         timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
 516         ohci->prev_frame_no = IO_WATCHDOG_OFF;
 517
 518         if (hcd->localmem_pool)
 519                 ohci->hcca = gen_pool_dma_alloc_align(hcd->localmem_pool,
 520                                                 sizeof(*ohci->hcca),
 521                                                 &ohci->hcca_dma, 256);
 522         else
 523                 ohci->hcca = dma_alloc_coherent(hcd->self.controller,
 524                                                 sizeof(*ohci->hcca),
 525                                                 &ohci->hcca_dma,
 526                                                 GFP_KERNEL);
 527         if (!ohci->hcca)
 528                 return -ENOMEM;
 529
 530         if ((ret = ohci_mem_init (ohci)) < 0)
 531                 ohci_stop (hcd);
 532         else {
 533                 create_debug_files (ohci);
 534         }
 535
 536         return ret;
 537 }
 538
 539 /*-------------------------------------------------------------------------*/
 540
 541 /* Start an OHCI controller, set the BUS operational
 542  * resets USB and controller
 543  * enable interrupts
 544  */
 545 static int ohci_run (struct ohci_hcd *ohci)
 546 {
 547         u32                     mask, val;
 548         int                     first = ohci->fminterval == 0;
 549         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 550
 551         ohci->rh_state = OHCI_RH_HALTED;
 552
 553         /* boot firmware should have set this up (5.1.1.3.1) */
 554         if (first) {
 555
 556                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 557                 ohci->fminterval = val & 0x3fff;
 558                 if (ohci->fminterval != FI)
 559                         ohci_dbg (ohci, "fminterval delta %d\n",
 560                                 ohci->fminterval - FI);
 561                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 562                 /* also: power/overcurrent flags in roothub.a */
 563         }
 564
 565         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 566          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 567          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 568          * If the bus glue detected wakeup capability then it should
 569          * already be enabled; if so we'll just enable it again.
 570          */
 571         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 572                 device_set_wakeup_capable(hcd->self.controller, 1);
 573
 574         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 575         case OHCI_USB_OPER:
 576                 val = 0;
 577                 break;
 578         case OHCI_USB_SUSPEND:
 579         case OHCI_USB_RESUME:
 580                 ohci->hc_control &= OHCI_CTRL_RWC;
 581                 ohci->hc_control |= OHCI_USB_RESUME;
 582                 val = 10 /* msec wait */;
 583                 break;
 584         // case OHCI_USB_RESET:
 585         default:
 586                 ohci->hc_control &= OHCI_CTRL_RWC;
 587                 ohci->hc_control |= OHCI_USB_RESET;
 588                 val = 50 /* msec wait */;
 589                 break;
 590         }
 591         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 592         // flush the writes
 593         (void) ohci_readl (ohci, &ohci->regs->control);
 594         msleep(val);
 595
 596         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 597
 598         /* 2msec timelimit here means no irqs/preempt */
 599         spin_lock_irq (&ohci->lock);
 600
 601 retry:
 602         /* HC Reset requires max 10 us delay */
 603         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 604         val = 30;       /* ... allow extra time */
 605         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 606                 if (--val == 0) {
 607                         spin_unlock_irq (&ohci->lock);
 608                         ohci_err (ohci, "USB HC reset timed out!\n");
 609                         return -1;
 610                 }
 611                 udelay (1);
 612         }
 613
 614         /* now we're in the SUSPEND state ... must go OPERATIONAL
 615          * within 2msec else HC enters RESUME
 616          *
 617          * ... but some hardware won't init fmInterval "by the book"
 618          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 619          * this if we write fmInterval after we're OPERATIONAL.
 620          * Unclear about ALi, ServerWorks, and others ... this could
 621          * easily be a longstanding bug in chip init on Linux.
 622          */
 623         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 624                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 625                 // flush those writes
 626                 (void) ohci_readl (ohci, &ohci->regs->control);
 627         }
 628
 629         /* Tell the controller where the control and bulk lists are
 630          * The lists are empty now. */
 631         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 632         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 633
 634         /* a reset clears this */
 635         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 636
 637         periodic_reinit (ohci);
 638
 639         /* some OHCI implementations are finicky about how they init.
 640          * bogus values here mean not even enumeration could work.
 641          */
 642         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 643                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 644                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 645                         ohci->flags |= OHCI_QUIRK_INITRESET;
 646                         ohci_dbg (ohci, "enabling initreset quirk\n");
 647                         goto retry;
 648                 }
 649                 spin_unlock_irq (&ohci->lock);
 650                 ohci_err (ohci, "init err (%08x %04x)\n",
 651                         ohci_readl (ohci, &ohci->regs->fminterval),
 652                         ohci_readl (ohci, &ohci->regs->periodicstart));
 653                 return -EOVERFLOW;
 654         }
 655
 656         /* use rhsc irqs after hub_wq is allocated */
 657         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 658         hcd->uses_new_polling = 1;
 659
 660         /* start controller operations */
 661         ohci->hc_control &= OHCI_CTRL_RWC;
 662         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 663         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 664         ohci->rh_state = OHCI_RH_RUNNING;
 665
 666         /* wake on ConnectStatusChange, matching external hubs */
 667         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 668
 669         /* Choose the interrupts we care about now, others later on demand */
 670         mask = OHCI_INTR_INIT;
 671         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 672         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 673
 674         /* handle root hub init quirks ... */
 675         val = roothub_a (ohci);
 676         val &= ~(RH_A_PSM | RH_A_OCPM);
 677         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 678                 /* NSC 87560 and maybe others */
 679                 val |= RH_A_NOCP;
 680                 val &= ~(RH_A_POTPGT | RH_A_NPS);
 681                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 682         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 683                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 684                 /* hub power always on; required for AMD-756 and some
 685                  * Mac platforms.  ganged overcurrent reporting, if any.
 686                  */
 687                 val |= RH_A_NPS;
 688                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 689         }
 690         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 691         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 692                                                 &ohci->regs->roothub.b);
 693         // flush those writes
 694         (void) ohci_readl (ohci, &ohci->regs->control);
 695
 696         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 697         spin_unlock_irq (&ohci->lock);
 698
 699         // POTPGT delay is bits 24-31, in 2 ms units.
 700         mdelay ((val >> 23) & 0x1fe);
 701
 702         ohci_dump(ohci);
 703
 704         return 0;
 705 }
 706
 707 /* ohci_setup routine for generic controller initialization */
 708
 709 int ohci_setup(struct usb_hcd *hcd)
 710 {
 711         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 712
 713         ohci_hcd_init(ohci);
 714
 715         return ohci_init(ohci);
 716 }
 717 EXPORT_SYMBOL_GPL(ohci_setup);
 718
 719 /* ohci_start routine for generic controller start of all OHCI bus glue */
 720 static int ohci_start(struct usb_hcd *hcd)
 721 {
 722         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 723         int     ret;
 724
 725         ret = ohci_run(ohci);
 726         if (ret < 0) {
 727                 ohci_err(ohci, "can't start\n");
 728                 ohci_stop(hcd);
 729         }
 730         return ret;
 731 }
 732
 733 /*-------------------------------------------------------------------------*/
 734
 735 /*
 736  * Some OHCI controllers are known to lose track of completed TDs.  They
 737  * don't add the TDs to the hardware done queue, which means we never see
 738  * them as being completed.
 739  *
 740  * This watchdog routine checks for such problems.  Without some way to
 741  * tell when those TDs have completed, we would never take their EDs off
 742  * the unlink list.  As a result, URBs could never be dequeued and
 743  * endpoints could never be released.
 744  */
 745 static void io_watchdog_func(struct timer_list *t)
 746 {
 747         struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
 748         bool            takeback_all_pending = false;
 749         u32             status;
 750         u32             head;
 751         struct ed       *ed;
 752         struct td       *td, *td_start, *td_next;
 753         unsigned        frame_no, prev_frame_no = IO_WATCHDOG_OFF;
 754         unsigned long   flags;
 755
 756         spin_lock_irqsave(&ohci->lock, flags);
 757
 758         /*
 759          * One way to lose track of completed TDs is if the controller
 760          * never writes back the done queue head.  If it hasn't been
 761          * written back since the last time this function ran and if it
 762          * was non-empty at that time, something is badly wrong with the
 763          * hardware.
 764          */
 765         status = ohci_readl(ohci, &ohci->regs->intrstatus);
 766         if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
 767                 if (ohci->prev_donehead) {
 768                         ohci_err(ohci, "HcDoneHead not written back; disabled\n");
 769  died:
 770                         usb_hc_died(ohci_to_hcd(ohci));
 771                         ohci_dump(ohci);
 772                         _ohci_shutdown(ohci_to_hcd(ohci));
 773                         goto done;
 774                 } else {
 775                         /* No write back because the done queue was empty */
 776                         takeback_all_pending = true;
 777                 }
 778         }
 779
 780         /* Check every ED which might have pending TDs */
 781         list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
 782                 if (ed->pending_td) {
 783                         if (takeback_all_pending ||
 784                                         OKAY_TO_TAKEBACK(ohci, ed)) {
 785                                 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
 786
 787                                 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
 788                                                 0x007f & tmp,
 789                                                 (0x000f & (tmp >> 7)) +
 790                                                         ((tmp & ED_IN) >> 5));
 791                                 add_to_done_list(ohci, ed->pending_td);
 792                         }
 793                 }
 794
 795                 /* Starting from the latest pending TD, */
 796                 td = ed->pending_td;
 797
 798                 /* or the last TD on the done list, */
 799                 if (!td) {
 800                         list_for_each_entry(td_next, &ed->td_list, td_list) {
 801                                 if (!td_next->next_dl_td)
 802                                         break;
 803                                 td = td_next;
 804                         }
 805                 }
 806
 807                 /* find the last TD processed by the controller. */
 808                 head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
 809                 td_start = td;
 810                 td_next = list_prepare_entry(td, &ed->td_list, td_list);
 811                 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
 812                         if (head == (u32) td_next->td_dma)
 813                                 break;
 814                         td = td_next;   /* head pointer has passed this TD */
 815                 }
 816                 if (td != td_start) {
 817                         /*
 818                          * In case a WDH cycle is in progress, we will wait
 819                          * for the next two cycles to complete before assuming
 820                          * this TD will never get on the done queue.
 821                          */
 822                         ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
 823                         ed->pending_td = td;
 824                 }
 825         }
 826
 827         ohci_work(ohci);
 828
 829         if (ohci->rh_state == OHCI_RH_RUNNING) {
 830
 831                 /*
 832                  * Sometimes a controller just stops working.  We can tell
 833                  * by checking that the frame counter has advanced since
 834                  * the last time we ran.
 835                  *
 836                  * But be careful: Some controllers violate the spec by
 837                  * stopping their frame counter when no ports are active.
 838                  */
 839                 frame_no = ohci_frame_no(ohci);
 840                 if (frame_no == ohci->prev_frame_no) {
 841                         int             active_cnt = 0;
 842                         int             i;
 843                         unsigned        tmp;
 844
 845                         for (i = 0; i < ohci->num_ports; ++i) {
 846                                 tmp = roothub_portstatus(ohci, i);
 847                                 /* Enabled and not suspended? */
 848                                 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
 849                                         ++active_cnt;
 850                         }
 851
 852                         if (active_cnt > 0) {
 853                                 ohci_err(ohci, "frame counter not updating; disabled\n");
 854                                 goto died;
 855                         }
 856                 }
 857                 if (!list_empty(&ohci->eds_in_use)) {
 858                         prev_frame_no = frame_no;
 859                         ohci->prev_wdh_cnt = ohci->wdh_cnt;
 860                         ohci->prev_donehead = ohci_readl(ohci,
 861                                         &ohci->regs->donehead);
 862                         mod_timer(&ohci->io_watchdog,
 863                                         jiffies + IO_WATCHDOG_DELAY);
 864                 }
 865         }
 866
 867  done:
 868         ohci->prev_frame_no = prev_frame_no;
 869         spin_unlock_irqrestore(&ohci->lock, flags);
 870 }
 871
 872 /* an interrupt happens */
 873
 874 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 875 {
 876         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 877         struct ohci_regs __iomem *regs = ohci->regs;
 878         int                     ints;
 879
 880         /* Read interrupt status (and flush pending writes).  We ignore the
 881          * optimization of checking the LSB of hcca->done_head; it doesn't
 882          * work on all systems (edge triggering for OHCI can be a factor).
 883          */
 884         ints = ohci_readl(ohci, &regs->intrstatus);
 885
 886         /* Check for an all 1's result which is a typical consequence
 887          * of dead, unclocked, or unplugged (CardBus...) devices
 888          */
 889         if (ints == ~(u32)0) {
 890                 ohci->rh_state = OHCI_RH_HALTED;
 891                 ohci_dbg (ohci, "device removed!\n");
 892                 usb_hc_died(hcd);
 893                 return IRQ_HANDLED;
 894         }
 895
 896         /* We only care about interrupts that are enabled */
 897         ints &= ohci_readl(ohci, &regs->intrenable);
 898
 899         /* interrupt for some other device? */
 900         if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
 901                 return IRQ_NOTMINE;
 902
 903         if (ints & OHCI_INTR_UE) {
 904                 // e.g. due to PCI Master/Target Abort
 905                 if (quirk_nec(ohci)) {
 906                         /* Workaround for a silicon bug in some NEC chips used
 907                          * in Apple's PowerBooks. Adapted from Darwin code.
 908                          */
 909                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 910
 911                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 912
 913                         schedule_work (&ohci->nec_work);
 914                 } else {
 915                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 916                         ohci->rh_state = OHCI_RH_HALTED;
 917                         usb_hc_died(hcd);
 918                 }
 919
 920                 ohci_dump(ohci);
 921                 ohci_usb_reset (ohci);
 922         }
 923
 924         if (ints & OHCI_INTR_RHSC) {
 925                 ohci_dbg(ohci, "rhsc\n");
 926                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 927                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 928                                 &regs->intrstatus);
 929
 930                 /* NOTE: Vendors didn't always make the same implementation
 931                  * choices for RHSC.  Many followed the spec; RHSC triggers
 932                  * on an edge, like setting and maybe clearing a port status
 933                  * change bit.  With others it's level-triggered, active
 934                  * until hub_wq clears all the port status change bits.  We'll
 935                  * always disable it here and rely on polling until hub_wq
 936                  * re-enables it.
 937                  */
 938                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 939                 usb_hcd_poll_rh_status(hcd);
 940         }
 941
 942         /* For connect and disconnect events, we expect the controller
 943          * to turn on RHSC along with RD.  But for remote wakeup events
 944          * this might not happen.
 945          */
 946         else if (ints & OHCI_INTR_RD) {
 947                 ohci_dbg(ohci, "resume detect\n");
 948                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 949                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 950                 if (ohci->autostop) {
 951                         spin_lock (&ohci->lock);
 952                         ohci_rh_resume (ohci);
 953                         spin_unlock (&ohci->lock);
 954                 } else
 955                         usb_hcd_resume_root_hub(hcd);
 956         }
 957
 958         spin_lock(&ohci->lock);
 959         if (ints & OHCI_INTR_WDH)
 960                 update_done_list(ohci);
 961
 962         /* could track INTR_SO to reduce available PCI/... bandwidth */
 963
 964         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 965          * when there's still unlinking to be done (next frame).
 966          */
 967         ohci_work(ohci);
 968         if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
 969                         && ohci->rh_state == OHCI_RH_RUNNING)
 970                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 971
 972         if (ohci->rh_state == OHCI_RH_RUNNING) {
 973                 ohci_writel (ohci, ints, &regs->intrstatus);
 974                 if (ints & OHCI_INTR_WDH)
 975                         ++ohci->wdh_cnt;
 976
 977                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 978                 // flush those writes
 979                 (void) ohci_readl (ohci, &ohci->regs->control);
 980         }
 981         spin_unlock(&ohci->lock);
 982
 983         return IRQ_HANDLED;
 984 }
 985
 986 /*-------------------------------------------------------------------------*/
 987
 988 static void ohci_stop (struct usb_hcd *hcd)
 989 {
 990         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 991
 992         ohci_dump(ohci);
 993
 994         if (quirk_nec(ohci))
 995                 flush_work(&ohci->nec_work);
 996         del_timer_sync(&ohci->io_watchdog);
 997         ohci->prev_frame_no = IO_WATCHDOG_OFF;
 998
 999         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1000         ohci_usb_reset(ohci);
1001         free_irq(hcd->irq, hcd);
1002         hcd->irq = 0;
1003
1004         if (quirk_amdiso(ohci))
1005                 usb_amd_dev_put();
1006
1007         remove_debug_files (ohci);
1008         ohci_mem_cleanup (ohci);
1009         if (ohci->hcca) {
1010                 if (hcd->localmem_pool)
1011                         gen_pool_free(hcd->localmem_pool,
1012                                       (unsigned long)ohci->hcca,
1013                                       sizeof(*ohci->hcca));
1014                 else
1015                         dma_free_coherent(hcd->self.controller,
1016                                           sizeof(*ohci->hcca),
1017                                           ohci->hcca, ohci->hcca_dma);
1018                 ohci->hcca = NULL;
1019                 ohci->hcca_dma = 0;
1020         }
1021 }
1022
1023 /*-------------------------------------------------------------------------*/
1024
1025 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1026
1027 /* must not be called from interrupt context */
1028 int ohci_restart(struct ohci_hcd *ohci)
1029 {
1030         int temp;
1031         int i;
1032         struct urb_priv *priv;
1033
1034         ohci_init(ohci);
1035         spin_lock_irq(&ohci->lock);
1036         ohci->rh_state = OHCI_RH_HALTED;
1037
1038         /* Recycle any "live" eds/tds (and urbs). */
1039         if (!list_empty (&ohci->pending))
1040                 ohci_dbg(ohci, "abort schedule...\n");
1041         list_for_each_entry (priv, &ohci->pending, pending) {
1042                 struct urb      *urb = priv->td[0]->urb;
1043                 struct ed       *ed = priv->ed;
1044
1045                 switch (ed->state) {
1046                 case ED_OPER:
1047                         ed->state = ED_UNLINK;
1048                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1049                         ed_deschedule (ohci, ed);
1050
1051                         ed->ed_next = ohci->ed_rm_list;
1052                         ed->ed_prev = NULL;
1053                         ohci->ed_rm_list = ed;
1054                         /* FALLTHROUGH */
1055                 case ED_UNLINK:
1056                         break;
1057                 default:
1058                         ohci_dbg(ohci, "bogus ed %p state %d\n",
1059                                         ed, ed->state);
1060                 }
1061
1062                 if (!urb->unlinked)
1063                         urb->unlinked = -ESHUTDOWN;
1064         }
1065         ohci_work(ohci);
1066         spin_unlock_irq(&ohci->lock);
1067
1068         /* paranoia, in case that didn't work: */
1069
1070         /* empty the interrupt branches */
1071         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1072         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1073
1074         /* no EDs to remove */
1075         ohci->ed_rm_list = NULL;
1076
1077         /* empty control and bulk lists */
1078         ohci->ed_controltail = NULL;
1079         ohci->ed_bulktail    = NULL;
1080
1081         if ((temp = ohci_run (ohci)) < 0) {
1082                 ohci_err (ohci, "can't restart, %d\n", temp);
1083                 return temp;
1084         }
1085         ohci_dbg(ohci, "restart complete\n");
1086         return 0;
1087 }
1088 EXPORT_SYMBOL_GPL(ohci_restart);
1089
1090 #endif
1091
1092 #ifdef CONFIG_PM
1093
1094 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1095 {
1096         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1097         unsigned long   flags;
1098         int             rc = 0;
1099
1100         /* Disable irq emission and mark HW unaccessible. Use
1101          * the spinlock to properly synchronize with possible pending
1102          * RH suspend or resume activity.
1103          */
1104         spin_lock_irqsave (&ohci->lock, flags);
1105         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1106         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1107
1108         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1109         spin_unlock_irqrestore (&ohci->lock, flags);
1110
1111         synchronize_irq(hcd->irq);
1112
1113         if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1114                 ohci_resume(hcd, false);
1115                 rc = -EBUSY;
1116         }
1117         return rc;
1118 }
1119 EXPORT_SYMBOL_GPL(ohci_suspend);
1120
1121
1122 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1123 {
1124         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
1125         int                     port;
1126         bool                    need_reinit = false;
1127
1128         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1129
1130         /* Make sure resume from hibernation re-enumerates everything */
1131         if (hibernated)
1132                 ohci_usb_reset(ohci);
1133
1134         /* See if the controller is already running or has been reset */
1135         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1136         if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1137                 need_reinit = true;
1138         } else {
1139                 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1140                 case OHCI_USB_OPER:
1141                 case OHCI_USB_RESET:
1142                         need_reinit = true;
1143                 }
1144         }
1145
1146         /* If needed, reinitialize and suspend the root hub */
1147         if (need_reinit) {
1148                 spin_lock_irq(&ohci->lock);
1149                 ohci_rh_resume(ohci);
1150                 ohci_rh_suspend(ohci, 0);
1151                 spin_unlock_irq(&ohci->lock);
1152         }
1153
1154         /* Normally just turn on port power and enable interrupts */
1155         else {
1156                 ohci_dbg(ohci, "powerup ports\n");
1157                 for (port = 0; port < ohci->num_ports; port++)
1158                         ohci_writel(ohci, RH_PS_PPS,
1159                                         &ohci->regs->roothub.portstatus[port]);
1160
1161                 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1162                 ohci_readl(ohci, &ohci->regs->intrenable);
1163                 msleep(20);
1164         }
1165
1166         usb_hcd_resume_root_hub(hcd);
1167
1168         return 0;
1169 }
1170 EXPORT_SYMBOL_GPL(ohci_resume);
1171
1172 #endif
1173
1174 /*-------------------------------------------------------------------------*/
1175
1176 /*
1177  * Generic structure: This gets copied for platform drivers so that
1178  * individual entries can be overridden as needed.
1179  */
1180
1181 static const struct hc_driver ohci_hc_driver = {
1182         .description =          hcd_name,
1183         .product_desc =         "OHCI Host Controller",
1184         .hcd_priv_size =        sizeof(struct ohci_hcd),
1185
1186         /*
1187          * generic hardware linkage
1188         */
1189         .irq =                  ohci_irq,
1190         .flags =                HCD_MEMORY | HCD_USB11,
1191
1192         /*
1193         * basic lifecycle operations
1194         */
1195         .reset =                ohci_setup,
1196         .start =                ohci_start,
1197         .stop =                 ohci_stop,
1198         .shutdown =             ohci_shutdown,
1199
1200         /*
1201          * managing i/o requests and associated device resources
1202         */
1203         .urb_enqueue =          ohci_urb_enqueue,
1204         .urb_dequeue =          ohci_urb_dequeue,
1205         .endpoint_disable =     ohci_endpoint_disable,
1206
1207         /*
1208         * scheduling support
1209         */
1210         .get_frame_number =     ohci_get_frame,
1211
1212         /*
1213         * root hub support
1214         */
1215         .hub_status_data =      ohci_hub_status_data,
1216         .hub_control =          ohci_hub_control,
1217 #ifdef CONFIG_PM
1218         .bus_suspend =          ohci_bus_suspend,
1219         .bus_resume =           ohci_bus_resume,
1220 #endif
1221         .start_port_reset =     ohci_start_port_reset,
1222 };
1223
1224 void ohci_init_driver(struct hc_driver *drv,
1225                 const struct ohci_driver_overrides *over)
1226 {
1227         /* Copy the generic table to drv and then apply the overrides */
1228         *drv = ohci_hc_driver;
1229
1230         if (over) {
1231                 drv->product_desc = over->product_desc;
1232                 drv->hcd_priv_size += over->extra_priv_size;
1233                 if (over->reset)
1234                         drv->reset = over->reset;
1235         }
1236 }
1237 EXPORT_SYMBOL_GPL(ohci_init_driver);
1238
1239 /*-------------------------------------------------------------------------*/
1240
1241 MODULE_AUTHOR (DRIVER_AUTHOR);
1242 MODULE_DESCRIPTION(DRIVER_DESC);
1243 MODULE_LICENSE ("GPL");
1244
1245 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1246 #include "ohci-sa1111.c"
1247 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1248 #endif
1249
1250 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1251 #include "ohci-ppc-of.c"
1252 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1253 #endif
1254
1255 #ifdef CONFIG_PPC_PS3
1256 #include "ohci-ps3.c"
1257 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1258 #endif
1259
1260 #ifdef CONFIG_MFD_SM501
1261 #include "ohci-sm501.c"
1262 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1263 #endif
1264
1265 #ifdef CONFIG_MFD_TC6393XB
1266 #include "ohci-tmio.c"
1267 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1268 #endif
1269
1270 static int __init ohci_hcd_mod_init(void)
1271 {
1272         int retval = 0;
1273
1274         if (usb_disabled())
1275                 return -ENODEV;
1276
1277         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1278         pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1279                 sizeof (struct ed), sizeof (struct td));
1280         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1281
1282         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1283
1284 #ifdef PS3_SYSTEM_BUS_DRIVER
1285         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1286         if (retval < 0)
1287                 goto error_ps3;
1288 #endif
1289
1290 #ifdef OF_PLATFORM_DRIVER
1291         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1292         if (retval < 0)
1293                 goto error_of_platform;
1294 #endif
1295
1296 #ifdef SA1111_DRIVER
1297         retval = sa1111_driver_register(&SA1111_DRIVER);
1298         if (retval < 0)
1299                 goto error_sa1111;
1300 #endif
1301
1302 #ifdef SM501_OHCI_DRIVER
1303         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1304         if (retval < 0)
1305                 goto error_sm501;
1306 #endif
1307
1308 #ifdef TMIO_OHCI_DRIVER
1309         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1310         if (retval < 0)
1311                 goto error_tmio;
1312 #endif
1313
1314         return retval;
1315
1316         /* Error path */
1317 #ifdef TMIO_OHCI_DRIVER
1318         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1319  error_tmio:
1320 #endif
1321 #ifdef SM501_OHCI_DRIVER
1322         platform_driver_unregister(&SM501_OHCI_DRIVER);
1323  error_sm501:
1324 #endif
1325 #ifdef SA1111_DRIVER
1326         sa1111_driver_unregister(&SA1111_DRIVER);
1327  error_sa1111:
1328 #endif
1329 #ifdef OF_PLATFORM_DRIVER
1330         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1331  error_of_platform:
1332 #endif
1333 #ifdef PS3_SYSTEM_BUS_DRIVER
1334         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1335  error_ps3:
1336 #endif
1337         debugfs_remove(ohci_debug_root);
1338         ohci_debug_root = NULL;
1339
1340         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1341         return retval;
1342 }
1343 module_init(ohci_hcd_mod_init);
1344
1345 static void __exit ohci_hcd_mod_exit(void)
1346 {
1347 #ifdef TMIO_OHCI_DRIVER
1348         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1349 #endif
1350 #ifdef SM501_OHCI_DRIVER
1351         platform_driver_unregister(&SM501_OHCI_DRIVER);
1352 #endif
1353 #ifdef SA1111_DRIVER
1354         sa1111_driver_unregister(&SA1111_DRIVER);
1355 #endif
1356 #ifdef OF_PLATFORM_DRIVER
1357         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1358 #endif
1359 #ifdef PS3_SYSTEM_BUS_DRIVER
1360         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1361 #endif
1362         debugfs_remove(ohci_debug_root);
1363         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1364 }
1365 module_exit(ohci_hcd_mod_exit);
1366