drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
   3  *
   4  * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
   5  * Tested on OMAP3430 ES2.0 SDP
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  *      Author: Vikram Pandita <vikram.pandita@ti.com>
   9  *
  10  * Copyright (C) 2009 Nokia Corporation
  11  *      Contact: Felipe Balbi <felipe.balbi@nokia.com>
  12  *
  13  * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  28  *
  29  * TODO (last updated Feb 23rd, 2009):
  30  *      - add kernel-doc
  31  *      - enable AUTOIDLE
  32  *      - move DPLL5 programming to clock fw
  33  *      - add suspend/resume
  34  *      - move workarounds to board-files
  35  */
  36
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/gpio.h>
  40 #include <plat/usb.h>
  41
  42 /*
  43  * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
  44  *      Use ehci_omap_readl()/ehci_omap_writel() functions
  45  */
  46
  47 /* TLL Register Set */
  48 #define OMAP_USBTLL_REVISION                            (0x00)
  49 #define OMAP_USBTLL_SYSCONFIG                           (0x10)
  50 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY                 (1 << 8)
  51 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE                 (1 << 3)
  52 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP                 (1 << 2)
  53 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET                 (1 << 1)
  54 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE                  (1 << 0)
  55
  56 #define OMAP_USBTLL_SYSSTATUS                           (0x14)
  57 #define OMAP_USBTLL_SYSSTATUS_RESETDONE                 (1 << 0)
  58
  59 #define OMAP_USBTLL_IRQSTATUS                           (0x18)
  60 #define OMAP_USBTLL_IRQENABLE                           (0x1C)
  61
  62 #define OMAP_TLL_SHARED_CONF                            (0x30)
  63 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN             (1 << 6)
  64 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN            (1 << 5)
  65 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION              (1 << 2)
  66 #define OMAP_TLL_SHARED_CONF_FCLK_REQ                   (1 << 1)
  67 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON                 (1 << 0)
  68
  69 #define OMAP_TLL_CHANNEL_CONF(num)                      (0x040 + 0x004 * num)
  70 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF            (1 << 11)
  71 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE         (1 << 10)
  72 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE              (1 << 9)
  73 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE               (1 << 8)
  74 #define OMAP_TLL_CHANNEL_CONF_CHANEN                    (1 << 0)
  75
  76 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num)                (0x804 + 0x100 * num)
  77 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num)               (0x807 + 0x100 * num)
  78 #define OMAP_TLL_ULPI_OTG_CTRL(num)                     (0x80A + 0x100 * num)
  79 #define OMAP_TLL_ULPI_INT_EN_RISE(num)                  (0x80D + 0x100 * num)
  80 #define OMAP_TLL_ULPI_INT_EN_FALL(num)                  (0x810 + 0x100 * num)
  81 #define OMAP_TLL_ULPI_INT_STATUS(num)                   (0x813 + 0x100 * num)
  82 #define OMAP_TLL_ULPI_INT_LATCH(num)                    (0x814 + 0x100 * num)
  83 #define OMAP_TLL_ULPI_DEBUG(num)                        (0x815 + 0x100 * num)
  84 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num)             (0x816 + 0x100 * num)
  85
  86 #define OMAP_TLL_CHANNEL_COUNT                          3
  87 #define OMAP_TLL_CHANNEL_1_EN_MASK                      (1 << 1)
  88 #define OMAP_TLL_CHANNEL_2_EN_MASK                      (1 << 2)
  89 #define OMAP_TLL_CHANNEL_3_EN_MASK                      (1 << 4)
  90
  91 /* UHH Register Set */
  92 #define OMAP_UHH_REVISION                               (0x00)
  93 #define OMAP_UHH_SYSCONFIG                              (0x10)
  94 #define OMAP_UHH_SYSCONFIG_MIDLEMODE                    (1 << 12)
  95 #define OMAP_UHH_SYSCONFIG_CACTIVITY                    (1 << 8)
  96 #define OMAP_UHH_SYSCONFIG_SIDLEMODE                    (1 << 3)
  97 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP                    (1 << 2)
  98 #define OMAP_UHH_SYSCONFIG_SOFTRESET                    (1 << 1)
  99 #define OMAP_UHH_SYSCONFIG_AUTOIDLE                     (1 << 0)
 100
 101 #define OMAP_UHH_SYSSTATUS                              (0x14)
 102 #define OMAP_UHH_HOSTCONFIG                             (0x40)
 103 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS                 (1 << 0)
 104 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS              (1 << 0)
 105 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS              (1 << 11)
 106 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS              (1 << 12)
 107 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN              (1 << 2)
 108 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN              (1 << 3)
 109 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN             (1 << 4)
 110 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN              (1 << 5)
 111 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS           (1 << 8)
 112 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS           (1 << 9)
 113 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS           (1 << 10)
 114
 115 #define OMAP_UHH_DEBUG_CSR                              (0x44)
 116
 117 /* EHCI Register Set */
 118 #define EHCI_INSNREG05_ULPI                             (0xA4)
 119 #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT               31
 120 #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT               24
 121 #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT                 22
 122 #define EHCI_INSNREG05_ULPI_REGADD_SHIFT                16
 123 #define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT             8
 124 #define EHCI_INSNREG05_ULPI_WRDATA_SHIFT                0
 125
 126 /*-------------------------------------------------------------------------*/
 127
 128 static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val)
 129 {
 130         __raw_writel(val, base + reg);
 131 }
 132
 133 static inline u32 ehci_omap_readl(void __iomem *base, u32 reg)
 134 {
 135         return __raw_readl(base + reg);
 136 }
 137
 138 static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val)
 139 {
 140         __raw_writeb(val, base + reg);
 141 }
 142
 143 static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
 144 {
 145         return __raw_readb(base + reg);
 146 }
 147
 148 /*-------------------------------------------------------------------------*/
 149
 150 struct ehci_hcd_omap {
 151         struct ehci_hcd         *ehci;
 152         struct device           *dev;
 153
 154         struct clk              *usbhost_ick;
 155         struct clk              *usbhost2_120m_fck;
 156         struct clk              *usbhost1_48m_fck;
 157         struct clk              *usbtll_fck;
 158         struct clk              *usbtll_ick;
 159
 160         /* FIXME the following two workarounds are
 161          * board specific not silicon-specific so these
 162          * should be moved to board-file instead.
 163          *
 164          * Maybe someone from TI will know better which
 165          * board is affected and needs the workarounds
 166          * to be applied
 167          */
 168
 169         /* gpio for resetting phy */
 170         int                     reset_gpio_port[OMAP3_HS_USB_PORTS];
 171
 172         /* phy reset workaround */
 173         int                     phy_reset;
 174
 175         /* desired phy_mode: TLL, PHY */
 176         enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
 177
 178         void __iomem            *uhh_base;
 179         void __iomem            *tll_base;
 180         void __iomem            *ehci_base;
 181 };
 182
 183 /*-------------------------------------------------------------------------*/
 184
 185 static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask)
 186 {
 187         unsigned reg;
 188         int i;
 189
 190         /* Program the 3 TLL channels upfront */
 191         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 192                 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
 193
 194                 /* Disable AutoIdle, BitStuffing and use SDR Mode */
 195                 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
 196                                 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
 197                                 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
 198                 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
 199         }
 200
 201         /* Program Common TLL register */
 202         reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
 203         reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
 204                         | OMAP_TLL_SHARED_CONF_USB_DIVRATION
 205                         | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
 206         reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
 207
 208         ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
 209
 210         /* Enable channels now */
 211         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 212                 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
 213
 214                 /* Enable only the reg that is needed */
 215                 if (!(tll_channel_mask & 1<<i))
 216                         continue;
 217
 218                 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
 219                 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
 220
 221                 ehci_omap_writeb(omap->tll_base,
 222                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
 223                 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
 224                                 i+1, ehci_omap_readb(omap->tll_base,
 225                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
 226         }
 227 }
 228
 229 /*-------------------------------------------------------------------------*/
 230
 231 /* omap_start_ehc
 232  *      - Start the TI USBHOST controller
 233  */
 234 static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
 235 {
 236         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 237         u8 tll_ch_mask = 0;
 238         unsigned reg = 0;
 239         int ret = 0;
 240
 241         dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
 242
 243         /* Enable Clocks for USBHOST */
 244         omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
 245         if (IS_ERR(omap->usbhost_ick)) {
 246                 ret =  PTR_ERR(omap->usbhost_ick);
 247                 goto err_host_ick;
 248         }
 249         clk_enable(omap->usbhost_ick);
 250
 251         omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
 252         if (IS_ERR(omap->usbhost2_120m_fck)) {
 253                 ret = PTR_ERR(omap->usbhost2_120m_fck);
 254                 goto err_host_120m_fck;
 255         }
 256         clk_enable(omap->usbhost2_120m_fck);
 257
 258         omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
 259         if (IS_ERR(omap->usbhost1_48m_fck)) {
 260                 ret = PTR_ERR(omap->usbhost1_48m_fck);
 261                 goto err_host_48m_fck;
 262         }
 263         clk_enable(omap->usbhost1_48m_fck);
 264
 265         if (omap->phy_reset) {
 266                 /* Refer: ISSUE1 */
 267                 if (gpio_is_valid(omap->reset_gpio_port[0])) {
 268                         gpio_request(omap->reset_gpio_port[0],
 269                                                 "USB1 PHY reset");
 270                         gpio_direction_output(omap->reset_gpio_port[0], 0);
 271                 }
 272
 273                 if (gpio_is_valid(omap->reset_gpio_port[1])) {
 274                         gpio_request(omap->reset_gpio_port[1],
 275                                                 "USB2 PHY reset");
 276                         gpio_direction_output(omap->reset_gpio_port[1], 0);
 277                 }
 278
 279                 /* Hold the PHY in RESET for enough time till DIR is high */
 280                 udelay(10);
 281         }
 282
 283         /* Configure TLL for 60Mhz clk for ULPI */
 284         omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
 285         if (IS_ERR(omap->usbtll_fck)) {
 286                 ret = PTR_ERR(omap->usbtll_fck);
 287                 goto err_tll_fck;
 288         }
 289         clk_enable(omap->usbtll_fck);
 290
 291         omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
 292         if (IS_ERR(omap->usbtll_ick)) {
 293                 ret = PTR_ERR(omap->usbtll_ick);
 294                 goto err_tll_ick;
 295         }
 296         clk_enable(omap->usbtll_ick);
 297
 298         /* perform TLL soft reset, and wait until reset is complete */
 299         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
 300                         OMAP_USBTLL_SYSCONFIG_SOFTRESET);
 301
 302         /* Wait for TLL reset to complete */
 303         while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
 304                         & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
 305                 cpu_relax();
 306
 307                 if (time_after(jiffies, timeout)) {
 308                         dev_dbg(omap->dev, "operation timed out\n");
 309                         ret = -EINVAL;
 310                         goto err_sys_status;
 311                 }
 312         }
 313
 314         dev_dbg(omap->dev, "TLL RESET DONE\n");
 315
 316         /* (1<<3) = no idle mode only for initial debugging */
 317         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
 318                         OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
 319                         OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
 320                         OMAP_USBTLL_SYSCONFIG_CACTIVITY);
 321
 322
 323         /* Put UHH in NoIdle/NoStandby mode */
 324         reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
 325         reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
 326                         | OMAP_UHH_SYSCONFIG_SIDLEMODE
 327                         | OMAP_UHH_SYSCONFIG_CACTIVITY
 328                         | OMAP_UHH_SYSCONFIG_MIDLEMODE);
 329         reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
 330
 331         ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
 332
 333         reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
 334
 335         /* setup ULPI bypass and burst configurations */
 336         reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
 337                         | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
 338                         | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
 339         reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
 340
 341         if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 342                 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
 343         if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 344                 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
 345         if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 346                 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
 347
 348         /* Bypass the TLL module for PHY mode operation */
 349          if (omap_rev() <= OMAP3430_REV_ES2_1) {
 350                 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
 351                 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
 352                         (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
 353                                 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
 354                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
 355                 else
 356                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
 357         } else {
 358                 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
 359                 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
 360                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
 361                 else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
 362                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
 363
 364                 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
 365                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
 366                 else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
 367                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
 368
 369                 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
 370                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
 371                 else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
 372                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
 373
 374         }
 375         ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
 376         dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
 377
 378
 379         if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
 380                 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
 381                         (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
 382
 383                 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
 384                         tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
 385                 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
 386                         tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
 387                 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
 388                         tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
 389
 390                 /* Enable UTMI mode for required TLL channels */
 391                 omap_usb_utmi_init(omap, tll_ch_mask);
 392         }
 393
 394         if (omap->phy_reset) {
 395                 /* Refer ISSUE1:
 396                  * Hold the PHY in RESET for enough time till
 397                  * PHY is settled and ready
 398                  */
 399                 udelay(10);
 400
 401                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 402                         gpio_set_value(omap->reset_gpio_port[0], 1);
 403
 404                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 405                         gpio_set_value(omap->reset_gpio_port[1], 1);
 406         }
 407
 408         return 0;
 409
 410 err_sys_status:
 411         clk_disable(omap->usbtll_ick);
 412         clk_put(omap->usbtll_ick);
 413
 414 err_tll_ick:
 415         clk_disable(omap->usbtll_fck);
 416         clk_put(omap->usbtll_fck);
 417
 418 err_tll_fck:
 419         clk_disable(omap->usbhost1_48m_fck);
 420         clk_put(omap->usbhost1_48m_fck);
 421
 422         if (omap->phy_reset) {
 423                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 424                         gpio_free(omap->reset_gpio_port[0]);
 425
 426                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 427                         gpio_free(omap->reset_gpio_port[1]);
 428         }
 429
 430 err_host_48m_fck:
 431         clk_disable(omap->usbhost2_120m_fck);
 432         clk_put(omap->usbhost2_120m_fck);
 433
 434 err_host_120m_fck:
 435         clk_disable(omap->usbhost_ick);
 436         clk_put(omap->usbhost_ick);
 437
 438 err_host_ick:
 439         return ret;
 440 }
 441
 442 static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
 443 {
 444         unsigned long timeout = jiffies + msecs_to_jiffies(100);
 445
 446         dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
 447
 448         /* Reset OMAP modules for insmod/rmmod to work */
 449         ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
 450                         OMAP_UHH_SYSCONFIG_SOFTRESET);
 451         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 452                                 & (1 << 0))) {
 453                 cpu_relax();
 454
 455                 if (time_after(jiffies, timeout))
 456                         dev_dbg(omap->dev, "operation timed out\n");
 457         }
 458
 459         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 460                                 & (1 << 1))) {
 461                 cpu_relax();
 462
 463                 if (time_after(jiffies, timeout))
 464                         dev_dbg(omap->dev, "operation timed out\n");
 465         }
 466
 467         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 468                                 & (1 << 2))) {
 469                 cpu_relax();
 470
 471                 if (time_after(jiffies, timeout))
 472                         dev_dbg(omap->dev, "operation timed out\n");
 473         }
 474
 475         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
 476
 477         while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
 478                                 & (1 << 0))) {
 479                 cpu_relax();
 480
 481                 if (time_after(jiffies, timeout))
 482                         dev_dbg(omap->dev, "operation timed out\n");
 483         }
 484
 485         if (omap->usbtll_fck != NULL) {
 486                 clk_disable(omap->usbtll_fck);
 487                 clk_put(omap->usbtll_fck);
 488                 omap->usbtll_fck = NULL;
 489         }
 490
 491         if (omap->usbhost_ick != NULL) {
 492                 clk_disable(omap->usbhost_ick);
 493                 clk_put(omap->usbhost_ick);
 494                 omap->usbhost_ick = NULL;
 495         }
 496
 497         if (omap->usbhost1_48m_fck != NULL) {
 498                 clk_disable(omap->usbhost1_48m_fck);
 499                 clk_put(omap->usbhost1_48m_fck);
 500                 omap->usbhost1_48m_fck = NULL;
 501         }
 502
 503         if (omap->usbhost2_120m_fck != NULL) {
 504                 clk_disable(omap->usbhost2_120m_fck);
 505                 clk_put(omap->usbhost2_120m_fck);
 506                 omap->usbhost2_120m_fck = NULL;
 507         }
 508
 509         if (omap->usbtll_ick != NULL) {
 510                 clk_disable(omap->usbtll_ick);
 511                 clk_put(omap->usbtll_ick);
 512                 omap->usbtll_ick = NULL;
 513         }
 514
 515         if (omap->phy_reset) {
 516                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 517                         gpio_free(omap->reset_gpio_port[0]);
 518
 519                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 520                         gpio_free(omap->reset_gpio_port[1]);
 521         }
 522
 523         dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
 524 }
 525
 526 /*-------------------------------------------------------------------------*/
 527
 528 static const struct hc_driver ehci_omap_hc_driver;
 529
 530 /* configure so an HC device and id are always provided */
 531 /* always called with process context; sleeping is OK */
 532
 533 /**
 534  * ehci_hcd_omap_probe - initialize TI-based HCDs
 535  *
 536  * Allocates basic resources for this USB host controller, and
 537  * then invokes the start() method for the HCD associated with it
 538  * through the hotplug entry's driver_data.
 539  */
 540 static int ehci_hcd_omap_probe(struct platform_device *pdev)
 541 {
 542         struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
 543         struct ehci_hcd_omap *omap;
 544         struct resource *res;
 545         struct usb_hcd *hcd;
 546
 547         int irq = platform_get_irq(pdev, 0);
 548         int ret = -ENODEV;
 549
 550         if (!pdata) {
 551                 dev_dbg(&pdev->dev, "missing platform_data\n");
 552                 goto err_pdata;
 553         }
 554
 555         if (usb_disabled())
 556                 goto err_disabled;
 557
 558         omap = kzalloc(sizeof(*omap), GFP_KERNEL);
 559         if (!omap) {
 560                 ret = -ENOMEM;
 561                 goto err_disabled;
 562         }
 563
 564         hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
 565                         dev_name(&pdev->dev));
 566         if (!hcd) {
 567                 dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret);
 568                 ret = -ENOMEM;
 569                 goto err_create_hcd;
 570         }
 571
 572         platform_set_drvdata(pdev, omap);
 573         omap->dev               = &pdev->dev;
 574         omap->phy_reset         = pdata->phy_reset;
 575         omap->reset_gpio_port[0]        = pdata->reset_gpio_port[0];
 576         omap->reset_gpio_port[1]        = pdata->reset_gpio_port[1];
 577         omap->reset_gpio_port[2]        = pdata->reset_gpio_port[2];
 578         omap->port_mode[0]              = pdata->port_mode[0];
 579         omap->port_mode[1]              = pdata->port_mode[1];
 580         omap->port_mode[2]              = pdata->port_mode[2];
 581         omap->ehci              = hcd_to_ehci(hcd);
 582         omap->ehci->sbrn        = 0x20;
 583
 584         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 585
 586         hcd->rsrc_start = res->start;
 587         hcd->rsrc_len = resource_size(res);
 588
 589         hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
 590         if (!hcd->regs) {
 591                 dev_err(&pdev->dev, "EHCI ioremap failed\n");
 592                 ret = -ENOMEM;
 593                 goto err_ioremap;
 594         }
 595
 596         /* we know this is the memory we want, no need to ioremap again */
 597         omap->ehci->caps = hcd->regs;
 598         omap->ehci_base = hcd->regs;
 599
 600         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 601         omap->uhh_base = ioremap(res->start, resource_size(res));
 602         if (!omap->uhh_base) {
 603                 dev_err(&pdev->dev, "UHH ioremap failed\n");
 604                 ret = -ENOMEM;
 605                 goto err_uhh_ioremap;
 606         }
 607
 608         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 609         omap->tll_base = ioremap(res->start, resource_size(res));
 610         if (!omap->tll_base) {
 611                 dev_err(&pdev->dev, "TLL ioremap failed\n");
 612                 ret = -ENOMEM;
 613                 goto err_tll_ioremap;
 614         }
 615
 616         ret = omap_start_ehc(omap, hcd);
 617         if (ret) {
 618                 dev_dbg(&pdev->dev, "failed to start ehci\n");
 619                 goto err_start;
 620         }
 621
 622         omap->ehci->regs = hcd->regs
 623                 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
 624
 625         /* cache this readonly data; minimize chip reads */
 626         omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
 627
 628         /* SET 1 micro-frame Interrupt interval */
 629         writel(readl(&omap->ehci->regs->command) | (1 << 16),
 630                         &omap->ehci->regs->command);
 631
 632         ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
 633         if (ret) {
 634                 dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
 635                 goto err_add_hcd;
 636         }
 637
 638         return 0;
 639
 640 err_add_hcd:
 641         omap_stop_ehc(omap, hcd);
 642
 643 err_start:
 644         iounmap(omap->tll_base);
 645
 646 err_tll_ioremap:
 647         iounmap(omap->uhh_base);
 648
 649 err_uhh_ioremap:
 650         iounmap(hcd->regs);
 651
 652 err_ioremap:
 653         usb_put_hcd(hcd);
 654
 655 err_create_hcd:
 656         kfree(omap);
 657 err_disabled:
 658 err_pdata:
 659         return ret;
 660 }
 661
 662 /* may be called without controller electrically present */
 663 /* may be called with controller, bus, and devices active */
 664
 665 /**
 666  * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
 667  * @pdev: USB Host Controller being removed
 668  *
 669  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 670  * the HCD's stop() method.  It is always called from a thread
 671  * context, normally "rmmod", "apmd", or something similar.
 672  */
 673 static int ehci_hcd_omap_remove(struct platform_device *pdev)
 674 {
 675         struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
 676         struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
 677
 678         usb_remove_hcd(hcd);
 679         omap_stop_ehc(omap, hcd);
 680         iounmap(hcd->regs);
 681         iounmap(omap->tll_base);
 682         iounmap(omap->uhh_base);
 683         usb_put_hcd(hcd);
 684
 685         return 0;
 686 }
 687
 688 static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
 689 {
 690         struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
 691         struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
 692
 693         if (hcd->driver->shutdown)
 694                 hcd->driver->shutdown(hcd);
 695 }
 696
 697 static struct platform_driver ehci_hcd_omap_driver = {
 698         .probe                  = ehci_hcd_omap_probe,
 699         .remove                 = ehci_hcd_omap_remove,
 700         .shutdown               = ehci_hcd_omap_shutdown,
 701         /*.suspend              = ehci_hcd_omap_suspend, */
 702         /*.resume               = ehci_hcd_omap_resume, */
 703         .driver = {
 704                 .name           = "ehci-omap",
 705         }
 706 };
 707
 708 /*-------------------------------------------------------------------------*/
 709
 710 static const struct hc_driver ehci_omap_hc_driver = {
 711         .description            = hcd_name,
 712         .product_desc           = "OMAP-EHCI Host Controller",
 713         .hcd_priv_size          = sizeof(struct ehci_hcd),
 714
 715         /*
 716          * generic hardware linkage
 717          */
 718         .irq                    = ehci_irq,
 719         .flags                  = HCD_MEMORY | HCD_USB2,
 720
 721         /*
 722          * basic lifecycle operations
 723          */
 724         .reset                  = ehci_init,
 725         .start                  = ehci_run,
 726         .stop                   = ehci_stop,
 727         .shutdown               = ehci_shutdown,
 728
 729         /*
 730          * managing i/o requests and associated device resources
 731          */
 732         .urb_enqueue            = ehci_urb_enqueue,
 733         .urb_dequeue            = ehci_urb_dequeue,
 734         .endpoint_disable       = ehci_endpoint_disable,
 735         .endpoint_reset         = ehci_endpoint_reset,
 736
 737         /*
 738          * scheduling support
 739          */
 740         .get_frame_number       = ehci_get_frame,
 741
 742         /*
 743          * root hub support
 744          */
 745         .hub_status_data        = ehci_hub_status_data,
 746         .hub_control            = ehci_hub_control,
 747         .bus_suspend            = ehci_bus_suspend,
 748         .bus_resume             = ehci_bus_resume,
 749
 750         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 751 };
 752
 753 MODULE_ALIAS("platform:omap-ehci");
 754 MODULE_AUTHOR("Texas Instruments, Inc.");
 755 MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
 756