1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc->revision >= DWC3_REVISION_194A) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc->revision >= DWC3_REVISION_194A)
125 /* wait for a change in DSTS */
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
130 if (DWC3_DSTS_USBLNKST(reg) == state)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8 *index)
150 if (*index == (DWC3_TRB_NUM - 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
175 struct dwc3 *dwc = dep->dwc;
177 req->started = false;
178 list_del(&req->list);
180 req->needs_extra_trb = false;
182 if (req->request.status == -EINPROGRESS)
183 req->request.status = status;
186 usb_gadget_unmap_request_by_dev(dwc->sysdev,
187 &req->request, req->direction);
190 trace_dwc3_gadget_giveback(req);
193 pm_runtime_put(dwc->dev);
197 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
198 * @dep: The endpoint to whom the request belongs to
199 * @req: The request we're giving back
200 * @status: completion code for the request
202 * Must be called with controller's lock held and interrupts disabled. This
203 * function will unmap @req and call its ->complete() callback to notify upper
204 * layers that it has completed.
206 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
209 struct dwc3 *dwc = dep->dwc;
211 dwc3_gadget_del_and_unmap_request(dep, req, status);
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
227 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
257 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
268 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
274 u32 saved_config = 0;
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 dwc->link_state == DWC3_LINK_STATE_U2 ||
311 dwc->link_state == DWC3_LINK_STATE_U3);
313 if (unlikely(needs_wakeup)) {
314 ret = __dwc3_gadget_wakeup(dwc);
315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 !usb_endpoint_xfer_isoc(desc))
341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
343 cmd |= DWC3_DEPCMD_CMDACT;
345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 cmd_status = DWC3_DEPCMD_STATUS(reg);
351 switch (cmd_status) {
355 case DEPEVT_TRANSFER_NO_RESOURCE:
358 case DEPEVT_TRANSFER_BUS_EXPIRY:
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
382 cmd_status = -ETIMEDOUT;
385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
388 switch (DWC3_DEPCMD_CMD(cmd)) {
389 case DWC3_DEPCMD_STARTTRANSFER:
390 dep->flags |= DWC3_EP_TRANSFER_STARTED;
391 dwc3_gadget_ep_get_transfer_index(dep);
393 case DWC3_DEPCMD_ENDTRANSFER:
394 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
403 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
405 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
411 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
413 struct dwc3 *dwc = dep->dwc;
414 struct dwc3_gadget_ep_cmd_params params;
415 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
418 * As of core revision 2.60a the recommended programming model
419 * is to set the ClearPendIN bit when issuing a Clear Stall EP
420 * command for IN endpoints. This is to prevent an issue where
421 * some (non-compliant) hosts may not send ACK TPs for pending
422 * IN transfers due to a mishandled error condition. Synopsys
425 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
426 (dwc->gadget.speed >= USB_SPEED_SUPER))
427 cmd |= DWC3_DEPCMD_CLEARPENDIN;
429 memset(¶ms, 0, sizeof(params));
431 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
434 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
435 struct dwc3_trb *trb)
437 u32 offset = (char *) trb - (char *) dep->trb_pool;
439 return dep->trb_pool_dma + offset;
442 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
444 struct dwc3 *dwc = dep->dwc;
449 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
450 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
451 &dep->trb_pool_dma, GFP_KERNEL);
452 if (!dep->trb_pool) {
453 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
461 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
463 struct dwc3 *dwc = dep->dwc;
465 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
466 dep->trb_pool, dep->trb_pool_dma);
468 dep->trb_pool = NULL;
469 dep->trb_pool_dma = 0;
472 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
474 struct dwc3_gadget_ep_cmd_params params;
476 memset(¶ms, 0x00, sizeof(params));
478 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
480 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
485 * dwc3_gadget_start_config - configure ep resources
486 * @dep: endpoint that is being enabled
488 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
489 * completion, it will set Transfer Resource for all available endpoints.
491 * The assignment of transfer resources cannot perfectly follow the data book
492 * due to the fact that the controller driver does not have all knowledge of the
493 * configuration in advance. It is given this information piecemeal by the
494 * composite gadget framework after every SET_CONFIGURATION and
495 * SET_INTERFACE. Trying to follow the databook programming model in this
496 * scenario can cause errors. For two reasons:
498 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
499 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
500 * incorrect in the scenario of multiple interfaces.
502 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
503 * endpoint on alt setting (8.1.6).
505 * The following simplified method is used instead:
507 * All hardware endpoints can be assigned a transfer resource and this setting
508 * will stay persistent until either a core reset or hibernation. So whenever we
509 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
510 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
511 * guaranteed that there are as many transfer resources as endpoints.
513 * This function is called for each endpoint when it is being enabled but is
514 * triggered only when called for EP0-out, which always happens first, and which
515 * should only happen in one of the above conditions.
517 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
519 struct dwc3_gadget_ep_cmd_params params;
528 memset(¶ms, 0x00, sizeof(params));
529 cmd = DWC3_DEPCMD_DEPSTARTCFG;
532 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
536 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
537 struct dwc3_ep *dep = dwc->eps[i];
542 ret = dwc3_gadget_set_xfer_resource(dep);
550 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
552 const struct usb_ss_ep_comp_descriptor *comp_desc;
553 const struct usb_endpoint_descriptor *desc;
554 struct dwc3_gadget_ep_cmd_params params;
555 struct dwc3 *dwc = dep->dwc;
557 comp_desc = dep->endpoint.comp_desc;
558 desc = dep->endpoint.desc;
560 memset(¶ms, 0x00, sizeof(params));
562 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
563 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
565 /* Burst size is only needed in SuperSpeed mode */
566 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
567 u32 burst = dep->endpoint.maxburst;
568 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
571 params.param0 |= action;
572 if (action == DWC3_DEPCFG_ACTION_RESTORE)
573 params.param2 |= dep->saved_state;
575 if (usb_endpoint_xfer_control(desc))
576 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
578 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
579 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
581 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
582 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
583 | DWC3_DEPCFG_STREAM_EVENT_EN;
584 dep->stream_capable = true;
587 if (!usb_endpoint_xfer_control(desc))
588 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
591 * We are doing 1:1 mapping for endpoints, meaning
592 * Physical Endpoints 2 maps to Logical Endpoint 2 and
593 * so on. We consider the direction bit as part of the physical
594 * endpoint number. So USB endpoint 0x81 is 0x03.
596 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
599 * We must use the lower 16 TX FIFOs even though
603 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
605 if (desc->bInterval) {
606 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
607 dep->interval = 1 << (desc->bInterval - 1);
610 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
614 * __dwc3_gadget_ep_enable - initializes a hw endpoint
615 * @dep: endpoint to be initialized
616 * @action: one of INIT, MODIFY or RESTORE
618 * Caller should take care of locking. Execute all necessary commands to
619 * initialize a HW endpoint so it can be used by a gadget driver.
621 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
623 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
624 struct dwc3 *dwc = dep->dwc;
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 ret = dwc3_gadget_start_config(dep);
635 ret = dwc3_gadget_set_ep_config(dep, action);
639 if (!(dep->flags & DWC3_EP_ENABLED)) {
640 struct dwc3_trb *trb_st_hw;
641 struct dwc3_trb *trb_link;
643 dep->type = usb_endpoint_type(desc);
644 dep->flags |= DWC3_EP_ENABLED;
645 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
647 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
648 reg |= DWC3_DALEPENA_EP(dep->number);
649 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
651 if (usb_endpoint_xfer_control(desc))
654 /* Initialize the TRB ring */
655 dep->trb_dequeue = 0;
656 dep->trb_enqueue = 0;
657 memset(dep->trb_pool, 0,
658 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
660 /* Link TRB. The HWO bit is never reset */
661 trb_st_hw = &dep->trb_pool[0];
663 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
664 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
665 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
667 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
671 * Issue StartTransfer here with no-op TRB so we can always rely on No
672 * Response Update Transfer command.
674 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
675 usb_endpoint_xfer_int(desc)) {
676 struct dwc3_gadget_ep_cmd_params params;
677 struct dwc3_trb *trb;
681 memset(¶ms, 0, sizeof(params));
682 trb = &dep->trb_pool[0];
683 trb_dma = dwc3_trb_dma_offset(dep, trb);
685 params.param0 = upper_32_bits(trb_dma);
686 params.param1 = lower_32_bits(trb_dma);
688 cmd = DWC3_DEPCMD_STARTTRANSFER;
690 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
696 trace_dwc3_gadget_ep_enable(dep);
701 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
702 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
704 struct dwc3_request *req;
706 dwc3_stop_active_transfer(dep, true);
708 /* - giveback all requests to gadget driver */
709 while (!list_empty(&dep->started_list)) {
710 req = next_request(&dep->started_list);
712 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 while (!list_empty(&dep->pending_list)) {
716 req = next_request(&dep->pending_list);
718 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
723 * __dwc3_gadget_ep_disable - disables a hw endpoint
724 * @dep: the endpoint to disable
726 * This function undoes what __dwc3_gadget_ep_enable did and also removes
727 * requests which are currently being processed by the hardware and those which
728 * are not yet scheduled.
730 * Caller should take care of locking.
732 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
734 struct dwc3 *dwc = dep->dwc;
737 trace_dwc3_gadget_ep_disable(dep);
739 dwc3_remove_requests(dwc, dep);
741 /* make sure HW endpoint isn't stalled */
742 if (dep->flags & DWC3_EP_STALL)
743 __dwc3_gadget_ep_set_halt(dep, 0, false);
745 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
746 reg &= ~DWC3_DALEPENA_EP(dep->number);
747 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
749 dep->stream_capable = false;
751 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
753 /* Clear out the ep descriptors for non-ep0 */
754 if (dep->number > 1) {
755 dep->endpoint.comp_desc = NULL;
756 dep->endpoint.desc = NULL;
762 /* -------------------------------------------------------------------------- */
764 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
765 const struct usb_endpoint_descriptor *desc)
770 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
775 /* -------------------------------------------------------------------------- */
777 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
778 const struct usb_endpoint_descriptor *desc)
785 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
786 pr_debug("dwc3: invalid parameters\n");
790 if (!desc->wMaxPacketSize) {
791 pr_debug("dwc3: missing wMaxPacketSize\n");
795 dep = to_dwc3_ep(ep);
798 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
799 "%s is already enabled\n",
803 spin_lock_irqsave(&dwc->lock, flags);
804 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
805 spin_unlock_irqrestore(&dwc->lock, flags);
810 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
818 pr_debug("dwc3: invalid parameters\n");
822 dep = to_dwc3_ep(ep);
825 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
826 "%s is already disabled\n",
830 spin_lock_irqsave(&dwc->lock, flags);
831 ret = __dwc3_gadget_ep_disable(dep);
832 spin_unlock_irqrestore(&dwc->lock, flags);
837 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
840 struct dwc3_request *req;
841 struct dwc3_ep *dep = to_dwc3_ep(ep);
843 req = kzalloc(sizeof(*req), gfp_flags);
847 req->direction = dep->direction;
848 req->epnum = dep->number;
851 trace_dwc3_alloc_request(req);
853 return &req->request;
856 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
857 struct usb_request *request)
859 struct dwc3_request *req = to_dwc3_request(request);
861 trace_dwc3_free_request(req);
866 * dwc3_ep_prev_trb - returns the previous TRB in the ring
867 * @dep: The endpoint with the TRB ring
868 * @index: The index of the current TRB in the ring
870 * Returns the TRB prior to the one pointed to by the index. If the
871 * index is 0, we will wrap backwards, skip the link TRB, and return
872 * the one just before that.
874 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
879 tmp = DWC3_TRB_NUM - 1;
881 return &dep->trb_pool[tmp - 1];
884 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
886 struct dwc3_trb *tmp;
890 * If enqueue & dequeue are equal than it is either full or empty.
892 * One way to know for sure is if the TRB right before us has HWO bit
893 * set or not. If it has, then we're definitely full and can't fit any
894 * more transfers in our ring.
896 if (dep->trb_enqueue == dep->trb_dequeue) {
897 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
898 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
901 return DWC3_TRB_NUM - 1;
904 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
905 trbs_left &= (DWC3_TRB_NUM - 1);
907 if (dep->trb_dequeue < dep->trb_enqueue)
913 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
914 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
915 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
917 struct dwc3 *dwc = dep->dwc;
918 struct usb_gadget *gadget = &dwc->gadget;
919 enum usb_device_speed speed = gadget->speed;
921 trb->size = DWC3_TRB_SIZE_LENGTH(length);
922 trb->bpl = lower_32_bits(dma);
923 trb->bph = upper_32_bits(dma);
925 switch (usb_endpoint_type(dep->endpoint.desc)) {
926 case USB_ENDPOINT_XFER_CONTROL:
927 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
930 case USB_ENDPOINT_XFER_ISOC:
932 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
935 * USB Specification 2.0 Section 5.9.2 states that: "If
936 * there is only a single transaction in the microframe,
937 * only a DATA0 data packet PID is used. If there are
938 * two transactions per microframe, DATA1 is used for
939 * the first transaction data packet and DATA0 is used
940 * for the second transaction data packet. If there are
941 * three transactions per microframe, DATA2 is used for
942 * the first transaction data packet, DATA1 is used for
943 * the second, and DATA0 is used for the third."
945 * IOW, we should satisfy the following cases:
947 * 1) length <= maxpacket
950 * 2) maxpacket < length <= (2 * maxpacket)
953 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
954 * - DATA2, DATA1, DATA0
956 if (speed == USB_SPEED_HIGH) {
957 struct usb_ep *ep = &dep->endpoint;
958 unsigned int mult = 2;
959 unsigned int maxp = usb_endpoint_maxp(ep->desc);
961 if (length <= (2 * maxp))
967 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
970 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
973 /* always enable Interrupt on Missed ISOC */
974 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
977 case USB_ENDPOINT_XFER_BULK:
978 case USB_ENDPOINT_XFER_INT:
979 trb->ctrl = DWC3_TRBCTL_NORMAL;
983 * This is only possible with faulty memory because we
984 * checked it already :)
986 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
987 usb_endpoint_type(dep->endpoint.desc));
991 * Enable Continue on Short Packet
992 * when endpoint is not a stream capable
994 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
995 if (!dep->stream_capable)
996 trb->ctrl |= DWC3_TRB_CTRL_CSP;
999 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1002 if ((!no_interrupt && !chain) ||
1003 (dwc3_calc_trbs_left(dep) == 1))
1004 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1007 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1009 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1010 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1012 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1014 dwc3_ep_inc_enq(dep);
1016 trace_dwc3_prepare_trb(dep, trb);
1020 * dwc3_prepare_one_trb - setup one TRB from one request
1021 * @dep: endpoint for which this request is prepared
1022 * @req: dwc3_request pointer
1023 * @chain: should this TRB be chained to the next?
1024 * @node: only for isochronous endpoints. First TRB needs different type.
1026 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1027 struct dwc3_request *req, unsigned chain, unsigned node)
1029 struct dwc3_trb *trb;
1030 unsigned int length;
1032 unsigned stream_id = req->request.stream_id;
1033 unsigned short_not_ok = req->request.short_not_ok;
1034 unsigned no_interrupt = req->request.no_interrupt;
1036 if (req->request.num_sgs > 0) {
1037 length = sg_dma_len(req->start_sg);
1038 dma = sg_dma_address(req->start_sg);
1040 length = req->request.length;
1041 dma = req->request.dma;
1044 trb = &dep->trb_pool[dep->trb_enqueue];
1047 dwc3_gadget_move_started_request(req);
1049 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1054 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1055 stream_id, short_not_ok, no_interrupt);
1058 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1059 struct dwc3_request *req)
1061 struct scatterlist *sg = req->start_sg;
1062 struct scatterlist *s;
1065 unsigned int remaining = req->request.num_mapped_sgs
1066 - req->num_queued_sgs;
1068 for_each_sg(sg, s, remaining, i) {
1069 unsigned int length = req->request.length;
1070 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1071 unsigned int rem = length % maxp;
1072 unsigned chain = true;
1077 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1078 struct dwc3 *dwc = dep->dwc;
1079 struct dwc3_trb *trb;
1081 req->needs_extra_trb = true;
1083 /* prepare normal TRB */
1084 dwc3_prepare_one_trb(dep, req, true, i);
1086 /* Now prepare one extra TRB to align transfer size */
1087 trb = &dep->trb_pool[dep->trb_enqueue];
1089 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1090 maxp - rem, false, 1,
1091 req->request.stream_id,
1092 req->request.short_not_ok,
1093 req->request.no_interrupt);
1095 dwc3_prepare_one_trb(dep, req, chain, i);
1099 * There can be a situation where all sgs in sglist are not
1100 * queued because of insufficient trb number. To handle this
1101 * case, update start_sg to next sg to be queued, so that
1102 * we have free trbs we can continue queuing from where we
1103 * previously stopped
1106 req->start_sg = sg_next(s);
1108 req->num_queued_sgs++;
1110 if (!dwc3_calc_trbs_left(dep))
1115 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1116 struct dwc3_request *req)
1118 unsigned int length = req->request.length;
1119 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1120 unsigned int rem = length % maxp;
1122 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1123 struct dwc3 *dwc = dep->dwc;
1124 struct dwc3_trb *trb;
1126 req->needs_extra_trb = true;
1128 /* prepare normal TRB */
1129 dwc3_prepare_one_trb(dep, req, true, 0);
1131 /* Now prepare one extra TRB to align transfer size */
1132 trb = &dep->trb_pool[dep->trb_enqueue];
1134 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1135 false, 1, req->request.stream_id,
1136 req->request.short_not_ok,
1137 req->request.no_interrupt);
1138 } else if (req->request.zero && req->request.length &&
1139 (IS_ALIGNED(req->request.length, maxp))) {
1140 struct dwc3 *dwc = dep->dwc;
1141 struct dwc3_trb *trb;
1143 req->needs_extra_trb = true;
1145 /* prepare normal TRB */
1146 dwc3_prepare_one_trb(dep, req, true, 0);
1148 /* Now prepare one extra TRB to handle ZLP */
1149 trb = &dep->trb_pool[dep->trb_enqueue];
1151 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1152 false, 1, req->request.stream_id,
1153 req->request.short_not_ok,
1154 req->request.no_interrupt);
1156 dwc3_prepare_one_trb(dep, req, false, 0);
1161 * dwc3_prepare_trbs - setup TRBs from requests
1162 * @dep: endpoint for which requests are being prepared
1164 * The function goes through the requests list and sets up TRBs for the
1165 * transfers. The function returns once there are no more TRBs available or
1166 * it runs out of requests.
1168 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1170 struct dwc3_request *req, *n;
1172 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1175 * We can get in a situation where there's a request in the started list
1176 * but there weren't enough TRBs to fully kick it in the first time
1177 * around, so it has been waiting for more TRBs to be freed up.
1179 * In that case, we should check if we have a request with pending_sgs
1180 * in the started list and prepare TRBs for that request first,
1181 * otherwise we will prepare TRBs completely out of order and that will
1184 list_for_each_entry(req, &dep->started_list, list) {
1185 if (req->num_pending_sgs > 0)
1186 dwc3_prepare_one_trb_sg(dep, req);
1188 if (!dwc3_calc_trbs_left(dep))
1192 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1193 struct dwc3 *dwc = dep->dwc;
1196 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1201 req->sg = req->request.sg;
1202 req->start_sg = req->sg;
1203 req->num_queued_sgs = 0;
1204 req->num_pending_sgs = req->request.num_mapped_sgs;
1206 if (req->num_pending_sgs > 0)
1207 dwc3_prepare_one_trb_sg(dep, req);
1209 dwc3_prepare_one_trb_linear(dep, req);
1211 if (!dwc3_calc_trbs_left(dep))
1216 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1218 struct dwc3_gadget_ep_cmd_params params;
1219 struct dwc3_request *req;
1224 if (!dwc3_calc_trbs_left(dep))
1227 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1229 dwc3_prepare_trbs(dep);
1230 req = next_request(&dep->started_list);
1232 dep->flags |= DWC3_EP_PENDING_REQUEST;
1236 memset(¶ms, 0, sizeof(params));
1239 params.param0 = upper_32_bits(req->trb_dma);
1240 params.param1 = lower_32_bits(req->trb_dma);
1241 cmd = DWC3_DEPCMD_STARTTRANSFER;
1243 if (dep->stream_capable)
1244 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1246 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1247 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1249 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1250 DWC3_DEPCMD_PARAM(dep->resource_index);
1253 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1256 * FIXME we need to iterate over the list of requests
1257 * here and stop, unmap, free and del each of the linked
1258 * requests instead of what we do now.
1261 memset(req->trb, 0, sizeof(struct dwc3_trb));
1262 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1269 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1273 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1274 return DWC3_DSTS_SOFFN(reg);
1278 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1279 * @dep: isoc endpoint
1281 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1282 * microframe number reported by the XferNotReady event for the future frame
1283 * number to start the isoc transfer.
1285 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1286 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1287 * XferNotReady event are invalid. The driver uses this number to schedule the
1288 * isochronous transfer and passes it to the START TRANSFER command. Because
1289 * this number is invalid, the command may fail. If BIT[15:14] matches the
1290 * internal 16-bit microframe, the START TRANSFER command will pass and the
1291 * transfer will start at the scheduled time, if it is off by 1, the command
1292 * will still pass, but the transfer will start 2 seconds in the future. For all
1293 * other conditions, the START TRANSFER command will fail with bus-expiry.
1295 * In order to workaround this issue, we can test for the correct combination of
1296 * BIT[15:14] by sending START TRANSFER commands with different values of
1297 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1298 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1299 * As the result, within the 4 possible combinations for BIT[15:14], there will
1300 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1301 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1302 * value is the correct combination.
1304 * Since there are only 4 outcomes and the results are ordered, we can simply
1305 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1306 * deduce the smaller successful combination.
1308 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1309 * of BIT[15:14]. The correct combination is as follow:
1311 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1312 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1313 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1314 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1316 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1319 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1325 while (dep->combo_num < 2) {
1326 struct dwc3_gadget_ep_cmd_params params;
1327 u32 test_frame_number;
1331 * Check if we can start isoc transfer on the next interval or
1332 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1334 test_frame_number = dep->frame_number & 0x3fff;
1335 test_frame_number |= dep->combo_num << 14;
1336 test_frame_number += max_t(u32, 4, dep->interval);
1338 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1339 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1341 cmd = DWC3_DEPCMD_STARTTRANSFER;
1342 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1343 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1345 /* Redo if some other failure beside bus-expiry is received */
1346 if (cmd_status && cmd_status != -EAGAIN) {
1347 dep->start_cmd_status = 0;
1352 /* Store the first test status */
1353 if (dep->combo_num == 0)
1354 dep->start_cmd_status = cmd_status;
1359 * End the transfer if the START_TRANSFER command is successful
1360 * to wait for the next XferNotReady to test the command again
1362 if (cmd_status == 0) {
1363 dwc3_stop_active_transfer(dep, true);
1368 /* test0 and test1 are both completed at this point */
1369 test0 = (dep->start_cmd_status == 0);
1370 test1 = (cmd_status == 0);
1372 if (!test0 && test1)
1374 else if (!test0 && !test1)
1376 else if (test0 && !test1)
1378 else if (test0 && test1)
1381 dep->frame_number &= 0x3fff;
1382 dep->frame_number |= dep->combo_num << 14;
1383 dep->frame_number += max_t(u32, 4, dep->interval);
1385 /* Reinitialize test variables */
1386 dep->start_cmd_status = 0;
1389 return __dwc3_gadget_kick_transfer(dep);
1392 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1394 struct dwc3 *dwc = dep->dwc;
1398 if (list_empty(&dep->pending_list)) {
1399 dep->flags |= DWC3_EP_PENDING_REQUEST;
1403 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1404 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1405 (dwc->revision == DWC3_USB31_REVISION_170A &&
1406 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1407 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1409 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1410 return dwc3_gadget_start_isoc_quirk(dep);
1413 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1414 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1416 ret = __dwc3_gadget_kick_transfer(dep);
1424 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1426 struct dwc3 *dwc = dep->dwc;
1428 if (!dep->endpoint.desc) {
1429 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1434 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1435 &req->request, req->dep->name))
1438 pm_runtime_get(dwc->dev);
1440 req->request.actual = 0;
1441 req->request.status = -EINPROGRESS;
1443 trace_dwc3_ep_queue(req);
1445 list_add_tail(&req->list, &dep->pending_list);
1448 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1449 * wait for a XferNotReady event so we will know what's the current
1450 * (micro-)frame number.
1452 * Without this trick, we are very, very likely gonna get Bus Expiry
1453 * errors which will force us issue EndTransfer command.
1455 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1456 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1457 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1460 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1461 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1462 return __dwc3_gadget_start_isoc(dep);
1467 return __dwc3_gadget_kick_transfer(dep);
1470 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1473 struct dwc3_request *req = to_dwc3_request(request);
1474 struct dwc3_ep *dep = to_dwc3_ep(ep);
1475 struct dwc3 *dwc = dep->dwc;
1477 unsigned long flags;
1481 spin_lock_irqsave(&dwc->lock, flags);
1482 ret = __dwc3_gadget_ep_queue(dep, req);
1483 spin_unlock_irqrestore(&dwc->lock, flags);
1488 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1493 * If request was already started, this means we had to
1494 * stop the transfer. With that we also need to ignore
1495 * all TRBs used by the request, however TRBs can only
1496 * be modified after completion of END_TRANSFER
1497 * command. So what we do here is that we wait for
1498 * END_TRANSFER completion and only after that, we jump
1499 * over TRBs by clearing HWO and incrementing dequeue
1502 for (i = 0; i < req->num_trbs; i++) {
1503 struct dwc3_trb *trb;
1506 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1507 dwc3_ep_inc_deq(dep);
1511 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1513 struct dwc3_request *req;
1514 struct dwc3_request *tmp;
1516 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1517 dwc3_gadget_ep_skip_trbs(dep, req);
1518 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1522 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1523 struct usb_request *request)
1525 struct dwc3_request *req = to_dwc3_request(request);
1526 struct dwc3_request *r = NULL;
1528 struct dwc3_ep *dep = to_dwc3_ep(ep);
1529 struct dwc3 *dwc = dep->dwc;
1531 unsigned long flags;
1534 trace_dwc3_ep_dequeue(req);
1536 spin_lock_irqsave(&dwc->lock, flags);
1538 list_for_each_entry(r, &dep->pending_list, list) {
1544 list_for_each_entry(r, &dep->started_list, list) {
1549 /* wait until it is processed */
1550 dwc3_stop_active_transfer(dep, true);
1555 dwc3_gadget_move_cancelled_request(req);
1558 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1564 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1567 spin_unlock_irqrestore(&dwc->lock, flags);
1572 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1574 struct dwc3_gadget_ep_cmd_params params;
1575 struct dwc3 *dwc = dep->dwc;
1578 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1579 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1583 memset(¶ms, 0x00, sizeof(params));
1586 struct dwc3_trb *trb;
1588 unsigned transfer_in_flight;
1591 if (dep->number > 1)
1592 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1594 trb = &dwc->ep0_trb[dep->trb_enqueue];
1596 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1597 started = !list_empty(&dep->started_list);
1599 if (!protocol && ((dep->direction && transfer_in_flight) ||
1600 (!dep->direction && started))) {
1604 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1607 dev_err(dwc->dev, "failed to set STALL on %s\n",
1610 dep->flags |= DWC3_EP_STALL;
1613 ret = dwc3_send_clear_stall_ep_cmd(dep);
1615 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1618 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1624 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1626 struct dwc3_ep *dep = to_dwc3_ep(ep);
1627 struct dwc3 *dwc = dep->dwc;
1629 unsigned long flags;
1633 spin_lock_irqsave(&dwc->lock, flags);
1634 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1635 spin_unlock_irqrestore(&dwc->lock, flags);
1640 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1642 struct dwc3_ep *dep = to_dwc3_ep(ep);
1643 struct dwc3 *dwc = dep->dwc;
1644 unsigned long flags;
1647 spin_lock_irqsave(&dwc->lock, flags);
1648 dep->flags |= DWC3_EP_WEDGE;
1650 if (dep->number == 0 || dep->number == 1)
1651 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1653 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1654 spin_unlock_irqrestore(&dwc->lock, flags);
1659 /* -------------------------------------------------------------------------- */
1661 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1662 .bLength = USB_DT_ENDPOINT_SIZE,
1663 .bDescriptorType = USB_DT_ENDPOINT,
1664 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1667 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1668 .enable = dwc3_gadget_ep0_enable,
1669 .disable = dwc3_gadget_ep0_disable,
1670 .alloc_request = dwc3_gadget_ep_alloc_request,
1671 .free_request = dwc3_gadget_ep_free_request,
1672 .queue = dwc3_gadget_ep0_queue,
1673 .dequeue = dwc3_gadget_ep_dequeue,
1674 .set_halt = dwc3_gadget_ep0_set_halt,
1675 .set_wedge = dwc3_gadget_ep_set_wedge,
1678 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1679 .enable = dwc3_gadget_ep_enable,
1680 .disable = dwc3_gadget_ep_disable,
1681 .alloc_request = dwc3_gadget_ep_alloc_request,
1682 .free_request = dwc3_gadget_ep_free_request,
1683 .queue = dwc3_gadget_ep_queue,
1684 .dequeue = dwc3_gadget_ep_dequeue,
1685 .set_halt = dwc3_gadget_ep_set_halt,
1686 .set_wedge = dwc3_gadget_ep_set_wedge,
1689 /* -------------------------------------------------------------------------- */
1691 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1693 struct dwc3 *dwc = gadget_to_dwc(g);
1695 return __dwc3_gadget_get_frame(dwc);
1698 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1709 * According to the Databook Remote wakeup request should
1710 * be issued only when the device is in early suspend state.
1712 * We can check that via USB Link State bits in DSTS register.
1714 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1716 speed = reg & DWC3_DSTS_CONNECTSPD;
1717 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1718 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1721 link_state = DWC3_DSTS_USBLNKST(reg);
1723 switch (link_state) {
1724 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1725 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1731 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1733 dev_err(dwc->dev, "failed to put link in Recovery\n");
1737 /* Recent versions do this automatically */
1738 if (dwc->revision < DWC3_REVISION_194A) {
1739 /* write zeroes to Link Change Request */
1740 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1741 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1742 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1745 /* poll until Link State changes to ON */
1749 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1751 /* in HS, means ON */
1752 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1756 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1757 dev_err(dwc->dev, "failed to send remote wakeup\n");
1764 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1766 struct dwc3 *dwc = gadget_to_dwc(g);
1767 unsigned long flags;
1770 spin_lock_irqsave(&dwc->lock, flags);
1771 ret = __dwc3_gadget_wakeup(dwc);
1772 spin_unlock_irqrestore(&dwc->lock, flags);
1777 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1780 struct dwc3 *dwc = gadget_to_dwc(g);
1781 unsigned long flags;
1783 spin_lock_irqsave(&dwc->lock, flags);
1784 g->is_selfpowered = !!is_selfpowered;
1785 spin_unlock_irqrestore(&dwc->lock, flags);
1790 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1795 if (pm_runtime_suspended(dwc->dev))
1798 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1800 if (dwc->revision <= DWC3_REVISION_187A) {
1801 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1802 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1805 if (dwc->revision >= DWC3_REVISION_194A)
1806 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1807 reg |= DWC3_DCTL_RUN_STOP;
1809 if (dwc->has_hibernation)
1810 reg |= DWC3_DCTL_KEEP_CONNECT;
1812 dwc->pullups_connected = true;
1814 reg &= ~DWC3_DCTL_RUN_STOP;
1816 if (dwc->has_hibernation && !suspend)
1817 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1819 dwc->pullups_connected = false;
1822 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1825 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1826 reg &= DWC3_DSTS_DEVCTRLHLT;
1827 } while (--timeout && !(!is_on ^ !reg));
1835 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1837 struct dwc3 *dwc = gadget_to_dwc(g);
1838 unsigned long flags;
1844 * Per databook, when we want to stop the gadget, if a control transfer
1845 * is still in process, complete it and get the core into setup phase.
1847 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1848 reinit_completion(&dwc->ep0_in_setup);
1850 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1851 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1853 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1858 spin_lock_irqsave(&dwc->lock, flags);
1859 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1860 spin_unlock_irqrestore(&dwc->lock, flags);
1865 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1869 /* Enable all but Start and End of Frame IRQs */
1870 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1871 DWC3_DEVTEN_EVNTOVERFLOWEN |
1872 DWC3_DEVTEN_CMDCMPLTEN |
1873 DWC3_DEVTEN_ERRTICERREN |
1874 DWC3_DEVTEN_WKUPEVTEN |
1875 DWC3_DEVTEN_CONNECTDONEEN |
1876 DWC3_DEVTEN_USBRSTEN |
1877 DWC3_DEVTEN_DISCONNEVTEN);
1879 if (dwc->revision < DWC3_REVISION_250A)
1880 reg |= DWC3_DEVTEN_ULSTCNGEN;
1882 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1885 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1887 /* mask all interrupts */
1888 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1891 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1892 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1895 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1896 * @dwc: pointer to our context structure
1898 * The following looks like complex but it's actually very simple. In order to
1899 * calculate the number of packets we can burst at once on OUT transfers, we're
1900 * gonna use RxFIFO size.
1902 * To calculate RxFIFO size we need two numbers:
1903 * MDWIDTH = size, in bits, of the internal memory bus
1904 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1906 * Given these two numbers, the formula is simple:
1908 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1910 * 24 bytes is for 3x SETUP packets
1911 * 16 bytes is a clock domain crossing tolerance
1913 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1915 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1922 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1923 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1925 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1926 nump = min_t(u32, nump, 16);
1929 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1930 reg &= ~DWC3_DCFG_NUMP_MASK;
1931 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1932 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1935 static int __dwc3_gadget_start(struct dwc3 *dwc)
1937 struct dwc3_ep *dep;
1942 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1943 * the core supports IMOD, disable it.
1945 if (dwc->imod_interval) {
1946 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1947 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1948 } else if (dwc3_has_imod(dwc)) {
1949 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1953 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1954 * field instead of letting dwc3 itself calculate that automatically.
1956 * This way, we maximize the chances that we'll be able to get several
1957 * bursts of data without going through any sort of endpoint throttling.
1959 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1960 if (dwc3_is_usb31(dwc))
1961 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1963 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1965 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1967 dwc3_gadget_setup_nump(dwc);
1969 /* Start with SuperSpeed Default */
1970 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1973 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1975 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1980 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1982 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1986 /* begin to receive SETUP packets */
1987 dwc->ep0state = EP0_SETUP_PHASE;
1988 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1989 dwc3_ep0_out_start(dwc);
1991 dwc3_gadget_enable_irq(dwc);
1996 __dwc3_gadget_ep_disable(dwc->eps[0]);
2002 static int dwc3_gadget_start(struct usb_gadget *g,
2003 struct usb_gadget_driver *driver)
2005 struct dwc3 *dwc = gadget_to_dwc(g);
2006 unsigned long flags;
2010 irq = dwc->irq_gadget;
2011 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2012 IRQF_SHARED, "dwc3", dwc->ev_buf);
2014 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2019 spin_lock_irqsave(&dwc->lock, flags);
2020 if (dwc->gadget_driver) {
2021 dev_err(dwc->dev, "%s is already bound to %s\n",
2023 dwc->gadget_driver->driver.name);
2028 dwc->gadget_driver = driver;
2030 if (pm_runtime_active(dwc->dev))
2031 __dwc3_gadget_start(dwc);
2033 spin_unlock_irqrestore(&dwc->lock, flags);
2038 spin_unlock_irqrestore(&dwc->lock, flags);
2045 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2047 dwc3_gadget_disable_irq(dwc);
2048 __dwc3_gadget_ep_disable(dwc->eps[0]);
2049 __dwc3_gadget_ep_disable(dwc->eps[1]);
2052 static int dwc3_gadget_stop(struct usb_gadget *g)
2054 struct dwc3 *dwc = gadget_to_dwc(g);
2055 unsigned long flags;
2057 spin_lock_irqsave(&dwc->lock, flags);
2059 if (pm_runtime_suspended(dwc->dev))
2062 __dwc3_gadget_stop(dwc);
2065 dwc->gadget_driver = NULL;
2066 spin_unlock_irqrestore(&dwc->lock, flags);
2068 free_irq(dwc->irq_gadget, dwc->ev_buf);
2073 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2074 enum usb_device_speed speed)
2076 struct dwc3 *dwc = gadget_to_dwc(g);
2077 unsigned long flags;
2080 spin_lock_irqsave(&dwc->lock, flags);
2081 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2082 reg &= ~(DWC3_DCFG_SPEED_MASK);
2085 * WORKAROUND: DWC3 revision < 2.20a have an issue
2086 * which would cause metastability state on Run/Stop
2087 * bit if we try to force the IP to USB2-only mode.
2089 * Because of that, we cannot configure the IP to any
2090 * speed other than the SuperSpeed
2094 * STAR#9000525659: Clock Domain Crossing on DCTL in
2097 if (dwc->revision < DWC3_REVISION_220A &&
2098 !dwc->dis_metastability_quirk) {
2099 reg |= DWC3_DCFG_SUPERSPEED;
2103 reg |= DWC3_DCFG_LOWSPEED;
2105 case USB_SPEED_FULL:
2106 reg |= DWC3_DCFG_FULLSPEED;
2108 case USB_SPEED_HIGH:
2109 reg |= DWC3_DCFG_HIGHSPEED;
2111 case USB_SPEED_SUPER:
2112 reg |= DWC3_DCFG_SUPERSPEED;
2114 case USB_SPEED_SUPER_PLUS:
2115 if (dwc3_is_usb31(dwc))
2116 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2118 reg |= DWC3_DCFG_SUPERSPEED;
2121 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2123 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2124 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2126 reg |= DWC3_DCFG_SUPERSPEED;
2129 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2131 spin_unlock_irqrestore(&dwc->lock, flags);
2134 static const struct usb_gadget_ops dwc3_gadget_ops = {
2135 .get_frame = dwc3_gadget_get_frame,
2136 .wakeup = dwc3_gadget_wakeup,
2137 .set_selfpowered = dwc3_gadget_set_selfpowered,
2138 .pullup = dwc3_gadget_pullup,
2139 .udc_start = dwc3_gadget_start,
2140 .udc_stop = dwc3_gadget_stop,
2141 .udc_set_speed = dwc3_gadget_set_speed,
2144 /* -------------------------------------------------------------------------- */
2146 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2148 struct dwc3 *dwc = dep->dwc;
2150 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2151 dep->endpoint.maxburst = 1;
2152 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2153 if (!dep->direction)
2154 dwc->gadget.ep0 = &dep->endpoint;
2156 dep->endpoint.caps.type_control = true;
2161 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2163 struct dwc3 *dwc = dep->dwc;
2168 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2169 /* MDWIDTH is represented in bits, we need it in bytes */
2172 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2173 if (dwc3_is_usb31(dwc))
2174 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2176 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2178 /* FIFO Depth is in MDWDITH bytes. Multiply */
2181 kbytes = size / 1024;
2186 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2187 * internal overhead. We don't really know how these are used,
2188 * but documentation say it exists.
2190 size -= mdwidth * (kbytes + 1);
2193 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2195 dep->endpoint.max_streams = 15;
2196 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2197 list_add_tail(&dep->endpoint.ep_list,
2198 &dwc->gadget.ep_list);
2199 dep->endpoint.caps.type_iso = true;
2200 dep->endpoint.caps.type_bulk = true;
2201 dep->endpoint.caps.type_int = true;
2203 return dwc3_alloc_trb_pool(dep);
2206 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2208 struct dwc3 *dwc = dep->dwc;
2210 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2211 dep->endpoint.max_streams = 15;
2212 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2213 list_add_tail(&dep->endpoint.ep_list,
2214 &dwc->gadget.ep_list);
2215 dep->endpoint.caps.type_iso = true;
2216 dep->endpoint.caps.type_bulk = true;
2217 dep->endpoint.caps.type_int = true;
2219 return dwc3_alloc_trb_pool(dep);
2222 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2224 struct dwc3_ep *dep;
2225 bool direction = epnum & 1;
2227 u8 num = epnum >> 1;
2229 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2234 dep->number = epnum;
2235 dep->direction = direction;
2236 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2237 dwc->eps[epnum] = dep;
2239 dep->start_cmd_status = 0;
2241 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2242 direction ? "in" : "out");
2244 dep->endpoint.name = dep->name;
2246 if (!(dep->number > 1)) {
2247 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2248 dep->endpoint.comp_desc = NULL;
2251 spin_lock_init(&dep->lock);
2254 ret = dwc3_gadget_init_control_endpoint(dep);
2256 ret = dwc3_gadget_init_in_endpoint(dep);
2258 ret = dwc3_gadget_init_out_endpoint(dep);
2263 dep->endpoint.caps.dir_in = direction;
2264 dep->endpoint.caps.dir_out = !direction;
2266 INIT_LIST_HEAD(&dep->pending_list);
2267 INIT_LIST_HEAD(&dep->started_list);
2268 INIT_LIST_HEAD(&dep->cancelled_list);
2273 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2277 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2279 for (epnum = 0; epnum < total; epnum++) {
2282 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2290 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2292 struct dwc3_ep *dep;
2295 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2296 dep = dwc->eps[epnum];
2300 * Physical endpoints 0 and 1 are special; they form the
2301 * bi-directional USB endpoint 0.
2303 * For those two physical endpoints, we don't allocate a TRB
2304 * pool nor do we add them the endpoints list. Due to that, we
2305 * shouldn't do these two operations otherwise we would end up
2306 * with all sorts of bugs when removing dwc3.ko.
2308 if (epnum != 0 && epnum != 1) {
2309 dwc3_free_trb_pool(dep);
2310 list_del(&dep->endpoint.ep_list);
2317 /* -------------------------------------------------------------------------- */
2319 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2320 struct dwc3_request *req, struct dwc3_trb *trb,
2321 const struct dwc3_event_depevt *event, int status, int chain)
2325 dwc3_ep_inc_deq(dep);
2327 trace_dwc3_complete_trb(dep, trb);
2331 * If we're in the middle of series of chained TRBs and we
2332 * receive a short transfer along the way, DWC3 will skip
2333 * through all TRBs including the last TRB in the chain (the
2334 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2335 * bit and SW has to do it manually.
2337 * We're going to do that here to avoid problems of HW trying
2338 * to use bogus TRBs for transfers.
2340 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2341 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2344 * For isochronous transfers, the first TRB in a service interval must
2345 * have the Isoc-First type. Track and report its interval frame number.
2347 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2348 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2349 unsigned int frame_number;
2351 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2352 frame_number &= ~(dep->interval - 1);
2353 req->request.frame_number = frame_number;
2357 * If we're dealing with unaligned size OUT transfer, we will be left
2358 * with one TRB pending in the ring. We need to manually clear HWO bit
2362 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2363 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2367 count = trb->size & DWC3_TRB_SIZE_MASK;
2368 req->remaining += count;
2370 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2373 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2376 if (event->status & DEPEVT_STATUS_IOC)
2382 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2383 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2386 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2387 struct scatterlist *sg = req->sg;
2388 struct scatterlist *s;
2389 unsigned int pending = req->num_pending_sgs;
2393 for_each_sg(sg, s, pending, i) {
2394 trb = &dep->trb_pool[dep->trb_dequeue];
2396 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2399 req->sg = sg_next(s);
2400 req->num_pending_sgs--;
2402 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2403 trb, event, status, true);
2411 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2412 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2415 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2417 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2418 event, status, false);
2421 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2423 return req->request.actual == req->request.length;
2426 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2427 const struct dwc3_event_depevt *event,
2428 struct dwc3_request *req, int status)
2432 if (req->num_pending_sgs)
2433 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2436 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2439 if (req->needs_extra_trb) {
2440 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2442 req->needs_extra_trb = false;
2445 req->request.actual = req->request.length - req->remaining;
2447 if (!dwc3_gadget_ep_request_completed(req) &&
2448 req->num_pending_sgs) {
2449 __dwc3_gadget_kick_transfer(dep);
2453 dwc3_gadget_giveback(dep, req, status);
2459 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2460 const struct dwc3_event_depevt *event, int status)
2462 struct dwc3_request *req;
2463 struct dwc3_request *tmp;
2465 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2468 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2475 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2476 const struct dwc3_event_depevt *event)
2478 dep->frame_number = event->parameters;
2481 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2482 const struct dwc3_event_depevt *event)
2484 struct dwc3 *dwc = dep->dwc;
2485 unsigned status = 0;
2488 dwc3_gadget_endpoint_frame_from_event(dep, event);
2490 if (event->status & DEPEVT_STATUS_BUSERR)
2491 status = -ECONNRESET;
2493 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2496 if (list_empty(&dep->started_list))
2500 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2503 dwc3_stop_active_transfer(dep, true);
2504 dep->flags = DWC3_EP_ENABLED;
2508 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2509 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2511 if (dwc->revision < DWC3_REVISION_183A) {
2515 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2518 if (!(dep->flags & DWC3_EP_ENABLED))
2521 if (!list_empty(&dep->started_list))
2525 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2527 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2533 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2534 const struct dwc3_event_depevt *event)
2536 dwc3_gadget_endpoint_frame_from_event(dep, event);
2537 (void) __dwc3_gadget_start_isoc(dep);
2540 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2541 const struct dwc3_event_depevt *event)
2543 struct dwc3_ep *dep;
2544 u8 epnum = event->endpoint_number;
2547 dep = dwc->eps[epnum];
2549 if (!(dep->flags & DWC3_EP_ENABLED)) {
2550 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2553 /* Handle only EPCMDCMPLT when EP disabled */
2554 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2558 if (epnum == 0 || epnum == 1) {
2559 dwc3_ep0_interrupt(dwc, event);
2563 switch (event->endpoint_event) {
2564 case DWC3_DEPEVT_XFERINPROGRESS:
2565 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2567 case DWC3_DEPEVT_XFERNOTREADY:
2568 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2570 case DWC3_DEPEVT_EPCMDCMPLT:
2571 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2573 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2574 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2575 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2578 case DWC3_DEPEVT_STREAMEVT:
2579 case DWC3_DEPEVT_XFERCOMPLETE:
2580 case DWC3_DEPEVT_RXTXFIFOEVT:
2585 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2587 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2588 spin_unlock(&dwc->lock);
2589 dwc->gadget_driver->disconnect(&dwc->gadget);
2590 spin_lock(&dwc->lock);
2594 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2596 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2597 spin_unlock(&dwc->lock);
2598 dwc->gadget_driver->suspend(&dwc->gadget);
2599 spin_lock(&dwc->lock);
2603 static void dwc3_resume_gadget(struct dwc3 *dwc)
2605 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2606 spin_unlock(&dwc->lock);
2607 dwc->gadget_driver->resume(&dwc->gadget);
2608 spin_lock(&dwc->lock);
2612 static void dwc3_reset_gadget(struct dwc3 *dwc)
2614 if (!dwc->gadget_driver)
2617 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2618 spin_unlock(&dwc->lock);
2619 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2620 spin_lock(&dwc->lock);
2624 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2626 struct dwc3 *dwc = dep->dwc;
2627 struct dwc3_gadget_ep_cmd_params params;
2631 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2632 !dep->resource_index)
2636 * NOTICE: We are violating what the Databook says about the
2637 * EndTransfer command. Ideally we would _always_ wait for the
2638 * EndTransfer Command Completion IRQ, but that's causing too
2639 * much trouble synchronizing between us and gadget driver.
2641 * We have discussed this with the IP Provider and it was
2642 * suggested to giveback all requests here, but give HW some
2643 * extra time to synchronize with the interconnect. We're using
2644 * an arbitrary 100us delay for that.
2646 * Note also that a similar handling was tested by Synopsys
2647 * (thanks a lot Paul) and nothing bad has come out of it.
2648 * In short, what we're doing is:
2650 * - Issue EndTransfer WITH CMDIOC bit set
2653 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2654 * supports a mode to work around the above limitation. The
2655 * software can poll the CMDACT bit in the DEPCMD register
2656 * after issuing a EndTransfer command. This mode is enabled
2657 * by writing GUCTL2[14]. This polling is already done in the
2658 * dwc3_send_gadget_ep_cmd() function so if the mode is
2659 * enabled, the EndTransfer command will have completed upon
2660 * returning from this function and we don't need to delay for
2663 * This mode is NOT available on the DWC_usb31 IP.
2666 cmd = DWC3_DEPCMD_ENDTRANSFER;
2667 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2668 cmd |= DWC3_DEPCMD_CMDIOC;
2669 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2670 memset(¶ms, 0, sizeof(params));
2671 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2673 dep->resource_index = 0;
2675 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2676 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2681 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2685 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2686 struct dwc3_ep *dep;
2689 dep = dwc->eps[epnum];
2693 if (!(dep->flags & DWC3_EP_STALL))
2696 dep->flags &= ~DWC3_EP_STALL;
2698 ret = dwc3_send_clear_stall_ep_cmd(dep);
2703 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2707 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2708 reg &= ~DWC3_DCTL_INITU1ENA;
2709 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2711 reg &= ~DWC3_DCTL_INITU2ENA;
2712 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2714 dwc3_disconnect_gadget(dwc);
2716 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2717 dwc->setup_packet_pending = false;
2718 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2720 dwc->connected = false;
2723 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2727 dwc->connected = true;
2730 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2731 * would cause a missing Disconnect Event if there's a
2732 * pending Setup Packet in the FIFO.
2734 * There's no suggested workaround on the official Bug
2735 * report, which states that "unless the driver/application
2736 * is doing any special handling of a disconnect event,
2737 * there is no functional issue".
2739 * Unfortunately, it turns out that we _do_ some special
2740 * handling of a disconnect event, namely complete all
2741 * pending transfers, notify gadget driver of the
2742 * disconnection, and so on.
2744 * Our suggested workaround is to follow the Disconnect
2745 * Event steps here, instead, based on a setup_packet_pending
2746 * flag. Such flag gets set whenever we have a SETUP_PENDING
2747 * status for EP0 TRBs and gets cleared on XferComplete for the
2752 * STAR#9000466709: RTL: Device : Disconnect event not
2753 * generated if setup packet pending in FIFO
2755 if (dwc->revision < DWC3_REVISION_188A) {
2756 if (dwc->setup_packet_pending)
2757 dwc3_gadget_disconnect_interrupt(dwc);
2760 dwc3_reset_gadget(dwc);
2762 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2763 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2764 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2765 dwc->test_mode = false;
2766 dwc3_clear_stall_all_ep(dwc);
2768 /* Reset device address to zero */
2769 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2770 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2771 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2774 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2776 struct dwc3_ep *dep;
2781 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2782 speed = reg & DWC3_DSTS_CONNECTSPD;
2786 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2787 * each time on Connect Done.
2789 * Currently we always use the reset value. If any platform
2790 * wants to set this to a different value, we need to add a
2791 * setting and update GCTL.RAMCLKSEL here.
2795 case DWC3_DSTS_SUPERSPEED_PLUS:
2796 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2797 dwc->gadget.ep0->maxpacket = 512;
2798 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2800 case DWC3_DSTS_SUPERSPEED:
2802 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2803 * would cause a missing USB3 Reset event.
2805 * In such situations, we should force a USB3 Reset
2806 * event by calling our dwc3_gadget_reset_interrupt()
2811 * STAR#9000483510: RTL: SS : USB3 reset event may
2812 * not be generated always when the link enters poll
2814 if (dwc->revision < DWC3_REVISION_190A)
2815 dwc3_gadget_reset_interrupt(dwc);
2817 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2818 dwc->gadget.ep0->maxpacket = 512;
2819 dwc->gadget.speed = USB_SPEED_SUPER;
2821 case DWC3_DSTS_HIGHSPEED:
2822 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2823 dwc->gadget.ep0->maxpacket = 64;
2824 dwc->gadget.speed = USB_SPEED_HIGH;
2826 case DWC3_DSTS_FULLSPEED:
2827 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2828 dwc->gadget.ep0->maxpacket = 64;
2829 dwc->gadget.speed = USB_SPEED_FULL;
2831 case DWC3_DSTS_LOWSPEED:
2832 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2833 dwc->gadget.ep0->maxpacket = 8;
2834 dwc->gadget.speed = USB_SPEED_LOW;
2838 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2840 /* Enable USB2 LPM Capability */
2842 if ((dwc->revision > DWC3_REVISION_194A) &&
2843 (speed != DWC3_DSTS_SUPERSPEED) &&
2844 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2845 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2846 reg |= DWC3_DCFG_LPM_CAP;
2847 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2849 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2850 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2852 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2855 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2856 * DCFG.LPMCap is set, core responses with an ACK and the
2857 * BESL value in the LPM token is less than or equal to LPM
2860 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2861 && dwc->has_lpm_erratum,
2862 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2864 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2865 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2867 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2869 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2870 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2871 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2875 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2877 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2882 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2884 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2889 * Configure PHY via GUSB3PIPECTLn if required.
2891 * Update GTXFIFOSIZn
2893 * In both cases reset values should be sufficient.
2897 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2900 * TODO take core out of low power mode when that's
2904 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2905 spin_unlock(&dwc->lock);
2906 dwc->gadget_driver->resume(&dwc->gadget);
2907 spin_lock(&dwc->lock);
2911 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2912 unsigned int evtinfo)
2914 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2915 unsigned int pwropt;
2918 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2919 * Hibernation mode enabled which would show up when device detects
2920 * host-initiated U3 exit.
2922 * In that case, device will generate a Link State Change Interrupt
2923 * from U3 to RESUME which is only necessary if Hibernation is
2926 * There are no functional changes due to such spurious event and we
2927 * just need to ignore it.
2931 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2934 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2935 if ((dwc->revision < DWC3_REVISION_250A) &&
2936 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2937 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2938 (next == DWC3_LINK_STATE_RESUME)) {
2944 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2945 * on the link partner, the USB session might do multiple entry/exit
2946 * of low power states before a transfer takes place.
2948 * Due to this problem, we might experience lower throughput. The
2949 * suggested workaround is to disable DCTL[12:9] bits if we're
2950 * transitioning from U1/U2 to U0 and enable those bits again
2951 * after a transfer completes and there are no pending transfers
2952 * on any of the enabled endpoints.
2954 * This is the first half of that workaround.
2958 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2959 * core send LGO_Ux entering U0
2961 if (dwc->revision < DWC3_REVISION_183A) {
2962 if (next == DWC3_LINK_STATE_U0) {
2966 switch (dwc->link_state) {
2967 case DWC3_LINK_STATE_U1:
2968 case DWC3_LINK_STATE_U2:
2969 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2970 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2971 | DWC3_DCTL_ACCEPTU2ENA
2972 | DWC3_DCTL_INITU1ENA
2973 | DWC3_DCTL_ACCEPTU1ENA);
2976 dwc->u1u2 = reg & u1u2;
2980 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2990 case DWC3_LINK_STATE_U1:
2991 if (dwc->speed == USB_SPEED_SUPER)
2992 dwc3_suspend_gadget(dwc);
2994 case DWC3_LINK_STATE_U2:
2995 case DWC3_LINK_STATE_U3:
2996 dwc3_suspend_gadget(dwc);
2998 case DWC3_LINK_STATE_RESUME:
2999 dwc3_resume_gadget(dwc);
3006 dwc->link_state = next;
3009 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3010 unsigned int evtinfo)
3012 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3014 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3015 dwc3_suspend_gadget(dwc);
3017 dwc->link_state = next;
3020 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3021 unsigned int evtinfo)
3023 unsigned int is_ss = evtinfo & BIT(4);
3026 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3027 * have a known issue which can cause USB CV TD.9.23 to fail
3030 * Because of this issue, core could generate bogus hibernation
3031 * events which SW needs to ignore.
3035 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3036 * Device Fallback from SuperSpeed
3038 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3041 /* enter hibernation here */
3044 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3045 const struct dwc3_event_devt *event)
3047 switch (event->type) {
3048 case DWC3_DEVICE_EVENT_DISCONNECT:
3049 dwc3_gadget_disconnect_interrupt(dwc);
3051 case DWC3_DEVICE_EVENT_RESET:
3052 dwc3_gadget_reset_interrupt(dwc);
3054 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3055 dwc3_gadget_conndone_interrupt(dwc);
3057 case DWC3_DEVICE_EVENT_WAKEUP:
3058 dwc3_gadget_wakeup_interrupt(dwc);
3060 case DWC3_DEVICE_EVENT_HIBER_REQ:
3061 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3062 "unexpected hibernation event\n"))
3065 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3067 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3068 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3070 case DWC3_DEVICE_EVENT_EOPF:
3071 /* It changed to be suspend event for version 2.30a and above */
3072 if (dwc->revision >= DWC3_REVISION_230A) {
3074 * Ignore suspend event until the gadget enters into
3075 * USB_STATE_CONFIGURED state.
3077 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3078 dwc3_gadget_suspend_interrupt(dwc,
3082 case DWC3_DEVICE_EVENT_SOF:
3083 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3084 case DWC3_DEVICE_EVENT_CMD_CMPL:
3085 case DWC3_DEVICE_EVENT_OVERFLOW:
3088 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3092 static void dwc3_process_event_entry(struct dwc3 *dwc,
3093 const union dwc3_event *event)
3095 trace_dwc3_event(event->raw, dwc);
3097 if (!event->type.is_devspec)
3098 dwc3_endpoint_interrupt(dwc, &event->depevt);
3099 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3100 dwc3_gadget_interrupt(dwc, &event->devt);
3102 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3105 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3107 struct dwc3 *dwc = evt->dwc;
3108 irqreturn_t ret = IRQ_NONE;
3114 if (!(evt->flags & DWC3_EVENT_PENDING))
3118 union dwc3_event event;
3120 event.raw = *(u32 *) (evt->cache + evt->lpos);
3122 dwc3_process_event_entry(dwc, &event);
3125 * FIXME we wrap around correctly to the next entry as
3126 * almost all entries are 4 bytes in size. There is one
3127 * entry which has 12 bytes which is a regular entry
3128 * followed by 8 bytes data. ATM I don't know how
3129 * things are organized if we get next to the a
3130 * boundary so I worry about that once we try to handle
3133 evt->lpos = (evt->lpos + 4) % evt->length;
3138 evt->flags &= ~DWC3_EVENT_PENDING;
3141 /* Unmask interrupt */
3142 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3143 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3144 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3146 if (dwc->imod_interval) {
3147 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3148 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3154 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3156 struct dwc3_event_buffer *evt = _evt;
3157 struct dwc3 *dwc = evt->dwc;
3158 unsigned long flags;
3159 irqreturn_t ret = IRQ_NONE;
3161 spin_lock_irqsave(&dwc->lock, flags);
3162 ret = dwc3_process_event_buf(evt);
3163 spin_unlock_irqrestore(&dwc->lock, flags);
3168 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3170 struct dwc3 *dwc = evt->dwc;
3175 if (pm_runtime_suspended(dwc->dev)) {
3176 pm_runtime_get(dwc->dev);
3177 disable_irq_nosync(dwc->irq_gadget);
3178 dwc->pending_events = true;
3183 * With PCIe legacy interrupt, test shows that top-half irq handler can
3184 * be called again after HW interrupt deassertion. Check if bottom-half
3185 * irq event handler completes before caching new event to prevent
3188 if (evt->flags & DWC3_EVENT_PENDING)
3191 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3192 count &= DWC3_GEVNTCOUNT_MASK;
3197 evt->flags |= DWC3_EVENT_PENDING;
3199 /* Mask interrupt */
3200 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3201 reg |= DWC3_GEVNTSIZ_INTMASK;
3202 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3204 amount = min(count, evt->length - evt->lpos);
3205 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3208 memcpy(evt->cache, evt->buf, count - amount);
3210 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3212 return IRQ_WAKE_THREAD;
3215 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3217 struct dwc3_event_buffer *evt = _evt;
3219 return dwc3_check_event_buf(evt);
3222 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3224 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3227 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3231 if (irq == -EPROBE_DEFER)
3234 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3238 if (irq == -EPROBE_DEFER)
3241 irq = platform_get_irq(dwc3_pdev, 0);
3245 if (irq != -EPROBE_DEFER)
3246 dev_err(dwc->dev, "missing peripheral IRQ\n");
3256 * dwc3_gadget_init - initializes gadget related registers
3257 * @dwc: pointer to our controller context structure
3259 * Returns 0 on success otherwise negative errno.
3261 int dwc3_gadget_init(struct dwc3 *dwc)
3266 irq = dwc3_gadget_get_irq(dwc);
3272 dwc->irq_gadget = irq;
3274 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3275 sizeof(*dwc->ep0_trb) * 2,
3276 &dwc->ep0_trb_addr, GFP_KERNEL);
3277 if (!dwc->ep0_trb) {
3278 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3283 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3284 if (!dwc->setup_buf) {
3289 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3290 &dwc->bounce_addr, GFP_KERNEL);
3296 init_completion(&dwc->ep0_in_setup);
3298 dwc->gadget.ops = &dwc3_gadget_ops;
3299 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3300 dwc->gadget.sg_supported = true;
3301 dwc->gadget.name = "dwc3-gadget";
3302 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3305 * FIXME We might be setting max_speed to <SUPER, however versions
3306 * <2.20a of dwc3 have an issue with metastability (documented
3307 * elsewhere in this driver) which tells us we can't set max speed to
3308 * anything lower than SUPER.
3310 * Because gadget.max_speed is only used by composite.c and function
3311 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3312 * to happen so we avoid sending SuperSpeed Capability descriptor
3313 * together with our BOS descriptor as that could confuse host into
3314 * thinking we can handle super speed.
3316 * Note that, in fact, we won't even support GetBOS requests when speed
3317 * is less than super speed because we don't have means, yet, to tell
3318 * composite.c that we are USB 2.0 + LPM ECN.
3320 if (dwc->revision < DWC3_REVISION_220A &&
3321 !dwc->dis_metastability_quirk)
3322 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3325 dwc->gadget.max_speed = dwc->maximum_speed;
3328 * REVISIT: Here we should clear all pending IRQs to be
3329 * sure we're starting from a well known location.
3332 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3336 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3338 dev_err(dwc->dev, "failed to register udc\n");
3345 dwc3_gadget_free_endpoints(dwc);
3348 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3352 kfree(dwc->setup_buf);
3355 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3356 dwc->ep0_trb, dwc->ep0_trb_addr);
3362 /* -------------------------------------------------------------------------- */
3364 void dwc3_gadget_exit(struct dwc3 *dwc)
3366 usb_del_gadget_udc(&dwc->gadget);
3367 dwc3_gadget_free_endpoints(dwc);
3368 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3370 kfree(dwc->setup_buf);
3371 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3372 dwc->ep0_trb, dwc->ep0_trb_addr);
3375 int dwc3_gadget_suspend(struct dwc3 *dwc)
3377 if (!dwc->gadget_driver)
3380 dwc3_gadget_run_stop(dwc, false, false);
3381 dwc3_disconnect_gadget(dwc);
3382 __dwc3_gadget_stop(dwc);
3384 synchronize_irq(dwc->irq_gadget);
3389 int dwc3_gadget_resume(struct dwc3 *dwc)
3393 if (!dwc->gadget_driver)
3396 ret = __dwc3_gadget_start(dwc);
3400 ret = dwc3_gadget_run_stop(dwc, true, false);
3407 __dwc3_gadget_stop(dwc);
3413 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3415 if (dwc->pending_events) {
3416 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3417 dwc->pending_events = false;
3418 enable_irq(dwc->irq_gadget);