drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include <linux/usb/ch9.h>
  23 #include <linux/usb/gadget.h>
  24
  25 #include "debug.h"
  26 #include "core.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 /**
  31  * dwc3_gadget_set_test_mode - enables usb2 test modes
  32  * @dwc: pointer to our context structure
  33  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  34  *
  35  * Caller should take care of locking. This function will return 0 on
  36  * success or -EINVAL if wrong Test Selector is passed.
  37  */
  38 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  39 {
  40         u32             reg;
  41
  42         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  43         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  44
  45         switch (mode) {
  46         case TEST_J:
  47         case TEST_K:
  48         case TEST_SE0_NAK:
  49         case TEST_PACKET:
  50         case TEST_FORCE_EN:
  51                 reg |= mode << 1;
  52                 break;
  53         default:
  54                 return -EINVAL;
  55         }
  56
  57         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  58
  59         return 0;
  60 }
  61
  62 /**
  63  * dwc3_gadget_get_link_state - gets current state of usb link
  64  * @dwc: pointer to our context structure
  65  *
  66  * Caller should take care of locking. This function will
  67  * return the link state on success (>= 0) or -ETIMEDOUT.
  68  */
  69 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  70 {
  71         u32             reg;
  72
  73         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  74
  75         return DWC3_DSTS_USBLNKST(reg);
  76 }
  77
  78 /**
  79  * dwc3_gadget_set_link_state - sets usb link to a particular state
  80  * @dwc: pointer to our context structure
  81  * @state: the state to put link into
  82  *
  83  * Caller should take care of locking. This function will
  84  * return 0 on success or -ETIMEDOUT.
  85  */
  86 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  87 {
  88         int             retries = 10000;
  89         u32             reg;
  90
  91         /*
  92          * Wait until device controller is ready. Only applies to 1.94a and
  93          * later RTL.
  94          */
  95         if (dwc->revision >= DWC3_REVISION_194A) {
  96                 while (--retries) {
  97                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  98                         if (reg & DWC3_DSTS_DCNRD)
  99                                 udelay(5);
 100                         else
 101                                 break;
 102                 }
 103
 104                 if (retries <= 0)
 105                         return -ETIMEDOUT;
 106         }
 107
 108         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 109         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 110
 111         /* set requested state */
 112         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 113         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 114
 115         /*
 116          * The following code is racy when called from dwc3_gadget_wakeup,
 117          * and is not needed, at least on newer versions
 118          */
 119         if (dwc->revision >= DWC3_REVISION_194A)
 120                 return 0;
 121
 122         /* wait for a change in DSTS */
 123         retries = 10000;
 124         while (--retries) {
 125                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 126
 127                 if (DWC3_DSTS_USBLNKST(reg) == state)
 128                         return 0;
 129
 130                 udelay(5);
 131         }
 132
 133         return -ETIMEDOUT;
 134 }
 135
 136 /**
 137  * dwc3_ep_inc_trb - increment a trb index.
 138  * @index: Pointer to the TRB index to increment.
 139  *
 140  * The index should never point to the link TRB. After incrementing,
 141  * if it is point to the link TRB, wrap around to the beginning. The
 142  * link TRB is always at the last TRB entry.
 143  */
 144 static void dwc3_ep_inc_trb(u8 *index)
 145 {
 146         (*index)++;
 147         if (*index == (DWC3_TRB_NUM - 1))
 148                 *index = 0;
 149 }
 150
 151 /**
 152  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 153  * @dep: The endpoint whose enqueue pointer we're incrementing
 154  */
 155 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 156 {
 157         dwc3_ep_inc_trb(&dep->trb_enqueue);
 158 }
 159
 160 /**
 161  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 162  * @dep: The endpoint whose enqueue pointer we're incrementing
 163  */
 164 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 165 {
 166         dwc3_ep_inc_trb(&dep->trb_dequeue);
 167 }
 168
 169 /**
 170  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 171  * @dep: The endpoint to whom the request belongs to
 172  * @req: The request we're giving back
 173  * @status: completion code for the request
 174  *
 175  * Must be called with controller's lock held and interrupts disabled. This
 176  * function will unmap @req and call its ->complete() callback to notify upper
 177  * layers that it has completed.
 178  */
 179 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 180                 int status)
 181 {
 182         struct dwc3                     *dwc = dep->dwc;
 183
 184         req->started = false;
 185         list_del(&req->list);
 186         req->remaining = 0;
 187
 188         if (req->request.status == -EINPROGRESS)
 189                 req->request.status = status;
 190
 191         if (req->trb)
 192                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
 193                                                 &req->request, req->direction);
 194
 195         req->trb = NULL;
 196
 197         trace_dwc3_gadget_giveback(req);
 198
 199         spin_unlock(&dwc->lock);
 200         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 201         spin_lock(&dwc->lock);
 202
 203         if (dep->number > 1)
 204                 pm_runtime_put(dwc->dev);
 205 }
 206
 207 /**
 208  * dwc3_send_gadget_generic_command - issue a generic command for the controller
 209  * @dwc: pointer to the controller context
 210  * @cmd: the command to be issued
 211  * @param: command parameter
 212  *
 213  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 214  * and wait for its completion.
 215  */
 216 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 217 {
 218         u32             timeout = 500;
 219         int             status = 0;
 220         int             ret = 0;
 221         u32             reg;
 222
 223         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 224         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 225
 226         do {
 227                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 228                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 229                         status = DWC3_DGCMD_STATUS(reg);
 230                         if (status)
 231                                 ret = -EINVAL;
 232                         break;
 233                 }
 234         } while (--timeout);
 235
 236         if (!timeout) {
 237                 ret = -ETIMEDOUT;
 238                 status = -ETIMEDOUT;
 239         }
 240
 241         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 242
 243         return ret;
 244 }
 245
 246 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 247
 248 /**
 249  * dwc3_send_gadget_ep_cmd - issue an endpoint command
 250  * @dep: the endpoint to which the command is going to be issued
 251  * @cmd: the command to be issued
 252  * @params: parameters to the command
 253  *
 254  * Caller should handle locking. This function will issue @cmd with given
 255  * @params to @dep and wait for its completion.
 256  */
 257 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 258                 struct dwc3_gadget_ep_cmd_params *params)
 259 {
 260         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 261         struct dwc3             *dwc = dep->dwc;
 262         u32                     timeout = 1000;
 263         u32                     reg;
 264
 265         int                     cmd_status = 0;
 266         int                     susphy = false;
 267         int                     ret = -EINVAL;
 268
 269         /*
 270          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 271          * we're issuing an endpoint command, we must check if
 272          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 273          *
 274          * We will also set SUSPHY bit to what it was before returning as stated
 275          * by the same section on Synopsys databook.
 276          */
 277         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 278                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 279                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 280                         susphy = true;
 281                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 282                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 283                 }
 284         }
 285
 286         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 287                 int             needs_wakeup;
 288
 289                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 290                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 291                                 dwc->link_state == DWC3_LINK_STATE_U3);
 292
 293                 if (unlikely(needs_wakeup)) {
 294                         ret = __dwc3_gadget_wakeup(dwc);
 295                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 296                                         ret);
 297                 }
 298         }
 299
 300         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 301         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 302         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 303
 304         /*
 305          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 306          * not relying on XferNotReady, we can make use of a special "No
 307          * Response Update Transfer" command where we should clear both CmdAct
 308          * and CmdIOC bits.
 309          *
 310          * With this, we don't need to wait for command completion and can
 311          * straight away issue further commands to the endpoint.
 312          *
 313          * NOTICE: We're making an assumption that control endpoints will never
 314          * make use of Update Transfer command. This is a safe assumption
 315          * because we can never have more than one request at a time with
 316          * Control Endpoints. If anybody changes that assumption, this chunk
 317          * needs to be updated accordingly.
 318          */
 319         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 320                         !usb_endpoint_xfer_isoc(desc))
 321                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 322         else
 323                 cmd |= DWC3_DEPCMD_CMDACT;
 324
 325         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 326         do {
 327                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 328                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 329                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 330
 331                         switch (cmd_status) {
 332                         case 0:
 333                                 ret = 0;
 334                                 break;
 335                         case DEPEVT_TRANSFER_NO_RESOURCE:
 336                                 ret = -EINVAL;
 337                                 break;
 338                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 339                                 /*
 340                                  * SW issues START TRANSFER command to
 341                                  * isochronous ep with future frame interval. If
 342                                  * future interval time has already passed when
 343                                  * core receives the command, it will respond
 344                                  * with an error status of 'Bus Expiry'.
 345                                  *
 346                                  * Instead of always returning -EINVAL, let's
 347                                  * give a hint to the gadget driver that this is
 348                                  * the case by returning -EAGAIN.
 349                                  */
 350                                 ret = -EAGAIN;
 351                                 break;
 352                         default:
 353                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 354                         }
 355
 356                         break;
 357                 }
 358         } while (--timeout);
 359
 360         if (timeout == 0) {
 361                 ret = -ETIMEDOUT;
 362                 cmd_status = -ETIMEDOUT;
 363         }
 364
 365         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 366
 367         if (ret == 0) {
 368                 switch (DWC3_DEPCMD_CMD(cmd)) {
 369                 case DWC3_DEPCMD_STARTTRANSFER:
 370                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 371                         break;
 372                 case DWC3_DEPCMD_ENDTRANSFER:
 373                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 374                         break;
 375                 default:
 376                         /* nothing */
 377                         break;
 378                 }
 379         }
 380
 381         if (unlikely(susphy)) {
 382                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 383                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 384                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 385         }
 386
 387         return ret;
 388 }
 389
 390 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 391 {
 392         struct dwc3 *dwc = dep->dwc;
 393         struct dwc3_gadget_ep_cmd_params params;
 394         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 395
 396         /*
 397          * As of core revision 2.60a the recommended programming model
 398          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 399          * command for IN endpoints. This is to prevent an issue where
 400          * some (non-compliant) hosts may not send ACK TPs for pending
 401          * IN transfers due to a mishandled error condition. Synopsys
 402          * STAR 9000614252.
 403          */
 404         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
 405             (dwc->gadget.speed >= USB_SPEED_SUPER))
 406                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 407
 408         memset(&params, 0, sizeof(params));
 409
 410         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 411 }
 412
 413 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 414                 struct dwc3_trb *trb)
 415 {
 416         u32             offset = (char *) trb - (char *) dep->trb_pool;
 417
 418         return dep->trb_pool_dma + offset;
 419 }
 420
 421 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 422 {
 423         struct dwc3             *dwc = dep->dwc;
 424
 425         if (dep->trb_pool)
 426                 return 0;
 427
 428         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 429                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 430                         &dep->trb_pool_dma, GFP_KERNEL);
 431         if (!dep->trb_pool) {
 432                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 433                                 dep->name);
 434                 return -ENOMEM;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 441 {
 442         struct dwc3             *dwc = dep->dwc;
 443
 444         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 445                         dep->trb_pool, dep->trb_pool_dma);
 446
 447         dep->trb_pool = NULL;
 448         dep->trb_pool_dma = 0;
 449 }
 450
 451 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 452
 453 /**
 454  * dwc3_gadget_start_config - configure ep resources
 455  * @dwc: pointer to our controller context structure
 456  * @dep: endpoint that is being enabled
 457  *
 458  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
 459  * completion, it will set Transfer Resource for all available endpoints.
 460  *
 461  * The assignment of transfer resources cannot perfectly follow the data book
 462  * due to the fact that the controller driver does not have all knowledge of the
 463  * configuration in advance. It is given this information piecemeal by the
 464  * composite gadget framework after every SET_CONFIGURATION and
 465  * SET_INTERFACE. Trying to follow the databook programming model in this
 466  * scenario can cause errors. For two reasons:
 467  *
 468  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
 469  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
 470  * incorrect in the scenario of multiple interfaces.
 471  *
 472  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
 473  * endpoint on alt setting (8.1.6).
 474  *
 475  * The following simplified method is used instead:
 476  *
 477  * All hardware endpoints can be assigned a transfer resource and this setting
 478  * will stay persistent until either a core reset or hibernation. So whenever we
 479  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
 480  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
 481  * guaranteed that there are as many transfer resources as endpoints.
 482  *
 483  * This function is called for each endpoint when it is being enabled but is
 484  * triggered only when called for EP0-out, which always happens first, and which
 485  * should only happen in one of the above conditions.
 486  */
 487 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 488 {
 489         struct dwc3_gadget_ep_cmd_params params;
 490         u32                     cmd;
 491         int                     i;
 492         int                     ret;
 493
 494         if (dep->number)
 495                 return 0;
 496
 497         memset(&params, 0x00, sizeof(params));
 498         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 499
 500         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 501         if (ret)
 502                 return ret;
 503
 504         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 505                 struct dwc3_ep *dep = dwc->eps[i];
 506
 507                 if (!dep)
 508                         continue;
 509
 510                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 511                 if (ret)
 512                         return ret;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 519                 bool modify, bool restore)
 520 {
 521         const struct usb_ss_ep_comp_descriptor *comp_desc;
 522         const struct usb_endpoint_descriptor *desc;
 523         struct dwc3_gadget_ep_cmd_params params;
 524
 525         if (dev_WARN_ONCE(dwc->dev, modify && restore,
 526                                         "Can't modify and restore\n"))
 527                 return -EINVAL;
 528
 529         comp_desc = dep->endpoint.comp_desc;
 530         desc = dep->endpoint.desc;
 531
 532         memset(&params, 0x00, sizeof(params));
 533
 534         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 535                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 536
 537         /* Burst size is only needed in SuperSpeed mode */
 538         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 539                 u32 burst = dep->endpoint.maxburst;
 540                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 541         }
 542
 543         if (modify) {
 544                 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
 545         } else if (restore) {
 546                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 547                 params.param2 |= dep->saved_state;
 548         } else {
 549                 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
 550         }
 551
 552         if (usb_endpoint_xfer_control(desc))
 553                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 554
 555         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 556                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 557
 558         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 559                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 560                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 561                 dep->stream_capable = true;
 562         }
 563
 564         if (!usb_endpoint_xfer_control(desc))
 565                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 566
 567         /*
 568          * We are doing 1:1 mapping for endpoints, meaning
 569          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 570          * so on. We consider the direction bit as part of the physical
 571          * endpoint number. So USB endpoint 0x81 is 0x03.
 572          */
 573         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 574
 575         /*
 576          * We must use the lower 16 TX FIFOs even though
 577          * HW might have more
 578          */
 579         if (dep->direction)
 580                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 581
 582         if (desc->bInterval) {
 583                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 584                 dep->interval = 1 << (desc->bInterval - 1);
 585         }
 586
 587         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 588 }
 589
 590 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 591 {
 592         struct dwc3_gadget_ep_cmd_params params;
 593
 594         memset(&params, 0x00, sizeof(params));
 595
 596         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 597
 598         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 599                         &params);
 600 }
 601
 602 /**
 603  * __dwc3_gadget_ep_enable - initializes a hw endpoint
 604  * @dep: endpoint to be initialized
 605  * @modify: if true, modify existing endpoint configuration
 606  * @restore: if true, restore endpoint configuration from scratch buffer
 607  *
 608  * Caller should take care of locking. Execute all necessary commands to
 609  * initialize a HW endpoint so it can be used by a gadget driver.
 610  */
 611 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 612                 bool modify, bool restore)
 613 {
 614         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 615         struct dwc3             *dwc = dep->dwc;
 616
 617         u32                     reg;
 618         int                     ret;
 619
 620         if (!(dep->flags & DWC3_EP_ENABLED)) {
 621                 ret = dwc3_gadget_start_config(dwc, dep);
 622                 if (ret)
 623                         return ret;
 624         }
 625
 626         ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
 627         if (ret)
 628                 return ret;
 629
 630         if (!(dep->flags & DWC3_EP_ENABLED)) {
 631                 struct dwc3_trb *trb_st_hw;
 632                 struct dwc3_trb *trb_link;
 633
 634                 dep->type = usb_endpoint_type(desc);
 635                 dep->flags |= DWC3_EP_ENABLED;
 636                 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
 637
 638                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 639                 reg |= DWC3_DALEPENA_EP(dep->number);
 640                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 641
 642                 init_waitqueue_head(&dep->wait_end_transfer);
 643
 644                 if (usb_endpoint_xfer_control(desc))
 645                         goto out;
 646
 647                 /* Initialize the TRB ring */
 648                 dep->trb_dequeue = 0;
 649                 dep->trb_enqueue = 0;
 650                 memset(dep->trb_pool, 0,
 651                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 652
 653                 /* Link TRB. The HWO bit is never reset */
 654                 trb_st_hw = &dep->trb_pool[0];
 655
 656                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 657                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 658                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 659                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 660                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 661         }
 662
 663         /*
 664          * Issue StartTransfer here with no-op TRB so we can always rely on No
 665          * Response Update Transfer command.
 666          */
 667         if (usb_endpoint_xfer_bulk(desc)) {
 668                 struct dwc3_gadget_ep_cmd_params params;
 669                 struct dwc3_trb *trb;
 670                 dma_addr_t trb_dma;
 671                 u32 cmd;
 672
 673                 memset(&params, 0, sizeof(params));
 674                 trb = &dep->trb_pool[0];
 675                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 676
 677                 params.param0 = upper_32_bits(trb_dma);
 678                 params.param1 = lower_32_bits(trb_dma);
 679
 680                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 681
 682                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 683                 if (ret < 0)
 684                         return ret;
 685
 686                 dep->flags |= DWC3_EP_BUSY;
 687
 688                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 689                 WARN_ON_ONCE(!dep->resource_index);
 690         }
 691
 692
 693 out:
 694         trace_dwc3_gadget_ep_enable(dep);
 695
 696         return 0;
 697 }
 698
 699 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 700 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 701 {
 702         struct dwc3_request             *req;
 703
 704         dwc3_stop_active_transfer(dwc, dep->number, true);
 705
 706         /* - giveback all requests to gadget driver */
 707         while (!list_empty(&dep->started_list)) {
 708                 req = next_request(&dep->started_list);
 709
 710                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 711         }
 712
 713         while (!list_empty(&dep->pending_list)) {
 714                 req = next_request(&dep->pending_list);
 715
 716                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 717         }
 718 }
 719
 720 /**
 721  * __dwc3_gadget_ep_disable - disables a hw endpoint
 722  * @dep: the endpoint to disable
 723  *
 724  * This function undoes what __dwc3_gadget_ep_enable did and also removes
 725  * requests which are currently being processed by the hardware and those which
 726  * are not yet scheduled.
 727  *
 728  * Caller should take care of locking.
 729  */
 730 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 731 {
 732         struct dwc3             *dwc = dep->dwc;
 733         u32                     reg;
 734
 735         trace_dwc3_gadget_ep_disable(dep);
 736
 737         dwc3_remove_requests(dwc, dep);
 738
 739         /* make sure HW endpoint isn't stalled */
 740         if (dep->flags & DWC3_EP_STALL)
 741                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 742
 743         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 744         reg &= ~DWC3_DALEPENA_EP(dep->number);
 745         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 746
 747         dep->stream_capable = false;
 748         dep->type = 0;
 749         dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
 750
 751         /* Clear out the ep descriptors for non-ep0 */
 752         if (dep->number > 1) {
 753                 dep->endpoint.comp_desc = NULL;
 754                 dep->endpoint.desc = NULL;
 755         }
 756
 757         return 0;
 758 }
 759
 760 /* -------------------------------------------------------------------------- */
 761
 762 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 763                 const struct usb_endpoint_descriptor *desc)
 764 {
 765         return -EINVAL;
 766 }
 767
 768 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 769 {
 770         return -EINVAL;
 771 }
 772
 773 /* -------------------------------------------------------------------------- */
 774
 775 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 776                 const struct usb_endpoint_descriptor *desc)
 777 {
 778         struct dwc3_ep                  *dep;
 779         struct dwc3                     *dwc;
 780         unsigned long                   flags;
 781         int                             ret;
 782
 783         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 784                 pr_debug("dwc3: invalid parameters\n");
 785                 return -EINVAL;
 786         }
 787
 788         if (!desc->wMaxPacketSize) {
 789                 pr_debug("dwc3: missing wMaxPacketSize\n");
 790                 return -EINVAL;
 791         }
 792
 793         dep = to_dwc3_ep(ep);
 794         dwc = dep->dwc;
 795
 796         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 797                                         "%s is already enabled\n",
 798                                         dep->name))
 799                 return 0;
 800
 801         spin_lock_irqsave(&dwc->lock, flags);
 802         ret = __dwc3_gadget_ep_enable(dep, false, false);
 803         spin_unlock_irqrestore(&dwc->lock, flags);
 804
 805         return ret;
 806 }
 807
 808 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 809 {
 810         struct dwc3_ep                  *dep;
 811         struct dwc3                     *dwc;
 812         unsigned long                   flags;
 813         int                             ret;
 814
 815         if (!ep) {
 816                 pr_debug("dwc3: invalid parameters\n");
 817                 return -EINVAL;
 818         }
 819
 820         dep = to_dwc3_ep(ep);
 821         dwc = dep->dwc;
 822
 823         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 824                                         "%s is already disabled\n",
 825                                         dep->name))
 826                 return 0;
 827
 828         spin_lock_irqsave(&dwc->lock, flags);
 829         ret = __dwc3_gadget_ep_disable(dep);
 830         spin_unlock_irqrestore(&dwc->lock, flags);
 831
 832         return ret;
 833 }
 834
 835 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 836         gfp_t gfp_flags)
 837 {
 838         struct dwc3_request             *req;
 839         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 840
 841         req = kzalloc(sizeof(*req), gfp_flags);
 842         if (!req)
 843                 return NULL;
 844
 845         req->epnum      = dep->number;
 846         req->dep        = dep;
 847
 848         dep->allocated_requests++;
 849
 850         trace_dwc3_alloc_request(req);
 851
 852         return &req->request;
 853 }
 854
 855 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 856                 struct usb_request *request)
 857 {
 858         struct dwc3_request             *req = to_dwc3_request(request);
 859         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 860
 861         dep->allocated_requests--;
 862         trace_dwc3_free_request(req);
 863         kfree(req);
 864 }
 865
 866 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
 867
 868 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
 869                 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
 870                 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
 871 {
 872         struct dwc3             *dwc = dep->dwc;
 873         struct usb_gadget       *gadget = &dwc->gadget;
 874         enum usb_device_speed   speed = gadget->speed;
 875
 876         dwc3_ep_inc_enq(dep);
 877
 878         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 879         trb->bpl = lower_32_bits(dma);
 880         trb->bph = upper_32_bits(dma);
 881
 882         switch (usb_endpoint_type(dep->endpoint.desc)) {
 883         case USB_ENDPOINT_XFER_CONTROL:
 884                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 885                 break;
 886
 887         case USB_ENDPOINT_XFER_ISOC:
 888                 if (!node) {
 889                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 890
 891                         /*
 892                          * USB Specification 2.0 Section 5.9.2 states that: "If
 893                          * there is only a single transaction in the microframe,
 894                          * only a DATA0 data packet PID is used.  If there are
 895                          * two transactions per microframe, DATA1 is used for
 896                          * the first transaction data packet and DATA0 is used
 897                          * for the second transaction data packet.  If there are
 898                          * three transactions per microframe, DATA2 is used for
 899                          * the first transaction data packet, DATA1 is used for
 900                          * the second, and DATA0 is used for the third."
 901                          *
 902                          * IOW, we should satisfy the following cases:
 903                          *
 904                          * 1) length <= maxpacket
 905                          *      - DATA0
 906                          *
 907                          * 2) maxpacket < length <= (2 * maxpacket)
 908                          *      - DATA1, DATA0
 909                          *
 910                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
 911                          *      - DATA2, DATA1, DATA0
 912                          */
 913                         if (speed == USB_SPEED_HIGH) {
 914                                 struct usb_ep *ep = &dep->endpoint;
 915                                 unsigned int mult = 2;
 916                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
 917
 918                                 if (length <= (2 * maxp))
 919                                         mult--;
 920
 921                                 if (length <= maxp)
 922                                         mult--;
 923
 924                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
 925                         }
 926                 } else {
 927                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 928                 }
 929
 930                 /* always enable Interrupt on Missed ISOC */
 931                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 932                 break;
 933
 934         case USB_ENDPOINT_XFER_BULK:
 935         case USB_ENDPOINT_XFER_INT:
 936                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 937                 break;
 938         default:
 939                 /*
 940                  * This is only possible with faulty memory because we
 941                  * checked it already :)
 942                  */
 943                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
 944                                 usb_endpoint_type(dep->endpoint.desc));
 945         }
 946
 947         /* always enable Continue on Short Packet */
 948         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
 949                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 950
 951                 if (short_not_ok)
 952                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 953         }
 954
 955         if ((!no_interrupt && !chain) ||
 956                         (dwc3_calc_trbs_left(dep) == 0))
 957                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 958
 959         if (chain)
 960                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 961
 962         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 963                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
 964
 965         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 966
 967         trace_dwc3_prepare_trb(dep, trb);
 968 }
 969
 970 /**
 971  * dwc3_prepare_one_trb - setup one TRB from one request
 972  * @dep: endpoint for which this request is prepared
 973  * @req: dwc3_request pointer
 974  * @chain: should this TRB be chained to the next?
 975  * @node: only for isochronous endpoints. First TRB needs different type.
 976  */
 977 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 978                 struct dwc3_request *req, unsigned chain, unsigned node)
 979 {
 980         struct dwc3_trb         *trb;
 981         unsigned                length = req->request.length;
 982         unsigned                stream_id = req->request.stream_id;
 983         unsigned                short_not_ok = req->request.short_not_ok;
 984         unsigned                no_interrupt = req->request.no_interrupt;
 985         dma_addr_t              dma = req->request.dma;
 986
 987         trb = &dep->trb_pool[dep->trb_enqueue];
 988
 989         if (!req->trb) {
 990                 dwc3_gadget_move_started_request(req);
 991                 req->trb = trb;
 992                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 993                 dep->queued_requests++;
 994         }
 995
 996         __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
 997                         stream_id, short_not_ok, no_interrupt);
 998 }
 999
1000 /**
1001  * dwc3_ep_prev_trb - returns the previous TRB in the ring
1002  * @dep: The endpoint with the TRB ring
1003  * @index: The index of the current TRB in the ring
1004  *
1005  * Returns the TRB prior to the one pointed to by the index. If the
1006  * index is 0, we will wrap backwards, skip the link TRB, and return
1007  * the one just before that.
1008  */
1009 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1010 {
1011         u8 tmp = index;
1012
1013         if (!tmp)
1014                 tmp = DWC3_TRB_NUM - 1;
1015
1016         return &dep->trb_pool[tmp - 1];
1017 }
1018
1019 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1020 {
1021         struct dwc3_trb         *tmp;
1022         u8                      trbs_left;
1023
1024         /*
1025          * If enqueue & dequeue are equal than it is either full or empty.
1026          *
1027          * One way to know for sure is if the TRB right before us has HWO bit
1028          * set or not. If it has, then we're definitely full and can't fit any
1029          * more transfers in our ring.
1030          */
1031         if (dep->trb_enqueue == dep->trb_dequeue) {
1032                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1033                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1034                         return 0;
1035
1036                 return DWC3_TRB_NUM - 1;
1037         }
1038
1039         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1040         trbs_left &= (DWC3_TRB_NUM - 1);
1041
1042         if (dep->trb_dequeue < dep->trb_enqueue)
1043                 trbs_left--;
1044
1045         return trbs_left;
1046 }
1047
1048 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1049                 struct dwc3_request *req)
1050 {
1051         struct scatterlist *sg = req->sg;
1052         struct scatterlist *s;
1053         int             i;
1054
1055         for_each_sg(sg, s, req->num_pending_sgs, i) {
1056                 unsigned int length = req->request.length;
1057                 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1058                 unsigned int rem = length % maxp;
1059                 unsigned chain = true;
1060
1061                 if (sg_is_last(s))
1062                         chain = false;
1063
1064                 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1065                         struct dwc3     *dwc = dep->dwc;
1066                         struct dwc3_trb *trb;
1067
1068                         req->unaligned = true;
1069
1070                         /* prepare normal TRB */
1071                         dwc3_prepare_one_trb(dep, req, true, i);
1072
1073                         /* Now prepare one extra TRB to align transfer size */
1074                         trb = &dep->trb_pool[dep->trb_enqueue];
1075                         __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1076                                         maxp - rem, false, 0,
1077                                         req->request.stream_id,
1078                                         req->request.short_not_ok,
1079                                         req->request.no_interrupt);
1080                 } else {
1081                         dwc3_prepare_one_trb(dep, req, chain, i);
1082                 }
1083
1084                 if (!dwc3_calc_trbs_left(dep))
1085                         break;
1086         }
1087 }
1088
1089 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1090                 struct dwc3_request *req)
1091 {
1092         unsigned int length = req->request.length;
1093         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1094         unsigned int rem = length % maxp;
1095
1096         if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1097                 struct dwc3     *dwc = dep->dwc;
1098                 struct dwc3_trb *trb;
1099
1100                 req->unaligned = true;
1101
1102                 /* prepare normal TRB */
1103                 dwc3_prepare_one_trb(dep, req, true, 0);
1104
1105                 /* Now prepare one extra TRB to align transfer size */
1106                 trb = &dep->trb_pool[dep->trb_enqueue];
1107                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1108                                 false, 0, req->request.stream_id,
1109                                 req->request.short_not_ok,
1110                                 req->request.no_interrupt);
1111         } else if (req->request.zero && req->request.length &&
1112                    (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1113                 struct dwc3     *dwc = dep->dwc;
1114                 struct dwc3_trb *trb;
1115
1116                 req->zero = true;
1117
1118                 /* prepare normal TRB */
1119                 dwc3_prepare_one_trb(dep, req, true, 0);
1120
1121                 /* Now prepare one extra TRB to handle ZLP */
1122                 trb = &dep->trb_pool[dep->trb_enqueue];
1123                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1124                                 false, 0, req->request.stream_id,
1125                                 req->request.short_not_ok,
1126                                 req->request.no_interrupt);
1127         } else {
1128                 dwc3_prepare_one_trb(dep, req, false, 0);
1129         }
1130 }
1131
1132 /*
1133  * dwc3_prepare_trbs - setup TRBs from requests
1134  * @dep: endpoint for which requests are being prepared
1135  *
1136  * The function goes through the requests list and sets up TRBs for the
1137  * transfers. The function returns once there are no more TRBs available or
1138  * it runs out of requests.
1139  */
1140 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1141 {
1142         struct dwc3_request     *req, *n;
1143
1144         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1145
1146         /*
1147          * We can get in a situation where there's a request in the started list
1148          * but there weren't enough TRBs to fully kick it in the first time
1149          * around, so it has been waiting for more TRBs to be freed up.
1150          *
1151          * In that case, we should check if we have a request with pending_sgs
1152          * in the started list and prepare TRBs for that request first,
1153          * otherwise we will prepare TRBs completely out of order and that will
1154          * break things.
1155          */
1156         list_for_each_entry(req, &dep->started_list, list) {
1157                 if (req->num_pending_sgs > 0)
1158                         dwc3_prepare_one_trb_sg(dep, req);
1159
1160                 if (!dwc3_calc_trbs_left(dep))
1161                         return;
1162         }
1163
1164         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1165                 struct dwc3     *dwc = dep->dwc;
1166                 int             ret;
1167
1168                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1169                                                     dep->direction);
1170                 if (ret)
1171                         return;
1172
1173                 req->sg                 = req->request.sg;
1174                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1175
1176                 if (req->num_pending_sgs > 0)
1177                         dwc3_prepare_one_trb_sg(dep, req);
1178                 else
1179                         dwc3_prepare_one_trb_linear(dep, req);
1180
1181                 if (!dwc3_calc_trbs_left(dep))
1182                         return;
1183         }
1184 }
1185
1186 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1187 {
1188         struct dwc3_gadget_ep_cmd_params params;
1189         struct dwc3_request             *req;
1190         int                             starting;
1191         int                             ret;
1192         u32                             cmd;
1193
1194         if (!dwc3_calc_trbs_left(dep))
1195                 return 0;
1196
1197         starting = !(dep->flags & DWC3_EP_BUSY);
1198
1199         dwc3_prepare_trbs(dep);
1200         req = next_request(&dep->started_list);
1201         if (!req) {
1202                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1203                 return 0;
1204         }
1205
1206         memset(&params, 0, sizeof(params));
1207
1208         if (starting) {
1209                 params.param0 = upper_32_bits(req->trb_dma);
1210                 params.param1 = lower_32_bits(req->trb_dma);
1211                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1212
1213                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1214                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1215         } else {
1216                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1217                         DWC3_DEPCMD_PARAM(dep->resource_index);
1218         }
1219
1220         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1221         if (ret < 0) {
1222                 /*
1223                  * FIXME we need to iterate over the list of requests
1224                  * here and stop, unmap, free and del each of the linked
1225                  * requests instead of what we do now.
1226                  */
1227                 if (req->trb)
1228                         memset(req->trb, 0, sizeof(struct dwc3_trb));
1229                 dep->queued_requests--;
1230                 dwc3_gadget_giveback(dep, req, ret);
1231                 return ret;
1232         }
1233
1234         dep->flags |= DWC3_EP_BUSY;
1235
1236         if (starting) {
1237                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1238                 WARN_ON_ONCE(!dep->resource_index);
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1245 {
1246         u32                     reg;
1247
1248         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1249         return DWC3_DSTS_SOFFN(reg);
1250 }
1251
1252 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1253                 struct dwc3_ep *dep, u32 cur_uf)
1254 {
1255         if (list_empty(&dep->pending_list)) {
1256                 dev_info(dwc->dev, "%s: ran out of requests\n",
1257                                 dep->name);
1258                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1259                 return;
1260         }
1261
1262         /*
1263          * Schedule the first trb for one interval in the future or at
1264          * least 4 microframes.
1265          */
1266         dep->frame_number = cur_uf + max_t(u32, 4, dep->interval);
1267         __dwc3_gadget_kick_transfer(dep);
1268 }
1269
1270 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1271                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1272 {
1273         u32 cur_uf, mask;
1274
1275         mask = ~(dep->interval - 1);
1276         cur_uf = event->parameters & mask;
1277
1278         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1279 }
1280
1281 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1282 {
1283         struct dwc3             *dwc = dep->dwc;
1284
1285         if (!dep->endpoint.desc) {
1286                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1287                                 dep->name);
1288                 return -ESHUTDOWN;
1289         }
1290
1291         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1292                                 &req->request, req->dep->name))
1293                 return -EINVAL;
1294
1295         pm_runtime_get(dwc->dev);
1296
1297         req->request.actual     = 0;
1298         req->request.status     = -EINPROGRESS;
1299         req->direction          = dep->direction;
1300         req->epnum              = dep->number;
1301
1302         trace_dwc3_ep_queue(req);
1303
1304         list_add_tail(&req->list, &dep->pending_list);
1305
1306         /*
1307          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1308          * wait for a XferNotReady event so we will know what's the current
1309          * (micro-)frame number.
1310          *
1311          * Without this trick, we are very, very likely gonna get Bus Expiry
1312          * errors which will force us issue EndTransfer command.
1313          */
1314         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1315                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1316                         if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1317                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1318                                 dep->flags = DWC3_EP_ENABLED;
1319                         } else {
1320                                 u32 cur_uf;
1321
1322                                 cur_uf = __dwc3_gadget_get_frame(dwc);
1323                                 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1324                                 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1325                         }
1326                         return 0;
1327                 }
1328
1329                 if ((dep->flags & DWC3_EP_BUSY) &&
1330                     !(dep->flags & DWC3_EP_MISSED_ISOC))
1331                         goto out;
1332
1333                 return 0;
1334         }
1335
1336 out:
1337         return __dwc3_gadget_kick_transfer(dep);
1338 }
1339
1340 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1341         gfp_t gfp_flags)
1342 {
1343         struct dwc3_request             *req = to_dwc3_request(request);
1344         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1345         struct dwc3                     *dwc = dep->dwc;
1346
1347         unsigned long                   flags;
1348
1349         int                             ret;
1350
1351         spin_lock_irqsave(&dwc->lock, flags);
1352         ret = __dwc3_gadget_ep_queue(dep, req);
1353         spin_unlock_irqrestore(&dwc->lock, flags);
1354
1355         return ret;
1356 }
1357
1358 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1359                 struct usb_request *request)
1360 {
1361         struct dwc3_request             *req = to_dwc3_request(request);
1362         struct dwc3_request             *r = NULL;
1363
1364         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1365         struct dwc3                     *dwc = dep->dwc;
1366
1367         unsigned long                   flags;
1368         int                             ret = 0;
1369
1370         trace_dwc3_ep_dequeue(req);
1371
1372         spin_lock_irqsave(&dwc->lock, flags);
1373
1374         list_for_each_entry(r, &dep->pending_list, list) {
1375                 if (r == req)
1376                         break;
1377         }
1378
1379         if (r != req) {
1380                 list_for_each_entry(r, &dep->started_list, list) {
1381                         if (r == req)
1382                                 break;
1383                 }
1384                 if (r == req) {
1385                         /* wait until it is processed */
1386                         dwc3_stop_active_transfer(dwc, dep->number, true);
1387
1388                         /*
1389                          * If request was already started, this means we had to
1390                          * stop the transfer. With that we also need to ignore
1391                          * all TRBs used by the request, however TRBs can only
1392                          * be modified after completion of END_TRANSFER
1393                          * command. So what we do here is that we wait for
1394                          * END_TRANSFER completion and only after that, we jump
1395                          * over TRBs by clearing HWO and incrementing dequeue
1396                          * pointer.
1397                          *
1398                          * Note that we have 2 possible types of transfers here:
1399                          *
1400                          * i) Linear buffer request
1401                          * ii) SG-list based request
1402                          *
1403                          * SG-list based requests will have r->num_pending_sgs
1404                          * set to a valid number (> 0). Linear requests,
1405                          * normally use a single TRB.
1406                          *
1407                          * For each of these two cases, if r->unaligned flag is
1408                          * set, one extra TRB has been used to align transfer
1409                          * size to wMaxPacketSize.
1410                          *
1411                          * All of these cases need to be taken into
1412                          * consideration so we don't mess up our TRB ring
1413                          * pointers.
1414                          */
1415                         wait_event_lock_irq(dep->wait_end_transfer,
1416                                         !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1417                                         dwc->lock);
1418
1419                         if (!r->trb)
1420                                 goto out1;
1421
1422                         if (r->num_pending_sgs) {
1423                                 struct dwc3_trb *trb;
1424                                 int i = 0;
1425
1426                                 for (i = 0; i < r->num_pending_sgs; i++) {
1427                                         trb = r->trb + i;
1428                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1429                                         dwc3_ep_inc_deq(dep);
1430                                 }
1431
1432                                 if (r->unaligned || r->zero) {
1433                                         trb = r->trb + r->num_pending_sgs + 1;
1434                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1435                                         dwc3_ep_inc_deq(dep);
1436                                 }
1437                         } else {
1438                                 struct dwc3_trb *trb = r->trb;
1439
1440                                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1441                                 dwc3_ep_inc_deq(dep);
1442
1443                                 if (r->unaligned || r->zero) {
1444                                         trb = r->trb + 1;
1445                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1446                                         dwc3_ep_inc_deq(dep);
1447                                 }
1448                         }
1449                         goto out1;
1450                 }
1451                 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1452                                 request, ep->name);
1453                 ret = -EINVAL;
1454                 goto out0;
1455         }
1456
1457 out1:
1458         /* giveback the request */
1459         dep->queued_requests--;
1460         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1461
1462 out0:
1463         spin_unlock_irqrestore(&dwc->lock, flags);
1464
1465         return ret;
1466 }
1467
1468 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1469 {
1470         struct dwc3_gadget_ep_cmd_params        params;
1471         struct dwc3                             *dwc = dep->dwc;
1472         int                                     ret;
1473
1474         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1475                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1476                 return -EINVAL;
1477         }
1478
1479         memset(&params, 0x00, sizeof(params));
1480
1481         if (value) {
1482                 struct dwc3_trb *trb;
1483
1484                 unsigned transfer_in_flight;
1485                 unsigned started;
1486
1487                 if (dep->flags & DWC3_EP_STALL)
1488                         return 0;
1489
1490                 if (dep->number > 1)
1491                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1492                 else
1493                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1494
1495                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1496                 started = !list_empty(&dep->started_list);
1497
1498                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1499                                 (!dep->direction && started))) {
1500                         return -EAGAIN;
1501                 }
1502
1503                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1504                                 &params);
1505                 if (ret)
1506                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1507                                         dep->name);
1508                 else
1509                         dep->flags |= DWC3_EP_STALL;
1510         } else {
1511                 if (!(dep->flags & DWC3_EP_STALL))
1512                         return 0;
1513
1514                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1515                 if (ret)
1516                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1517                                         dep->name);
1518                 else
1519                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1520         }
1521
1522         return ret;
1523 }
1524
1525 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1526 {
1527         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1528         struct dwc3                     *dwc = dep->dwc;
1529
1530         unsigned long                   flags;
1531
1532         int                             ret;
1533
1534         spin_lock_irqsave(&dwc->lock, flags);
1535         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1536         spin_unlock_irqrestore(&dwc->lock, flags);
1537
1538         return ret;
1539 }
1540
1541 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1542 {
1543         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1544         struct dwc3                     *dwc = dep->dwc;
1545         unsigned long                   flags;
1546         int                             ret;
1547
1548         spin_lock_irqsave(&dwc->lock, flags);
1549         dep->flags |= DWC3_EP_WEDGE;
1550
1551         if (dep->number == 0 || dep->number == 1)
1552                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1553         else
1554                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1555         spin_unlock_irqrestore(&dwc->lock, flags);
1556
1557         return ret;
1558 }
1559
1560 /* -------------------------------------------------------------------------- */
1561
1562 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1563         .bLength        = USB_DT_ENDPOINT_SIZE,
1564         .bDescriptorType = USB_DT_ENDPOINT,
1565         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1566 };
1567
1568 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1569         .enable         = dwc3_gadget_ep0_enable,
1570         .disable        = dwc3_gadget_ep0_disable,
1571         .alloc_request  = dwc3_gadget_ep_alloc_request,
1572         .free_request   = dwc3_gadget_ep_free_request,
1573         .queue          = dwc3_gadget_ep0_queue,
1574         .dequeue        = dwc3_gadget_ep_dequeue,
1575         .set_halt       = dwc3_gadget_ep0_set_halt,
1576         .set_wedge      = dwc3_gadget_ep_set_wedge,
1577 };
1578
1579 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1580         .enable         = dwc3_gadget_ep_enable,
1581         .disable        = dwc3_gadget_ep_disable,
1582         .alloc_request  = dwc3_gadget_ep_alloc_request,
1583         .free_request   = dwc3_gadget_ep_free_request,
1584         .queue          = dwc3_gadget_ep_queue,
1585         .dequeue        = dwc3_gadget_ep_dequeue,
1586         .set_halt       = dwc3_gadget_ep_set_halt,
1587         .set_wedge      = dwc3_gadget_ep_set_wedge,
1588 };
1589
1590 /* -------------------------------------------------------------------------- */
1591
1592 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1593 {
1594         struct dwc3             *dwc = gadget_to_dwc(g);
1595
1596         return __dwc3_gadget_get_frame(dwc);
1597 }
1598
1599 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1600 {
1601         int                     retries;
1602
1603         int                     ret;
1604         u32                     reg;
1605
1606         u8                      link_state;
1607         u8                      speed;
1608
1609         /*
1610          * According to the Databook Remote wakeup request should
1611          * be issued only when the device is in early suspend state.
1612          *
1613          * We can check that via USB Link State bits in DSTS register.
1614          */
1615         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1616
1617         speed = reg & DWC3_DSTS_CONNECTSPD;
1618         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1619             (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1620                 return 0;
1621
1622         link_state = DWC3_DSTS_USBLNKST(reg);
1623
1624         switch (link_state) {
1625         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1626         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1627                 break;
1628         default:
1629                 return -EINVAL;
1630         }
1631
1632         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1633         if (ret < 0) {
1634                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1635                 return ret;
1636         }
1637
1638         /* Recent versions do this automatically */
1639         if (dwc->revision < DWC3_REVISION_194A) {
1640                 /* write zeroes to Link Change Request */
1641                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1642                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1643                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1644         }
1645
1646         /* poll until Link State changes to ON */
1647         retries = 20000;
1648
1649         while (retries--) {
1650                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1651
1652                 /* in HS, means ON */
1653                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1654                         break;
1655         }
1656
1657         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1658                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1659                 return -EINVAL;
1660         }
1661
1662         return 0;
1663 }
1664
1665 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1666 {
1667         struct dwc3             *dwc = gadget_to_dwc(g);
1668         unsigned long           flags;
1669         int                     ret;
1670
1671         spin_lock_irqsave(&dwc->lock, flags);
1672         ret = __dwc3_gadget_wakeup(dwc);
1673         spin_unlock_irqrestore(&dwc->lock, flags);
1674
1675         return ret;
1676 }
1677
1678 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1679                 int is_selfpowered)
1680 {
1681         struct dwc3             *dwc = gadget_to_dwc(g);
1682         unsigned long           flags;
1683
1684         spin_lock_irqsave(&dwc->lock, flags);
1685         g->is_selfpowered = !!is_selfpowered;
1686         spin_unlock_irqrestore(&dwc->lock, flags);
1687
1688         return 0;
1689 }
1690
1691 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1692 {
1693         u32                     reg;
1694         u32                     timeout = 500;
1695
1696         if (pm_runtime_suspended(dwc->dev))
1697                 return 0;
1698
1699         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1700         if (is_on) {
1701                 if (dwc->revision <= DWC3_REVISION_187A) {
1702                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1703                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1704                 }
1705
1706                 if (dwc->revision >= DWC3_REVISION_194A)
1707                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1708                 reg |= DWC3_DCTL_RUN_STOP;
1709
1710                 if (dwc->has_hibernation)
1711                         reg |= DWC3_DCTL_KEEP_CONNECT;
1712
1713                 dwc->pullups_connected = true;
1714         } else {
1715                 reg &= ~DWC3_DCTL_RUN_STOP;
1716
1717                 if (dwc->has_hibernation && !suspend)
1718                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1719
1720                 dwc->pullups_connected = false;
1721         }
1722
1723         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1724
1725         do {
1726                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1727                 reg &= DWC3_DSTS_DEVCTRLHLT;
1728         } while (--timeout && !(!is_on ^ !reg));
1729
1730         if (!timeout)
1731                 return -ETIMEDOUT;
1732
1733         return 0;
1734 }
1735
1736 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1737 {
1738         struct dwc3             *dwc = gadget_to_dwc(g);
1739         unsigned long           flags;
1740         int                     ret;
1741
1742         is_on = !!is_on;
1743
1744         /*
1745          * Per databook, when we want to stop the gadget, if a control transfer
1746          * is still in process, complete it and get the core into setup phase.
1747          */
1748         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1749                 reinit_completion(&dwc->ep0_in_setup);
1750
1751                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1752                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1753                 if (ret == 0) {
1754                         dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1755                         return -ETIMEDOUT;
1756                 }
1757         }
1758
1759         spin_lock_irqsave(&dwc->lock, flags);
1760         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1761         spin_unlock_irqrestore(&dwc->lock, flags);
1762
1763         return ret;
1764 }
1765
1766 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1767 {
1768         u32                     reg;
1769
1770         /* Enable all but Start and End of Frame IRQs */
1771         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1772                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1773                         DWC3_DEVTEN_CMDCMPLTEN |
1774                         DWC3_DEVTEN_ERRTICERREN |
1775                         DWC3_DEVTEN_WKUPEVTEN |
1776                         DWC3_DEVTEN_CONNECTDONEEN |
1777                         DWC3_DEVTEN_USBRSTEN |
1778                         DWC3_DEVTEN_DISCONNEVTEN);
1779
1780         if (dwc->revision < DWC3_REVISION_250A)
1781                 reg |= DWC3_DEVTEN_ULSTCNGEN;
1782
1783         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1784 }
1785
1786 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1787 {
1788         /* mask all interrupts */
1789         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1790 }
1791
1792 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1793 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1794
1795 /**
1796  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1797  * @dwc: pointer to our context structure
1798  *
1799  * The following looks like complex but it's actually very simple. In order to
1800  * calculate the number of packets we can burst at once on OUT transfers, we're
1801  * gonna use RxFIFO size.
1802  *
1803  * To calculate RxFIFO size we need two numbers:
1804  * MDWIDTH = size, in bits, of the internal memory bus
1805  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1806  *
1807  * Given these two numbers, the formula is simple:
1808  *
1809  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1810  *
1811  * 24 bytes is for 3x SETUP packets
1812  * 16 bytes is a clock domain crossing tolerance
1813  *
1814  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1815  */
1816 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1817 {
1818         u32 ram2_depth;
1819         u32 mdwidth;
1820         u32 nump;
1821         u32 reg;
1822
1823         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1824         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1825
1826         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1827         nump = min_t(u32, nump, 16);
1828
1829         /* update NumP */
1830         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1831         reg &= ~DWC3_DCFG_NUMP_MASK;
1832         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1833         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1834 }
1835
1836 static int __dwc3_gadget_start(struct dwc3 *dwc)
1837 {
1838         struct dwc3_ep          *dep;
1839         int                     ret = 0;
1840         u32                     reg;
1841
1842         /*
1843          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1844          * the core supports IMOD, disable it.
1845          */
1846         if (dwc->imod_interval) {
1847                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1848                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1849         } else if (dwc3_has_imod(dwc)) {
1850                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1851         }
1852
1853         /*
1854          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1855          * field instead of letting dwc3 itself calculate that automatically.
1856          *
1857          * This way, we maximize the chances that we'll be able to get several
1858          * bursts of data without going through any sort of endpoint throttling.
1859          */
1860         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1861         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1862         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1863
1864         dwc3_gadget_setup_nump(dwc);
1865
1866         /* Start with SuperSpeed Default */
1867         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1868
1869         dep = dwc->eps[0];
1870         ret = __dwc3_gadget_ep_enable(dep, false, false);
1871         if (ret) {
1872                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1873                 goto err0;
1874         }
1875
1876         dep = dwc->eps[1];
1877         ret = __dwc3_gadget_ep_enable(dep, false, false);
1878         if (ret) {
1879                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1880                 goto err1;
1881         }
1882
1883         /* begin to receive SETUP packets */
1884         dwc->ep0state = EP0_SETUP_PHASE;
1885         dwc3_ep0_out_start(dwc);
1886
1887         dwc3_gadget_enable_irq(dwc);
1888
1889         return 0;
1890
1891 err1:
1892         __dwc3_gadget_ep_disable(dwc->eps[0]);
1893
1894 err0:
1895         return ret;
1896 }
1897
1898 static int dwc3_gadget_start(struct usb_gadget *g,
1899                 struct usb_gadget_driver *driver)
1900 {
1901         struct dwc3             *dwc = gadget_to_dwc(g);
1902         unsigned long           flags;
1903         int                     ret = 0;
1904         int                     irq;
1905
1906         irq = dwc->irq_gadget;
1907         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1908                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1909         if (ret) {
1910                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1911                                 irq, ret);
1912                 goto err0;
1913         }
1914
1915         spin_lock_irqsave(&dwc->lock, flags);
1916         if (dwc->gadget_driver) {
1917                 dev_err(dwc->dev, "%s is already bound to %s\n",
1918                                 dwc->gadget.name,
1919                                 dwc->gadget_driver->driver.name);
1920                 ret = -EBUSY;
1921                 goto err1;
1922         }
1923
1924         dwc->gadget_driver      = driver;
1925
1926         if (pm_runtime_active(dwc->dev))
1927                 __dwc3_gadget_start(dwc);
1928
1929         spin_unlock_irqrestore(&dwc->lock, flags);
1930
1931         return 0;
1932
1933 err1:
1934         spin_unlock_irqrestore(&dwc->lock, flags);
1935         free_irq(irq, dwc);
1936
1937 err0:
1938         return ret;
1939 }
1940
1941 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1942 {
1943         dwc3_gadget_disable_irq(dwc);
1944         __dwc3_gadget_ep_disable(dwc->eps[0]);
1945         __dwc3_gadget_ep_disable(dwc->eps[1]);
1946 }
1947
1948 static int dwc3_gadget_stop(struct usb_gadget *g)
1949 {
1950         struct dwc3             *dwc = gadget_to_dwc(g);
1951         unsigned long           flags;
1952         int                     epnum;
1953
1954         spin_lock_irqsave(&dwc->lock, flags);
1955
1956         if (pm_runtime_suspended(dwc->dev))
1957                 goto out;
1958
1959         __dwc3_gadget_stop(dwc);
1960
1961         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1962                 struct dwc3_ep  *dep = dwc->eps[epnum];
1963
1964                 if (!dep)
1965                         continue;
1966
1967                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1968                         continue;
1969
1970                 wait_event_lock_irq(dep->wait_end_transfer,
1971                                     !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1972                                     dwc->lock);
1973         }
1974
1975 out:
1976         dwc->gadget_driver      = NULL;
1977         spin_unlock_irqrestore(&dwc->lock, flags);
1978
1979         free_irq(dwc->irq_gadget, dwc->ev_buf);
1980
1981         return 0;
1982 }
1983
1984 static void dwc3_gadget_set_speed(struct usb_gadget *g,
1985                                   enum usb_device_speed speed)
1986 {
1987         struct dwc3             *dwc = gadget_to_dwc(g);
1988         unsigned long           flags;
1989         u32                     reg;
1990
1991         spin_lock_irqsave(&dwc->lock, flags);
1992         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1993         reg &= ~(DWC3_DCFG_SPEED_MASK);
1994
1995         /*
1996          * WORKAROUND: DWC3 revision < 2.20a have an issue
1997          * which would cause metastability state on Run/Stop
1998          * bit if we try to force the IP to USB2-only mode.
1999          *
2000          * Because of that, we cannot configure the IP to any
2001          * speed other than the SuperSpeed
2002          *
2003          * Refers to:
2004          *
2005          * STAR#9000525659: Clock Domain Crossing on DCTL in
2006          * USB 2.0 Mode
2007          */
2008         if (dwc->revision < DWC3_REVISION_220A) {
2009                 reg |= DWC3_DCFG_SUPERSPEED;
2010         } else {
2011                 switch (speed) {
2012                 case USB_SPEED_LOW:
2013                         reg |= DWC3_DCFG_LOWSPEED;
2014                         break;
2015                 case USB_SPEED_FULL:
2016                         reg |= DWC3_DCFG_FULLSPEED;
2017                         break;
2018                 case USB_SPEED_HIGH:
2019                         reg |= DWC3_DCFG_HIGHSPEED;
2020                         break;
2021                 case USB_SPEED_SUPER:
2022                         reg |= DWC3_DCFG_SUPERSPEED;
2023                         break;
2024                 case USB_SPEED_SUPER_PLUS:
2025                         reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2026                         break;
2027                 default:
2028                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2029
2030                         if (dwc->revision & DWC3_REVISION_IS_DWC31)
2031                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2032                         else
2033                                 reg |= DWC3_DCFG_SUPERSPEED;
2034                 }
2035         }
2036         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2037
2038         spin_unlock_irqrestore(&dwc->lock, flags);
2039 }
2040
2041 static const struct usb_gadget_ops dwc3_gadget_ops = {
2042         .get_frame              = dwc3_gadget_get_frame,
2043         .wakeup                 = dwc3_gadget_wakeup,
2044         .set_selfpowered        = dwc3_gadget_set_selfpowered,
2045         .pullup                 = dwc3_gadget_pullup,
2046         .udc_start              = dwc3_gadget_start,
2047         .udc_stop               = dwc3_gadget_stop,
2048         .udc_set_speed          = dwc3_gadget_set_speed,
2049 };
2050
2051 /* -------------------------------------------------------------------------- */
2052
2053 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2054 {
2055         struct dwc3_ep                  *dep;
2056         u8                              epnum;
2057
2058         INIT_LIST_HEAD(&dwc->gadget.ep_list);
2059
2060         for (epnum = 0; epnum < total; epnum++) {
2061                 bool                    direction = epnum & 1;
2062                 u8                      num = epnum >> 1;
2063
2064                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2065                 if (!dep)
2066                         return -ENOMEM;
2067
2068                 dep->dwc = dwc;
2069                 dep->number = epnum;
2070                 dep->direction = direction;
2071                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2072                 dwc->eps[epnum] = dep;
2073
2074                 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2075                                 direction ? "in" : "out");
2076
2077                 dep->endpoint.name = dep->name;
2078
2079                 if (!(dep->number > 1)) {
2080                         dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2081                         dep->endpoint.comp_desc = NULL;
2082                 }
2083
2084                 spin_lock_init(&dep->lock);
2085
2086                 if (num == 0) {
2087                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2088                         dep->endpoint.maxburst = 1;
2089                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2090                         if (!direction)
2091                                 dwc->gadget.ep0 = &dep->endpoint;
2092                 } else if (direction) {
2093                         int mdwidth;
2094                         int kbytes;
2095                         int size;
2096                         int ret;
2097
2098                         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2099                         /* MDWIDTH is represented in bits, we need it in bytes */
2100                         mdwidth /= 8;
2101
2102                         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2103                         size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2104
2105                         /* FIFO Depth is in MDWDITH bytes. Multiply */
2106                         size *= mdwidth;
2107
2108                         kbytes = size / 1024;
2109                         if (kbytes == 0)
2110                                 kbytes = 1;
2111
2112                         /*
2113                          * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2114                          * internal overhead. We don't really know how these are used,
2115                          * but documentation say it exists.
2116                          */
2117                         size -= mdwidth * (kbytes + 1);
2118                         size /= kbytes;
2119
2120                         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2121
2122                         dep->endpoint.max_streams = 15;
2123                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2124                         list_add_tail(&dep->endpoint.ep_list,
2125                                         &dwc->gadget.ep_list);
2126
2127                         ret = dwc3_alloc_trb_pool(dep);
2128                         if (ret)
2129                                 return ret;
2130                 } else {
2131                         int             ret;
2132
2133                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2134                         dep->endpoint.max_streams = 15;
2135                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2136                         list_add_tail(&dep->endpoint.ep_list,
2137                                         &dwc->gadget.ep_list);
2138
2139                         ret = dwc3_alloc_trb_pool(dep);
2140                         if (ret)
2141                                 return ret;
2142                 }
2143
2144                 if (num == 0) {
2145                         dep->endpoint.caps.type_control = true;
2146                 } else {
2147                         dep->endpoint.caps.type_iso = true;
2148                         dep->endpoint.caps.type_bulk = true;
2149                         dep->endpoint.caps.type_int = true;
2150                 }
2151
2152                 dep->endpoint.caps.dir_in = direction;
2153                 dep->endpoint.caps.dir_out = !direction;
2154
2155                 INIT_LIST_HEAD(&dep->pending_list);
2156                 INIT_LIST_HEAD(&dep->started_list);
2157         }
2158
2159         return 0;
2160 }
2161
2162 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2163 {
2164         struct dwc3_ep                  *dep;
2165         u8                              epnum;
2166
2167         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2168                 dep = dwc->eps[epnum];
2169                 if (!dep)
2170                         continue;
2171                 /*
2172                  * Physical endpoints 0 and 1 are special; they form the
2173                  * bi-directional USB endpoint 0.
2174                  *
2175                  * For those two physical endpoints, we don't allocate a TRB
2176                  * pool nor do we add them the endpoints list. Due to that, we
2177                  * shouldn't do these two operations otherwise we would end up
2178                  * with all sorts of bugs when removing dwc3.ko.
2179                  */
2180                 if (epnum != 0 && epnum != 1) {
2181                         dwc3_free_trb_pool(dep);
2182                         list_del(&dep->endpoint.ep_list);
2183                 }
2184
2185                 kfree(dep);
2186         }
2187 }
2188
2189 /* -------------------------------------------------------------------------- */
2190
2191 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2192                 struct dwc3_request *req, struct dwc3_trb *trb,
2193                 const struct dwc3_event_depevt *event, int status,
2194                 int chain)
2195 {
2196         unsigned int            count;
2197         unsigned int            s_pkt = 0;
2198         unsigned int            trb_status;
2199
2200         dwc3_ep_inc_deq(dep);
2201
2202         if (req->trb == trb)
2203                 dep->queued_requests--;
2204
2205         trace_dwc3_complete_trb(dep, trb);
2206
2207         /*
2208          * If we're in the middle of series of chained TRBs and we
2209          * receive a short transfer along the way, DWC3 will skip
2210          * through all TRBs including the last TRB in the chain (the
2211          * where CHN bit is zero. DWC3 will also avoid clearing HWO
2212          * bit and SW has to do it manually.
2213          *
2214          * We're going to do that here to avoid problems of HW trying
2215          * to use bogus TRBs for transfers.
2216          */
2217         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2218                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2219
2220         /*
2221          * If we're dealing with unaligned size OUT transfer, we will be left
2222          * with one TRB pending in the ring. We need to manually clear HWO bit
2223          * from that TRB.
2224          */
2225         if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2226                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2227                 return 1;
2228         }
2229
2230         count = trb->size & DWC3_TRB_SIZE_MASK;
2231         req->remaining += count;
2232
2233         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2234                 return 1;
2235
2236         if (dep->direction) {
2237                 if (count) {
2238                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2239                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2240                                 /*
2241                                  * If missed isoc occurred and there is
2242                                  * no request queued then issue END
2243                                  * TRANSFER, so that core generates
2244                                  * next xfernotready and we will issue
2245                                  * a fresh START TRANSFER.
2246                                  * If there are still queued request
2247                                  * then wait, do not issue either END
2248                                  * or UPDATE TRANSFER, just attach next
2249                                  * request in pending_list during
2250                                  * giveback.If any future queued request
2251                                  * is successfully transferred then we
2252                                  * will issue UPDATE TRANSFER for all
2253                                  * request in the pending_list.
2254                                  */
2255                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2256                         } else {
2257                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2258                                                 dep->name);
2259                                 status = -ECONNRESET;
2260                         }
2261                 } else {
2262                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2263                 }
2264         } else {
2265                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2266                         s_pkt = 1;
2267         }
2268
2269         if (s_pkt && !chain)
2270                 return 1;
2271
2272         if ((event->status & DEPEVT_STATUS_IOC) &&
2273                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2274                 return 1;
2275
2276         return 0;
2277 }
2278
2279 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2280                 const struct dwc3_event_depevt *event, int status)
2281 {
2282         struct dwc3_request     *req, *n;
2283         struct dwc3_trb         *trb;
2284         bool                    ioc = false;
2285         int                     ret = 0;
2286
2287         list_for_each_entry_safe(req, n, &dep->started_list, list) {
2288                 unsigned length;
2289                 int chain;
2290
2291                 length = req->request.length;
2292                 chain = req->num_pending_sgs > 0;
2293                 if (chain) {
2294                         struct scatterlist *sg = req->sg;
2295                         struct scatterlist *s;
2296                         unsigned int pending = req->num_pending_sgs;
2297                         unsigned int i;
2298
2299                         for_each_sg(sg, s, pending, i) {
2300                                 trb = &dep->trb_pool[dep->trb_dequeue];
2301
2302                                 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2303                                         break;
2304
2305                                 req->sg = sg_next(s);
2306                                 req->num_pending_sgs--;
2307
2308                                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2309                                                 event, status, chain);
2310                                 if (ret)
2311                                         break;
2312                         }
2313                 } else {
2314                         trb = &dep->trb_pool[dep->trb_dequeue];
2315                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2316                                         event, status, chain);
2317                 }
2318
2319                 if (req->unaligned || req->zero) {
2320                         trb = &dep->trb_pool[dep->trb_dequeue];
2321                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2322                                         event, status, false);
2323                         req->unaligned = false;
2324                         req->zero = false;
2325                 }
2326
2327                 req->request.actual = length - req->remaining;
2328
2329                 if ((req->request.actual < length) && req->num_pending_sgs)
2330                         return __dwc3_gadget_kick_transfer(dep);
2331
2332                 dwc3_gadget_giveback(dep, req, status);
2333
2334                 if (ret) {
2335                         if ((event->status & DEPEVT_STATUS_IOC) &&
2336                             (trb->ctrl & DWC3_TRB_CTRL_IOC))
2337                                 ioc = true;
2338                         break;
2339                 }
2340         }
2341
2342         /*
2343          * Our endpoint might get disabled by another thread during
2344          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2345          * early on so DWC3_EP_BUSY flag gets cleared
2346          */
2347         if (!dep->endpoint.desc)
2348                 return 1;
2349
2350         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2351                         list_empty(&dep->started_list)) {
2352                 if (list_empty(&dep->pending_list)) {
2353                         /*
2354                          * If there is no entry in request list then do
2355                          * not issue END TRANSFER now. Just set PENDING
2356                          * flag, so that END TRANSFER is issued when an
2357                          * entry is added into request list.
2358                          */
2359                         dep->flags = DWC3_EP_PENDING_REQUEST;
2360                 } else {
2361                         dwc3_stop_active_transfer(dwc, dep->number, true);
2362                         dep->flags = DWC3_EP_ENABLED;
2363                 }
2364                 return 1;
2365         }
2366
2367         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2368                 return 0;
2369
2370         return 1;
2371 }
2372
2373 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2374                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2375 {
2376         unsigned                status = 0;
2377         int                     clean_busy;
2378         u32                     is_xfer_complete;
2379
2380         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2381
2382         if (event->status & DEPEVT_STATUS_BUSERR)
2383                 status = -ECONNRESET;
2384
2385         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2386         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2387                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2388                 dep->flags &= ~DWC3_EP_BUSY;
2389
2390         /*
2391          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2392          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2393          */
2394         if (dwc->revision < DWC3_REVISION_183A) {
2395                 u32             reg;
2396                 int             i;
2397
2398                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2399                         dep = dwc->eps[i];
2400
2401                         if (!(dep->flags & DWC3_EP_ENABLED))
2402                                 continue;
2403
2404                         if (!list_empty(&dep->started_list))
2405                                 return;
2406                 }
2407
2408                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2409                 reg |= dwc->u1u2;
2410                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2411
2412                 dwc->u1u2 = 0;
2413         }
2414
2415         /*
2416          * Our endpoint might get disabled by another thread during
2417          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2418          * early on so DWC3_EP_BUSY flag gets cleared
2419          */
2420         if (!dep->endpoint.desc)
2421                 return;
2422
2423         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc))
2424                 __dwc3_gadget_kick_transfer(dep);
2425 }
2426
2427 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2428                 const struct dwc3_event_depevt *event)
2429 {
2430         struct dwc3_ep          *dep;
2431         u8                      epnum = event->endpoint_number;
2432         u8                      cmd;
2433
2434         dep = dwc->eps[epnum];
2435
2436         if (!(dep->flags & DWC3_EP_ENABLED)) {
2437                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2438                         return;
2439
2440                 /* Handle only EPCMDCMPLT when EP disabled */
2441                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2442                         return;
2443         }
2444
2445         if (epnum == 0 || epnum == 1) {
2446                 dwc3_ep0_interrupt(dwc, event);
2447                 return;
2448         }
2449
2450         switch (event->endpoint_event) {
2451         case DWC3_DEPEVT_XFERCOMPLETE:
2452                 dep->resource_index = 0;
2453
2454                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2455                         dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2456                         return;
2457                 }
2458
2459                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2460                 break;
2461         case DWC3_DEPEVT_XFERINPROGRESS:
2462                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2463                 break;
2464         case DWC3_DEPEVT_XFERNOTREADY:
2465                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2466                         dwc3_gadget_start_isoc(dwc, dep, event);
2467                 else
2468                         __dwc3_gadget_kick_transfer(dep);
2469
2470                 break;
2471         case DWC3_DEPEVT_STREAMEVT:
2472                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2473                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2474                                         dep->name);
2475                         return;
2476                 }
2477                 break;
2478         case DWC3_DEPEVT_EPCMDCMPLT:
2479                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2480
2481                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2482                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2483                         wake_up(&dep->wait_end_transfer);
2484                 }
2485                 break;
2486         case DWC3_DEPEVT_RXTXFIFOEVT:
2487                 break;
2488         }
2489 }
2490
2491 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2492 {
2493         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2494                 spin_unlock(&dwc->lock);
2495                 dwc->gadget_driver->disconnect(&dwc->gadget);
2496                 spin_lock(&dwc->lock);
2497         }
2498 }
2499
2500 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2501 {
2502         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2503                 spin_unlock(&dwc->lock);
2504                 dwc->gadget_driver->suspend(&dwc->gadget);
2505                 spin_lock(&dwc->lock);
2506         }
2507 }
2508
2509 static void dwc3_resume_gadget(struct dwc3 *dwc)
2510 {
2511         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2512                 spin_unlock(&dwc->lock);
2513                 dwc->gadget_driver->resume(&dwc->gadget);
2514                 spin_lock(&dwc->lock);
2515         }
2516 }
2517
2518 static void dwc3_reset_gadget(struct dwc3 *dwc)
2519 {
2520         if (!dwc->gadget_driver)
2521                 return;
2522
2523         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2524                 spin_unlock(&dwc->lock);
2525                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2526                 spin_lock(&dwc->lock);
2527         }
2528 }
2529
2530 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2531 {
2532         struct dwc3_ep *dep;
2533         struct dwc3_gadget_ep_cmd_params params;
2534         u32 cmd;
2535         int ret;
2536
2537         dep = dwc->eps[epnum];
2538
2539         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2540             !dep->resource_index)
2541                 return;
2542
2543         /*
2544          * NOTICE: We are violating what the Databook says about the
2545          * EndTransfer command. Ideally we would _always_ wait for the
2546          * EndTransfer Command Completion IRQ, but that's causing too
2547          * much trouble synchronizing between us and gadget driver.
2548          *
2549          * We have discussed this with the IP Provider and it was
2550          * suggested to giveback all requests here, but give HW some
2551          * extra time to synchronize with the interconnect. We're using
2552          * an arbitrary 100us delay for that.
2553          *
2554          * Note also that a similar handling was tested by Synopsys
2555          * (thanks a lot Paul) and nothing bad has come out of it.
2556          * In short, what we're doing is:
2557          *
2558          * - Issue EndTransfer WITH CMDIOC bit set
2559          * - Wait 100us
2560          *
2561          * As of IP version 3.10a of the DWC_usb3 IP, the controller
2562          * supports a mode to work around the above limitation. The
2563          * software can poll the CMDACT bit in the DEPCMD register
2564          * after issuing a EndTransfer command. This mode is enabled
2565          * by writing GUCTL2[14]. This polling is already done in the
2566          * dwc3_send_gadget_ep_cmd() function so if the mode is
2567          * enabled, the EndTransfer command will have completed upon
2568          * returning from this function and we don't need to delay for
2569          * 100us.
2570          *
2571          * This mode is NOT available on the DWC_usb31 IP.
2572          */
2573
2574         cmd = DWC3_DEPCMD_ENDTRANSFER;
2575         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2576         cmd |= DWC3_DEPCMD_CMDIOC;
2577         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2578         memset(&params, 0, sizeof(params));
2579         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2580         WARN_ON_ONCE(ret);
2581         dep->resource_index = 0;
2582         dep->flags &= ~DWC3_EP_BUSY;
2583
2584         if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2585                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2586                 udelay(100);
2587         }
2588 }
2589
2590 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2591 {
2592         u32 epnum;
2593
2594         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2595                 struct dwc3_ep *dep;
2596                 int ret;
2597
2598                 dep = dwc->eps[epnum];
2599                 if (!dep)
2600                         continue;
2601
2602                 if (!(dep->flags & DWC3_EP_STALL))
2603                         continue;
2604
2605                 dep->flags &= ~DWC3_EP_STALL;
2606
2607                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2608                 WARN_ON_ONCE(ret);
2609         }
2610 }
2611
2612 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2613 {
2614         int                     reg;
2615
2616         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2617         reg &= ~DWC3_DCTL_INITU1ENA;
2618         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2619
2620         reg &= ~DWC3_DCTL_INITU2ENA;
2621         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2622
2623         dwc3_disconnect_gadget(dwc);
2624
2625         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2626         dwc->setup_packet_pending = false;
2627         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2628
2629         dwc->connected = false;
2630 }
2631
2632 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2633 {
2634         u32                     reg;
2635
2636         dwc->connected = true;
2637
2638         /*
2639          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2640          * would cause a missing Disconnect Event if there's a
2641          * pending Setup Packet in the FIFO.
2642          *
2643          * There's no suggested workaround on the official Bug
2644          * report, which states that "unless the driver/application
2645          * is doing any special handling of a disconnect event,
2646          * there is no functional issue".
2647          *
2648          * Unfortunately, it turns out that we _do_ some special
2649          * handling of a disconnect event, namely complete all
2650          * pending transfers, notify gadget driver of the
2651          * disconnection, and so on.
2652          *
2653          * Our suggested workaround is to follow the Disconnect
2654          * Event steps here, instead, based on a setup_packet_pending
2655          * flag. Such flag gets set whenever we have a SETUP_PENDING
2656          * status for EP0 TRBs and gets cleared on XferComplete for the
2657          * same endpoint.
2658          *
2659          * Refers to:
2660          *
2661          * STAR#9000466709: RTL: Device : Disconnect event not
2662          * generated if setup packet pending in FIFO
2663          */
2664         if (dwc->revision < DWC3_REVISION_188A) {
2665                 if (dwc->setup_packet_pending)
2666                         dwc3_gadget_disconnect_interrupt(dwc);
2667         }
2668
2669         dwc3_reset_gadget(dwc);
2670
2671         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2672         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2673         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2674         dwc->test_mode = false;
2675         dwc3_clear_stall_all_ep(dwc);
2676
2677         /* Reset device address to zero */
2678         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2679         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2680         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2681 }
2682
2683 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2684 {
2685         struct dwc3_ep          *dep;
2686         int                     ret;
2687         u32                     reg;
2688         u8                      speed;
2689
2690         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2691         speed = reg & DWC3_DSTS_CONNECTSPD;
2692         dwc->speed = speed;
2693
2694         /*
2695          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2696          * each time on Connect Done.
2697          *
2698          * Currently we always use the reset value. If any platform
2699          * wants to set this to a different value, we need to add a
2700          * setting and update GCTL.RAMCLKSEL here.
2701          */
2702
2703         switch (speed) {
2704         case DWC3_DSTS_SUPERSPEED_PLUS:
2705                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2706                 dwc->gadget.ep0->maxpacket = 512;
2707                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2708                 break;
2709         case DWC3_DSTS_SUPERSPEED:
2710                 /*
2711                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2712                  * would cause a missing USB3 Reset event.
2713                  *
2714                  * In such situations, we should force a USB3 Reset
2715                  * event by calling our dwc3_gadget_reset_interrupt()
2716                  * routine.
2717                  *
2718                  * Refers to:
2719                  *
2720                  * STAR#9000483510: RTL: SS : USB3 reset event may
2721                  * not be generated always when the link enters poll
2722                  */
2723                 if (dwc->revision < DWC3_REVISION_190A)
2724                         dwc3_gadget_reset_interrupt(dwc);
2725
2726                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2727                 dwc->gadget.ep0->maxpacket = 512;
2728                 dwc->gadget.speed = USB_SPEED_SUPER;
2729                 break;
2730         case DWC3_DSTS_HIGHSPEED:
2731                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2732                 dwc->gadget.ep0->maxpacket = 64;
2733                 dwc->gadget.speed = USB_SPEED_HIGH;
2734                 break;
2735         case DWC3_DSTS_FULLSPEED:
2736                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2737                 dwc->gadget.ep0->maxpacket = 64;
2738                 dwc->gadget.speed = USB_SPEED_FULL;
2739                 break;
2740         case DWC3_DSTS_LOWSPEED:
2741                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2742                 dwc->gadget.ep0->maxpacket = 8;
2743                 dwc->gadget.speed = USB_SPEED_LOW;
2744                 break;
2745         }
2746
2747         /* Enable USB2 LPM Capability */
2748
2749         if ((dwc->revision > DWC3_REVISION_194A) &&
2750             (speed != DWC3_DSTS_SUPERSPEED) &&
2751             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2752                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2753                 reg |= DWC3_DCFG_LPM_CAP;
2754                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2755
2756                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2757                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2758
2759                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2760
2761                 /*
2762                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2763                  * DCFG.LPMCap is set, core responses with an ACK and the
2764                  * BESL value in the LPM token is less than or equal to LPM
2765                  * NYET threshold.
2766                  */
2767                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2768                                 && dwc->has_lpm_erratum,
2769                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2770
2771                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2772                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2773
2774                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2775         } else {
2776                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2777                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2778                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2779         }
2780
2781         dep = dwc->eps[0];
2782         ret = __dwc3_gadget_ep_enable(dep, true, false);
2783         if (ret) {
2784                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2785                 return;
2786         }
2787
2788         dep = dwc->eps[1];
2789         ret = __dwc3_gadget_ep_enable(dep, true, false);
2790         if (ret) {
2791                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2792                 return;
2793         }
2794
2795         /*
2796          * Configure PHY via GUSB3PIPECTLn if required.
2797          *
2798          * Update GTXFIFOSIZn
2799          *
2800          * In both cases reset values should be sufficient.
2801          */
2802 }
2803
2804 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2805 {
2806         /*
2807          * TODO take core out of low power mode when that's
2808          * implemented.
2809          */
2810
2811         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2812                 spin_unlock(&dwc->lock);
2813                 dwc->gadget_driver->resume(&dwc->gadget);
2814                 spin_lock(&dwc->lock);
2815         }
2816 }
2817
2818 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2819                 unsigned int evtinfo)
2820 {
2821         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2822         unsigned int            pwropt;
2823
2824         /*
2825          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2826          * Hibernation mode enabled which would show up when device detects
2827          * host-initiated U3 exit.
2828          *
2829          * In that case, device will generate a Link State Change Interrupt
2830          * from U3 to RESUME which is only necessary if Hibernation is
2831          * configured in.
2832          *
2833          * There are no functional changes due to such spurious event and we
2834          * just need to ignore it.
2835          *
2836          * Refers to:
2837          *
2838          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2839          * operational mode
2840          */
2841         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2842         if ((dwc->revision < DWC3_REVISION_250A) &&
2843                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2844                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2845                                 (next == DWC3_LINK_STATE_RESUME)) {
2846                         return;
2847                 }
2848         }
2849
2850         /*
2851          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2852          * on the link partner, the USB session might do multiple entry/exit
2853          * of low power states before a transfer takes place.
2854          *
2855          * Due to this problem, we might experience lower throughput. The
2856          * suggested workaround is to disable DCTL[12:9] bits if we're
2857          * transitioning from U1/U2 to U0 and enable those bits again
2858          * after a transfer completes and there are no pending transfers
2859          * on any of the enabled endpoints.
2860          *
2861          * This is the first half of that workaround.
2862          *
2863          * Refers to:
2864          *
2865          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2866          * core send LGO_Ux entering U0
2867          */
2868         if (dwc->revision < DWC3_REVISION_183A) {
2869                 if (next == DWC3_LINK_STATE_U0) {
2870                         u32     u1u2;
2871                         u32     reg;
2872
2873                         switch (dwc->link_state) {
2874                         case DWC3_LINK_STATE_U1:
2875                         case DWC3_LINK_STATE_U2:
2876                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2877                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2878                                                 | DWC3_DCTL_ACCEPTU2ENA
2879                                                 | DWC3_DCTL_INITU1ENA
2880                                                 | DWC3_DCTL_ACCEPTU1ENA);
2881
2882                                 if (!dwc->u1u2)
2883                                         dwc->u1u2 = reg & u1u2;
2884
2885                                 reg &= ~u1u2;
2886
2887                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2888                                 break;
2889                         default:
2890                                 /* do nothing */
2891                                 break;
2892                         }
2893                 }
2894         }
2895
2896         switch (next) {
2897         case DWC3_LINK_STATE_U1:
2898                 if (dwc->speed == USB_SPEED_SUPER)
2899                         dwc3_suspend_gadget(dwc);
2900                 break;
2901         case DWC3_LINK_STATE_U2:
2902         case DWC3_LINK_STATE_U3:
2903                 dwc3_suspend_gadget(dwc);
2904                 break;
2905         case DWC3_LINK_STATE_RESUME:
2906                 dwc3_resume_gadget(dwc);
2907                 break;
2908         default:
2909                 /* do nothing */
2910                 break;
2911         }
2912
2913         dwc->link_state = next;
2914 }
2915
2916 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2917                                           unsigned int evtinfo)
2918 {
2919         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2920
2921         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2922                 dwc3_suspend_gadget(dwc);
2923
2924         dwc->link_state = next;
2925 }
2926
2927 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2928                 unsigned int evtinfo)
2929 {
2930         unsigned int is_ss = evtinfo & BIT(4);
2931
2932         /*
2933          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2934          * have a known issue which can cause USB CV TD.9.23 to fail
2935          * randomly.
2936          *
2937          * Because of this issue, core could generate bogus hibernation
2938          * events which SW needs to ignore.
2939          *
2940          * Refers to:
2941          *
2942          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2943          * Device Fallback from SuperSpeed
2944          */
2945         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2946                 return;
2947
2948         /* enter hibernation here */
2949 }
2950
2951 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2952                 const struct dwc3_event_devt *event)
2953 {
2954         switch (event->type) {
2955         case DWC3_DEVICE_EVENT_DISCONNECT:
2956                 dwc3_gadget_disconnect_interrupt(dwc);
2957                 break;
2958         case DWC3_DEVICE_EVENT_RESET:
2959                 dwc3_gadget_reset_interrupt(dwc);
2960                 break;
2961         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2962                 dwc3_gadget_conndone_interrupt(dwc);
2963                 break;
2964         case DWC3_DEVICE_EVENT_WAKEUP:
2965                 dwc3_gadget_wakeup_interrupt(dwc);
2966                 break;
2967         case DWC3_DEVICE_EVENT_HIBER_REQ:
2968                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2969                                         "unexpected hibernation event\n"))
2970                         break;
2971
2972                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2973                 break;
2974         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2975                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2976                 break;
2977         case DWC3_DEVICE_EVENT_EOPF:
2978                 /* It changed to be suspend event for version 2.30a and above */
2979                 if (dwc->revision >= DWC3_REVISION_230A) {
2980                         /*
2981                          * Ignore suspend event until the gadget enters into
2982                          * USB_STATE_CONFIGURED state.
2983                          */
2984                         if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2985                                 dwc3_gadget_suspend_interrupt(dwc,
2986                                                 event->event_info);
2987                 }
2988                 break;
2989         case DWC3_DEVICE_EVENT_SOF:
2990         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2991         case DWC3_DEVICE_EVENT_CMD_CMPL:
2992         case DWC3_DEVICE_EVENT_OVERFLOW:
2993                 break;
2994         default:
2995                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2996         }
2997 }
2998
2999 static void dwc3_process_event_entry(struct dwc3 *dwc,
3000                 const union dwc3_event *event)
3001 {
3002         trace_dwc3_event(event->raw, dwc);
3003
3004         if (!event->type.is_devspec)
3005                 dwc3_endpoint_interrupt(dwc, &event->depevt);
3006         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3007                 dwc3_gadget_interrupt(dwc, &event->devt);
3008         else
3009                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3010 }
3011
3012 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3013 {
3014         struct dwc3 *dwc = evt->dwc;
3015         irqreturn_t ret = IRQ_NONE;
3016         int left;
3017         u32 reg;
3018
3019         left = evt->count;
3020
3021         if (!(evt->flags & DWC3_EVENT_PENDING))
3022                 return IRQ_NONE;
3023
3024         while (left > 0) {
3025                 union dwc3_event event;
3026
3027                 event.raw = *(u32 *) (evt->cache + evt->lpos);
3028
3029                 dwc3_process_event_entry(dwc, &event);
3030
3031                 /*
3032                  * FIXME we wrap around correctly to the next entry as
3033                  * almost all entries are 4 bytes in size. There is one
3034                  * entry which has 12 bytes which is a regular entry
3035                  * followed by 8 bytes data. ATM I don't know how
3036                  * things are organized if we get next to the a
3037                  * boundary so I worry about that once we try to handle
3038                  * that.
3039                  */
3040                 evt->lpos = (evt->lpos + 4) % evt->length;
3041                 left -= 4;
3042         }
3043
3044         evt->count = 0;
3045         evt->flags &= ~DWC3_EVENT_PENDING;
3046         ret = IRQ_HANDLED;
3047
3048         /* Unmask interrupt */
3049         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3050         reg &= ~DWC3_GEVNTSIZ_INTMASK;
3051         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3052
3053         if (dwc->imod_interval) {
3054                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3055                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3056         }
3057
3058         return ret;
3059 }
3060
3061 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3062 {
3063         struct dwc3_event_buffer *evt = _evt;
3064         struct dwc3 *dwc = evt->dwc;
3065         unsigned long flags;
3066         irqreturn_t ret = IRQ_NONE;
3067
3068         spin_lock_irqsave(&dwc->lock, flags);
3069         ret = dwc3_process_event_buf(evt);
3070         spin_unlock_irqrestore(&dwc->lock, flags);
3071
3072         return ret;
3073 }
3074
3075 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3076 {
3077         struct dwc3 *dwc = evt->dwc;
3078         u32 amount;
3079         u32 count;
3080         u32 reg;
3081
3082         if (pm_runtime_suspended(dwc->dev)) {
3083                 pm_runtime_get(dwc->dev);
3084                 disable_irq_nosync(dwc->irq_gadget);
3085                 dwc->pending_events = true;
3086                 return IRQ_HANDLED;
3087         }
3088
3089         /*
3090          * With PCIe legacy interrupt, test shows that top-half irq handler can
3091          * be called again after HW interrupt deassertion. Check if bottom-half
3092          * irq event handler completes before caching new event to prevent
3093          * losing events.
3094          */
3095         if (evt->flags & DWC3_EVENT_PENDING)
3096                 return IRQ_HANDLED;
3097
3098         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3099         count &= DWC3_GEVNTCOUNT_MASK;
3100         if (!count)
3101                 return IRQ_NONE;
3102
3103         evt->count = count;
3104         evt->flags |= DWC3_EVENT_PENDING;
3105
3106         /* Mask interrupt */
3107         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3108         reg |= DWC3_GEVNTSIZ_INTMASK;
3109         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3110
3111         amount = min(count, evt->length - evt->lpos);
3112         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3113
3114         if (amount < count)
3115                 memcpy(evt->cache, evt->buf, count - amount);
3116
3117         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3118
3119         return IRQ_WAKE_THREAD;
3120 }
3121
3122 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3123 {
3124         struct dwc3_event_buffer        *evt = _evt;
3125
3126         return dwc3_check_event_buf(evt);
3127 }
3128
3129 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3130 {
3131         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3132         int irq;
3133
3134         irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3135         if (irq > 0)
3136                 goto out;
3137
3138         if (irq == -EPROBE_DEFER)
3139                 goto out;
3140
3141         irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3142         if (irq > 0)
3143                 goto out;
3144
3145         if (irq == -EPROBE_DEFER)
3146                 goto out;
3147
3148         irq = platform_get_irq(dwc3_pdev, 0);
3149         if (irq > 0)
3150                 goto out;
3151
3152         if (irq != -EPROBE_DEFER)
3153                 dev_err(dwc->dev, "missing peripheral IRQ\n");
3154
3155         if (!irq)
3156                 irq = -EINVAL;
3157
3158 out:
3159         return irq;
3160 }
3161
3162 /**
3163  * dwc3_gadget_init - initializes gadget related registers
3164  * @dwc: pointer to our controller context structure
3165  *
3166  * Returns 0 on success otherwise negative errno.
3167  */
3168 int dwc3_gadget_init(struct dwc3 *dwc)
3169 {
3170         int ret;
3171         int irq;
3172
3173         irq = dwc3_gadget_get_irq(dwc);
3174         if (irq < 0) {
3175                 ret = irq;
3176                 goto err0;
3177         }
3178
3179         dwc->irq_gadget = irq;
3180
3181         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3182                                           sizeof(*dwc->ep0_trb) * 2,
3183                                           &dwc->ep0_trb_addr, GFP_KERNEL);
3184         if (!dwc->ep0_trb) {
3185                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3186                 ret = -ENOMEM;
3187                 goto err0;
3188         }
3189
3190         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3191         if (!dwc->setup_buf) {
3192                 ret = -ENOMEM;
3193                 goto err1;
3194         }
3195
3196         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3197                         &dwc->bounce_addr, GFP_KERNEL);
3198         if (!dwc->bounce) {
3199                 ret = -ENOMEM;
3200                 goto err2;
3201         }
3202
3203         init_completion(&dwc->ep0_in_setup);
3204
3205         dwc->gadget.ops                 = &dwc3_gadget_ops;
3206         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
3207         dwc->gadget.sg_supported        = true;
3208         dwc->gadget.name                = "dwc3-gadget";
3209         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
3210
3211         /*
3212          * FIXME We might be setting max_speed to <SUPER, however versions
3213          * <2.20a of dwc3 have an issue with metastability (documented
3214          * elsewhere in this driver) which tells us we can't set max speed to
3215          * anything lower than SUPER.
3216          *
3217          * Because gadget.max_speed is only used by composite.c and function
3218          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3219          * to happen so we avoid sending SuperSpeed Capability descriptor
3220          * together with our BOS descriptor as that could confuse host into
3221          * thinking we can handle super speed.
3222          *
3223          * Note that, in fact, we won't even support GetBOS requests when speed
3224          * is less than super speed because we don't have means, yet, to tell
3225          * composite.c that we are USB 2.0 + LPM ECN.
3226          */
3227         if (dwc->revision < DWC3_REVISION_220A)
3228                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3229                                 dwc->revision);
3230
3231         dwc->gadget.max_speed           = dwc->maximum_speed;
3232
3233         /*
3234          * REVISIT: Here we should clear all pending IRQs to be
3235          * sure we're starting from a well known location.
3236          */
3237
3238         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3239         if (ret)
3240                 goto err3;
3241
3242         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3243         if (ret) {
3244                 dev_err(dwc->dev, "failed to register udc\n");
3245                 goto err4;
3246         }
3247
3248         return 0;
3249
3250 err4:
3251         dwc3_gadget_free_endpoints(dwc);
3252
3253 err3:
3254         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3255                         dwc->bounce_addr);
3256
3257 err2:
3258         kfree(dwc->setup_buf);
3259
3260 err1:
3261         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3262                         dwc->ep0_trb, dwc->ep0_trb_addr);
3263
3264 err0:
3265         return ret;
3266 }
3267
3268 /* -------------------------------------------------------------------------- */
3269
3270 void dwc3_gadget_exit(struct dwc3 *dwc)
3271 {
3272         usb_del_gadget_udc(&dwc->gadget);
3273         dwc3_gadget_free_endpoints(dwc);
3274         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3275                           dwc->bounce_addr);
3276         kfree(dwc->setup_buf);
3277         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3278                           dwc->ep0_trb, dwc->ep0_trb_addr);
3279 }
3280
3281 int dwc3_gadget_suspend(struct dwc3 *dwc)
3282 {
3283         if (!dwc->gadget_driver)
3284                 return 0;
3285
3286         dwc3_gadget_run_stop(dwc, false, false);
3287         dwc3_disconnect_gadget(dwc);
3288         __dwc3_gadget_stop(dwc);
3289
3290         return 0;
3291 }
3292
3293 int dwc3_gadget_resume(struct dwc3 *dwc)
3294 {
3295         int                     ret;
3296
3297         if (!dwc->gadget_driver)
3298                 return 0;
3299
3300         ret = __dwc3_gadget_start(dwc);
3301         if (ret < 0)
3302                 goto err0;
3303
3304         ret = dwc3_gadget_run_stop(dwc, true, false);
3305         if (ret < 0)
3306                 goto err1;
3307
3308         return 0;
3309
3310 err1:
3311         __dwc3_gadget_stop(dwc);
3312
3313 err0:
3314         return ret;
3315 }
3316
3317 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3318 {
3319         if (dwc->pending_events) {
3320                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3321                 dwc->pending_events = false;
3322                 enable_irq(dwc->irq_gadget);
3323         }
3324 }