Merge tag 'usb-4.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
[sfrench/cifs-2.6.git] / drivers / usb / dwc3 / gadget.c
1 /**
2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2  of
11  * the License as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32
33 #include "debug.h"
34 #include "core.h"
35 #include "gadget.h"
36 #include "io.h"
37
38 /**
39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40  * @dwc: pointer to our context structure
41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42  *
43  * Caller should take care of locking. This function will
44  * return 0 on success or -EINVAL if wrong Test Selector
45  * is passed
46  */
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48 {
49         u32             reg;
50
51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54         switch (mode) {
55         case TEST_J:
56         case TEST_K:
57         case TEST_SE0_NAK:
58         case TEST_PACKET:
59         case TEST_FORCE_EN:
60                 reg |= mode << 1;
61                 break;
62         default:
63                 return -EINVAL;
64         }
65
66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68         return 0;
69 }
70
71 /**
72  * dwc3_gadget_get_link_state - Gets current state of USB Link
73  * @dwc: pointer to our context structure
74  *
75  * Caller should take care of locking. This function will
76  * return the link state on success (>= 0) or -ETIMEDOUT.
77  */
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79 {
80         u32             reg;
81
82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84         return DWC3_DSTS_USBLNKST(reg);
85 }
86
87 /**
88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89  * @dwc: pointer to our context structure
90  * @state: the state to put link into
91  *
92  * Caller should take care of locking. This function will
93  * return 0 on success or -ETIMEDOUT.
94  */
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96 {
97         int             retries = 10000;
98         u32             reg;
99
100         /*
101          * Wait until device controller is ready. Only applies to 1.94a and
102          * later RTL.
103          */
104         if (dwc->revision >= DWC3_REVISION_194A) {
105                 while (--retries) {
106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107                         if (reg & DWC3_DSTS_DCNRD)
108                                 udelay(5);
109                         else
110                                 break;
111                 }
112
113                 if (retries <= 0)
114                         return -ETIMEDOUT;
115         }
116
117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120         /* set requested state */
121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
124         /*
125          * The following code is racy when called from dwc3_gadget_wakeup,
126          * and is not needed, at least on newer versions
127          */
128         if (dwc->revision >= DWC3_REVISION_194A)
129                 return 0;
130
131         /* wait for a change in DSTS */
132         retries = 10000;
133         while (--retries) {
134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
136                 if (DWC3_DSTS_USBLNKST(reg) == state)
137                         return 0;
138
139                 udelay(5);
140         }
141
142         return -ETIMEDOUT;
143 }
144
145 /**
146  * dwc3_ep_inc_trb() - Increment a TRB index.
147  * @index - Pointer to the TRB index to increment.
148  *
149  * The index should never point to the link TRB. After incrementing,
150  * if it is point to the link TRB, wrap around to the beginning. The
151  * link TRB is always at the last TRB entry.
152  */
153 static void dwc3_ep_inc_trb(u8 *index)
154 {
155         (*index)++;
156         if (*index == (DWC3_TRB_NUM - 1))
157                 *index = 0;
158 }
159
160 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
161 {
162         dwc3_ep_inc_trb(&dep->trb_enqueue);
163 }
164
165 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
166 {
167         dwc3_ep_inc_trb(&dep->trb_dequeue);
168 }
169
170 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171                 int status)
172 {
173         struct dwc3                     *dwc = dep->dwc;
174
175         req->started = false;
176         list_del(&req->list);
177         req->trb = NULL;
178         req->remaining = 0;
179
180         if (req->request.status == -EINPROGRESS)
181                 req->request.status = status;
182
183         if (dwc->ep0_bounced && dep->number <= 1)
184                 dwc->ep0_bounced = false;
185
186         usb_gadget_unmap_request_by_dev(dwc->sysdev,
187                         &req->request, req->direction);
188
189         trace_dwc3_gadget_giveback(req);
190
191         spin_unlock(&dwc->lock);
192         usb_gadget_giveback_request(&dep->endpoint, &req->request);
193         spin_lock(&dwc->lock);
194
195         if (dep->number > 1)
196                 pm_runtime_put(dwc->dev);
197 }
198
199 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
200 {
201         u32             timeout = 500;
202         int             status = 0;
203         int             ret = 0;
204         u32             reg;
205
206         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
207         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
208
209         do {
210                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
211                 if (!(reg & DWC3_DGCMD_CMDACT)) {
212                         status = DWC3_DGCMD_STATUS(reg);
213                         if (status)
214                                 ret = -EINVAL;
215                         break;
216                 }
217         } while (--timeout);
218
219         if (!timeout) {
220                 ret = -ETIMEDOUT;
221                 status = -ETIMEDOUT;
222         }
223
224         trace_dwc3_gadget_generic_cmd(cmd, param, status);
225
226         return ret;
227 }
228
229 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
230
231 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
232                 struct dwc3_gadget_ep_cmd_params *params)
233 {
234         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
235         struct dwc3             *dwc = dep->dwc;
236         u32                     timeout = 500;
237         u32                     reg;
238
239         int                     cmd_status = 0;
240         int                     susphy = false;
241         int                     ret = -EINVAL;
242
243         /*
244          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
245          * we're issuing an endpoint command, we must check if
246          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
247          *
248          * We will also set SUSPHY bit to what it was before returning as stated
249          * by the same section on Synopsys databook.
250          */
251         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
252                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
253                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
254                         susphy = true;
255                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
256                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
257                 }
258         }
259
260         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
261                 int             needs_wakeup;
262
263                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
264                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
265                                 dwc->link_state == DWC3_LINK_STATE_U3);
266
267                 if (unlikely(needs_wakeup)) {
268                         ret = __dwc3_gadget_wakeup(dwc);
269                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
270                                         ret);
271                 }
272         }
273
274         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
275         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
276         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
277
278         /*
279          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
280          * not relying on XferNotReady, we can make use of a special "No
281          * Response Update Transfer" command where we should clear both CmdAct
282          * and CmdIOC bits.
283          *
284          * With this, we don't need to wait for command completion and can
285          * straight away issue further commands to the endpoint.
286          *
287          * NOTICE: We're making an assumption that control endpoints will never
288          * make use of Update Transfer command. This is a safe assumption
289          * because we can never have more than one request at a time with
290          * Control Endpoints. If anybody changes that assumption, this chunk
291          * needs to be updated accordingly.
292          */
293         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
294                         !usb_endpoint_xfer_isoc(desc))
295                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
296         else
297                 cmd |= DWC3_DEPCMD_CMDACT;
298
299         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
300         do {
301                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
302                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
303                         cmd_status = DWC3_DEPCMD_STATUS(reg);
304
305                         switch (cmd_status) {
306                         case 0:
307                                 ret = 0;
308                                 break;
309                         case DEPEVT_TRANSFER_NO_RESOURCE:
310                                 ret = -EINVAL;
311                                 break;
312                         case DEPEVT_TRANSFER_BUS_EXPIRY:
313                                 /*
314                                  * SW issues START TRANSFER command to
315                                  * isochronous ep with future frame interval. If
316                                  * future interval time has already passed when
317                                  * core receives the command, it will respond
318                                  * with an error status of 'Bus Expiry'.
319                                  *
320                                  * Instead of always returning -EINVAL, let's
321                                  * give a hint to the gadget driver that this is
322                                  * the case by returning -EAGAIN.
323                                  */
324                                 ret = -EAGAIN;
325                                 break;
326                         default:
327                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
328                         }
329
330                         break;
331                 }
332         } while (--timeout);
333
334         if (timeout == 0) {
335                 ret = -ETIMEDOUT;
336                 cmd_status = -ETIMEDOUT;
337         }
338
339         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
340
341         if (ret == 0) {
342                 switch (DWC3_DEPCMD_CMD(cmd)) {
343                 case DWC3_DEPCMD_STARTTRANSFER:
344                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
345                         break;
346                 case DWC3_DEPCMD_ENDTRANSFER:
347                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
348                         break;
349                 default:
350                         /* nothing */
351                         break;
352                 }
353         }
354
355         if (unlikely(susphy)) {
356                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
357                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
358                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
359         }
360
361         return ret;
362 }
363
364 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
365 {
366         struct dwc3 *dwc = dep->dwc;
367         struct dwc3_gadget_ep_cmd_params params;
368         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
369
370         /*
371          * As of core revision 2.60a the recommended programming model
372          * is to set the ClearPendIN bit when issuing a Clear Stall EP
373          * command for IN endpoints. This is to prevent an issue where
374          * some (non-compliant) hosts may not send ACK TPs for pending
375          * IN transfers due to a mishandled error condition. Synopsys
376          * STAR 9000614252.
377          */
378         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
379             (dwc->gadget.speed >= USB_SPEED_SUPER))
380                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
381
382         memset(&params, 0, sizeof(params));
383
384         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
385 }
386
387 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
388                 struct dwc3_trb *trb)
389 {
390         u32             offset = (char *) trb - (char *) dep->trb_pool;
391
392         return dep->trb_pool_dma + offset;
393 }
394
395 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
396 {
397         struct dwc3             *dwc = dep->dwc;
398
399         if (dep->trb_pool)
400                 return 0;
401
402         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
403                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
404                         &dep->trb_pool_dma, GFP_KERNEL);
405         if (!dep->trb_pool) {
406                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
407                                 dep->name);
408                 return -ENOMEM;
409         }
410
411         return 0;
412 }
413
414 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
415 {
416         struct dwc3             *dwc = dep->dwc;
417
418         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
419                         dep->trb_pool, dep->trb_pool_dma);
420
421         dep->trb_pool = NULL;
422         dep->trb_pool_dma = 0;
423 }
424
425 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
426
427 /**
428  * dwc3_gadget_start_config - Configure EP resources
429  * @dwc: pointer to our controller context structure
430  * @dep: endpoint that is being enabled
431  *
432  * The assignment of transfer resources cannot perfectly follow the
433  * data book due to the fact that the controller driver does not have
434  * all knowledge of the configuration in advance. It is given this
435  * information piecemeal by the composite gadget framework after every
436  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
437  * programming model in this scenario can cause errors. For two
438  * reasons:
439  *
440  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
441  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
442  * multiple interfaces.
443  *
444  * 2) The databook does not mention doing more DEPXFERCFG for new
445  * endpoint on alt setting (8.1.6).
446  *
447  * The following simplified method is used instead:
448  *
449  * All hardware endpoints can be assigned a transfer resource and this
450  * setting will stay persistent until either a core reset or
451  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
452  * do DEPXFERCFG for every hardware endpoint as well. We are
453  * guaranteed that there are as many transfer resources as endpoints.
454  *
455  * This function is called for each endpoint when it is being enabled
456  * but is triggered only when called for EP0-out, which always happens
457  * first, and which should only happen in one of the above conditions.
458  */
459 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
460 {
461         struct dwc3_gadget_ep_cmd_params params;
462         u32                     cmd;
463         int                     i;
464         int                     ret;
465
466         if (dep->number)
467                 return 0;
468
469         memset(&params, 0x00, sizeof(params));
470         cmd = DWC3_DEPCMD_DEPSTARTCFG;
471
472         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
473         if (ret)
474                 return ret;
475
476         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
477                 struct dwc3_ep *dep = dwc->eps[i];
478
479                 if (!dep)
480                         continue;
481
482                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
483                 if (ret)
484                         return ret;
485         }
486
487         return 0;
488 }
489
490 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
491                 bool modify, bool restore)
492 {
493         const struct usb_ss_ep_comp_descriptor *comp_desc;
494         const struct usb_endpoint_descriptor *desc;
495         struct dwc3_gadget_ep_cmd_params params;
496
497         if (dev_WARN_ONCE(dwc->dev, modify && restore,
498                                         "Can't modify and restore\n"))
499                 return -EINVAL;
500
501         comp_desc = dep->endpoint.comp_desc;
502         desc = dep->endpoint.desc;
503
504         memset(&params, 0x00, sizeof(params));
505
506         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
507                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
508
509         /* Burst size is only needed in SuperSpeed mode */
510         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
511                 u32 burst = dep->endpoint.maxburst;
512                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
513         }
514
515         if (modify) {
516                 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
517         } else if (restore) {
518                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
519                 params.param2 |= dep->saved_state;
520         } else {
521                 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
522         }
523
524         if (usb_endpoint_xfer_control(desc))
525                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
526
527         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
528                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
529
530         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
531                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
532                         | DWC3_DEPCFG_STREAM_EVENT_EN;
533                 dep->stream_capable = true;
534         }
535
536         if (!usb_endpoint_xfer_control(desc))
537                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
538
539         /*
540          * We are doing 1:1 mapping for endpoints, meaning
541          * Physical Endpoints 2 maps to Logical Endpoint 2 and
542          * so on. We consider the direction bit as part of the physical
543          * endpoint number. So USB endpoint 0x81 is 0x03.
544          */
545         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
546
547         /*
548          * We must use the lower 16 TX FIFOs even though
549          * HW might have more
550          */
551         if (dep->direction)
552                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
553
554         if (desc->bInterval) {
555                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
556                 dep->interval = 1 << (desc->bInterval - 1);
557         }
558
559         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
560 }
561
562 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
563 {
564         struct dwc3_gadget_ep_cmd_params params;
565
566         memset(&params, 0x00, sizeof(params));
567
568         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
569
570         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
571                         &params);
572 }
573
574 /**
575  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
576  * @dep: endpoint to be initialized
577  * @desc: USB Endpoint Descriptor
578  *
579  * Caller should take care of locking
580  */
581 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
582                 bool modify, bool restore)
583 {
584         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
585         struct dwc3             *dwc = dep->dwc;
586
587         u32                     reg;
588         int                     ret;
589
590         if (!(dep->flags & DWC3_EP_ENABLED)) {
591                 ret = dwc3_gadget_start_config(dwc, dep);
592                 if (ret)
593                         return ret;
594         }
595
596         ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
597         if (ret)
598                 return ret;
599
600         if (!(dep->flags & DWC3_EP_ENABLED)) {
601                 struct dwc3_trb *trb_st_hw;
602                 struct dwc3_trb *trb_link;
603
604                 dep->type = usb_endpoint_type(desc);
605                 dep->flags |= DWC3_EP_ENABLED;
606                 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
607
608                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
609                 reg |= DWC3_DALEPENA_EP(dep->number);
610                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
611
612                 init_waitqueue_head(&dep->wait_end_transfer);
613
614                 if (usb_endpoint_xfer_control(desc))
615                         goto out;
616
617                 /* Initialize the TRB ring */
618                 dep->trb_dequeue = 0;
619                 dep->trb_enqueue = 0;
620                 memset(dep->trb_pool, 0,
621                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
622
623                 /* Link TRB. The HWO bit is never reset */
624                 trb_st_hw = &dep->trb_pool[0];
625
626                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
627                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
628                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
629                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
630                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
631         }
632
633         /*
634          * Issue StartTransfer here with no-op TRB so we can always rely on No
635          * Response Update Transfer command.
636          */
637         if (usb_endpoint_xfer_bulk(desc)) {
638                 struct dwc3_gadget_ep_cmd_params params;
639                 struct dwc3_trb *trb;
640                 dma_addr_t trb_dma;
641                 u32 cmd;
642
643                 memset(&params, 0, sizeof(params));
644                 trb = &dep->trb_pool[0];
645                 trb_dma = dwc3_trb_dma_offset(dep, trb);
646
647                 params.param0 = upper_32_bits(trb_dma);
648                 params.param1 = lower_32_bits(trb_dma);
649
650                 cmd = DWC3_DEPCMD_STARTTRANSFER;
651
652                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
653                 if (ret < 0)
654                         return ret;
655
656                 dep->flags |= DWC3_EP_BUSY;
657
658                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
659                 WARN_ON_ONCE(!dep->resource_index);
660         }
661
662
663 out:
664         trace_dwc3_gadget_ep_enable(dep);
665
666         return 0;
667 }
668
669 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
670 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
671 {
672         struct dwc3_request             *req;
673
674         dwc3_stop_active_transfer(dwc, dep->number, true);
675
676         /* - giveback all requests to gadget driver */
677         while (!list_empty(&dep->started_list)) {
678                 req = next_request(&dep->started_list);
679
680                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
681         }
682
683         while (!list_empty(&dep->pending_list)) {
684                 req = next_request(&dep->pending_list);
685
686                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
687         }
688 }
689
690 /**
691  * __dwc3_gadget_ep_disable - Disables a HW endpoint
692  * @dep: the endpoint to disable
693  *
694  * This function also removes requests which are currently processed ny the
695  * hardware and those which are not yet scheduled.
696  * Caller should take care of locking.
697  */
698 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
699 {
700         struct dwc3             *dwc = dep->dwc;
701         u32                     reg;
702
703         trace_dwc3_gadget_ep_disable(dep);
704
705         dwc3_remove_requests(dwc, dep);
706
707         /* make sure HW endpoint isn't stalled */
708         if (dep->flags & DWC3_EP_STALL)
709                 __dwc3_gadget_ep_set_halt(dep, 0, false);
710
711         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
712         reg &= ~DWC3_DALEPENA_EP(dep->number);
713         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
714
715         dep->stream_capable = false;
716         dep->type = 0;
717         dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
718
719         /* Clear out the ep descriptors for non-ep0 */
720         if (dep->number > 1) {
721                 dep->endpoint.comp_desc = NULL;
722                 dep->endpoint.desc = NULL;
723         }
724
725         return 0;
726 }
727
728 /* -------------------------------------------------------------------------- */
729
730 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
731                 const struct usb_endpoint_descriptor *desc)
732 {
733         return -EINVAL;
734 }
735
736 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
737 {
738         return -EINVAL;
739 }
740
741 /* -------------------------------------------------------------------------- */
742
743 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
744                 const struct usb_endpoint_descriptor *desc)
745 {
746         struct dwc3_ep                  *dep;
747         struct dwc3                     *dwc;
748         unsigned long                   flags;
749         int                             ret;
750
751         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
752                 pr_debug("dwc3: invalid parameters\n");
753                 return -EINVAL;
754         }
755
756         if (!desc->wMaxPacketSize) {
757                 pr_debug("dwc3: missing wMaxPacketSize\n");
758                 return -EINVAL;
759         }
760
761         dep = to_dwc3_ep(ep);
762         dwc = dep->dwc;
763
764         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
765                                         "%s is already enabled\n",
766                                         dep->name))
767                 return 0;
768
769         spin_lock_irqsave(&dwc->lock, flags);
770         ret = __dwc3_gadget_ep_enable(dep, false, false);
771         spin_unlock_irqrestore(&dwc->lock, flags);
772
773         return ret;
774 }
775
776 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
777 {
778         struct dwc3_ep                  *dep;
779         struct dwc3                     *dwc;
780         unsigned long                   flags;
781         int                             ret;
782
783         if (!ep) {
784                 pr_debug("dwc3: invalid parameters\n");
785                 return -EINVAL;
786         }
787
788         dep = to_dwc3_ep(ep);
789         dwc = dep->dwc;
790
791         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
792                                         "%s is already disabled\n",
793                                         dep->name))
794                 return 0;
795
796         spin_lock_irqsave(&dwc->lock, flags);
797         ret = __dwc3_gadget_ep_disable(dep);
798         spin_unlock_irqrestore(&dwc->lock, flags);
799
800         return ret;
801 }
802
803 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
804         gfp_t gfp_flags)
805 {
806         struct dwc3_request             *req;
807         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
808
809         req = kzalloc(sizeof(*req), gfp_flags);
810         if (!req)
811                 return NULL;
812
813         req->epnum      = dep->number;
814         req->dep        = dep;
815
816         dep->allocated_requests++;
817
818         trace_dwc3_alloc_request(req);
819
820         return &req->request;
821 }
822
823 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
824                 struct usb_request *request)
825 {
826         struct dwc3_request             *req = to_dwc3_request(request);
827         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
828
829         dep->allocated_requests--;
830         trace_dwc3_free_request(req);
831         kfree(req);
832 }
833
834 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
835
836 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
837                 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
838                 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
839 {
840         struct dwc3             *dwc = dep->dwc;
841         struct usb_gadget       *gadget = &dwc->gadget;
842         enum usb_device_speed   speed = gadget->speed;
843
844         dwc3_ep_inc_enq(dep);
845
846         trb->size = DWC3_TRB_SIZE_LENGTH(length);
847         trb->bpl = lower_32_bits(dma);
848         trb->bph = upper_32_bits(dma);
849
850         switch (usb_endpoint_type(dep->endpoint.desc)) {
851         case USB_ENDPOINT_XFER_CONTROL:
852                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
853                 break;
854
855         case USB_ENDPOINT_XFER_ISOC:
856                 if (!node) {
857                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
858
859                         if (speed == USB_SPEED_HIGH) {
860                                 struct usb_ep *ep = &dep->endpoint;
861                                 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
862                         }
863                 } else {
864                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
865                 }
866
867                 /* always enable Interrupt on Missed ISOC */
868                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
869                 break;
870
871         case USB_ENDPOINT_XFER_BULK:
872         case USB_ENDPOINT_XFER_INT:
873                 trb->ctrl = DWC3_TRBCTL_NORMAL;
874                 break;
875         default:
876                 /*
877                  * This is only possible with faulty memory because we
878                  * checked it already :)
879                  */
880                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
881                                 usb_endpoint_type(dep->endpoint.desc));
882         }
883
884         /* always enable Continue on Short Packet */
885         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
886                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
887
888                 if (short_not_ok)
889                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
890         }
891
892         if ((!no_interrupt && !chain) ||
893                         (dwc3_calc_trbs_left(dep) == 0))
894                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
895
896         if (chain)
897                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
898
899         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
900                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
901
902         trb->ctrl |= DWC3_TRB_CTRL_HWO;
903
904         trace_dwc3_prepare_trb(dep, trb);
905 }
906
907 /**
908  * dwc3_prepare_one_trb - setup one TRB from one request
909  * @dep: endpoint for which this request is prepared
910  * @req: dwc3_request pointer
911  * @chain: should this TRB be chained to the next?
912  * @node: only for isochronous endpoints. First TRB needs different type.
913  */
914 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
915                 struct dwc3_request *req, unsigned chain, unsigned node)
916 {
917         struct dwc3_trb         *trb;
918         unsigned                length = req->request.length;
919         unsigned                stream_id = req->request.stream_id;
920         unsigned                short_not_ok = req->request.short_not_ok;
921         unsigned                no_interrupt = req->request.no_interrupt;
922         dma_addr_t              dma = req->request.dma;
923
924         trb = &dep->trb_pool[dep->trb_enqueue];
925
926         if (!req->trb) {
927                 dwc3_gadget_move_started_request(req);
928                 req->trb = trb;
929                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
930                 dep->queued_requests++;
931         }
932
933         __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
934                         stream_id, short_not_ok, no_interrupt);
935 }
936
937 /**
938  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
939  * @dep: The endpoint with the TRB ring
940  * @index: The index of the current TRB in the ring
941  *
942  * Returns the TRB prior to the one pointed to by the index. If the
943  * index is 0, we will wrap backwards, skip the link TRB, and return
944  * the one just before that.
945  */
946 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
947 {
948         u8 tmp = index;
949
950         if (!tmp)
951                 tmp = DWC3_TRB_NUM - 1;
952
953         return &dep->trb_pool[tmp - 1];
954 }
955
956 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
957 {
958         struct dwc3_trb         *tmp;
959         struct dwc3             *dwc = dep->dwc;
960         u8                      trbs_left;
961
962         /*
963          * If enqueue & dequeue are equal than it is either full or empty.
964          *
965          * One way to know for sure is if the TRB right before us has HWO bit
966          * set or not. If it has, then we're definitely full and can't fit any
967          * more transfers in our ring.
968          */
969         if (dep->trb_enqueue == dep->trb_dequeue) {
970                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
971                 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
972                                   "%s No TRBS left\n", dep->name))
973                         return 0;
974
975                 return DWC3_TRB_NUM - 1;
976         }
977
978         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
979         trbs_left &= (DWC3_TRB_NUM - 1);
980
981         if (dep->trb_dequeue < dep->trb_enqueue)
982                 trbs_left--;
983
984         return trbs_left;
985 }
986
987 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
988                 struct dwc3_request *req)
989 {
990         struct scatterlist *sg = req->sg;
991         struct scatterlist *s;
992         int             i;
993
994         for_each_sg(sg, s, req->num_pending_sgs, i) {
995                 unsigned int length = req->request.length;
996                 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
997                 unsigned int rem = length % maxp;
998                 unsigned chain = true;
999
1000                 if (sg_is_last(s))
1001                         chain = false;
1002
1003                 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1004                         struct dwc3     *dwc = dep->dwc;
1005                         struct dwc3_trb *trb;
1006
1007                         req->unaligned = true;
1008
1009                         /* prepare normal TRB */
1010                         dwc3_prepare_one_trb(dep, req, true, i);
1011
1012                         /* Now prepare one extra TRB to align transfer size */
1013                         trb = &dep->trb_pool[dep->trb_enqueue];
1014                         __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1015                                         maxp - rem, false, 0,
1016                                         req->request.stream_id,
1017                                         req->request.short_not_ok,
1018                                         req->request.no_interrupt);
1019                 } else {
1020                         dwc3_prepare_one_trb(dep, req, chain, i);
1021                 }
1022
1023                 if (!dwc3_calc_trbs_left(dep))
1024                         break;
1025         }
1026 }
1027
1028 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1029                 struct dwc3_request *req)
1030 {
1031         unsigned int length = req->request.length;
1032         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1033         unsigned int rem = length % maxp;
1034
1035         if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1036                 struct dwc3     *dwc = dep->dwc;
1037                 struct dwc3_trb *trb;
1038
1039                 req->unaligned = true;
1040
1041                 /* prepare normal TRB */
1042                 dwc3_prepare_one_trb(dep, req, true, 0);
1043
1044                 /* Now prepare one extra TRB to align transfer size */
1045                 trb = &dep->trb_pool[dep->trb_enqueue];
1046                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1047                                 false, 0, req->request.stream_id,
1048                                 req->request.short_not_ok,
1049                                 req->request.no_interrupt);
1050         } else {
1051                 dwc3_prepare_one_trb(dep, req, false, 0);
1052         }
1053 }
1054
1055 /*
1056  * dwc3_prepare_trbs - setup TRBs from requests
1057  * @dep: endpoint for which requests are being prepared
1058  *
1059  * The function goes through the requests list and sets up TRBs for the
1060  * transfers. The function returns once there are no more TRBs available or
1061  * it runs out of requests.
1062  */
1063 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1064 {
1065         struct dwc3_request     *req, *n;
1066
1067         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1068
1069         if (!dwc3_calc_trbs_left(dep))
1070                 return;
1071
1072         /*
1073          * We can get in a situation where there's a request in the started list
1074          * but there weren't enough TRBs to fully kick it in the first time
1075          * around, so it has been waiting for more TRBs to be freed up.
1076          *
1077          * In that case, we should check if we have a request with pending_sgs
1078          * in the started list and prepare TRBs for that request first,
1079          * otherwise we will prepare TRBs completely out of order and that will
1080          * break things.
1081          */
1082         list_for_each_entry(req, &dep->started_list, list) {
1083                 if (req->num_pending_sgs > 0)
1084                         dwc3_prepare_one_trb_sg(dep, req);
1085
1086                 if (!dwc3_calc_trbs_left(dep))
1087                         return;
1088         }
1089
1090         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1091                 if (req->num_pending_sgs > 0)
1092                         dwc3_prepare_one_trb_sg(dep, req);
1093                 else
1094                         dwc3_prepare_one_trb_linear(dep, req);
1095
1096                 if (!dwc3_calc_trbs_left(dep))
1097                         return;
1098         }
1099 }
1100
1101 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1102 {
1103         struct dwc3_gadget_ep_cmd_params params;
1104         struct dwc3_request             *req;
1105         int                             starting;
1106         int                             ret;
1107         u32                             cmd;
1108
1109         starting = !(dep->flags & DWC3_EP_BUSY);
1110
1111         dwc3_prepare_trbs(dep);
1112         req = next_request(&dep->started_list);
1113         if (!req) {
1114                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1115                 return 0;
1116         }
1117
1118         memset(&params, 0, sizeof(params));
1119
1120         if (starting) {
1121                 params.param0 = upper_32_bits(req->trb_dma);
1122                 params.param1 = lower_32_bits(req->trb_dma);
1123                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1124                         DWC3_DEPCMD_PARAM(cmd_param);
1125         } else {
1126                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1127                         DWC3_DEPCMD_PARAM(dep->resource_index);
1128         }
1129
1130         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1131         if (ret < 0) {
1132                 /*
1133                  * FIXME we need to iterate over the list of requests
1134                  * here and stop, unmap, free and del each of the linked
1135                  * requests instead of what we do now.
1136                  */
1137                 if (req->trb)
1138                         memset(req->trb, 0, sizeof(struct dwc3_trb));
1139                 dep->queued_requests--;
1140                 dwc3_gadget_giveback(dep, req, ret);
1141                 return ret;
1142         }
1143
1144         dep->flags |= DWC3_EP_BUSY;
1145
1146         if (starting) {
1147                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1148                 WARN_ON_ONCE(!dep->resource_index);
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1155 {
1156         u32                     reg;
1157
1158         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1159         return DWC3_DSTS_SOFFN(reg);
1160 }
1161
1162 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1163                 struct dwc3_ep *dep, u32 cur_uf)
1164 {
1165         u32 uf;
1166
1167         if (list_empty(&dep->pending_list)) {
1168                 dev_info(dwc->dev, "%s: ran out of requests\n",
1169                                 dep->name);
1170                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1171                 return;
1172         }
1173
1174         /* 4 micro frames in the future */
1175         uf = cur_uf + dep->interval * 4;
1176
1177         __dwc3_gadget_kick_transfer(dep, uf);
1178 }
1179
1180 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1181                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1182 {
1183         u32 cur_uf, mask;
1184
1185         mask = ~(dep->interval - 1);
1186         cur_uf = event->parameters & mask;
1187
1188         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1189 }
1190
1191 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1192 {
1193         struct dwc3             *dwc = dep->dwc;
1194         int                     ret;
1195
1196         if (!dep->endpoint.desc) {
1197                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1198                                 dep->name);
1199                 return -ESHUTDOWN;
1200         }
1201
1202         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1203                                 &req->request, req->dep->name)) {
1204                 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1205                                 dep->name, &req->request, req->dep->name);
1206                 return -EINVAL;
1207         }
1208
1209         pm_runtime_get(dwc->dev);
1210
1211         req->request.actual     = 0;
1212         req->request.status     = -EINPROGRESS;
1213         req->direction          = dep->direction;
1214         req->epnum              = dep->number;
1215
1216         trace_dwc3_ep_queue(req);
1217
1218         ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1219                                             dep->direction);
1220         if (ret)
1221                 return ret;
1222
1223         req->sg                 = req->request.sg;
1224         req->num_pending_sgs    = req->request.num_mapped_sgs;
1225
1226         list_add_tail(&req->list, &dep->pending_list);
1227
1228         /*
1229          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1230          * wait for a XferNotReady event so we will know what's the current
1231          * (micro-)frame number.
1232          *
1233          * Without this trick, we are very, very likely gonna get Bus Expiry
1234          * errors which will force us issue EndTransfer command.
1235          */
1236         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1237                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1238                         if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1239                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1240                                 dep->flags = DWC3_EP_ENABLED;
1241                         } else {
1242                                 u32 cur_uf;
1243
1244                                 cur_uf = __dwc3_gadget_get_frame(dwc);
1245                                 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1246                                 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1247                         }
1248                 }
1249                 return 0;
1250         }
1251
1252         if (!dwc3_calc_trbs_left(dep))
1253                 return 0;
1254
1255         ret = __dwc3_gadget_kick_transfer(dep, 0);
1256         if (ret == -EBUSY)
1257                 ret = 0;
1258
1259         return ret;
1260 }
1261
1262 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1263                 struct usb_request *request)
1264 {
1265         dwc3_gadget_ep_free_request(ep, request);
1266 }
1267
1268 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1269 {
1270         struct dwc3_request             *req;
1271         struct usb_request              *request;
1272         struct usb_ep                   *ep = &dep->endpoint;
1273
1274         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1275         if (!request)
1276                 return -ENOMEM;
1277
1278         request->length = 0;
1279         request->buf = dwc->zlp_buf;
1280         request->complete = __dwc3_gadget_ep_zlp_complete;
1281
1282         req = to_dwc3_request(request);
1283
1284         return __dwc3_gadget_ep_queue(dep, req);
1285 }
1286
1287 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1288         gfp_t gfp_flags)
1289 {
1290         struct dwc3_request             *req = to_dwc3_request(request);
1291         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1292         struct dwc3                     *dwc = dep->dwc;
1293
1294         unsigned long                   flags;
1295
1296         int                             ret;
1297
1298         spin_lock_irqsave(&dwc->lock, flags);
1299         ret = __dwc3_gadget_ep_queue(dep, req);
1300
1301         /*
1302          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1303          * setting request->zero, instead of doing magic, we will just queue an
1304          * extra usb_request ourselves so that it gets handled the same way as
1305          * any other request.
1306          */
1307         if (ret == 0 && request->zero && request->length &&
1308             (request->length % ep->maxpacket == 0))
1309                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1310
1311         spin_unlock_irqrestore(&dwc->lock, flags);
1312
1313         return ret;
1314 }
1315
1316 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1317                 struct usb_request *request)
1318 {
1319         struct dwc3_request             *req = to_dwc3_request(request);
1320         struct dwc3_request             *r = NULL;
1321
1322         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1323         struct dwc3                     *dwc = dep->dwc;
1324
1325         unsigned long                   flags;
1326         int                             ret = 0;
1327
1328         trace_dwc3_ep_dequeue(req);
1329
1330         spin_lock_irqsave(&dwc->lock, flags);
1331
1332         list_for_each_entry(r, &dep->pending_list, list) {
1333                 if (r == req)
1334                         break;
1335         }
1336
1337         if (r != req) {
1338                 list_for_each_entry(r, &dep->started_list, list) {
1339                         if (r == req)
1340                                 break;
1341                 }
1342                 if (r == req) {
1343                         /* wait until it is processed */
1344                         dwc3_stop_active_transfer(dwc, dep->number, true);
1345
1346                         /*
1347                          * If request was already started, this means we had to
1348                          * stop the transfer. With that we also need to ignore
1349                          * all TRBs used by the request, however TRBs can only
1350                          * be modified after completion of END_TRANSFER
1351                          * command. So what we do here is that we wait for
1352                          * END_TRANSFER completion and only after that, we jump
1353                          * over TRBs by clearing HWO and incrementing dequeue
1354                          * pointer.
1355                          *
1356                          * Note that we have 2 possible types of transfers here:
1357                          *
1358                          * i) Linear buffer request
1359                          * ii) SG-list based request
1360                          *
1361                          * SG-list based requests will have r->num_pending_sgs
1362                          * set to a valid number (> 0). Linear requests,
1363                          * normally use a single TRB.
1364                          *
1365                          * For each of these two cases, if r->unaligned flag is
1366                          * set, one extra TRB has been used to align transfer
1367                          * size to wMaxPacketSize.
1368                          *
1369                          * All of these cases need to be taken into
1370                          * consideration so we don't mess up our TRB ring
1371                          * pointers.
1372                          */
1373                         wait_event_lock_irq(dep->wait_end_transfer,
1374                                         !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1375                                         dwc->lock);
1376
1377                         if (!r->trb)
1378                                 goto out1;
1379
1380                         if (r->num_pending_sgs) {
1381                                 struct dwc3_trb *trb;
1382                                 int i = 0;
1383
1384                                 for (i = 0; i < r->num_pending_sgs; i++) {
1385                                         trb = r->trb + i;
1386                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1387                                         dwc3_ep_inc_deq(dep);
1388                                 }
1389
1390                                 if (r->unaligned) {
1391                                         trb = r->trb + r->num_pending_sgs + 1;
1392                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1393                                         dwc3_ep_inc_deq(dep);
1394                                 }
1395                         } else {
1396                                 struct dwc3_trb *trb = r->trb;
1397
1398                                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1399                                 dwc3_ep_inc_deq(dep);
1400
1401                                 if (r->unaligned) {
1402                                         trb = r->trb + 1;
1403                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1404                                         dwc3_ep_inc_deq(dep);
1405                                 }
1406                         }
1407                         goto out1;
1408                 }
1409                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1410                                 request, ep->name);
1411                 ret = -EINVAL;
1412                 goto out0;
1413         }
1414
1415 out1:
1416         /* giveback the request */
1417         dep->queued_requests--;
1418         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1419
1420 out0:
1421         spin_unlock_irqrestore(&dwc->lock, flags);
1422
1423         return ret;
1424 }
1425
1426 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1427 {
1428         struct dwc3_gadget_ep_cmd_params        params;
1429         struct dwc3                             *dwc = dep->dwc;
1430         int                                     ret;
1431
1432         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1433                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1434                 return -EINVAL;
1435         }
1436
1437         memset(&params, 0x00, sizeof(params));
1438
1439         if (value) {
1440                 struct dwc3_trb *trb;
1441
1442                 unsigned transfer_in_flight;
1443                 unsigned started;
1444
1445                 if (dep->flags & DWC3_EP_STALL)
1446                         return 0;
1447
1448                 if (dep->number > 1)
1449                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1450                 else
1451                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1452
1453                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1454                 started = !list_empty(&dep->started_list);
1455
1456                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1457                                 (!dep->direction && started))) {
1458                         return -EAGAIN;
1459                 }
1460
1461                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1462                                 &params);
1463                 if (ret)
1464                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1465                                         dep->name);
1466                 else
1467                         dep->flags |= DWC3_EP_STALL;
1468         } else {
1469                 if (!(dep->flags & DWC3_EP_STALL))
1470                         return 0;
1471
1472                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1473                 if (ret)
1474                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1475                                         dep->name);
1476                 else
1477                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1478         }
1479
1480         return ret;
1481 }
1482
1483 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1484 {
1485         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1486         struct dwc3                     *dwc = dep->dwc;
1487
1488         unsigned long                   flags;
1489
1490         int                             ret;
1491
1492         spin_lock_irqsave(&dwc->lock, flags);
1493         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1494         spin_unlock_irqrestore(&dwc->lock, flags);
1495
1496         return ret;
1497 }
1498
1499 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1500 {
1501         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1502         struct dwc3                     *dwc = dep->dwc;
1503         unsigned long                   flags;
1504         int                             ret;
1505
1506         spin_lock_irqsave(&dwc->lock, flags);
1507         dep->flags |= DWC3_EP_WEDGE;
1508
1509         if (dep->number == 0 || dep->number == 1)
1510                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1511         else
1512                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1513         spin_unlock_irqrestore(&dwc->lock, flags);
1514
1515         return ret;
1516 }
1517
1518 /* -------------------------------------------------------------------------- */
1519
1520 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1521         .bLength        = USB_DT_ENDPOINT_SIZE,
1522         .bDescriptorType = USB_DT_ENDPOINT,
1523         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1524 };
1525
1526 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1527         .enable         = dwc3_gadget_ep0_enable,
1528         .disable        = dwc3_gadget_ep0_disable,
1529         .alloc_request  = dwc3_gadget_ep_alloc_request,
1530         .free_request   = dwc3_gadget_ep_free_request,
1531         .queue          = dwc3_gadget_ep0_queue,
1532         .dequeue        = dwc3_gadget_ep_dequeue,
1533         .set_halt       = dwc3_gadget_ep0_set_halt,
1534         .set_wedge      = dwc3_gadget_ep_set_wedge,
1535 };
1536
1537 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1538         .enable         = dwc3_gadget_ep_enable,
1539         .disable        = dwc3_gadget_ep_disable,
1540         .alloc_request  = dwc3_gadget_ep_alloc_request,
1541         .free_request   = dwc3_gadget_ep_free_request,
1542         .queue          = dwc3_gadget_ep_queue,
1543         .dequeue        = dwc3_gadget_ep_dequeue,
1544         .set_halt       = dwc3_gadget_ep_set_halt,
1545         .set_wedge      = dwc3_gadget_ep_set_wedge,
1546 };
1547
1548 /* -------------------------------------------------------------------------- */
1549
1550 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1551 {
1552         struct dwc3             *dwc = gadget_to_dwc(g);
1553
1554         return __dwc3_gadget_get_frame(dwc);
1555 }
1556
1557 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1558 {
1559         int                     retries;
1560
1561         int                     ret;
1562         u32                     reg;
1563
1564         u8                      link_state;
1565         u8                      speed;
1566
1567         /*
1568          * According to the Databook Remote wakeup request should
1569          * be issued only when the device is in early suspend state.
1570          *
1571          * We can check that via USB Link State bits in DSTS register.
1572          */
1573         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1574
1575         speed = reg & DWC3_DSTS_CONNECTSPD;
1576         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1577             (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1578                 return 0;
1579
1580         link_state = DWC3_DSTS_USBLNKST(reg);
1581
1582         switch (link_state) {
1583         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1584         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1585                 break;
1586         default:
1587                 return -EINVAL;
1588         }
1589
1590         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1591         if (ret < 0) {
1592                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1593                 return ret;
1594         }
1595
1596         /* Recent versions do this automatically */
1597         if (dwc->revision < DWC3_REVISION_194A) {
1598                 /* write zeroes to Link Change Request */
1599                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1600                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1601                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1602         }
1603
1604         /* poll until Link State changes to ON */
1605         retries = 20000;
1606
1607         while (retries--) {
1608                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1609
1610                 /* in HS, means ON */
1611                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1612                         break;
1613         }
1614
1615         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1616                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1617                 return -EINVAL;
1618         }
1619
1620         return 0;
1621 }
1622
1623 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1624 {
1625         struct dwc3             *dwc = gadget_to_dwc(g);
1626         unsigned long           flags;
1627         int                     ret;
1628
1629         spin_lock_irqsave(&dwc->lock, flags);
1630         ret = __dwc3_gadget_wakeup(dwc);
1631         spin_unlock_irqrestore(&dwc->lock, flags);
1632
1633         return ret;
1634 }
1635
1636 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1637                 int is_selfpowered)
1638 {
1639         struct dwc3             *dwc = gadget_to_dwc(g);
1640         unsigned long           flags;
1641
1642         spin_lock_irqsave(&dwc->lock, flags);
1643         g->is_selfpowered = !!is_selfpowered;
1644         spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646         return 0;
1647 }
1648
1649 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1650 {
1651         u32                     reg;
1652         u32                     timeout = 500;
1653
1654         if (pm_runtime_suspended(dwc->dev))
1655                 return 0;
1656
1657         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1658         if (is_on) {
1659                 if (dwc->revision <= DWC3_REVISION_187A) {
1660                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1661                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1662                 }
1663
1664                 if (dwc->revision >= DWC3_REVISION_194A)
1665                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1666                 reg |= DWC3_DCTL_RUN_STOP;
1667
1668                 if (dwc->has_hibernation)
1669                         reg |= DWC3_DCTL_KEEP_CONNECT;
1670
1671                 dwc->pullups_connected = true;
1672         } else {
1673                 reg &= ~DWC3_DCTL_RUN_STOP;
1674
1675                 if (dwc->has_hibernation && !suspend)
1676                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1677
1678                 dwc->pullups_connected = false;
1679         }
1680
1681         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1682
1683         do {
1684                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1685                 reg &= DWC3_DSTS_DEVCTRLHLT;
1686         } while (--timeout && !(!is_on ^ !reg));
1687
1688         if (!timeout)
1689                 return -ETIMEDOUT;
1690
1691         return 0;
1692 }
1693
1694 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1695 {
1696         struct dwc3             *dwc = gadget_to_dwc(g);
1697         unsigned long           flags;
1698         int                     ret;
1699
1700         is_on = !!is_on;
1701
1702         /*
1703          * Per databook, when we want to stop the gadget, if a control transfer
1704          * is still in process, complete it and get the core into setup phase.
1705          */
1706         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1707                 reinit_completion(&dwc->ep0_in_setup);
1708
1709                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1710                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1711                 if (ret == 0) {
1712                         dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1713                         return -ETIMEDOUT;
1714                 }
1715         }
1716
1717         spin_lock_irqsave(&dwc->lock, flags);
1718         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1719         spin_unlock_irqrestore(&dwc->lock, flags);
1720
1721         return ret;
1722 }
1723
1724 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1725 {
1726         u32                     reg;
1727
1728         /* Enable all but Start and End of Frame IRQs */
1729         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1730                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1731                         DWC3_DEVTEN_CMDCMPLTEN |
1732                         DWC3_DEVTEN_ERRTICERREN |
1733                         DWC3_DEVTEN_WKUPEVTEN |
1734                         DWC3_DEVTEN_CONNECTDONEEN |
1735                         DWC3_DEVTEN_USBRSTEN |
1736                         DWC3_DEVTEN_DISCONNEVTEN);
1737
1738         if (dwc->revision < DWC3_REVISION_250A)
1739                 reg |= DWC3_DEVTEN_ULSTCNGEN;
1740
1741         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1742 }
1743
1744 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1745 {
1746         /* mask all interrupts */
1747         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1748 }
1749
1750 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1751 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1752
1753 /**
1754  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1755  * dwc: pointer to our context structure
1756  *
1757  * The following looks like complex but it's actually very simple. In order to
1758  * calculate the number of packets we can burst at once on OUT transfers, we're
1759  * gonna use RxFIFO size.
1760  *
1761  * To calculate RxFIFO size we need two numbers:
1762  * MDWIDTH = size, in bits, of the internal memory bus
1763  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1764  *
1765  * Given these two numbers, the formula is simple:
1766  *
1767  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1768  *
1769  * 24 bytes is for 3x SETUP packets
1770  * 16 bytes is a clock domain crossing tolerance
1771  *
1772  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1773  */
1774 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1775 {
1776         u32 ram2_depth;
1777         u32 mdwidth;
1778         u32 nump;
1779         u32 reg;
1780
1781         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1782         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1783
1784         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1785         nump = min_t(u32, nump, 16);
1786
1787         /* update NumP */
1788         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1789         reg &= ~DWC3_DCFG_NUMP_MASK;
1790         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1791         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1792 }
1793
1794 static int __dwc3_gadget_start(struct dwc3 *dwc)
1795 {
1796         struct dwc3_ep          *dep;
1797         int                     ret = 0;
1798         u32                     reg;
1799
1800         /*
1801          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1802          * the core supports IMOD, disable it.
1803          */
1804         if (dwc->imod_interval) {
1805                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1806                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1807         } else if (dwc3_has_imod(dwc)) {
1808                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1809         }
1810
1811         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1812         reg &= ~(DWC3_DCFG_SPEED_MASK);
1813
1814         /**
1815          * WORKAROUND: DWC3 revision < 2.20a have an issue
1816          * which would cause metastability state on Run/Stop
1817          * bit if we try to force the IP to USB2-only mode.
1818          *
1819          * Because of that, we cannot configure the IP to any
1820          * speed other than the SuperSpeed
1821          *
1822          * Refers to:
1823          *
1824          * STAR#9000525659: Clock Domain Crossing on DCTL in
1825          * USB 2.0 Mode
1826          */
1827         if (dwc->revision < DWC3_REVISION_220A) {
1828                 reg |= DWC3_DCFG_SUPERSPEED;
1829         } else {
1830                 switch (dwc->maximum_speed) {
1831                 case USB_SPEED_LOW:
1832                         reg |= DWC3_DCFG_LOWSPEED;
1833                         break;
1834                 case USB_SPEED_FULL:
1835                         reg |= DWC3_DCFG_FULLSPEED;
1836                         break;
1837                 case USB_SPEED_HIGH:
1838                         reg |= DWC3_DCFG_HIGHSPEED;
1839                         break;
1840                 case USB_SPEED_SUPER_PLUS:
1841                         reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1842                         break;
1843                 default:
1844                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1845                                 dwc->maximum_speed);
1846                         /* fall through */
1847                 case USB_SPEED_SUPER:
1848                         reg |= DWC3_DCFG_SUPERSPEED;
1849                         break;
1850                 }
1851         }
1852         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1853
1854         /*
1855          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1856          * field instead of letting dwc3 itself calculate that automatically.
1857          *
1858          * This way, we maximize the chances that we'll be able to get several
1859          * bursts of data without going through any sort of endpoint throttling.
1860          */
1861         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1862         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1863         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1864
1865         dwc3_gadget_setup_nump(dwc);
1866
1867         /* Start with SuperSpeed Default */
1868         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1869
1870         dep = dwc->eps[0];
1871         ret = __dwc3_gadget_ep_enable(dep, false, false);
1872         if (ret) {
1873                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1874                 goto err0;
1875         }
1876
1877         dep = dwc->eps[1];
1878         ret = __dwc3_gadget_ep_enable(dep, false, false);
1879         if (ret) {
1880                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1881                 goto err1;
1882         }
1883
1884         /* begin to receive SETUP packets */
1885         dwc->ep0state = EP0_SETUP_PHASE;
1886         dwc3_ep0_out_start(dwc);
1887
1888         dwc3_gadget_enable_irq(dwc);
1889
1890         return 0;
1891
1892 err1:
1893         __dwc3_gadget_ep_disable(dwc->eps[0]);
1894
1895 err0:
1896         return ret;
1897 }
1898
1899 static int dwc3_gadget_start(struct usb_gadget *g,
1900                 struct usb_gadget_driver *driver)
1901 {
1902         struct dwc3             *dwc = gadget_to_dwc(g);
1903         unsigned long           flags;
1904         int                     ret = 0;
1905         int                     irq;
1906
1907         irq = dwc->irq_gadget;
1908         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1909                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1910         if (ret) {
1911                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1912                                 irq, ret);
1913                 goto err0;
1914         }
1915
1916         spin_lock_irqsave(&dwc->lock, flags);
1917         if (dwc->gadget_driver) {
1918                 dev_err(dwc->dev, "%s is already bound to %s\n",
1919                                 dwc->gadget.name,
1920                                 dwc->gadget_driver->driver.name);
1921                 ret = -EBUSY;
1922                 goto err1;
1923         }
1924
1925         dwc->gadget_driver      = driver;
1926
1927         if (pm_runtime_active(dwc->dev))
1928                 __dwc3_gadget_start(dwc);
1929
1930         spin_unlock_irqrestore(&dwc->lock, flags);
1931
1932         return 0;
1933
1934 err1:
1935         spin_unlock_irqrestore(&dwc->lock, flags);
1936         free_irq(irq, dwc);
1937
1938 err0:
1939         return ret;
1940 }
1941
1942 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1943 {
1944         dwc3_gadget_disable_irq(dwc);
1945         __dwc3_gadget_ep_disable(dwc->eps[0]);
1946         __dwc3_gadget_ep_disable(dwc->eps[1]);
1947 }
1948
1949 static int dwc3_gadget_stop(struct usb_gadget *g)
1950 {
1951         struct dwc3             *dwc = gadget_to_dwc(g);
1952         unsigned long           flags;
1953         int                     epnum;
1954
1955         spin_lock_irqsave(&dwc->lock, flags);
1956
1957         if (pm_runtime_suspended(dwc->dev))
1958                 goto out;
1959
1960         __dwc3_gadget_stop(dwc);
1961
1962         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1963                 struct dwc3_ep  *dep = dwc->eps[epnum];
1964
1965                 if (!dep)
1966                         continue;
1967
1968                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1969                         continue;
1970
1971                 wait_event_lock_irq(dep->wait_end_transfer,
1972                                     !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1973                                     dwc->lock);
1974         }
1975
1976 out:
1977         dwc->gadget_driver      = NULL;
1978         spin_unlock_irqrestore(&dwc->lock, flags);
1979
1980         free_irq(dwc->irq_gadget, dwc->ev_buf);
1981
1982         return 0;
1983 }
1984
1985 static const struct usb_gadget_ops dwc3_gadget_ops = {
1986         .get_frame              = dwc3_gadget_get_frame,
1987         .wakeup                 = dwc3_gadget_wakeup,
1988         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1989         .pullup                 = dwc3_gadget_pullup,
1990         .udc_start              = dwc3_gadget_start,
1991         .udc_stop               = dwc3_gadget_stop,
1992 };
1993
1994 /* -------------------------------------------------------------------------- */
1995
1996 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1997                 u8 num, u32 direction)
1998 {
1999         struct dwc3_ep                  *dep;
2000         u8                              i;
2001
2002         for (i = 0; i < num; i++) {
2003                 u8 epnum = (i << 1) | (direction ? 1 : 0);
2004
2005                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2006                 if (!dep)
2007                         return -ENOMEM;
2008
2009                 dep->dwc = dwc;
2010                 dep->number = epnum;
2011                 dep->direction = !!direction;
2012                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2013                 dwc->eps[epnum] = dep;
2014
2015                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
2016                                 (epnum & 1) ? "in" : "out");
2017
2018                 dep->endpoint.name = dep->name;
2019
2020                 if (!(dep->number > 1)) {
2021                         dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2022                         dep->endpoint.comp_desc = NULL;
2023                 }
2024
2025                 spin_lock_init(&dep->lock);
2026
2027                 if (epnum == 0 || epnum == 1) {
2028                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2029                         dep->endpoint.maxburst = 1;
2030                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2031                         if (!epnum)
2032                                 dwc->gadget.ep0 = &dep->endpoint;
2033                 } else if (direction) {
2034                         int mdwidth;
2035                         int size;
2036                         int ret;
2037                         int num;
2038
2039                         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2040                         /* MDWIDTH is represented in bits, we need it in bytes */
2041                         mdwidth /= 8;
2042
2043                         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(i));
2044                         size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2045
2046                         /* FIFO Depth is in MDWDITH bytes. Multiply */
2047                         size *= mdwidth;
2048
2049                         num = size / 1024;
2050                         if (num == 0)
2051                                 num = 1;
2052
2053                         /*
2054                          * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2055                          * internal overhead. We don't really know how these are used,
2056                          * but documentation say it exists.
2057                          */
2058                         size -= mdwidth * (num + 1);
2059                         size /= num;
2060
2061                         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2062
2063                         dep->endpoint.max_streams = 15;
2064                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2065                         list_add_tail(&dep->endpoint.ep_list,
2066                                         &dwc->gadget.ep_list);
2067
2068                         ret = dwc3_alloc_trb_pool(dep);
2069                         if (ret)
2070                                 return ret;
2071                 } else {
2072                         int             ret;
2073
2074                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2075                         dep->endpoint.max_streams = 15;
2076                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2077                         list_add_tail(&dep->endpoint.ep_list,
2078                                         &dwc->gadget.ep_list);
2079
2080                         ret = dwc3_alloc_trb_pool(dep);
2081                         if (ret)
2082                                 return ret;
2083                 }
2084
2085                 if (epnum == 0 || epnum == 1) {
2086                         dep->endpoint.caps.type_control = true;
2087                 } else {
2088                         dep->endpoint.caps.type_iso = true;
2089                         dep->endpoint.caps.type_bulk = true;
2090                         dep->endpoint.caps.type_int = true;
2091                 }
2092
2093                 dep->endpoint.caps.dir_in = !!direction;
2094                 dep->endpoint.caps.dir_out = !direction;
2095
2096                 INIT_LIST_HEAD(&dep->pending_list);
2097                 INIT_LIST_HEAD(&dep->started_list);
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
2104 {
2105         int                             ret;
2106
2107         INIT_LIST_HEAD(&dwc->gadget.ep_list);
2108
2109         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
2110         if (ret < 0) {
2111                 dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
2112                 return ret;
2113         }
2114
2115         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
2116         if (ret < 0) {
2117                 dev_err(dwc->dev, "failed to initialize IN endpoints\n");
2118                 return ret;
2119         }
2120
2121         return 0;
2122 }
2123
2124 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2125 {
2126         struct dwc3_ep                  *dep;
2127         u8                              epnum;
2128
2129         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2130                 dep = dwc->eps[epnum];
2131                 if (!dep)
2132                         continue;
2133                 /*
2134                  * Physical endpoints 0 and 1 are special; they form the
2135                  * bi-directional USB endpoint 0.
2136                  *
2137                  * For those two physical endpoints, we don't allocate a TRB
2138                  * pool nor do we add them the endpoints list. Due to that, we
2139                  * shouldn't do these two operations otherwise we would end up
2140                  * with all sorts of bugs when removing dwc3.ko.
2141                  */
2142                 if (epnum != 0 && epnum != 1) {
2143                         dwc3_free_trb_pool(dep);
2144                         list_del(&dep->endpoint.ep_list);
2145                 }
2146
2147                 kfree(dep);
2148         }
2149 }
2150
2151 /* -------------------------------------------------------------------------- */
2152
2153 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2154                 struct dwc3_request *req, struct dwc3_trb *trb,
2155                 const struct dwc3_event_depevt *event, int status,
2156                 int chain)
2157 {
2158         unsigned int            count;
2159         unsigned int            s_pkt = 0;
2160         unsigned int            trb_status;
2161
2162         dwc3_ep_inc_deq(dep);
2163
2164         if (req->trb == trb)
2165                 dep->queued_requests--;
2166
2167         trace_dwc3_complete_trb(dep, trb);
2168
2169         /*
2170          * If we're in the middle of series of chained TRBs and we
2171          * receive a short transfer along the way, DWC3 will skip
2172          * through all TRBs including the last TRB in the chain (the
2173          * where CHN bit is zero. DWC3 will also avoid clearing HWO
2174          * bit and SW has to do it manually.
2175          *
2176          * We're going to do that here to avoid problems of HW trying
2177          * to use bogus TRBs for transfers.
2178          */
2179         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2180                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2181
2182         /*
2183          * If we're dealing with unaligned size OUT transfer, we will be left
2184          * with one TRB pending in the ring. We need to manually clear HWO bit
2185          * from that TRB.
2186          */
2187         if (req->unaligned && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2188                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2189                 return 1;
2190         }
2191
2192         count = trb->size & DWC3_TRB_SIZE_MASK;
2193         req->remaining += count;
2194
2195         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2196                 return 1;
2197
2198         if (dep->direction) {
2199                 if (count) {
2200                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2201                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2202                                 /*
2203                                  * If missed isoc occurred and there is
2204                                  * no request queued then issue END
2205                                  * TRANSFER, so that core generates
2206                                  * next xfernotready and we will issue
2207                                  * a fresh START TRANSFER.
2208                                  * If there are still queued request
2209                                  * then wait, do not issue either END
2210                                  * or UPDATE TRANSFER, just attach next
2211                                  * request in pending_list during
2212                                  * giveback.If any future queued request
2213                                  * is successfully transferred then we
2214                                  * will issue UPDATE TRANSFER for all
2215                                  * request in the pending_list.
2216                                  */
2217                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2218                         } else {
2219                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2220                                                 dep->name);
2221                                 status = -ECONNRESET;
2222                         }
2223                 } else {
2224                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2225                 }
2226         } else {
2227                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2228                         s_pkt = 1;
2229         }
2230
2231         if (s_pkt && !chain)
2232                 return 1;
2233
2234         if ((event->status & DEPEVT_STATUS_IOC) &&
2235                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2236                 return 1;
2237
2238         return 0;
2239 }
2240
2241 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2242                 const struct dwc3_event_depevt *event, int status)
2243 {
2244         struct dwc3_request     *req, *n;
2245         struct dwc3_trb         *trb;
2246         bool                    ioc = false;
2247         int                     ret = 0;
2248
2249         list_for_each_entry_safe(req, n, &dep->started_list, list) {
2250                 unsigned length;
2251                 int chain;
2252
2253                 length = req->request.length;
2254                 chain = req->num_pending_sgs > 0;
2255                 if (chain) {
2256                         struct scatterlist *sg = req->sg;
2257                         struct scatterlist *s;
2258                         unsigned int pending = req->num_pending_sgs;
2259                         unsigned int i;
2260
2261                         for_each_sg(sg, s, pending, i) {
2262                                 trb = &dep->trb_pool[dep->trb_dequeue];
2263
2264                                 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2265                                         break;
2266
2267                                 req->sg = sg_next(s);
2268                                 req->num_pending_sgs--;
2269
2270                                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2271                                                 event, status, chain);
2272                                 if (ret)
2273                                         break;
2274                         }
2275                 } else {
2276                         trb = &dep->trb_pool[dep->trb_dequeue];
2277                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2278                                         event, status, chain);
2279                 }
2280
2281                 if (req->unaligned) {
2282                         trb = &dep->trb_pool[dep->trb_dequeue];
2283                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2284                                         event, status, false);
2285                         req->unaligned = false;
2286                 }
2287
2288                 req->request.actual = length - req->remaining;
2289
2290                 if ((req->request.actual < length) && req->num_pending_sgs)
2291                         return __dwc3_gadget_kick_transfer(dep, 0);
2292
2293                 dwc3_gadget_giveback(dep, req, status);
2294
2295                 if (ret) {
2296                         if ((event->status & DEPEVT_STATUS_IOC) &&
2297                             (trb->ctrl & DWC3_TRB_CTRL_IOC))
2298                                 ioc = true;
2299                         break;
2300                 }
2301         }
2302
2303         /*
2304          * Our endpoint might get disabled by another thread during
2305          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2306          * early on so DWC3_EP_BUSY flag gets cleared
2307          */
2308         if (!dep->endpoint.desc)
2309                 return 1;
2310
2311         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2312                         list_empty(&dep->started_list)) {
2313                 if (list_empty(&dep->pending_list)) {
2314                         /*
2315                          * If there is no entry in request list then do
2316                          * not issue END TRANSFER now. Just set PENDING
2317                          * flag, so that END TRANSFER is issued when an
2318                          * entry is added into request list.
2319                          */
2320                         dep->flags = DWC3_EP_PENDING_REQUEST;
2321                 } else {
2322                         dwc3_stop_active_transfer(dwc, dep->number, true);
2323                         dep->flags = DWC3_EP_ENABLED;
2324                 }
2325                 return 1;
2326         }
2327
2328         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2329                 return 0;
2330
2331         return 1;
2332 }
2333
2334 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2335                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2336 {
2337         unsigned                status = 0;
2338         int                     clean_busy;
2339         u32                     is_xfer_complete;
2340
2341         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2342
2343         if (event->status & DEPEVT_STATUS_BUSERR)
2344                 status = -ECONNRESET;
2345
2346         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2347         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2348                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2349                 dep->flags &= ~DWC3_EP_BUSY;
2350
2351         /*
2352          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2353          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2354          */
2355         if (dwc->revision < DWC3_REVISION_183A) {
2356                 u32             reg;
2357                 int             i;
2358
2359                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2360                         dep = dwc->eps[i];
2361
2362                         if (!(dep->flags & DWC3_EP_ENABLED))
2363                                 continue;
2364
2365                         if (!list_empty(&dep->started_list))
2366                                 return;
2367                 }
2368
2369                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2370                 reg |= dwc->u1u2;
2371                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2372
2373                 dwc->u1u2 = 0;
2374         }
2375
2376         /*
2377          * Our endpoint might get disabled by another thread during
2378          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2379          * early on so DWC3_EP_BUSY flag gets cleared
2380          */
2381         if (!dep->endpoint.desc)
2382                 return;
2383
2384         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2385                 int ret;
2386
2387                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2388                 if (!ret || ret == -EBUSY)
2389                         return;
2390         }
2391 }
2392
2393 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2394                 const struct dwc3_event_depevt *event)
2395 {
2396         struct dwc3_ep          *dep;
2397         u8                      epnum = event->endpoint_number;
2398         u8                      cmd;
2399
2400         dep = dwc->eps[epnum];
2401
2402         if (!(dep->flags & DWC3_EP_ENABLED)) {
2403                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2404                         return;
2405
2406                 /* Handle only EPCMDCMPLT when EP disabled */
2407                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2408                         return;
2409         }
2410
2411         if (epnum == 0 || epnum == 1) {
2412                 dwc3_ep0_interrupt(dwc, event);
2413                 return;
2414         }
2415
2416         switch (event->endpoint_event) {
2417         case DWC3_DEPEVT_XFERCOMPLETE:
2418                 dep->resource_index = 0;
2419
2420                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2421                         dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2422                         return;
2423                 }
2424
2425                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2426                 break;
2427         case DWC3_DEPEVT_XFERINPROGRESS:
2428                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2429                 break;
2430         case DWC3_DEPEVT_XFERNOTREADY:
2431                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2432                         dwc3_gadget_start_isoc(dwc, dep, event);
2433                 } else {
2434                         int ret;
2435
2436                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2437                         if (!ret || ret == -EBUSY)
2438                                 return;
2439                 }
2440
2441                 break;
2442         case DWC3_DEPEVT_STREAMEVT:
2443                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2444                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2445                                         dep->name);
2446                         return;
2447                 }
2448                 break;
2449         case DWC3_DEPEVT_EPCMDCMPLT:
2450                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2451
2452                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2453                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2454                         wake_up(&dep->wait_end_transfer);
2455                 }
2456                 break;
2457         case DWC3_DEPEVT_RXTXFIFOEVT:
2458                 break;
2459         }
2460 }
2461
2462 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2463 {
2464         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2465                 spin_unlock(&dwc->lock);
2466                 dwc->gadget_driver->disconnect(&dwc->gadget);
2467                 spin_lock(&dwc->lock);
2468         }
2469 }
2470
2471 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2472 {
2473         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2474                 spin_unlock(&dwc->lock);
2475                 dwc->gadget_driver->suspend(&dwc->gadget);
2476                 spin_lock(&dwc->lock);
2477         }
2478 }
2479
2480 static void dwc3_resume_gadget(struct dwc3 *dwc)
2481 {
2482         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2483                 spin_unlock(&dwc->lock);
2484                 dwc->gadget_driver->resume(&dwc->gadget);
2485                 spin_lock(&dwc->lock);
2486         }
2487 }
2488
2489 static void dwc3_reset_gadget(struct dwc3 *dwc)
2490 {
2491         if (!dwc->gadget_driver)
2492                 return;
2493
2494         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2495                 spin_unlock(&dwc->lock);
2496                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2497                 spin_lock(&dwc->lock);
2498         }
2499 }
2500
2501 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2502 {
2503         struct dwc3_ep *dep;
2504         struct dwc3_gadget_ep_cmd_params params;
2505         u32 cmd;
2506         int ret;
2507
2508         dep = dwc->eps[epnum];
2509
2510         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2511             !dep->resource_index)
2512                 return;
2513
2514         /*
2515          * NOTICE: We are violating what the Databook says about the
2516          * EndTransfer command. Ideally we would _always_ wait for the
2517          * EndTransfer Command Completion IRQ, but that's causing too
2518          * much trouble synchronizing between us and gadget driver.
2519          *
2520          * We have discussed this with the IP Provider and it was
2521          * suggested to giveback all requests here, but give HW some
2522          * extra time to synchronize with the interconnect. We're using
2523          * an arbitrary 100us delay for that.
2524          *
2525          * Note also that a similar handling was tested by Synopsys
2526          * (thanks a lot Paul) and nothing bad has come out of it.
2527          * In short, what we're doing is:
2528          *
2529          * - Issue EndTransfer WITH CMDIOC bit set
2530          * - Wait 100us
2531          *
2532          * As of IP version 3.10a of the DWC_usb3 IP, the controller
2533          * supports a mode to work around the above limitation. The
2534          * software can poll the CMDACT bit in the DEPCMD register
2535          * after issuing a EndTransfer command. This mode is enabled
2536          * by writing GUCTL2[14]. This polling is already done in the
2537          * dwc3_send_gadget_ep_cmd() function so if the mode is
2538          * enabled, the EndTransfer command will have completed upon
2539          * returning from this function and we don't need to delay for
2540          * 100us.
2541          *
2542          * This mode is NOT available on the DWC_usb31 IP.
2543          */
2544
2545         cmd = DWC3_DEPCMD_ENDTRANSFER;
2546         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2547         cmd |= DWC3_DEPCMD_CMDIOC;
2548         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2549         memset(&params, 0, sizeof(params));
2550         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2551         WARN_ON_ONCE(ret);
2552         dep->resource_index = 0;
2553         dep->flags &= ~DWC3_EP_BUSY;
2554
2555         if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2556                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2557                 udelay(100);
2558         }
2559 }
2560
2561 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2562 {
2563         u32 epnum;
2564
2565         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2566                 struct dwc3_ep *dep;
2567                 int ret;
2568
2569                 dep = dwc->eps[epnum];
2570                 if (!dep)
2571                         continue;
2572
2573                 if (!(dep->flags & DWC3_EP_STALL))
2574                         continue;
2575
2576                 dep->flags &= ~DWC3_EP_STALL;
2577
2578                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2579                 WARN_ON_ONCE(ret);
2580         }
2581 }
2582
2583 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2584 {
2585         int                     reg;
2586
2587         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2588         reg &= ~DWC3_DCTL_INITU1ENA;
2589         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2590
2591         reg &= ~DWC3_DCTL_INITU2ENA;
2592         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2593
2594         dwc3_disconnect_gadget(dwc);
2595
2596         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2597         dwc->setup_packet_pending = false;
2598         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2599
2600         dwc->connected = false;
2601 }
2602
2603 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2604 {
2605         u32                     reg;
2606
2607         dwc->connected = true;
2608
2609         /*
2610          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2611          * would cause a missing Disconnect Event if there's a
2612          * pending Setup Packet in the FIFO.
2613          *
2614          * There's no suggested workaround on the official Bug
2615          * report, which states that "unless the driver/application
2616          * is doing any special handling of a disconnect event,
2617          * there is no functional issue".
2618          *
2619          * Unfortunately, it turns out that we _do_ some special
2620          * handling of a disconnect event, namely complete all
2621          * pending transfers, notify gadget driver of the
2622          * disconnection, and so on.
2623          *
2624          * Our suggested workaround is to follow the Disconnect
2625          * Event steps here, instead, based on a setup_packet_pending
2626          * flag. Such flag gets set whenever we have a SETUP_PENDING
2627          * status for EP0 TRBs and gets cleared on XferComplete for the
2628          * same endpoint.
2629          *
2630          * Refers to:
2631          *
2632          * STAR#9000466709: RTL: Device : Disconnect event not
2633          * generated if setup packet pending in FIFO
2634          */
2635         if (dwc->revision < DWC3_REVISION_188A) {
2636                 if (dwc->setup_packet_pending)
2637                         dwc3_gadget_disconnect_interrupt(dwc);
2638         }
2639
2640         dwc3_reset_gadget(dwc);
2641
2642         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2643         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2644         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2645         dwc->test_mode = false;
2646         dwc3_clear_stall_all_ep(dwc);
2647
2648         /* Reset device address to zero */
2649         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2650         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2651         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2652 }
2653
2654 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2655 {
2656         struct dwc3_ep          *dep;
2657         int                     ret;
2658         u32                     reg;
2659         u8                      speed;
2660
2661         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2662         speed = reg & DWC3_DSTS_CONNECTSPD;
2663         dwc->speed = speed;
2664
2665         /*
2666          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2667          * each time on Connect Done.
2668          *
2669          * Currently we always use the reset value. If any platform
2670          * wants to set this to a different value, we need to add a
2671          * setting and update GCTL.RAMCLKSEL here.
2672          */
2673
2674         switch (speed) {
2675         case DWC3_DSTS_SUPERSPEED_PLUS:
2676                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2677                 dwc->gadget.ep0->maxpacket = 512;
2678                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2679                 break;
2680         case DWC3_DSTS_SUPERSPEED:
2681                 /*
2682                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2683                  * would cause a missing USB3 Reset event.
2684                  *
2685                  * In such situations, we should force a USB3 Reset
2686                  * event by calling our dwc3_gadget_reset_interrupt()
2687                  * routine.
2688                  *
2689                  * Refers to:
2690                  *
2691                  * STAR#9000483510: RTL: SS : USB3 reset event may
2692                  * not be generated always when the link enters poll
2693                  */
2694                 if (dwc->revision < DWC3_REVISION_190A)
2695                         dwc3_gadget_reset_interrupt(dwc);
2696
2697                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2698                 dwc->gadget.ep0->maxpacket = 512;
2699                 dwc->gadget.speed = USB_SPEED_SUPER;
2700                 break;
2701         case DWC3_DSTS_HIGHSPEED:
2702                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2703                 dwc->gadget.ep0->maxpacket = 64;
2704                 dwc->gadget.speed = USB_SPEED_HIGH;
2705                 break;
2706         case DWC3_DSTS_FULLSPEED:
2707                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2708                 dwc->gadget.ep0->maxpacket = 64;
2709                 dwc->gadget.speed = USB_SPEED_FULL;
2710                 break;
2711         case DWC3_DSTS_LOWSPEED:
2712                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2713                 dwc->gadget.ep0->maxpacket = 8;
2714                 dwc->gadget.speed = USB_SPEED_LOW;
2715                 break;
2716         }
2717
2718         /* Enable USB2 LPM Capability */
2719
2720         if ((dwc->revision > DWC3_REVISION_194A) &&
2721             (speed != DWC3_DSTS_SUPERSPEED) &&
2722             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2723                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2724                 reg |= DWC3_DCFG_LPM_CAP;
2725                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2726
2727                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2728                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2729
2730                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2731
2732                 /*
2733                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2734                  * DCFG.LPMCap is set, core responses with an ACK and the
2735                  * BESL value in the LPM token is less than or equal to LPM
2736                  * NYET threshold.
2737                  */
2738                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2739                                 && dwc->has_lpm_erratum,
2740                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2741
2742                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2743                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2744
2745                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2746         } else {
2747                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2748                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2749                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2750         }
2751
2752         dep = dwc->eps[0];
2753         ret = __dwc3_gadget_ep_enable(dep, true, false);
2754         if (ret) {
2755                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2756                 return;
2757         }
2758
2759         dep = dwc->eps[1];
2760         ret = __dwc3_gadget_ep_enable(dep, true, false);
2761         if (ret) {
2762                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2763                 return;
2764         }
2765
2766         /*
2767          * Configure PHY via GUSB3PIPECTLn if required.
2768          *
2769          * Update GTXFIFOSIZn
2770          *
2771          * In both cases reset values should be sufficient.
2772          */
2773 }
2774
2775 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2776 {
2777         /*
2778          * TODO take core out of low power mode when that's
2779          * implemented.
2780          */
2781
2782         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2783                 spin_unlock(&dwc->lock);
2784                 dwc->gadget_driver->resume(&dwc->gadget);
2785                 spin_lock(&dwc->lock);
2786         }
2787 }
2788
2789 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2790                 unsigned int evtinfo)
2791 {
2792         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2793         unsigned int            pwropt;
2794
2795         /*
2796          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2797          * Hibernation mode enabled which would show up when device detects
2798          * host-initiated U3 exit.
2799          *
2800          * In that case, device will generate a Link State Change Interrupt
2801          * from U3 to RESUME which is only necessary if Hibernation is
2802          * configured in.
2803          *
2804          * There are no functional changes due to such spurious event and we
2805          * just need to ignore it.
2806          *
2807          * Refers to:
2808          *
2809          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2810          * operational mode
2811          */
2812         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2813         if ((dwc->revision < DWC3_REVISION_250A) &&
2814                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2815                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2816                                 (next == DWC3_LINK_STATE_RESUME)) {
2817                         return;
2818                 }
2819         }
2820
2821         /*
2822          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2823          * on the link partner, the USB session might do multiple entry/exit
2824          * of low power states before a transfer takes place.
2825          *
2826          * Due to this problem, we might experience lower throughput. The
2827          * suggested workaround is to disable DCTL[12:9] bits if we're
2828          * transitioning from U1/U2 to U0 and enable those bits again
2829          * after a transfer completes and there are no pending transfers
2830          * on any of the enabled endpoints.
2831          *
2832          * This is the first half of that workaround.
2833          *
2834          * Refers to:
2835          *
2836          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2837          * core send LGO_Ux entering U0
2838          */
2839         if (dwc->revision < DWC3_REVISION_183A) {
2840                 if (next == DWC3_LINK_STATE_U0) {
2841                         u32     u1u2;
2842                         u32     reg;
2843
2844                         switch (dwc->link_state) {
2845                         case DWC3_LINK_STATE_U1:
2846                         case DWC3_LINK_STATE_U2:
2847                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2848                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2849                                                 | DWC3_DCTL_ACCEPTU2ENA
2850                                                 | DWC3_DCTL_INITU1ENA
2851                                                 | DWC3_DCTL_ACCEPTU1ENA);
2852
2853                                 if (!dwc->u1u2)
2854                                         dwc->u1u2 = reg & u1u2;
2855
2856                                 reg &= ~u1u2;
2857
2858                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2859                                 break;
2860                         default:
2861                                 /* do nothing */
2862                                 break;
2863                         }
2864                 }
2865         }
2866
2867         switch (next) {
2868         case DWC3_LINK_STATE_U1:
2869                 if (dwc->speed == USB_SPEED_SUPER)
2870                         dwc3_suspend_gadget(dwc);
2871                 break;
2872         case DWC3_LINK_STATE_U2:
2873         case DWC3_LINK_STATE_U3:
2874                 dwc3_suspend_gadget(dwc);
2875                 break;
2876         case DWC3_LINK_STATE_RESUME:
2877                 dwc3_resume_gadget(dwc);
2878                 break;
2879         default:
2880                 /* do nothing */
2881                 break;
2882         }
2883
2884         dwc->link_state = next;
2885 }
2886
2887 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2888                                           unsigned int evtinfo)
2889 {
2890         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2891
2892         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2893                 dwc3_suspend_gadget(dwc);
2894
2895         dwc->link_state = next;
2896 }
2897
2898 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2899                 unsigned int evtinfo)
2900 {
2901         unsigned int is_ss = evtinfo & BIT(4);
2902
2903         /**
2904          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2905          * have a known issue which can cause USB CV TD.9.23 to fail
2906          * randomly.
2907          *
2908          * Because of this issue, core could generate bogus hibernation
2909          * events which SW needs to ignore.
2910          *
2911          * Refers to:
2912          *
2913          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2914          * Device Fallback from SuperSpeed
2915          */
2916         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2917                 return;
2918
2919         /* enter hibernation here */
2920 }
2921
2922 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2923                 const struct dwc3_event_devt *event)
2924 {
2925         switch (event->type) {
2926         case DWC3_DEVICE_EVENT_DISCONNECT:
2927                 dwc3_gadget_disconnect_interrupt(dwc);
2928                 break;
2929         case DWC3_DEVICE_EVENT_RESET:
2930                 dwc3_gadget_reset_interrupt(dwc);
2931                 break;
2932         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2933                 dwc3_gadget_conndone_interrupt(dwc);
2934                 break;
2935         case DWC3_DEVICE_EVENT_WAKEUP:
2936                 dwc3_gadget_wakeup_interrupt(dwc);
2937                 break;
2938         case DWC3_DEVICE_EVENT_HIBER_REQ:
2939                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2940                                         "unexpected hibernation event\n"))
2941                         break;
2942
2943                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2944                 break;
2945         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2946                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2947                 break;
2948         case DWC3_DEVICE_EVENT_EOPF:
2949                 /* It changed to be suspend event for version 2.30a and above */
2950                 if (dwc->revision >= DWC3_REVISION_230A) {
2951                         /*
2952                          * Ignore suspend event until the gadget enters into
2953                          * USB_STATE_CONFIGURED state.
2954                          */
2955                         if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2956                                 dwc3_gadget_suspend_interrupt(dwc,
2957                                                 event->event_info);
2958                 }
2959                 break;
2960         case DWC3_DEVICE_EVENT_SOF:
2961         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2962         case DWC3_DEVICE_EVENT_CMD_CMPL:
2963         case DWC3_DEVICE_EVENT_OVERFLOW:
2964                 break;
2965         default:
2966                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2967         }
2968 }
2969
2970 static void dwc3_process_event_entry(struct dwc3 *dwc,
2971                 const union dwc3_event *event)
2972 {
2973         trace_dwc3_event(event->raw, dwc);
2974
2975         /* Endpoint IRQ, handle it and return early */
2976         if (event->type.is_devspec == 0) {
2977                 /* depevt */
2978                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2979         }
2980
2981         switch (event->type.type) {
2982         case DWC3_EVENT_TYPE_DEV:
2983                 dwc3_gadget_interrupt(dwc, &event->devt);
2984                 break;
2985         /* REVISIT what to do with Carkit and I2C events ? */
2986         default:
2987                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2988         }
2989 }
2990
2991 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2992 {
2993         struct dwc3 *dwc = evt->dwc;
2994         irqreturn_t ret = IRQ_NONE;
2995         int left;
2996         u32 reg;
2997
2998         left = evt->count;
2999
3000         if (!(evt->flags & DWC3_EVENT_PENDING))
3001                 return IRQ_NONE;
3002
3003         while (left > 0) {
3004                 union dwc3_event event;
3005
3006                 event.raw = *(u32 *) (evt->cache + evt->lpos);
3007
3008                 dwc3_process_event_entry(dwc, &event);
3009
3010                 /*
3011                  * FIXME we wrap around correctly to the next entry as
3012                  * almost all entries are 4 bytes in size. There is one
3013                  * entry which has 12 bytes which is a regular entry
3014                  * followed by 8 bytes data. ATM I don't know how
3015                  * things are organized if we get next to the a
3016                  * boundary so I worry about that once we try to handle
3017                  * that.
3018                  */
3019                 evt->lpos = (evt->lpos + 4) % evt->length;
3020                 left -= 4;
3021         }
3022
3023         evt->count = 0;
3024         evt->flags &= ~DWC3_EVENT_PENDING;
3025         ret = IRQ_HANDLED;
3026
3027         /* Unmask interrupt */
3028         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3029         reg &= ~DWC3_GEVNTSIZ_INTMASK;
3030         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3031
3032         if (dwc->imod_interval) {
3033                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3034                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3035         }
3036
3037         return ret;
3038 }
3039
3040 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3041 {
3042         struct dwc3_event_buffer *evt = _evt;
3043         struct dwc3 *dwc = evt->dwc;
3044         unsigned long flags;
3045         irqreturn_t ret = IRQ_NONE;
3046
3047         spin_lock_irqsave(&dwc->lock, flags);
3048         ret = dwc3_process_event_buf(evt);
3049         spin_unlock_irqrestore(&dwc->lock, flags);
3050
3051         return ret;
3052 }
3053
3054 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3055 {
3056         struct dwc3 *dwc = evt->dwc;
3057         u32 amount;
3058         u32 count;
3059         u32 reg;
3060
3061         if (pm_runtime_suspended(dwc->dev)) {
3062                 pm_runtime_get(dwc->dev);
3063                 disable_irq_nosync(dwc->irq_gadget);
3064                 dwc->pending_events = true;
3065                 return IRQ_HANDLED;
3066         }
3067
3068         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3069         count &= DWC3_GEVNTCOUNT_MASK;
3070         if (!count)
3071                 return IRQ_NONE;
3072
3073         evt->count = count;
3074         evt->flags |= DWC3_EVENT_PENDING;
3075
3076         /* Mask interrupt */
3077         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3078         reg |= DWC3_GEVNTSIZ_INTMASK;
3079         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3080
3081         amount = min(count, evt->length - evt->lpos);
3082         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3083
3084         if (amount < count)
3085                 memcpy(evt->cache, evt->buf, count - amount);
3086
3087         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3088
3089         return IRQ_WAKE_THREAD;
3090 }
3091
3092 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3093 {
3094         struct dwc3_event_buffer        *evt = _evt;
3095
3096         return dwc3_check_event_buf(evt);
3097 }
3098
3099 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3100 {
3101         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3102         int irq;
3103
3104         irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3105         if (irq > 0)
3106                 goto out;
3107
3108         if (irq == -EPROBE_DEFER)
3109                 goto out;
3110
3111         irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3112         if (irq > 0)
3113                 goto out;
3114
3115         if (irq == -EPROBE_DEFER)
3116                 goto out;
3117
3118         irq = platform_get_irq(dwc3_pdev, 0);
3119         if (irq > 0)
3120                 goto out;
3121
3122         if (irq != -EPROBE_DEFER)
3123                 dev_err(dwc->dev, "missing peripheral IRQ\n");
3124
3125         if (!irq)
3126                 irq = -EINVAL;
3127
3128 out:
3129         return irq;
3130 }
3131
3132 /**
3133  * dwc3_gadget_init - Initializes gadget related registers
3134  * @dwc: pointer to our controller context structure
3135  *
3136  * Returns 0 on success otherwise negative errno.
3137  */
3138 int dwc3_gadget_init(struct dwc3 *dwc)
3139 {
3140         int ret;
3141         int irq;
3142
3143         irq = dwc3_gadget_get_irq(dwc);
3144         if (irq < 0) {
3145                 ret = irq;
3146                 goto err0;
3147         }
3148
3149         dwc->irq_gadget = irq;
3150
3151         dwc->ctrl_req = dma_alloc_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
3152                         &dwc->ctrl_req_addr, GFP_KERNEL);
3153         if (!dwc->ctrl_req) {
3154                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
3155                 ret = -ENOMEM;
3156                 goto err0;
3157         }
3158
3159         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3160                                           sizeof(*dwc->ep0_trb) * 2,
3161                                           &dwc->ep0_trb_addr, GFP_KERNEL);
3162         if (!dwc->ep0_trb) {
3163                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3164                 ret = -ENOMEM;
3165                 goto err1;
3166         }
3167