4b4968a294b293d0b17f43024487447b40bd450a
[sfrench/cifs-2.6.git] / drivers / tty / serial / 8250_pci.c
1 /*
2  *  Probe module for 8250/16550-type PCI serial ports.
3  *
4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License.
11  */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_core.h>
21 #include <linux/8250_pci.h>
22 #include <linux/bitops.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28
29 #undef SERIAL_DEBUG_PCI
30
31 /*
32  * init function returns:
33  *  > 0 - number of ports
34  *  = 0 - use board->num_ports
35  *  < 0 - error
36  */
37 struct pci_serial_quirk {
38         u32     vendor;
39         u32     device;
40         u32     subvendor;
41         u32     subdevice;
42         int     (*init)(struct pci_dev *dev);
43         int     (*setup)(struct serial_private *,
44                          const struct pciserial_board *,
45                          struct uart_port *, int);
46         void    (*exit)(struct pci_dev *dev);
47 };
48
49 #define PCI_NUM_BAR_RESOURCES   6
50
51 struct serial_private {
52         struct pci_dev          *dev;
53         unsigned int            nr;
54         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
55         struct pci_serial_quirk *quirk;
56         int                     line[0];
57 };
58
59 static void moan_device(const char *str, struct pci_dev *dev)
60 {
61         printk(KERN_WARNING
62                "%s: %s\n"
63                "Please send the output of lspci -vv, this\n"
64                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65                "manufacturer and name of serial board or\n"
66                "modem board to rmk+serial@arm.linux.org.uk.\n",
67                pci_name(dev), str, dev->vendor, dev->device,
68                dev->subsystem_vendor, dev->subsystem_device);
69 }
70
71 static int
72 setup_port(struct serial_private *priv, struct uart_port *port,
73            int bar, int offset, int regshift)
74 {
75         struct pci_dev *dev = priv->dev;
76         unsigned long base, len;
77
78         if (bar >= PCI_NUM_BAR_RESOURCES)
79                 return -EINVAL;
80
81         base = pci_resource_start(dev, bar);
82
83         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84                 len =  pci_resource_len(dev, bar);
85
86                 if (!priv->remapped_bar[bar])
87                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
88                 if (!priv->remapped_bar[bar])
89                         return -ENOMEM;
90
91                 port->iotype = UPIO_MEM;
92                 port->iobase = 0;
93                 port->mapbase = base + offset;
94                 port->membase = priv->remapped_bar[bar] + offset;
95                 port->regshift = regshift;
96         } else {
97                 port->iotype = UPIO_PORT;
98                 port->iobase = base + offset;
99                 port->mapbase = 0;
100                 port->membase = NULL;
101                 port->regshift = 0;
102         }
103         return 0;
104 }
105
106 /*
107  * ADDI-DATA GmbH communication cards <info@addi-data.com>
108  */
109 static int addidata_apci7800_setup(struct serial_private *priv,
110                                 const struct pciserial_board *board,
111                                 struct uart_port *port, int idx)
112 {
113         unsigned int bar = 0, offset = board->first_offset;
114         bar = FL_GET_BASE(board->flags);
115
116         if (idx < 2) {
117                 offset += idx * board->uart_offset;
118         } else if ((idx >= 2) && (idx < 4)) {
119                 bar += 1;
120                 offset += ((idx - 2) * board->uart_offset);
121         } else if ((idx >= 4) && (idx < 6)) {
122                 bar += 2;
123                 offset += ((idx - 4) * board->uart_offset);
124         } else if (idx >= 6) {
125                 bar += 3;
126                 offset += ((idx - 6) * board->uart_offset);
127         }
128
129         return setup_port(priv, port, bar, offset, board->reg_shift);
130 }
131
132 /*
133  * AFAVLAB uses a different mixture of BARs and offsets
134  * Not that ugly ;) -- HW
135  */
136 static int
137 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
138               struct uart_port *port, int idx)
139 {
140         unsigned int bar, offset = board->first_offset;
141
142         bar = FL_GET_BASE(board->flags);
143         if (idx < 4)
144                 bar += idx;
145         else {
146                 bar = 4;
147                 offset += (idx - 4) * board->uart_offset;
148         }
149
150         return setup_port(priv, port, bar, offset, board->reg_shift);
151 }
152
153 /*
154  * HP's Remote Management Console.  The Diva chip came in several
155  * different versions.  N-class, L2000 and A500 have two Diva chips, each
156  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
157  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
158  * one Diva chip, but it has been expanded to 5 UARTs.
159  */
160 static int pci_hp_diva_init(struct pci_dev *dev)
161 {
162         int rc = 0;
163
164         switch (dev->subsystem_device) {
165         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
166         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
167         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
168         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
169                 rc = 3;
170                 break;
171         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
172                 rc = 2;
173                 break;
174         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175                 rc = 4;
176                 break;
177         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
178         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
179                 rc = 1;
180                 break;
181         }
182
183         return rc;
184 }
185
186 /*
187  * HP's Diva chip puts the 4th/5th serial port further out, and
188  * some serial ports are supposed to be hidden on certain models.
189  */
190 static int
191 pci_hp_diva_setup(struct serial_private *priv,
192                 const struct pciserial_board *board,
193                 struct uart_port *port, int idx)
194 {
195         unsigned int offset = board->first_offset;
196         unsigned int bar = FL_GET_BASE(board->flags);
197
198         switch (priv->dev->subsystem_device) {
199         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
200                 if (idx == 3)
201                         idx++;
202                 break;
203         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
204                 if (idx > 0)
205                         idx++;
206                 if (idx > 2)
207                         idx++;
208                 break;
209         }
210         if (idx > 2)
211                 offset = 0x18;
212
213         offset += idx * board->uart_offset;
214
215         return setup_port(priv, port, bar, offset, board->reg_shift);
216 }
217
218 /*
219  * Added for EKF Intel i960 serial boards
220  */
221 static int pci_inteli960ni_init(struct pci_dev *dev)
222 {
223         unsigned long oldval;
224
225         if (!(dev->subsystem_device & 0x1000))
226                 return -ENODEV;
227
228         /* is firmware started? */
229         pci_read_config_dword(dev, 0x44, (void *)&oldval);
230         if (oldval == 0x00001000L) { /* RESET value */
231                 printk(KERN_DEBUG "Local i960 firmware missing");
232                 return -ENODEV;
233         }
234         return 0;
235 }
236
237 /*
238  * Some PCI serial cards using the PLX 9050 PCI interface chip require
239  * that the card interrupt be explicitly enabled or disabled.  This
240  * seems to be mainly needed on card using the PLX which also use I/O
241  * mapped memory.
242  */
243 static int pci_plx9050_init(struct pci_dev *dev)
244 {
245         u8 irq_config;
246         void __iomem *p;
247
248         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249                 moan_device("no memory in bar 0", dev);
250                 return 0;
251         }
252
253         irq_config = 0x41;
254         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
255             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
256                 irq_config = 0x43;
257
258         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
259             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
260                 /*
261                  * As the megawolf cards have the int pins active
262                  * high, and have 2 UART chips, both ints must be
263                  * enabled on the 9050. Also, the UARTS are set in
264                  * 16450 mode by default, so we have to enable the
265                  * 16C950 'enhanced' mode so that we can use the
266                  * deep FIFOs
267                  */
268                 irq_config = 0x5b;
269         /*
270          * enable/disable interrupts
271          */
272         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
273         if (p == NULL)
274                 return -ENOMEM;
275         writel(irq_config, p + 0x4c);
276
277         /*
278          * Read the register back to ensure that it took effect.
279          */
280         readl(p + 0x4c);
281         iounmap(p);
282
283         return 0;
284 }
285
286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
287 {
288         u8 __iomem *p;
289
290         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
291                 return;
292
293         /*
294          * disable interrupts
295          */
296         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
297         if (p != NULL) {
298                 writel(0, p + 0x4c);
299
300                 /*
301                  * Read the register back to ensure that it took effect.
302                  */
303                 readl(p + 0x4c);
304                 iounmap(p);
305         }
306 }
307
308 #define NI8420_INT_ENABLE_REG   0x38
309 #define NI8420_INT_ENABLE_BIT   0x2000
310
311 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
312 {
313         void __iomem *p;
314         unsigned long base, len;
315         unsigned int bar = 0;
316
317         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318                 moan_device("no memory in bar", dev);
319                 return;
320         }
321
322         base = pci_resource_start(dev, bar);
323         len =  pci_resource_len(dev, bar);
324         p = ioremap_nocache(base, len);
325         if (p == NULL)
326                 return;
327
328         /* Disable the CPU Interrupt */
329         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330                p + NI8420_INT_ENABLE_REG);
331         iounmap(p);
332 }
333
334
335 /* MITE registers */
336 #define MITE_IOWBSR1    0xc4
337 #define MITE_IOWCR1     0xf4
338 #define MITE_LCIMR1     0x08
339 #define MITE_LCIMR2     0x10
340
341 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
342
343 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
344 {
345         void __iomem *p;
346         unsigned long base, len;
347         unsigned int bar = 0;
348
349         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
350                 moan_device("no memory in bar", dev);
351                 return;
352         }
353
354         base = pci_resource_start(dev, bar);
355         len =  pci_resource_len(dev, bar);
356         p = ioremap_nocache(base, len);
357         if (p == NULL)
358                 return;
359
360         /* Disable the CPU Interrupt */
361         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
362         iounmap(p);
363 }
364
365 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
366 static int
367 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
368                 struct uart_port *port, int idx)
369 {
370         unsigned int bar, offset = board->first_offset;
371
372         bar = 0;
373
374         if (idx < 4) {
375                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
376                 offset += idx * board->uart_offset;
377         } else if (idx < 8) {
378                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
379                 offset += idx * board->uart_offset + 0xC00;
380         } else /* we have only 8 ports on PMC-OCTALPRO */
381                 return 1;
382
383         return setup_port(priv, port, bar, offset, board->reg_shift);
384 }
385
386 /*
387 * This does initialization for PMC OCTALPRO cards:
388 * maps the device memory, resets the UARTs (needed, bc
389 * if the module is removed and inserted again, the card
390 * is in the sleep mode) and enables global interrupt.
391 */
392
393 /* global control register offset for SBS PMC-OctalPro */
394 #define OCT_REG_CR_OFF          0x500
395
396 static int sbs_init(struct pci_dev *dev)
397 {
398         u8 __iomem *p;
399
400         p = pci_ioremap_bar(dev, 0);
401
402         if (p == NULL)
403                 return -ENOMEM;
404         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
405         writeb(0x10, p + OCT_REG_CR_OFF);
406         udelay(50);
407         writeb(0x0, p + OCT_REG_CR_OFF);
408
409         /* Set bit-2 (INTENABLE) of Control Register */
410         writeb(0x4, p + OCT_REG_CR_OFF);
411         iounmap(p);
412
413         return 0;
414 }
415
416 /*
417  * Disables the global interrupt of PMC-OctalPro
418  */
419
420 static void __devexit sbs_exit(struct pci_dev *dev)
421 {
422         u8 __iomem *p;
423
424         p = pci_ioremap_bar(dev, 0);
425         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
426         if (p != NULL)
427                 writeb(0, p + OCT_REG_CR_OFF);
428         iounmap(p);
429 }
430
431 /*
432  * SIIG serial cards have an PCI interface chip which also controls
433  * the UART clocking frequency. Each UART can be clocked independently
434  * (except cards equipped with 4 UARTs) and initial clocking settings
435  * are stored in the EEPROM chip. It can cause problems because this
436  * version of serial driver doesn't support differently clocked UART's
437  * on single PCI card. To prevent this, initialization functions set
438  * high frequency clocking for all UART's on given card. It is safe (I
439  * hope) because it doesn't touch EEPROM settings to prevent conflicts
440  * with other OSes (like M$ DOS).
441  *
442  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
443  *
444  * There is two family of SIIG serial cards with different PCI
445  * interface chip and different configuration methods:
446  *     - 10x cards have control registers in IO and/or memory space;
447  *     - 20x cards have control registers in standard PCI configuration space.
448  *
449  * Note: all 10x cards have PCI device ids 0x10..
450  *       all 20x cards have PCI device ids 0x20..
451  *
452  * There are also Quartet Serial cards which use Oxford Semiconductor
453  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
454  *
455  * Note: some SIIG cards are probed by the parport_serial object.
456  */
457
458 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
459 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
460
461 static int pci_siig10x_init(struct pci_dev *dev)
462 {
463         u16 data;
464         void __iomem *p;
465
466         switch (dev->device & 0xfff8) {
467         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
468                 data = 0xffdf;
469                 break;
470         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
471                 data = 0xf7ff;
472                 break;
473         default:                        /* 1S1P, 4S */
474                 data = 0xfffb;
475                 break;
476         }
477
478         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
479         if (p == NULL)
480                 return -ENOMEM;
481
482         writew(readw(p + 0x28) & data, p + 0x28);
483         readw(p + 0x28);
484         iounmap(p);
485         return 0;
486 }
487
488 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
489 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
490
491 static int pci_siig20x_init(struct pci_dev *dev)
492 {
493         u8 data;
494
495         /* Change clock frequency for the first UART. */
496         pci_read_config_byte(dev, 0x6f, &data);
497         pci_write_config_byte(dev, 0x6f, data & 0xef);
498
499         /* If this card has 2 UART, we have to do the same with second UART. */
500         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
501             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
502                 pci_read_config_byte(dev, 0x73, &data);
503                 pci_write_config_byte(dev, 0x73, data & 0xef);
504         }
505         return 0;
506 }
507
508 static int pci_siig_init(struct pci_dev *dev)
509 {
510         unsigned int type = dev->device & 0xff00;
511
512         if (type == 0x1000)
513                 return pci_siig10x_init(dev);
514         else if (type == 0x2000)
515                 return pci_siig20x_init(dev);
516
517         moan_device("Unknown SIIG card", dev);
518         return -ENODEV;
519 }
520
521 static int pci_siig_setup(struct serial_private *priv,
522                           const struct pciserial_board *board,
523                           struct uart_port *port, int idx)
524 {
525         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
526
527         if (idx > 3) {
528                 bar = 4;
529                 offset = (idx - 4) * 8;
530         }
531
532         return setup_port(priv, port, bar, offset, 0);
533 }
534
535 /*
536  * Timedia has an explosion of boards, and to avoid the PCI table from
537  * growing *huge*, we use this function to collapse some 70 entries
538  * in the PCI table into one, for sanity's and compactness's sake.
539  */
540 static const unsigned short timedia_single_port[] = {
541         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
542 };
543
544 static const unsigned short timedia_dual_port[] = {
545         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
546         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
547         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
548         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
549         0xD079, 0
550 };
551
552 static const unsigned short timedia_quad_port[] = {
553         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
554         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
555         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
556         0xB157, 0
557 };
558
559 static const unsigned short timedia_eight_port[] = {
560         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
561         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
562 };
563
564 static const struct timedia_struct {
565         int num;
566         const unsigned short *ids;
567 } timedia_data[] = {
568         { 1, timedia_single_port },
569         { 2, timedia_dual_port },
570         { 4, timedia_quad_port },
571         { 8, timedia_eight_port }
572 };
573
574 static int pci_timedia_init(struct pci_dev *dev)
575 {
576         const unsigned short *ids;
577         int i, j;
578
579         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
580                 ids = timedia_data[i].ids;
581                 for (j = 0; ids[j]; j++)
582                         if (dev->subsystem_device == ids[j])
583                                 return timedia_data[i].num;
584         }
585         return 0;
586 }
587
588 /*
589  * Timedia/SUNIX uses a mixture of BARs and offsets
590  * Ugh, this is ugly as all hell --- TYT
591  */
592 static int
593 pci_timedia_setup(struct serial_private *priv,
594                   const struct pciserial_board *board,
595                   struct uart_port *port, int idx)
596 {
597         unsigned int bar = 0, offset = board->first_offset;
598
599         switch (idx) {
600         case 0:
601                 bar = 0;
602                 break;
603         case 1:
604                 offset = board->uart_offset;
605                 bar = 0;
606                 break;
607         case 2:
608                 bar = 1;
609                 break;
610         case 3:
611                 offset = board->uart_offset;
612                 /* FALLTHROUGH */
613         case 4: /* BAR 2 */
614         case 5: /* BAR 3 */
615         case 6: /* BAR 4 */
616         case 7: /* BAR 5 */
617                 bar = idx - 2;
618         }
619
620         return setup_port(priv, port, bar, offset, board->reg_shift);
621 }
622
623 /*
624  * Some Titan cards are also a little weird
625  */
626 static int
627 titan_400l_800l_setup(struct serial_private *priv,
628                       const struct pciserial_board *board,
629                       struct uart_port *port, int idx)
630 {
631         unsigned int bar, offset = board->first_offset;
632
633         switch (idx) {
634         case 0:
635                 bar = 1;
636                 break;
637         case 1:
638                 bar = 2;
639                 break;
640         default:
641                 bar = 4;
642                 offset = (idx - 2) * board->uart_offset;
643         }
644
645         return setup_port(priv, port, bar, offset, board->reg_shift);
646 }
647
648 static int pci_xircom_init(struct pci_dev *dev)
649 {
650         msleep(100);
651         return 0;
652 }
653
654 static int pci_ni8420_init(struct pci_dev *dev)
655 {
656         void __iomem *p;
657         unsigned long base, len;
658         unsigned int bar = 0;
659
660         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
661                 moan_device("no memory in bar", dev);
662                 return 0;
663         }
664
665         base = pci_resource_start(dev, bar);
666         len =  pci_resource_len(dev, bar);
667         p = ioremap_nocache(base, len);
668         if (p == NULL)
669                 return -ENOMEM;
670
671         /* Enable CPU Interrupt */
672         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
673                p + NI8420_INT_ENABLE_REG);
674
675         iounmap(p);
676         return 0;
677 }
678
679 #define MITE_IOWBSR1_WSIZE      0xa
680 #define MITE_IOWBSR1_WIN_OFFSET 0x800
681 #define MITE_IOWBSR1_WENAB      (1 << 7)
682 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
683 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
684 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
685
686 static int pci_ni8430_init(struct pci_dev *dev)
687 {
688         void __iomem *p;
689         unsigned long base, len;
690         u32 device_window;
691         unsigned int bar = 0;
692
693         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
694                 moan_device("no memory in bar", dev);
695                 return 0;
696         }
697
698         base = pci_resource_start(dev, bar);
699         len =  pci_resource_len(dev, bar);
700         p = ioremap_nocache(base, len);
701         if (p == NULL)
702                 return -ENOMEM;
703
704         /* Set device window address and size in BAR0 */
705         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
706                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
707         writel(device_window, p + MITE_IOWBSR1);
708
709         /* Set window access to go to RAMSEL IO address space */
710         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
711                p + MITE_IOWCR1);
712
713         /* Enable IO Bus Interrupt 0 */
714         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
715
716         /* Enable CPU Interrupt */
717         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
718
719         iounmap(p);
720         return 0;
721 }
722
723 /* UART Port Control Register */
724 #define NI8430_PORTCON  0x0f
725 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
726
727 static int
728 pci_ni8430_setup(struct serial_private *priv,
729                  const struct pciserial_board *board,
730                  struct uart_port *port, int idx)
731 {
732         void __iomem *p;
733         unsigned long base, len;
734         unsigned int bar, offset = board->first_offset;
735
736         if (idx >= board->num_ports)
737                 return 1;
738
739         bar = FL_GET_BASE(board->flags);
740         offset += idx * board->uart_offset;
741
742         base = pci_resource_start(priv->dev, bar);
743         len =  pci_resource_len(priv->dev, bar);
744         p = ioremap_nocache(base, len);
745
746         /* enable the transciever */
747         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
748                p + offset + NI8430_PORTCON);
749
750         iounmap(p);
751
752         return setup_port(priv, port, bar, offset, board->reg_shift);
753 }
754
755
756 static int pci_netmos_init(struct pci_dev *dev)
757 {
758         /* subdevice 0x00PS means <P> parallel, <S> serial */
759         unsigned int num_serial = dev->subsystem_device & 0xf;
760
761         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
762                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
763                 return 0;
764         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
765                         dev->subsystem_device == 0x0299)
766                 return 0;
767
768         if (num_serial == 0)
769                 return -ENODEV;
770         return num_serial;
771 }
772
773 /*
774  * These chips are available with optionally one parallel port and up to
775  * two serial ports. Unfortunately they all have the same product id.
776  *
777  * Basic configuration is done over a region of 32 I/O ports. The base
778  * ioport is called INTA or INTC, depending on docs/other drivers.
779  *
780  * The region of the 32 I/O ports is configured in POSIO0R...
781  */
782
783 /* registers */
784 #define ITE_887x_MISCR          0x9c
785 #define ITE_887x_INTCBAR        0x78
786 #define ITE_887x_UARTBAR        0x7c
787 #define ITE_887x_PS0BAR         0x10
788 #define ITE_887x_POSIO0         0x60
789
790 /* I/O space size */
791 #define ITE_887x_IOSIZE         32
792 /* I/O space size (bits 26-24; 8 bytes = 011b) */
793 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
794 /* I/O space size (bits 26-24; 32 bytes = 101b) */
795 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
796 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
797 #define ITE_887x_POSIO_SPEED            (3 << 29)
798 /* enable IO_Space bit */
799 #define ITE_887x_POSIO_ENABLE           (1 << 31)
800
801 static int pci_ite887x_init(struct pci_dev *dev)
802 {
803         /* inta_addr are the configuration addresses of the ITE */
804         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
805                                                         0x200, 0x280, 0 };
806         int ret, i, type;
807         struct resource *iobase = NULL;
808         u32 miscr, uartbar, ioport;
809
810         /* search for the base-ioport */
811         i = 0;
812         while (inta_addr[i] && iobase == NULL) {
813                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
814                                                                 "ite887x");
815                 if (iobase != NULL) {
816                         /* write POSIO0R - speed | size | ioport */
817                         pci_write_config_dword(dev, ITE_887x_POSIO0,
818                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
819                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
820                         /* write INTCBAR - ioport */
821                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
822                                                                 inta_addr[i]);
823                         ret = inb(inta_addr[i]);
824                         if (ret != 0xff) {
825                                 /* ioport connected */
826                                 break;
827                         }
828                         release_region(iobase->start, ITE_887x_IOSIZE);
829                         iobase = NULL;
830                 }
831                 i++;
832         }
833
834         if (!inta_addr[i]) {
835                 printk(KERN_ERR "ite887x: could not find iobase\n");
836                 return -ENODEV;
837         }
838
839         /* start of undocumented type checking (see parport_pc.c) */
840         type = inb(iobase->start + 0x18) & 0x0f;
841
842         switch (type) {
843         case 0x2:       /* ITE8871 (1P) */
844         case 0xa:       /* ITE8875 (1P) */
845                 ret = 0;
846                 break;
847         case 0xe:       /* ITE8872 (2S1P) */
848                 ret = 2;
849                 break;
850         case 0x6:       /* ITE8873 (1S) */
851                 ret = 1;
852                 break;
853         case 0x8:       /* ITE8874 (2S) */
854                 ret = 2;
855                 break;
856         default:
857                 moan_device("Unknown ITE887x", dev);
858                 ret = -ENODEV;
859         }
860
861         /* configure all serial ports */
862         for (i = 0; i < ret; i++) {
863                 /* read the I/O port from the device */
864                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
865                                                                 &ioport);
866                 ioport &= 0x0000FF00;   /* the actual base address */
867                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
868                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
869                         ITE_887x_POSIO_IOSIZE_8 | ioport);
870
871                 /* write the ioport to the UARTBAR */
872                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
873                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
874                 uartbar |= (ioport << (16 * i));        /* set the ioport */
875                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
876
877                 /* get current config */
878                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
879                 /* disable interrupts (UARTx_Routing[3:0]) */
880                 miscr &= ~(0xf << (12 - 4 * i));
881                 /* activate the UART (UARTx_En) */
882                 miscr |= 1 << (23 - i);
883                 /* write new config with activated UART */
884                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
885         }
886
887         if (ret <= 0) {
888                 /* the device has no UARTs if we get here */
889                 release_region(iobase->start, ITE_887x_IOSIZE);
890         }
891
892         return ret;
893 }
894
895 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
896 {
897         u32 ioport;
898         /* the ioport is bit 0-15 in POSIO0R */
899         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
900         ioport &= 0xffff;
901         release_region(ioport, ITE_887x_IOSIZE);
902 }
903
904 /*
905  * Oxford Semiconductor Inc.
906  * Check that device is part of the Tornado range of devices, then determine
907  * the number of ports available on the device.
908  */
909 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
910 {
911         u8 __iomem *p;
912         unsigned long deviceID;
913         unsigned int  number_uarts = 0;
914
915         /* OxSemi Tornado devices are all 0xCxxx */
916         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
917             (dev->device & 0xF000) != 0xC000)
918                 return 0;
919
920         p = pci_iomap(dev, 0, 5);
921         if (p == NULL)
922                 return -ENOMEM;
923
924         deviceID = ioread32(p);
925         /* Tornado device */
926         if (deviceID == 0x07000200) {
927                 number_uarts = ioread8(p + 4);
928                 printk(KERN_DEBUG
929                         "%d ports detected on Oxford PCI Express device\n",
930                                                                 number_uarts);
931         }
932         pci_iounmap(dev, p);
933         return number_uarts;
934 }
935
936 static int
937 pci_default_setup(struct serial_private *priv,
938                   const struct pciserial_board *board,
939                   struct uart_port *port, int idx)
940 {
941         unsigned int bar, offset = board->first_offset, maxnr;
942
943         bar = FL_GET_BASE(board->flags);
944         if (board->flags & FL_BASE_BARS)
945                 bar += idx;
946         else
947                 offset += idx * board->uart_offset;
948
949         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
950                 (board->reg_shift + 3);
951
952         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
953                 return 1;
954
955         return setup_port(priv, port, bar, offset, board->reg_shift);
956 }
957
958 static int
959 ce4100_serial_setup(struct serial_private *priv,
960                   const struct pciserial_board *board,
961                   struct uart_port *port, int idx)
962 {
963         int ret;
964
965         ret = setup_port(priv, port, 0, 0, board->reg_shift);
966         port->iotype = UPIO_MEM32;
967         port->type = PORT_XSCALE;
968         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
969         port->regshift = 2;
970
971         return ret;
972 }
973
974 static int
975 pci_omegapci_setup(struct serial_private *priv,
976                       struct pciserial_board *board,
977                       struct uart_port *port, int idx)
978 {
979         return setup_port(priv, port, 2, idx * 8, 0);
980 }
981
982 static int skip_tx_en_setup(struct serial_private *priv,
983                         const struct pciserial_board *board,
984                         struct uart_port *port, int idx)
985 {
986         port->flags |= UPF_NO_TXEN_TEST;
987         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
988                           "[%04x:%04x] subsystem [%04x:%04x]\n",
989                           priv->dev->vendor,
990                           priv->dev->device,
991                           priv->dev->subsystem_vendor,
992                           priv->dev->subsystem_device);
993
994         return pci_default_setup(priv, board, port, idx);
995 }
996
997 /* This should be in linux/pci_ids.h */
998 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
999 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1000 #define PCI_DEVICE_ID_OCTPRO            0x0001
1001 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1002 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1003 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1004 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1005 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1006 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1007 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1008 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1009 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1010 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1011 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1012 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1013 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1014 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1015 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1016 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1017 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1018 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1019 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1020 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1021 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1022 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1023
1024 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1025 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1026
1027 /*
1028  * Master list of serial port init/setup/exit quirks.
1029  * This does not describe the general nature of the port.
1030  * (ie, baud base, number and location of ports, etc)
1031  *
1032  * This list is ordered alphabetically by vendor then device.
1033  * Specific entries must come before more generic entries.
1034  */
1035 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1036         /*
1037         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1038         */
1039         {
1040                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1041                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1042                 .subvendor      = PCI_ANY_ID,
1043                 .subdevice      = PCI_ANY_ID,
1044                 .setup          = addidata_apci7800_setup,
1045         },
1046         /*
1047          * AFAVLAB cards - these may be called via parport_serial
1048          *  It is not clear whether this applies to all products.
1049          */
1050         {
1051                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1052                 .device         = PCI_ANY_ID,
1053                 .subvendor      = PCI_ANY_ID,
1054                 .subdevice      = PCI_ANY_ID,
1055                 .setup          = afavlab_setup,
1056         },
1057         /*
1058          * HP Diva
1059          */
1060         {
1061                 .vendor         = PCI_VENDOR_ID_HP,
1062                 .device         = PCI_DEVICE_ID_HP_DIVA,
1063                 .subvendor      = PCI_ANY_ID,
1064                 .subdevice      = PCI_ANY_ID,
1065                 .init           = pci_hp_diva_init,
1066                 .setup          = pci_hp_diva_setup,
1067         },
1068         /*
1069          * Intel
1070          */
1071         {
1072                 .vendor         = PCI_VENDOR_ID_INTEL,
1073                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1074                 .subvendor      = 0xe4bf,
1075                 .subdevice      = PCI_ANY_ID,
1076                 .init           = pci_inteli960ni_init,
1077                 .setup          = pci_default_setup,
1078         },
1079         {
1080                 .vendor         = PCI_VENDOR_ID_INTEL,
1081                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1082                 .subvendor      = PCI_ANY_ID,
1083                 .subdevice      = PCI_ANY_ID,
1084                 .setup          = skip_tx_en_setup,
1085         },
1086         {
1087                 .vendor         = PCI_VENDOR_ID_INTEL,
1088                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1089                 .subvendor      = PCI_ANY_ID,
1090                 .subdevice      = PCI_ANY_ID,
1091                 .setup          = skip_tx_en_setup,
1092         },
1093         {
1094                 .vendor         = PCI_VENDOR_ID_INTEL,
1095                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1096                 .subvendor      = PCI_ANY_ID,
1097                 .subdevice      = PCI_ANY_ID,
1098                 .setup          = skip_tx_en_setup,
1099         },
1100         {
1101                 .vendor         = PCI_VENDOR_ID_INTEL,
1102                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1103                 .subvendor      = PCI_ANY_ID,
1104                 .subdevice      = PCI_ANY_ID,
1105                 .setup          = ce4100_serial_setup,
1106         },
1107         /*
1108          * ITE
1109          */
1110         {
1111                 .vendor         = PCI_VENDOR_ID_ITE,
1112                 .device         = PCI_DEVICE_ID_ITE_8872,
1113                 .subvendor      = PCI_ANY_ID,
1114                 .subdevice      = PCI_ANY_ID,
1115                 .init           = pci_ite887x_init,
1116                 .setup          = pci_default_setup,
1117                 .exit           = __devexit_p(pci_ite887x_exit),
1118         },
1119         /*
1120          * National Instruments
1121          */
1122         {
1123                 .vendor         = PCI_VENDOR_ID_NI,
1124                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1125                 .subvendor      = PCI_ANY_ID,
1126                 .subdevice      = PCI_ANY_ID,
1127                 .init           = pci_ni8420_init,
1128                 .setup          = pci_default_setup,
1129                 .exit           = __devexit_p(pci_ni8420_exit),
1130         },
1131         {
1132                 .vendor         = PCI_VENDOR_ID_NI,
1133                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1134                 .subvendor      = PCI_ANY_ID,
1135                 .subdevice      = PCI_ANY_ID,
1136                 .init           = pci_ni8420_init,
1137                 .setup          = pci_default_setup,
1138                 .exit           = __devexit_p(pci_ni8420_exit),
1139         },
1140         {
1141                 .vendor         = PCI_VENDOR_ID_NI,
1142                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1143                 .subvendor      = PCI_ANY_ID,
1144                 .subdevice      = PCI_ANY_ID,
1145                 .init           = pci_ni8420_init,
1146                 .setup          = pci_default_setup,
1147                 .exit           = __devexit_p(pci_ni8420_exit),
1148         },
1149         {
1150                 .vendor         = PCI_VENDOR_ID_NI,
1151                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1152                 .subvendor      = PCI_ANY_ID,
1153                 .subdevice      = PCI_ANY_ID,
1154                 .init           = pci_ni8420_init,
1155                 .setup          = pci_default_setup,
1156                 .exit           = __devexit_p(pci_ni8420_exit),
1157         },
1158         {
1159                 .vendor         = PCI_VENDOR_ID_NI,
1160                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1161                 .subvendor      = PCI_ANY_ID,
1162                 .subdevice      = PCI_ANY_ID,
1163                 .init           = pci_ni8420_init,
1164                 .setup          = pci_default_setup,
1165                 .exit           = __devexit_p(pci_ni8420_exit),
1166         },
1167         {
1168                 .vendor         = PCI_VENDOR_ID_NI,
1169                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1170                 .subvendor      = PCI_ANY_ID,
1171                 .subdevice      = PCI_ANY_ID,
1172                 .init           = pci_ni8420_init,
1173                 .setup          = pci_default_setup,
1174                 .exit           = __devexit_p(pci_ni8420_exit),
1175         },
1176         {
1177                 .vendor         = PCI_VENDOR_ID_NI,
1178                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1179                 .subvendor      = PCI_ANY_ID,
1180                 .subdevice      = PCI_ANY_ID,
1181                 .init           = pci_ni8420_init,
1182                 .setup          = pci_default_setup,
1183                 .exit           = __devexit_p(pci_ni8420_exit),
1184         },
1185         {
1186                 .vendor         = PCI_VENDOR_ID_NI,
1187                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1188                 .subvendor      = PCI_ANY_ID,
1189                 .subdevice      = PCI_ANY_ID,
1190                 .init           = pci_ni8420_init,
1191                 .setup          = pci_default_setup,
1192                 .exit           = __devexit_p(pci_ni8420_exit),
1193         },
1194         {
1195                 .vendor         = PCI_VENDOR_ID_NI,
1196                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1197                 .subvendor      = PCI_ANY_ID,
1198                 .subdevice      = PCI_ANY_ID,
1199                 .init           = pci_ni8420_init,
1200                 .setup          = pci_default_setup,
1201                 .exit           = __devexit_p(pci_ni8420_exit),
1202         },
1203         {
1204                 .vendor         = PCI_VENDOR_ID_NI,
1205                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1206                 .subvendor      = PCI_ANY_ID,
1207                 .subdevice      = PCI_ANY_ID,
1208                 .init           = pci_ni8420_init,
1209                 .setup          = pci_default_setup,
1210                 .exit           = __devexit_p(pci_ni8420_exit),
1211         },
1212         {
1213                 .vendor         = PCI_VENDOR_ID_NI,
1214                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1215                 .subvendor      = PCI_ANY_ID,
1216                 .subdevice      = PCI_ANY_ID,
1217                 .init           = pci_ni8420_init,
1218                 .setup          = pci_default_setup,
1219                 .exit           = __devexit_p(pci_ni8420_exit),
1220         },
1221         {
1222                 .vendor         = PCI_VENDOR_ID_NI,
1223                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1224                 .subvendor      = PCI_ANY_ID,
1225                 .subdevice      = PCI_ANY_ID,
1226                 .init           = pci_ni8420_init,
1227                 .setup          = pci_default_setup,
1228                 .exit           = __devexit_p(pci_ni8420_exit),
1229         },
1230         {
1231                 .vendor         = PCI_VENDOR_ID_NI,
1232                 .device         = PCI_ANY_ID,
1233                 .subvendor      = PCI_ANY_ID,
1234                 .subdevice      = PCI_ANY_ID,
1235                 .init           = pci_ni8430_init,
1236                 .setup          = pci_ni8430_setup,
1237                 .exit           = __devexit_p(pci_ni8430_exit),
1238         },
1239         /*
1240          * Panacom
1241          */
1242         {
1243                 .vendor         = PCI_VENDOR_ID_PANACOM,
1244                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1245                 .subvendor      = PCI_ANY_ID,
1246                 .subdevice      = PCI_ANY_ID,
1247                 .init           = pci_plx9050_init,
1248                 .setup          = pci_default_setup,
1249                 .exit           = __devexit_p(pci_plx9050_exit),
1250         },
1251         {
1252                 .vendor         = PCI_VENDOR_ID_PANACOM,
1253                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1254                 .subvendor      = PCI_ANY_ID,
1255                 .subdevice      = PCI_ANY_ID,
1256                 .init           = pci_plx9050_init,
1257                 .setup          = pci_default_setup,
1258                 .exit           = __devexit_p(pci_plx9050_exit),
1259         },
1260         /*
1261          * PLX
1262          */
1263         {
1264                 .vendor         = PCI_VENDOR_ID_PLX,
1265                 .device         = PCI_DEVICE_ID_PLX_9030,
1266                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1267                 .subdevice      = PCI_ANY_ID,
1268                 .setup          = pci_default_setup,
1269         },
1270         {
1271                 .vendor         = PCI_VENDOR_ID_PLX,
1272                 .device         = PCI_DEVICE_ID_PLX_9050,
1273                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1274                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1275                 .init           = pci_plx9050_init,
1276                 .setup          = pci_default_setup,
1277                 .exit           = __devexit_p(pci_plx9050_exit),
1278         },
1279         {
1280                 .vendor         = PCI_VENDOR_ID_PLX,
1281                 .device         = PCI_DEVICE_ID_PLX_9050,
1282                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1283                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1284                 .init           = pci_plx9050_init,
1285                 .setup          = pci_default_setup,
1286                 .exit           = __devexit_p(pci_plx9050_exit),
1287         },
1288         {
1289                 .vendor         = PCI_VENDOR_ID_PLX,
1290                 .device         = PCI_DEVICE_ID_PLX_9050,
1291                 .subvendor      = PCI_VENDOR_ID_PLX,
1292                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1293                 .init           = pci_plx9050_init,
1294                 .setup          = pci_default_setup,
1295                 .exit           = __devexit_p(pci_plx9050_exit),
1296         },
1297         {
1298                 .vendor         = PCI_VENDOR_ID_PLX,
1299                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1300                 .subvendor      = PCI_VENDOR_ID_PLX,
1301                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1302                 .init           = pci_plx9050_init,
1303                 .setup          = pci_default_setup,
1304                 .exit           = __devexit_p(pci_plx9050_exit),
1305         },
1306         /*
1307          * SBS Technologies, Inc., PMC-OCTALPRO 232
1308          */
1309         {
1310                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1311                 .device         = PCI_DEVICE_ID_OCTPRO,
1312                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1313                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1314                 .init           = sbs_init,
1315                 .setup          = sbs_setup,
1316                 .exit           = __devexit_p(sbs_exit),
1317         },
1318         /*
1319          * SBS Technologies, Inc., PMC-OCTALPRO 422
1320          */
1321         {
1322                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1323                 .device         = PCI_DEVICE_ID_OCTPRO,
1324                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1325                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1326                 .init           = sbs_init,
1327                 .setup          = sbs_setup,
1328                 .exit           = __devexit_p(sbs_exit),
1329         },
1330         /*
1331          * SBS Technologies, Inc., P-Octal 232
1332          */
1333         {
1334                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1335                 .device         = PCI_DEVICE_ID_OCTPRO,
1336                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1337                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1338                 .init           = sbs_init,
1339                 .setup          = sbs_setup,
1340                 .exit           = __devexit_p(sbs_exit),
1341         },
1342         /*
1343          * SBS Technologies, Inc., P-Octal 422
1344          */
1345         {
1346                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1347                 .device         = PCI_DEVICE_ID_OCTPRO,
1348                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1349                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1350                 .init           = sbs_init,
1351                 .setup          = sbs_setup,
1352                 .exit           = __devexit_p(sbs_exit),
1353         },
1354         /*
1355          * SIIG cards - these may be called via parport_serial
1356          */
1357         {
1358                 .vendor         = PCI_VENDOR_ID_SIIG,
1359                 .device         = PCI_ANY_ID,
1360                 .subvendor      = PCI_ANY_ID,
1361                 .subdevice      = PCI_ANY_ID,
1362                 .init           = pci_siig_init,
1363                 .setup          = pci_siig_setup,
1364         },
1365         /*
1366          * Titan cards
1367          */
1368         {
1369                 .vendor         = PCI_VENDOR_ID_TITAN,
1370                 .device         = PCI_DEVICE_ID_TITAN_400L,
1371                 .subvendor      = PCI_ANY_ID,
1372                 .subdevice      = PCI_ANY_ID,
1373                 .setup          = titan_400l_800l_setup,
1374         },
1375         {
1376                 .vendor         = PCI_VENDOR_ID_TITAN,
1377                 .device         = PCI_DEVICE_ID_TITAN_800L,
1378                 .subvendor      = PCI_ANY_ID,
1379                 .subdevice      = PCI_ANY_ID,
1380                 .setup          = titan_400l_800l_setup,
1381         },
1382         /*
1383          * Timedia cards
1384          */
1385         {
1386                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1387                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1388                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1389                 .subdevice      = PCI_ANY_ID,
1390                 .init           = pci_timedia_init,
1391                 .setup          = pci_timedia_setup,
1392         },
1393         {
1394                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1395                 .device         = PCI_ANY_ID,
1396                 .subvendor      = PCI_ANY_ID,
1397                 .subdevice      = PCI_ANY_ID,
1398                 .setup          = pci_timedia_setup,
1399         },
1400         /*
1401          * Xircom cards
1402          */
1403         {
1404                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1405                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1406                 .subvendor      = PCI_ANY_ID,
1407                 .subdevice      = PCI_ANY_ID,
1408                 .init           = pci_xircom_init,
1409                 .setup          = pci_default_setup,
1410         },
1411         /*
1412          * Netmos cards - these may be called via parport_serial
1413          */
1414         {
1415                 .vendor         = PCI_VENDOR_ID_NETMOS,
1416                 .device         = PCI_ANY_ID,
1417                 .subvendor      = PCI_ANY_ID,
1418                 .subdevice      = PCI_ANY_ID,
1419                 .init           = pci_netmos_init,
1420                 .setup          = pci_default_setup,
1421         },
1422         /*
1423          * For Oxford Semiconductor Tornado based devices
1424          */
1425         {
1426                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1427                 .device         = PCI_ANY_ID,
1428                 .subvendor      = PCI_ANY_ID,
1429                 .subdevice      = PCI_ANY_ID,
1430                 .init           = pci_oxsemi_tornado_init,
1431                 .setup          = pci_default_setup,
1432         },
1433         {
1434                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1435                 .device         = PCI_ANY_ID,
1436                 .subvendor      = PCI_ANY_ID,
1437                 .subdevice      = PCI_ANY_ID,
1438                 .init           = pci_oxsemi_tornado_init,
1439                 .setup          = pci_default_setup,
1440         },
1441         {
1442                 .vendor         = PCI_VENDOR_ID_DIGI,
1443                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1444                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1445                 .subdevice              = PCI_ANY_ID,
1446                 .init                   = pci_oxsemi_tornado_init,
1447                 .setup          = pci_default_setup,
1448         },
1449         /*
1450          * Cronyx Omega PCI (PLX-chip based)
1451          */
1452         {
1453                 .vendor         = PCI_VENDOR_ID_PLX,
1454                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1455                 .subvendor      = PCI_ANY_ID,
1456                 .subdevice      = PCI_ANY_ID,
1457                 .setup          = pci_omegapci_setup,
1458          },
1459         /*
1460          * Default "match everything" terminator entry
1461          */
1462         {
1463                 .vendor         = PCI_ANY_ID,
1464                 .device         = PCI_ANY_ID,
1465                 .subvendor      = PCI_ANY_ID,
1466                 .subdevice      = PCI_ANY_ID,
1467                 .setup          = pci_default_setup,
1468         }
1469 };
1470
1471 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1472 {
1473         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1474 }
1475
1476 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1477 {
1478         struct pci_serial_quirk *quirk;
1479
1480         for (quirk = pci_serial_quirks; ; quirk++)
1481                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1482                     quirk_id_matches(quirk->device, dev->device) &&
1483                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1484                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1485                         break;
1486         return quirk;
1487 }
1488
1489 static inline int get_pci_irq(struct pci_dev *dev,
1490                                 const struct pciserial_board *board)
1491 {
1492         if (board->flags & FL_NOIRQ)
1493                 return 0;
1494         else
1495                 return dev->irq;
1496 }
1497
1498 /*
1499  * This is the configuration table for all of the PCI serial boards
1500  * which we support.  It is directly indexed by the pci_board_num_t enum
1501  * value, which is encoded in the pci_device_id PCI probe table's
1502  * driver_data member.
1503  *
1504  * The makeup of these names are:
1505  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1506  *
1507  *  bn          = PCI BAR number
1508  *  bt          = Index using PCI BARs
1509  *  n           = number of serial ports
1510  *  baud        = baud rate
1511  *  offsetinhex = offset for each sequential port (in hex)
1512  *
1513  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1514  *
1515  * Please note: in theory if n = 1, _bt infix should make no difference.
1516  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1517  */
1518 enum pci_board_num_t {
1519         pbn_default = 0,
1520
1521         pbn_b0_1_115200,
1522         pbn_b0_2_115200,
1523         pbn_b0_4_115200,
1524         pbn_b0_5_115200,
1525         pbn_b0_8_115200,
1526
1527         pbn_b0_1_921600,
1528         pbn_b0_2_921600,
1529         pbn_b0_4_921600,
1530
1531         pbn_b0_2_1130000,
1532
1533         pbn_b0_4_1152000,
1534
1535         pbn_b0_2_1843200,
1536         pbn_b0_4_1843200,
1537
1538         pbn_b0_2_1843200_200,
1539         pbn_b0_4_1843200_200,
1540         pbn_b0_8_1843200_200,
1541
1542         pbn_b0_1_4000000,
1543
1544         pbn_b0_bt_1_115200,
1545         pbn_b0_bt_2_115200,
1546         pbn_b0_bt_4_115200,
1547         pbn_b0_bt_8_115200,
1548
1549         pbn_b0_bt_1_460800,
1550         pbn_b0_bt_2_460800,
1551         pbn_b0_bt_4_460800,
1552
1553         pbn_b0_bt_1_921600,
1554         pbn_b0_bt_2_921600,
1555         pbn_b0_bt_4_921600,
1556         pbn_b0_bt_8_921600,
1557
1558         pbn_b1_1_115200,
1559         pbn_b1_2_115200,
1560         pbn_b1_4_115200,
1561         pbn_b1_8_115200,
1562         pbn_b1_16_115200,
1563
1564         pbn_b1_1_921600,
1565         pbn_b1_2_921600,
1566         pbn_b1_4_921600,
1567         pbn_b1_8_921600,
1568
1569         pbn_b1_2_1250000,
1570
1571         pbn_b1_bt_1_115200,
1572         pbn_b1_bt_2_115200,
1573         pbn_b1_bt_4_115200,
1574
1575         pbn_b1_bt_2_921600,
1576
1577         pbn_b1_1_1382400,
1578         pbn_b1_2_1382400,
1579         pbn_b1_4_1382400,
1580         pbn_b1_8_1382400,
1581
1582         pbn_b2_1_115200,
1583         pbn_b2_2_115200,
1584         pbn_b2_4_115200,
1585         pbn_b2_8_115200,
1586
1587         pbn_b2_1_460800,
1588         pbn_b2_4_460800,
1589         pbn_b2_8_460800,
1590         pbn_b2_16_460800,
1591
1592         pbn_b2_1_921600,
1593         pbn_b2_4_921600,
1594         pbn_b2_8_921600,
1595
1596         pbn_b2_8_1152000,
1597
1598         pbn_b2_bt_1_115200,
1599         pbn_b2_bt_2_115200,
1600         pbn_b2_bt_4_115200,
1601
1602         pbn_b2_bt_2_921600,
1603         pbn_b2_bt_4_921600,
1604
1605         pbn_b3_2_115200,
1606         pbn_b3_4_115200,
1607         pbn_b3_8_115200,
1608
1609         pbn_b4_bt_2_921600,
1610         pbn_b4_bt_4_921600,
1611         pbn_b4_bt_8_921600,
1612
1613         /*
1614          * Board-specific versions.
1615          */
1616         pbn_panacom,
1617         pbn_panacom2,
1618         pbn_panacom4,
1619         pbn_exsys_4055,
1620         pbn_plx_romulus,
1621         pbn_oxsemi,
1622         pbn_oxsemi_1_4000000,
1623         pbn_oxsemi_2_4000000,
1624         pbn_oxsemi_4_4000000,
1625         pbn_oxsemi_8_4000000,
1626         pbn_intel_i960,
1627         pbn_sgi_ioc3,
1628         pbn_computone_4,
1629         pbn_computone_6,
1630         pbn_computone_8,
1631         pbn_sbsxrsio,
1632         pbn_exar_XR17C152,
1633         pbn_exar_XR17C154,
1634         pbn_exar_XR17C158,
1635         pbn_exar_ibm_saturn,
1636         pbn_pasemi_1682M,
1637         pbn_ni8430_2,
1638         pbn_ni8430_4,
1639         pbn_ni8430_8,
1640         pbn_ni8430_16,
1641         pbn_ADDIDATA_PCIe_1_3906250,
1642         pbn_ADDIDATA_PCIe_2_3906250,
1643         pbn_ADDIDATA_PCIe_4_3906250,
1644         pbn_ADDIDATA_PCIe_8_3906250,
1645         pbn_ce4100_1_115200,
1646         pbn_omegapci,
1647 };
1648
1649 /*
1650  * uart_offset - the space between channels
1651  * reg_shift   - describes how the UART registers are mapped
1652  *               to PCI memory by the card.
1653  * For example IER register on SBS, Inc. PMC-OctPro is located at
1654  * offset 0x10 from the UART base, while UART_IER is defined as 1
1655  * in include/linux/serial_reg.h,
1656  * see first lines of serial_in() and serial_out() in 8250.c
1657 */
1658
1659 static struct pciserial_board pci_boards[] __devinitdata = {
1660         [pbn_default] = {
1661                 .flags          = FL_BASE0,
1662                 .num_ports      = 1,
1663                 .base_baud      = 115200,
1664                 .uart_offset    = 8,
1665         },
1666         [pbn_b0_1_115200] = {
1667                 .flags          = FL_BASE0,
1668                 .num_ports      = 1,
1669                 .base_baud      = 115200,
1670                 .uart_offset    = 8,
1671         },
1672         [pbn_b0_2_115200] = {
1673                 .flags          = FL_BASE0,
1674                 .num_ports      = 2,
1675                 .base_baud      = 115200,
1676                 .uart_offset    = 8,
1677         },
1678         [pbn_b0_4_115200] = {
1679                 .flags          = FL_BASE0,
1680                 .num_ports      = 4,
1681                 .base_baud      = 115200,
1682                 .uart_offset    = 8,
1683         },
1684         [pbn_b0_5_115200] = {
1685                 .flags          = FL_BASE0,
1686                 .num_ports      = 5,
1687                 .base_baud      = 115200,
1688                 .uart_offset    = 8,
1689         },
1690         [pbn_b0_8_115200] = {
1691                 .flags          = FL_BASE0,
1692                 .num_ports      = 8,
1693                 .base_baud      = 115200,
1694                 .uart_offset    = 8,
1695         },
1696         [pbn_b0_1_921600] = {
1697                 .flags          = FL_BASE0,
1698                 .num_ports      = 1,
1699                 .base_baud      = 921600,
1700                 .uart_offset    = 8,
1701         },
1702         [pbn_b0_2_921600] = {
1703                 .flags          = FL_BASE0,
1704                 .num_ports      = 2,
1705                 .base_baud      = 921600,
1706                 .uart_offset    = 8,
1707         },
1708         [pbn_b0_4_921600] = {
1709                 .flags          = FL_BASE0,
1710                 .num_ports      = 4,
1711                 .base_baud      = 921600,
1712                 .uart_offset    = 8,
1713         },
1714
1715         [pbn_b0_2_1130000] = {
1716                 .flags          = FL_BASE0,
1717                 .num_ports      = 2,
1718                 .base_baud      = 1130000,
1719                 .uart_offset    = 8,
1720         },
1721
1722         [pbn_b0_4_1152000] = {
1723                 .flags          = FL_BASE0,
1724                 .num_ports      = 4,
1725                 .base_baud      = 1152000,
1726                 .uart_offset    = 8,
1727         },
1728
1729         [pbn_b0_2_1843200] = {
1730                 .flags          = FL_BASE0,
1731                 .num_ports      = 2,
1732                 .base_baud      = 1843200,
1733                 .uart_offset    = 8,
1734         },
1735         [pbn_b0_4_1843200] = {
1736                 .flags          = FL_BASE0,
1737                 .num_ports      = 4,
1738                 .base_baud      = 1843200,
1739                 .uart_offset    = 8,
1740         },
1741
1742         [pbn_b0_2_1843200_200] = {
1743                 .flags          = FL_BASE0,
1744                 .num_ports      = 2,
1745                 .base_baud      = 1843200,
1746                 .uart_offset    = 0x200,
1747         },
1748         [pbn_b0_4_1843200_200] = {
1749                 .flags          = FL_BASE0,
1750                 .num_ports      = 4,
1751                 .base_baud      = 1843200,
1752                 .uart_offset    = 0x200,
1753         },
1754         [pbn_b0_8_1843200_200] = {
1755                 .flags          = FL_BASE0,
1756                 .num_ports      = 8,
1757                 .base_baud      = 1843200,
1758                 .uart_offset    = 0x200,
1759         },
1760         [pbn_b0_1_4000000] = {
1761                 .flags          = FL_BASE0,
1762                 .num_ports      = 1,
1763                 .base_baud      = 4000000,
1764                 .uart_offset    = 8,
1765         },
1766
1767         [pbn_b0_bt_1_115200] = {
1768                 .flags          = FL_BASE0|FL_BASE_BARS,
1769                 .num_ports      = 1,
1770                 .base_baud      = 115200,
1771                 .uart_offset    = 8,
1772         },
1773         [pbn_b0_bt_2_115200] = {
1774                 .flags          = FL_BASE0|FL_BASE_BARS,
1775                 .num_ports      = 2,
1776                 .base_baud      = 115200,
1777                 .uart_offset    = 8,
1778         },
1779         [pbn_b0_bt_4_115200] = {
1780                 .flags          = FL_BASE0|FL_BASE_BARS,
1781                 .num_ports      = 4,
1782                 .base_baud      = 115200,
1783                 .uart_offset    = 8,
1784         },
1785         [pbn_b0_bt_8_115200] = {
1786                 .flags          = FL_BASE0|FL_BASE_BARS,
1787                 .num_ports      = 8,
1788                 .base_baud      = 115200,
1789                 .uart_offset    = 8,
1790         },
1791
1792         [pbn_b0_bt_1_460800] = {
1793                 .flags          = FL_BASE0|FL_BASE_BARS,
1794                 .num_ports      = 1,
1795                 .base_baud      = 460800,
1796                 .uart_offset    = 8,
1797         },
1798         [pbn_b0_bt_2_460800] = {
1799                 .flags          = FL_BASE0|FL_BASE_BARS,
1800                 .num_ports      = 2,
1801                 .base_baud      = 460800,
1802                 .uart_offset    = 8,
1803         },
1804         [pbn_b0_bt_4_460800] = {
1805                 .flags          = FL_BASE0|FL_BASE_BARS,
1806                 .num_ports      = 4,
1807                 .base_baud      = 460800,
1808                 .uart_offset    = 8,
1809         },
1810
1811         [pbn_b0_bt_1_921600] = {
1812                 .flags          = FL_BASE0|FL_BASE_BARS,
1813                 .num_ports      = 1,
1814                 .base_baud      = 921600,
1815                 .uart_offset    = 8,
1816         },
1817         [pbn_b0_bt_2_921600] = {
1818                 .flags          = FL_BASE0|FL_BASE_BARS,
1819                 .num_ports      = 2,
1820                 .base_baud      = 921600,
1821                 .uart_offset    = 8,
1822         },
1823         [pbn_b0_bt_4_921600] = {
1824                 .flags          = FL_BASE0|FL_BASE_BARS,
1825                 .num_ports      = 4,
1826                 .base_baud      = 921600,
1827                 .uart_offset    = 8,
1828         },
1829         [pbn_b0_bt_8_921600] = {
1830                 .flags          = FL_BASE0|FL_BASE_BARS,
1831                 .num_ports      = 8,
1832                 .base_baud      = 921600,
1833                 .uart_offset    = 8,
1834         },
1835
1836         [pbn_b1_1_115200] = {
1837                 .flags          = FL_BASE1,
1838                 .num_ports      = 1,
1839                 .base_baud      = 115200,
1840                 .uart_offset    = 8,
1841         },
1842         [pbn_b1_2_115200] = {
1843                 .flags          = FL_BASE1,
1844                 .num_ports      = 2,
1845                 .base_baud      = 115200,
1846                 .uart_offset    = 8,
1847         },
1848         [pbn_b1_4_115200] = {
1849                 .flags          = FL_BASE1,
1850                 .num_ports      = 4,
1851                 .base_baud      = 115200,
1852                 .uart_offset    = 8,
1853         },
1854         [pbn_b1_8_115200] = {
1855                 .flags          = FL_BASE1,
1856                 .num_ports      = 8,
1857                 .base_baud      = 115200,
1858                 .uart_offset    = 8,
1859         },
1860         [pbn_b1_16_115200] = {
1861                 .flags          = FL_BASE1,
1862                 .num_ports      = 16,
1863                 .base_baud      = 115200,
1864                 .uart_offset    = 8,
1865         },
1866
1867         [pbn_b1_1_921600] = {
1868                 .flags          = FL_BASE1,
1869                 .num_ports      = 1,
1870                 .base_baud      = 921600,
1871                 .uart_offset    = 8,
1872         },
1873         [pbn_b1_2_921600] = {
1874                 .flags          = FL_BASE1,
1875                 .num_ports      = 2,
1876                 .base_baud      = 921600,
1877                 .uart_offset    = 8,
1878         },
1879         [pbn_b1_4_921600] = {
1880                 .flags          = FL_BASE1,
1881                 .num_ports      = 4,
1882                 .base_baud      = 921600,
1883                 .uart_offset    = 8,
1884         },
1885         [pbn_b1_8_921600] = {
1886                 .flags          = FL_BASE1,
1887                 .num_ports      = 8,
1888                 .base_baud      = 921600,
1889                 .uart_offset    = 8,
1890         },
1891         [pbn_b1_2_1250000] = {
1892                 .flags          = FL_BASE1,
1893                 .num_ports      = 2,
1894                 .base_baud      = 1250000,
1895                 .uart_offset    = 8,
1896         },
1897
1898         [pbn_b1_bt_1_115200] = {
1899                 .flags          = FL_BASE1|FL_BASE_BARS,
1900                 .num_ports      = 1,
1901                 .base_baud      = 115200,
1902                 .uart_offset    = 8,
1903         },
1904         [pbn_b1_bt_2_115200] = {
1905                 .flags          = FL_BASE1|FL_BASE_BARS,
1906                 .num_ports      = 2,
1907                 .base_baud      = 115200,
1908                 .uart_offset    = 8,
1909         },
1910         [pbn_b1_bt_4_115200] = {
1911                 .flags          = FL_BASE1|FL_BASE_BARS,
1912                 .num_ports      = 4,
1913                 .base_baud      = 115200,
1914                 .uart_offset    = 8,
1915         },
1916
1917         [pbn_b1_bt_2_921600] = {
1918                 .flags          = FL_BASE1|FL_BASE_BARS,
1919                 .num_ports      = 2,
1920                 .base_baud      = 921600,
1921                 .uart_offset    = 8,
1922         },
1923
1924         [pbn_b1_1_1382400] = {
1925                 .flags          = FL_BASE1,
1926                 .num_ports      = 1,
1927                 .base_baud      = 1382400,
1928                 .uart_offset    = 8,
1929         },
1930         [pbn_b1_2_1382400] = {
1931                 .flags          = FL_BASE1,
1932                 .num_ports      = 2,
1933                 .base_baud      = 1382400,
1934                 .uart_offset    = 8,
1935         },
1936         [pbn_b1_4_1382400] = {
1937                 .flags          = FL_BASE1,
1938                 .num_ports      = 4,
1939                 .base_baud      = 1382400,
1940                 .uart_offset    = 8,
1941         },
1942         [pbn_b1_8_1382400] = {
1943                 .flags          = FL_BASE1,
1944                 .num_ports      = 8,
1945                 .base_baud      = 1382400,
1946                 .uart_offset    = 8,
1947         },
1948
1949         [pbn_b2_1_115200] = {
1950                 .flags          = FL_BASE2,
1951                 .num_ports      = 1,
1952                 .base_baud      = 115200,
1953                 .uart_offset    = 8,
1954         },
1955         [pbn_b2_2_115200] = {
1956                 .flags          = FL_BASE2,
1957                 .num_ports      = 2,
1958                 .base_baud      = 115200,
1959                 .uart_offset    = 8,
1960         },
1961         [pbn_b2_4_115200] = {
1962                 .flags          = FL_BASE2,
1963                 .num_ports      = 4,
1964                 .base_baud      = 115200,
1965                 .uart_offset    = 8,
1966         },
1967         [pbn_b2_8_115200] = {
1968                 .flags          = FL_BASE2,
1969                 .num_ports      = 8,
1970                 .base_baud      = 115200,
1971                 .uart_offset    = 8,
1972         },
1973
1974         [pbn_b2_1_460800] = {
1975                 .flags          = FL_BASE2,
1976                 .num_ports      = 1,
1977                 .base_baud      = 460800,
1978                 .uart_offset    = 8,
1979         },
1980         [pbn_b2_4_460800] = {
1981                 .flags          = FL_BASE2,
1982                 .num_ports      = 4,
1983                 .base_baud      = 460800,
1984                 .uart_offset    = 8,
1985         },
1986         [pbn_b2_8_460800] = {
1987                 .flags          = FL_BASE2,
1988                 .num_ports      = 8,
1989                 .base_baud      = 460800,
1990                 .uart_offset    = 8,
1991         },
1992         [pbn_b2_16_460800] = {
1993                 .flags          = FL_BASE2,
1994                 .num_ports      = 16,
1995                 .base_baud      = 460800,
1996                 .uart_offset    = 8,
1997          },
1998
1999         [pbn_b2_1_921600] = {
2000                 .flags          = FL_BASE2,
2001                 .num_ports      = 1,
2002                 .base_baud      = 921600,
2003                 .uart_offset    = 8,
2004         },
2005         [pbn_b2_4_921600] = {
2006                 .flags          = FL_BASE2,
2007                 .num_ports      = 4,
2008                 .base_baud      = 921600,
2009                 .uart_offset    = 8,
2010         },
2011         [pbn_b2_8_921600] = {
2012                 .flags          = FL_BASE2,
2013                 .num_ports      = 8,
2014                 .base_baud      = 921600,
2015                 .uart_offset    = 8,
2016         },
2017
2018         [pbn_b2_8_1152000] = {
2019                 .flags          = FL_BASE2,
2020                 .num_ports      = 8,
2021                 .base_baud      = 1152000,
2022                 .uart_offset    = 8,
2023         },
2024
2025         [pbn_b2_bt_1_115200] = {
2026                 .flags          = FL_BASE2|FL_BASE_BARS,
2027                 .num_ports      = 1,
2028                 .base_baud      = 115200,
2029                 .uart_offset    = 8,
2030         },
2031         [pbn_b2_bt_2_115200] = {
2032                 .flags          = FL_BASE2|FL_BASE_BARS,
2033                 .num_ports      = 2,
2034                 .base_baud      = 115200,
2035                 .uart_offset    = 8,
2036         },
2037         [pbn_b2_bt_4_115200] = {
2038                 .flags          = FL_BASE2|FL_BASE_BARS,
2039                 .num_ports      = 4,
2040                 .base_baud      = 115200,
2041                 .uart_offset    = 8,
2042         },
2043
2044         [pbn_b2_bt_2_921600] = {
2045                 .flags          = FL_BASE2|FL_BASE_BARS,
2046                 .num_ports      = 2,
2047                 .base_baud      = 921600,
2048                 .uart_offset    = 8,
2049         },
2050         [pbn_b2_bt_4_921600] = {
2051                 .flags          = FL_BASE2|FL_BASE_BARS,
2052                 .num_ports      = 4,
2053                 .base_baud      = 921600,
2054                 .uart_offset    = 8,
2055         },
2056
2057         [pbn_b3_2_115200] = {
2058                 .flags          = FL_BASE3,
2059                 .num_ports      = 2,
2060                 .base_baud      = 115200,
2061                 .uart_offset    = 8,
2062         },
2063         [pbn_b3_4_115200] = {
2064                 .flags          = FL_BASE3,
2065                 .num_ports      = 4,
2066                 .base_baud      = 115200,
2067                 .uart_offset    = 8,
2068         },
2069         [pbn_b3_8_115200] = {
2070                 .flags          = FL_BASE3,
2071                 .num_ports      = 8,
2072                 .base_baud      = 115200,
2073                 .uart_offset    = 8,
2074         },
2075
2076         [pbn_b4_bt_2_921600] = {
2077                 .flags          = FL_BASE4,
2078                 .num_ports      = 2,
2079                 .base_baud      = 921600,
2080                 .uart_offset    = 8,
2081         },
2082         [pbn_b4_bt_4_921600] = {
2083                 .flags          = FL_BASE4,
2084                 .num_ports      = 4,
2085                 .base_baud      = 921600,
2086                 .uart_offset    = 8,
2087         },
2088         [pbn_b4_bt_8_921600] = {
2089                 .flags          = FL_BASE4,
2090                 .num_ports      = 8,
2091                 .base_baud      = 921600,
2092                 .uart_offset    = 8,
2093         },
2094
2095         /*
2096          * Entries following this are board-specific.
2097          */
2098
2099         /*
2100          * Panacom - IOMEM
2101          */
2102         [pbn_panacom] = {
2103                 .flags          = FL_BASE2,
2104                 .num_ports      = 2,
2105                 .base_baud      = 921600,
2106                 .uart_offset    = 0x400,
2107                 .reg_shift      = 7,
2108         },
2109         [pbn_panacom2] = {
2110                 .flags          = FL_BASE2|FL_BASE_BARS,
2111                 .num_ports      = 2,
2112                 .base_baud      = 921600,
2113                 .uart_offset    = 0x400,
2114                 .reg_shift      = 7,
2115         },
2116         [pbn_panacom4] = {
2117                 .flags          = FL_BASE2|FL_BASE_BARS,
2118                 .num_ports      = 4,
2119                 .base_baud      = 921600,
2120                 .uart_offset    = 0x400,
2121                 .reg_shift      = 7,
2122         },
2123
2124         [pbn_exsys_4055] = {
2125                 .flags          = FL_BASE2,
2126                 .num_ports      = 4,
2127                 .base_baud      = 115200,
2128                 .uart_offset    = 8,
2129         },
2130
2131         /* I think this entry is broken - the first_offset looks wrong --rmk */
2132         [pbn_plx_romulus] = {
2133                 .flags          = FL_BASE2,
2134                 .num_ports      = 4,
2135                 .base_baud      = 921600,
2136                 .uart_offset    = 8 << 2,
2137                 .reg_shift      = 2,
2138                 .first_offset   = 0x03,
2139         },
2140
2141         /*
2142          * This board uses the size of PCI Base region 0 to
2143          * signal now many ports are available
2144          */
2145         [pbn_oxsemi] = {
2146                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2147                 .num_ports      = 32,
2148                 .base_baud      = 115200,
2149                 .uart_offset    = 8,
2150         },
2151         [pbn_oxsemi_1_4000000] = {
2152                 .flags          = FL_BASE0,
2153                 .num_ports      = 1,
2154                 .base_baud      = 4000000,
2155                 .uart_offset    = 0x200,
2156                 .first_offset   = 0x1000,
2157         },
2158         [pbn_oxsemi_2_4000000] = {
2159                 .flags          = FL_BASE0,
2160                 .num_ports      = 2,
2161                 .base_baud      = 4000000,
2162                 .uart_offset    = 0x200,
2163                 .first_offset   = 0x1000,
2164         },
2165         [pbn_oxsemi_4_4000000] = {
2166                 .flags          = FL_BASE0,
2167                 .num_ports      = 4,
2168                 .base_baud      = 4000000,
2169                 .uart_offset    = 0x200,
2170                 .first_offset   = 0x1000,
2171         },
2172         [pbn_oxsemi_8_4000000] = {
2173                 .flags          = FL_BASE0,
2174                 .num_ports      = 8,
2175                 .base_baud      = 4000000,
2176                 .uart_offset    = 0x200,
2177                 .first_offset   = 0x1000,
2178         },
2179
2180
2181         /*
2182          * EKF addition for i960 Boards form EKF with serial port.
2183          * Max 256 ports.
2184          */
2185         [pbn_intel_i960] = {
2186                 .flags          = FL_BASE0,
2187                 .num_ports      = 32,
2188                 .base_baud      = 921600,
2189                 .uart_offset    = 8 << 2,
2190                 .reg_shift      = 2,
2191                 .first_offset   = 0x10000,
2192         },
2193         [pbn_sgi_ioc3] = {
2194                 .flags          = FL_BASE0|FL_NOIRQ,
2195                 .num_ports      = 1,
2196                 .base_baud      = 458333,
2197                 .uart_offset    = 8,
2198                 .reg_shift      = 0,
2199                 .first_offset   = 0x20178,
2200         },
2201
2202         /*
2203          * Computone - uses IOMEM.
2204          */
2205         [pbn_computone_4] = {
2206                 .flags          = FL_BASE0,
2207                 .num_ports      = 4,
2208                 .base_baud      = 921600,
2209                 .uart_offset    = 0x40,
2210                 .reg_shift      = 2,
2211                 .first_offset   = 0x200,
2212         },
2213         [pbn_computone_6] = {
2214                 .flags          = FL_BASE0,
2215                 .num_ports      = 6,
2216                 .base_baud      = 921600,
2217                 .uart_offset    = 0x40,
2218                 .reg_shift      = 2,
2219                 .first_offset   = 0x200,
2220         },
2221         [pbn_computone_8] = {
2222                 .flags          = FL_BASE0,
2223                 .num_ports      = 8,
2224                 .base_baud      = 921600,
2225                 .uart_offset    = 0x40,
2226                 .reg_shift      = 2,
2227                 .first_offset   = 0x200,
2228         },
2229         [pbn_sbsxrsio] = {
2230                 .flags          = FL_BASE0,
2231                 .num_ports      = 8,
2232                 .base_baud      = 460800,
2233                 .uart_offset    = 256,
2234                 .reg_shift      = 4,
2235         },
2236         /*
2237          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2238          *  Only basic 16550A support.
2239          *  XR17C15[24] are not tested, but they should work.
2240          */
2241         [pbn_exar_XR17C152] = {
2242                 .flags          = FL_BASE0,
2243                 .num_ports      = 2,
2244                 .base_baud      = 921600,
2245                 .uart_offset    = 0x200,
2246         },
2247         [pbn_exar_XR17C154] = {
2248                 .flags          = FL_BASE0,
2249                 .num_ports      = 4,
2250                 .base_baud      = 921600,
2251                 .uart_offset    = 0x200,
2252         },
2253         [pbn_exar_XR17C158] = {
2254                 .flags          = FL_BASE0,
2255                 .num_ports      = 8,
2256                 .base_baud      = 921600,
2257                 .uart_offset    = 0x200,
2258         },
2259         [pbn_exar_ibm_saturn] = {
2260                 .flags          = FL_BASE0,
2261                 .num_ports      = 1,
2262                 .base_baud      = 921600,
2263                 .uart_offset    = 0x200,
2264         },
2265
2266         /*
2267          * PA Semi PWRficient PA6T-1682M on-chip UART
2268          */
2269         [pbn_pasemi_1682M] = {
2270                 .flags          = FL_BASE0,
2271                 .num_ports      = 1,
2272                 .base_baud      = 8333333,
2273         },
2274         /*
2275          * National Instruments 843x
2276          */
2277         [pbn_ni8430_16] = {
2278                 .flags          = FL_BASE0,
2279                 .num_ports      = 16,
2280                 .base_baud      = 3686400,
2281                 .uart_offset    = 0x10,
2282                 .first_offset   = 0x800,
2283         },
2284         [pbn_ni8430_8] = {
2285                 .flags          = FL_BASE0,
2286                 .num_ports      = 8,
2287                 .base_baud      = 3686400,
2288                 .uart_offset    = 0x10,
2289                 .first_offset   = 0x800,
2290         },
2291         [pbn_ni8430_4] = {
2292                 .flags          = FL_BASE0,
2293                 .num_ports      = 4,
2294                 .base_baud      = 3686400,
2295                 .uart_offset    = 0x10,
2296                 .first_offset   = 0x800,
2297         },
2298         [pbn_ni8430_2] = {
2299                 .flags          = FL_BASE0,
2300                 .num_ports      = 2,
2301                 .base_baud      = 3686400,
2302                 .uart_offset    = 0x10,
2303                 .first_offset   = 0x800,
2304         },
2305         /*
2306          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2307          */
2308         [pbn_ADDIDATA_PCIe_1_3906250] = {
2309                 .flags          = FL_BASE0,
2310                 .num_ports      = 1,
2311                 .base_baud      = 3906250,
2312                 .uart_offset    = 0x200,
2313                 .first_offset   = 0x1000,
2314         },
2315         [pbn_ADDIDATA_PCIe_2_3906250] = {
2316                 .flags          = FL_BASE0,
2317                 .num_ports      = 2,
2318                 .base_baud      = 3906250,
2319                 .uart_offset    = 0x200,
2320                 .first_offset   = 0x1000,
2321         },
2322         [pbn_ADDIDATA_PCIe_4_3906250] = {
2323                 .flags          = FL_BASE0,
2324                 .num_ports      = 4,
2325                 .base_baud      = 3906250,
2326                 .uart_offset    = 0x200,
2327                 .first_offset   = 0x1000,
2328         },
2329         [pbn_ADDIDATA_PCIe_8_3906250] = {
2330                 .flags          = FL_BASE0,
2331                 .num_ports      = 8,
2332                 .base_baud      = 3906250,
2333                 .uart_offset    = 0x200,
2334                 .first_offset   = 0x1000,
2335         },
2336         [pbn_ce4100_1_115200] = {
2337                 .flags          = FL_BASE0,
2338                 .num_ports      = 1,
2339                 .base_baud      = 921600,
2340                 .reg_shift      = 2,
2341         },
2342         [pbn_omegapci] = {
2343                 .flags          = FL_BASE0,
2344                 .num_ports      = 8,
2345                 .base_baud      = 115200,
2346                 .uart_offset    = 0x200,
2347         },
2348 };
2349
2350 static const struct pci_device_id softmodem_blacklist[] = {
2351         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2352         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2353         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2354 };
2355
2356 /*
2357  * Given a complete unknown PCI device, try to use some heuristics to
2358  * guess what the configuration might be, based on the pitiful PCI
2359  * serial specs.  Returns 0 on success, 1 on failure.
2360  */
2361 static int __devinit
2362 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2363 {
2364         const struct pci_device_id *blacklist;
2365         int num_iomem, num_port, first_port = -1, i;
2366
2367         /*
2368          * If it is not a communications device or the programming
2369          * interface is greater than 6, give up.
2370          *
2371          * (Should we try to make guesses for multiport serial devices
2372          * later?)
2373          */
2374         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2375              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2376             (dev->class & 0xff) > 6)
2377                 return -ENODEV;
2378
2379         /*
2380          * Do not access blacklisted devices that are known not to
2381          * feature serial ports.
2382          */
2383         for (blacklist = softmodem_blacklist;
2384              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2385              blacklist++) {
2386                 if (dev->vendor == blacklist->vendor &&
2387                     dev->device == blacklist->device)
2388                         return -ENODEV;
2389         }
2390
2391         num_iomem = num_port = 0;
2392         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2393                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2394                         num_port++;
2395                         if (first_port == -1)
2396                                 first_port = i;
2397                 }
2398                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2399                         num_iomem++;
2400         }
2401
2402         /*
2403          * If there is 1 or 0 iomem regions, and exactly one port,
2404          * use it.  We guess the number of ports based on the IO
2405          * region size.
2406          */
2407         if (num_iomem <= 1 && num_port == 1) {
2408                 board->flags = first_port;
2409                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2410                 return 0;
2411         }
2412
2413         /*
2414          * Now guess if we've got a board which indexes by BARs.
2415          * Each IO BAR should be 8 bytes, and they should follow
2416          * consecutively.
2417          */
2418         first_port = -1;
2419         num_port = 0;
2420         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2421                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2422                     pci_resource_len(dev, i) == 8 &&
2423                     (first_port == -1 || (first_port + num_port) == i)) {
2424                         num_port++;
2425                         if (first_port == -1)
2426                                 first_port = i;
2427                 }
2428         }
2429
2430         if (num_port > 1) {
2431                 board->flags = first_port | FL_BASE_BARS;
2432                 board->num_ports = num_port;
2433                 return 0;
2434         }
2435
2436         return -ENODEV;
2437 }
2438
2439 static inline int
2440 serial_pci_matches(const struct pciserial_board *board,
2441                    const struct pciserial_board *guessed)
2442 {
2443         return
2444             board->num_ports == guessed->num_ports &&
2445             board->base_baud == guessed->base_baud &&
2446             board->uart_offset == guessed->uart_offset &&
2447             board->reg_shift == guessed->reg_shift &&
2448             board->first_offset == guessed->first_offset;
2449 }
2450
2451 struct serial_private *
2452 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2453 {
2454         struct uart_port serial_port;
2455         struct serial_private *priv;
2456         struct pci_serial_quirk *quirk;
2457         int rc, nr_ports, i;
2458
2459         nr_ports = board->num_ports;
2460
2461         /*
2462          * Find an init and setup quirks.
2463          */
2464         quirk = find_quirk(dev);
2465
2466         /*
2467          * Run the new-style initialization function.
2468          * The initialization function returns:
2469          *  <0  - error
2470          *   0  - use board->num_ports
2471          *  >0  - number of ports
2472          */
2473         if (quirk->init) {
2474                 rc = quirk->init(dev);
2475                 if (rc < 0) {
2476                         priv = ERR_PTR(rc);
2477                         goto err_out;
2478                 }
2479                 if (rc)
2480                         nr_ports = rc;
2481         }
2482
2483         priv = kzalloc(sizeof(struct serial_private) +
2484                        sizeof(unsigned int) * nr_ports,
2485                        GFP_KERNEL);
2486         if (!priv) {
2487                 priv = ERR_PTR(-ENOMEM);
2488                 goto err_deinit;
2489         }
2490
2491         priv->dev = dev;
2492         priv->quirk = quirk;
2493
2494         memset(&serial_port, 0, sizeof(struct uart_port));
2495         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2496         serial_port.uartclk = board->base_baud * 16;
2497         serial_port.irq = get_pci_irq(dev, board);
2498         serial_port.dev = &dev->dev;
2499
2500         for (i = 0; i < nr_ports; i++) {
2501                 if (quirk->setup(priv, board, &serial_port, i))
2502                         break;
2503
2504 #ifdef SERIAL_DEBUG_PCI
2505                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2506                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2507 #endif
2508
2509                 priv->line[i] = serial8250_register_port(&serial_port);
2510                 if (priv->line[i] < 0) {
2511                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2512                         break;
2513                 }
2514         }
2515         priv->nr = i;
2516         return priv;
2517
2518 err_deinit:
2519         if (quirk->exit)
2520                 quirk->exit(dev);
2521 err_out:
2522         return priv;
2523 }
2524 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2525
2526 void pciserial_remove_ports(struct serial_private *priv)
2527 {
2528         struct pci_serial_quirk *quirk;
2529         int i;
2530
2531         for (i = 0; i < priv->nr; i++)
2532                 serial8250_unregister_port(priv->line[i]);
2533
2534         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2535                 if (priv->remapped_bar[i])
2536                         iounmap(priv->remapped_bar[i]);
2537                 priv->remapped_bar[i] = NULL;
2538         }
2539
2540         /*
2541          * Find the exit quirks.
2542          */
2543         quirk = find_quirk(priv->dev);
2544         if (quirk->exit)
2545                 quirk->exit(priv->dev);
2546
2547         kfree(priv);
2548 }
2549 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2550
2551 void pciserial_suspend_ports(struct serial_private *priv)
2552 {
2553         int i;
2554
2555         for (i = 0; i < priv->nr; i++)
2556                 if (priv->line[i] >= 0)
2557                         serial8250_suspend_port(priv->line[i]);
2558 }
2559 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2560
2561 void pciserial_resume_ports(struct serial_private *priv)
2562 {
2563         int i;
2564
2565         /*
2566          * Ensure that the board is correctly configured.
2567          */
2568         if (priv->quirk->init)
2569                 priv->quirk->init(priv->dev);
2570
2571         for (i = 0; i < priv->nr; i++)
2572                 if (priv->line[i] >= 0)
2573                         serial8250_resume_port(priv->line[i]);
2574 }
2575 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2576
2577 /*
2578  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2579  * to the arrangement of serial ports on a PCI card.
2580  */
2581 static int __devinit
2582 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2583 {
2584         struct serial_private *priv;
2585         const struct pciserial_board *board;
2586         struct pciserial_board tmp;
2587         int rc;
2588
2589         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2590                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2591                         ent->driver_data);
2592                 return -EINVAL;
2593         }
2594
2595         board = &pci_boards[ent->driver_data];
2596
2597         rc = pci_enable_device(dev);
2598         if (rc)
2599                 return rc;
2600
2601         if (ent->driver_data == pbn_default) {
2602                 /*
2603                  * Use a copy of the pci_board entry for this;
2604                  * avoid changing entries in the table.
2605                  */
2606                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2607                 board = &tmp;
2608
2609                 /*
2610                  * We matched one of our class entries.  Try to
2611                  * determine the parameters of this board.
2612                  */
2613                 rc = serial_pci_guess_board(dev, &tmp);
2614                 if (rc)
2615                         goto disable;
2616         } else {
2617                 /*
2618                  * We matched an explicit entry.  If we are able to
2619                  * detect this boards settings with our heuristic,
2620                  * then we no longer need this entry.
2621                  */
2622                 memcpy(&tmp, &pci_boards[pbn_default],
2623                        sizeof(struct pciserial_board));
2624                 rc = serial_pci_guess_board(dev, &tmp);
2625                 if (rc == 0 && serial_pci_matches(board, &tmp))
2626                         moan_device("Redundant entry in serial pci_table.",
2627                                     dev);
2628         }
2629
2630         priv = pciserial_init_ports(dev, board);
2631         if (!IS_ERR(priv)) {
2632                 pci_set_drvdata(dev, priv);
2633                 return 0;
2634         }
2635
2636         rc = PTR_ERR(priv);
2637
2638  disable:
2639         pci_disable_device(dev);
2640         return rc;
2641 }
2642
2643 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2644 {
2645         struct serial_private *priv = pci_get_drvdata(dev);
2646
2647         pci_set_drvdata(dev, NULL);
2648
2649         pciserial_remove_ports(priv);
2650
2651         pci_disable_device(dev);
2652 }
2653
2654 #ifdef CONFIG_PM
2655 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2656 {
2657         struct serial_private *priv = pci_get_drvdata(dev);
2658
2659         if (priv)
2660                 pciserial_suspend_ports(priv);
2661
2662         pci_save_state(dev);
2663         pci_set_power_state(dev, pci_choose_state(dev, state));
2664         return 0;
2665 }
2666
2667 static int pciserial_resume_one(struct pci_dev *dev)
2668 {
2669         int err;
2670         struct serial_private *priv = pci_get_drvdata(dev);
2671
2672         pci_set_power_state(dev, PCI_D0);
2673         pci_restore_state(dev);
2674
2675         if (priv) {
2676                 /*
2677                  * The device may have been disabled.  Re-enable it.
2678                  */
2679                 err = pci_enable_device(dev);
2680                 /* FIXME: We cannot simply error out here */
2681                 if (err)
2682                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2683                 pciserial_resume_ports(priv);
2684         }
2685         return 0;
2686 }
2687 #endif
2688
2689 static struct pci_device_id serial_pci_tbl[] = {
2690         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2691         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2692                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2693                 pbn_b2_8_921600 },
2694         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2695                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2696                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2697                 pbn_b1_8_1382400 },
2698         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2699                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2700                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2701                 pbn_b1_4_1382400 },
2702         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2703                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2704                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2705                 pbn_b1_2_1382400 },
2706         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2707                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2708                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2709                 pbn_b1_8_1382400 },
2710         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2711                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2712                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2713                 pbn_b1_4_1382400 },
2714         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2715                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2716                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2717                 pbn_b1_2_1382400 },
2718         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2719                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2720                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2721                 pbn_b1_8_921600 },
2722         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2723                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2724                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2725                 pbn_b1_8_921600 },
2726         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2727                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2728                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2729                 pbn_b1_4_921600 },
2730         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2731                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2732                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2733                 pbn_b1_4_921600 },
2734         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2735                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2736                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2737                 pbn_b1_2_921600 },
2738         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2739                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2740                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2741                 pbn_b1_8_921600 },
2742         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2743                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2744                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2745                 pbn_b1_8_921600 },
2746         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2747                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2748                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2749                 pbn_b1_4_921600 },
2750         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2751                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2752                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2753                 pbn_b1_2_1250000 },
2754         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2755                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2756                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2757                 pbn_b0_2_1843200 },
2758         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2759                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2760                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2761                 pbn_b0_4_1843200 },
2762         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2763                 PCI_VENDOR_ID_AFAVLAB,
2764                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2765                 pbn_b0_4_1152000 },
2766         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2767                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2768                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2769                 pbn_b0_2_1843200_200 },
2770         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2771                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2772                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2773                 pbn_b0_4_1843200_200 },
2774         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2775                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2776                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2777                 pbn_b0_8_1843200_200 },
2778         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2779                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2780                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2781                 pbn_b0_2_1843200_200 },
2782         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2783                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2784                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2785                 pbn_b0_4_1843200_200 },
2786         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2787                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2788                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2789                 pbn_b0_8_1843200_200 },
2790         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2791                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2792                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2793                 pbn_b0_2_1843200_200 },
2794         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2795                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2796                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2797                 pbn_b0_4_1843200_200 },
2798         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2799                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2800                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2801                 pbn_b0_8_1843200_200 },
2802         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2803                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2804                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2805                 pbn_b0_2_1843200_200 },
2806         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2807                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2808                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2809                 pbn_b0_4_1843200_200 },
2810         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2811                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2812                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2813                 pbn_b0_8_1843200_200 },
2814         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2815                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2816                 0, 0, pbn_exar_ibm_saturn },
2817
2818         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2820                 pbn_b2_bt_1_115200 },
2821         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2823                 pbn_b2_bt_2_115200 },
2824         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2826                 pbn_b2_bt_4_115200 },
2827         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2829                 pbn_b2_bt_2_115200 },
2830         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2832                 pbn_b2_bt_4_115200 },
2833         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2835                 pbn_b2_8_115200 },
2836         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2837                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2838                 pbn_b2_8_460800 },
2839         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2840                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2841                 pbn_b2_8_115200 },
2842
2843         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2845                 pbn_b2_bt_2_115200 },
2846         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2848                 pbn_b2_bt_2_921600 },
2849         /*
2850          * VScom SPCOM800, from sl@s.pl
2851          */
2852         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2853                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2854                 pbn_b2_8_921600 },
2855         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2856                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2857                 pbn_b2_4_921600 },
2858         /* Unknown card - subdevice 0x1584 */
2859         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2860                 PCI_VENDOR_ID_PLX,
2861                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2862                 pbn_b0_4_115200 },
2863         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2864                 PCI_SUBVENDOR_ID_KEYSPAN,
2865                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2866                 pbn_panacom },
2867         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2868                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2869                 pbn_panacom4 },
2870         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2871                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2872                 pbn_panacom2 },
2873         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2874                 PCI_VENDOR_ID_ESDGMBH,
2875                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2876                 pbn_b2_4_115200 },
2877         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2878                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2879                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2880                 pbn_b2_4_460800 },
2881         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2882                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2883                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2884                 pbn_b2_8_460800 },
2885         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2886                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2887                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2888                 pbn_b2_16_460800 },
2889         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2890                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2891                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2892                 pbn_b2_16_460800 },
2893         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2894                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2895                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2896                 pbn_b2_4_460800 },
2897         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2898                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2899                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2900                 pbn_b2_8_460800 },
2901         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2902                 PCI_SUBVENDOR_ID_EXSYS,
2903                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2904                 pbn_exsys_4055 },
2905         /*
2906          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2907          * (Exoray@isys.ca)
2908          */
2909         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2910                 0x10b5, 0x106a, 0, 0,
2911                 pbn_plx_romulus },
2912         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2913                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2914                 pbn_b1_4_115200 },
2915         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2917                 pbn_b1_2_115200 },
2918         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2920                 pbn_b1_8_115200 },
2921         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2923                 pbn_b1_8_115200 },
2924         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2925                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2926                 0, 0,
2927                 pbn_b0_4_921600 },
2928         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2929                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2930                 0, 0,
2931                 pbn_b0_4_1152000 },
2932         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
2933                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2934                 pbn_b0_bt_2_921600 },
2935
2936                 /*
2937                  * The below card is a little controversial since it is the
2938                  * subject of a PCI vendor/device ID clash.  (See
2939                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2940                  * For now just used the hex ID 0x950a.
2941                  */
2942         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2943                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2944                 pbn_b0_2_115200 },
2945         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2947                 pbn_b0_2_1130000 },
2948         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2949                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2950                 pbn_b0_1_921600 },
2951         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2952                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2953                 pbn_b0_4_115200 },
2954         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2955                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2956                 pbn_b0_bt_2_921600 },
2957         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2958                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2959                 pbn_b2_8_1152000 },
2960
2961         /*
2962          * Oxford Semiconductor Inc. Tornado PCI express device range.
2963          */
2964         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
2965                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2966                 pbn_b0_1_4000000 },
2967         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
2968                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2969                 pbn_b0_1_4000000 },
2970         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
2971                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2972                 pbn_oxsemi_1_4000000 },
2973         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
2974                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2975                 pbn_oxsemi_1_4000000 },
2976         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
2977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2978                 pbn_b0_1_4000000 },
2979         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
2980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2981                 pbn_b0_1_4000000 },
2982         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
2983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2984                 pbn_oxsemi_1_4000000 },
2985         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
2986                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2987                 pbn_oxsemi_1_4000000 },
2988         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
2989                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2990                 pbn_b0_1_4000000 },
2991         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
2992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993                 pbn_b0_1_4000000 },
2994         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
2995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996                 pbn_b0_1_4000000 },
2997         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
2998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999                 pbn_b0_1_4000000 },
3000         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3002                 pbn_oxsemi_2_4000000 },
3003         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005                 pbn_oxsemi_2_4000000 },
3006         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008                 pbn_oxsemi_4_4000000 },
3009         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011                 pbn_oxsemi_4_4000000 },
3012         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014                 pbn_oxsemi_8_4000000 },
3015         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3017                 pbn_oxsemi_8_4000000 },
3018         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3020                 pbn_oxsemi_1_4000000 },
3021         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3023                 pbn_oxsemi_1_4000000 },
3024         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3025                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026                 pbn_oxsemi_1_4000000 },
3027         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3028                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3029                 pbn_oxsemi_1_4000000 },
3030         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3031                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3032                 pbn_oxsemi_1_4000000 },
3033         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3034                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3035                 pbn_oxsemi_1_4000000 },
3036         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3037                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3038                 pbn_oxsemi_1_4000000 },
3039         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3040                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3041                 pbn_oxsemi_1_4000000 },
3042         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3043                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3044                 pbn_oxsemi_1_4000000 },
3045         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3047                 pbn_oxsemi_1_4000000 },
3048         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3050                 pbn_oxsemi_1_4000000 },
3051         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3052                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3053                 pbn_oxsemi_1_4000000 },
3054         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3055                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3056                 pbn_oxsemi_1_4000000 },
3057         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059                 pbn_oxsemi_1_4000000 },
3060         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062                 pbn_oxsemi_1_4000000 },
3063         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3065                 pbn_oxsemi_1_4000000 },
3066         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3068                 pbn_oxsemi_1_4000000 },
3069         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3071                 pbn_oxsemi_1_4000000 },
3072         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3073                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3074                 pbn_oxsemi_1_4000000 },
3075         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077                 pbn_oxsemi_1_4000000 },
3078         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080                 pbn_oxsemi_1_4000000 },
3081         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3082                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083                 pbn_oxsemi_1_4000000 },
3084         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086                 pbn_oxsemi_1_4000000 },
3087         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089                 pbn_oxsemi_1_4000000 },
3090         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092                 pbn_oxsemi_1_4000000 },
3093         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095                 pbn_oxsemi_1_4000000 },
3096         /*
3097          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3098          */
3099         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3100                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3101                 pbn_oxsemi_1_4000000 },
3102         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3103                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3104                 pbn_oxsemi_2_4000000 },
3105         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3106                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3107                 pbn_oxsemi_4_4000000 },
3108         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3109                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3110                 pbn_oxsemi_8_4000000 },
3111
3112         /*
3113          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3114          */
3115         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3116                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3117                 pbn_oxsemi_2_4000000 },
3118
3119         /*
3120          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3121          * from skokodyn@yahoo.com
3122          */
3123         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3124                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3125                 pbn_sbsxrsio },
3126         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3127                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3128                 pbn_sbsxrsio },
3129         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3130                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3131                 pbn_sbsxrsio },
3132         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3133                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3134                 pbn_sbsxrsio },
3135
3136         /*
3137          * Digitan DS560-558, from jimd@esoft.com
3138          */
3139         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3141                 pbn_b1_1_115200 },
3142
3143         /*
3144          * Titan Electronic cards
3145          *  The 400L and 800L have a custom setup quirk.
3146          */
3147         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149                 pbn_b0_1_921600 },
3150         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152                 pbn_b0_2_921600 },
3153         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155                 pbn_b0_4_921600 },
3156         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158                 pbn_b0_4_921600 },
3159         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161                 pbn_b1_1_921600 },
3162         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164                 pbn_b1_bt_2_921600 },
3165         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167                 pbn_b0_bt_4_921600 },
3168         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170                 pbn_b0_bt_8_921600 },
3171         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3172                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173                 pbn_b4_bt_2_921600 },
3174         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3175                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176                 pbn_b4_bt_4_921600 },
3177         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3178                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179                 pbn_b4_bt_8_921600 },
3180         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3181                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182                 pbn_b0_4_921600 },
3183         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3184                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185                 pbn_b0_4_921600 },
3186         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3187                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3188                 pbn_b0_4_921600 },
3189         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3190                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191                 pbn_oxsemi_1_4000000 },
3192         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3194                 pbn_oxsemi_2_4000000 },
3195         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197                 pbn_oxsemi_4_4000000 },
3198         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200                 pbn_oxsemi_8_4000000 },
3201         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203                 pbn_oxsemi_2_4000000 },
3204         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206                 pbn_oxsemi_2_4000000 },
3207
3208         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210                 pbn_b2_1_460800 },
3211         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213                 pbn_b2_1_460800 },
3214         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216                 pbn_b2_1_460800 },
3217         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219                 pbn_b2_bt_2_921600 },
3220         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222                 pbn_b2_bt_2_921600 },
3223         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3224                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3225                 pbn_b2_bt_2_921600 },
3226         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3227                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228                 pbn_b2_bt_4_921600 },
3229         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3230                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231                 pbn_b2_bt_4_921600 },
3232         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3233                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3234                 pbn_b2_bt_4_921600 },
3235         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3236                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237                 pbn_b0_1_921600 },
3238         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3239                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240                 pbn_b0_1_921600 },
3241         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3242                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3243                 pbn_b0_1_921600 },
3244         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246                 pbn_b0_bt_2_921600 },
3247         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3248                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3249                 pbn_b0_bt_2_921600 },
3250         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3252                 pbn_b0_bt_2_921600 },
3253         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3255                 pbn_b0_bt_4_921600 },
3256         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3258                 pbn_b0_bt_4_921600 },
3259         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3261                 pbn_b0_bt_4_921600 },
3262         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3264                 pbn_b0_bt_8_921600 },
3265         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3267                 pbn_b0_bt_8_921600 },
3268         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3270                 pbn_b0_bt_8_921600 },
3271
3272         /*
3273          * Computone devices submitted by Doug McNash dmcnash@computone.com
3274          */
3275         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3276                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3277                 0, 0, pbn_computone_4 },
3278         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3279                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3280                 0, 0, pbn_computone_8 },
3281         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3282                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3283                 0, 0, pbn_computone_6 },
3284
3285         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi },
3288         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3289                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3290                 pbn_b0_bt_1_921600 },
3291
3292         /*
3293          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3294          */
3295         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3297                 pbn_b0_bt_8_115200 },
3298         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300                 pbn_b0_bt_8_115200 },
3301
3302         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304                 pbn_b0_bt_2_115200 },
3305         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307                 pbn_b0_bt_2_115200 },
3308         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310                 pbn_b0_bt_2_115200 },
3311         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313                 pbn_b0_bt_2_115200 },
3314         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316                 pbn_b0_bt_2_115200 },
3317         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319                 pbn_b0_bt_4_460800 },
3320         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322                 pbn_b0_bt_4_460800 },
3323         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325                 pbn_b0_bt_2_460800 },
3326         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328                 pbn_b0_bt_2_460800 },
3329         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331                 pbn_b0_bt_2_460800 },
3332         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334                 pbn_b0_bt_1_115200 },
3335         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337                 pbn_b0_bt_1_460800 },
3338
3339         /*
3340          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3341          * Cards are identified by their subsystem vendor IDs, which
3342          * (in hex) match the model number.
3343          *
3344          * Note that JC140x are RS422/485 cards which require ox950
3345          * ACR = 0x10, and as such are not currently fully supported.
3346          */
3347         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3348                 0x1204, 0x0004, 0, 0,
3349                 pbn_b0_4_921600 },
3350         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3351                 0x1208, 0x0004, 0, 0,
3352                 pbn_b0_4_921600 },
3353 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3354                 0x1402, 0x0002, 0, 0,
3355                 pbn_b0_2_921600 }, */
3356 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3357                 0x1404, 0x0004, 0, 0,
3358                 pbn_b0_4_921600 }, */
3359         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3360                 0x1208, 0x0004, 0, 0,
3361                 pbn_b0_4_921600 },
3362
3363         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3364                 0x1204, 0x0004, 0, 0,
3365                 pbn_b0_4_921600 },
3366         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3367                 0x1208, 0x0004, 0, 0,
3368                 pbn_b0_4_921600 },
3369         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3370                 0x1208, 0x0004, 0, 0,
3371                 pbn_b0_4_921600 },
3372         /*
3373          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3374          */
3375         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3376                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3377                 pbn_b1_1_1382400 },
3378
3379         /*
3380          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3381          */
3382         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384                 pbn_b1_1_1382400 },
3385
3386         /*
3387          * RAStel 2 port modem, gerg@moreton.com.au
3388          */
3389         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3391                 pbn_b2_bt_2_115200 },
3392
3393         /*
3394          * EKF addition for i960 Boards form EKF with serial port
3395          */
3396         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3397                 0xE4BF, PCI_ANY_ID, 0, 0,
3398                 pbn_intel_i960 },
3399
3400         /*
3401          * Xircom Cardbus/Ethernet combos
3402          */
3403         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3404                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405                 pbn_b0_1_115200 },
3406         /*
3407          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3408          */
3409         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3410                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411                 pbn_b0_1_115200 },
3412
3413         /*
3414          * Untested PCI modems, sent in from various folks...
3415          */
3416
3417         /*
3418          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3419          */
3420         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3421                 0x1048, 0x1500, 0, 0,
3422                 pbn_b1_1_115200 },
3423
3424         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3425                 0xFF00, 0, 0, 0,
3426                 pbn_sgi_ioc3 },
3427
3428         /*
3429          * HP Diva card
3430          */
3431         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3432                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3433                 pbn_b1_1_115200 },
3434         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436                 pbn_b0_5_115200 },
3437         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439                 pbn_b2_1_115200 },
3440
3441         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443                 pbn_b3_2_115200 },
3444         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3445                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446                 pbn_b3_4_115200 },
3447         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449                 pbn_b3_8_115200 },
3450
3451         /*
3452          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3453          */
3454         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3455                 PCI_ANY_ID, PCI_ANY_ID,
3456                 0,
3457                 0, pbn_exar_XR17C152 },
3458         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3459                 PCI_ANY_ID, PCI_ANY_ID,
3460                 0,
3461                 0, pbn_exar_XR17C154 },
3462         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3463                 PCI_ANY_ID, PCI_ANY_ID,
3464                 0,
3465                 0, pbn_exar_XR17C158 },
3466
3467         /*
3468          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3469          */
3470         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472                 pbn_b0_1_115200 },
3473         /*
3474          * ITE
3475          */
3476         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3477                 PCI_ANY_ID, PCI_ANY_ID,
3478                 0, 0,
3479                 pbn_b1_bt_1_115200 },
3480
3481         /*
3482          * IntaShield IS-200
3483          */
3484         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3486                 pbn_b2_2_115200 },
3487         /*
3488          * IntaShield IS-400
3489          */
3490         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3492                 pbn_b2_4_115200 },
3493         /*
3494          * Perle PCI-RAS cards
3495          */
3496         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3497                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3498                 0, 0, pbn_b2_4_921600 },
3499         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3500                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3501                 0, 0, pbn_b2_8_921600 },
3502
3503         /*
3504          * Mainpine series cards: Fairly standard layout but fools
3505          * parts of the autodetect in some cases and uses otherwise
3506          * unmatched communications subclasses in the PCI Express case
3507          */
3508
3509         {       /* RockForceDUO */
3510                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,