drivers/tty/serial/8250/8250_exar.c

   1 /*
   2  *  Probe module for 8250/16550-type Exar chips PCI serial ports.
   3  *
   4  *  Based on drivers/tty/serial/8250/8250_pci.c,
   5  *
   6  *  Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/serial_core.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/tty.h>
  21 #include <linux/8250_pci.h>
  22
  23 #include <asm/byteorder.h>
  24
  25 #include "8250.h"
  26
  27 #define PCI_DEVICE_ID_COMMTECH_4224PCI335       0x0002
  28 #define PCI_DEVICE_ID_COMMTECH_4222PCI335       0x0004
  29 #define PCI_DEVICE_ID_COMMTECH_2324PCI335       0x000a
  30 #define PCI_DEVICE_ID_COMMTECH_2328PCI335       0x000b
  31 #define PCI_DEVICE_ID_COMMTECH_4224PCIE         0x0020
  32 #define PCI_DEVICE_ID_COMMTECH_4228PCIE         0x0021
  33 #define PCI_DEVICE_ID_COMMTECH_4222PCIE         0x0022
  34 #define PCI_DEVICE_ID_EXAR_XR17V4358            0x4358
  35 #define PCI_DEVICE_ID_EXAR_XR17V8358            0x8358
  36
  37 #define UART_EXAR_8XMODE        0x88    /* 8X sampling rate select */
  38
  39 #define UART_EXAR_FCTR          0x08    /* Feature Control Register */
  40 #define UART_FCTR_EXAR_IRDA     0x10    /* IrDa data encode select */
  41 #define UART_FCTR_EXAR_485      0x20    /* Auto 485 half duplex dir ctl */
  42 #define UART_FCTR_EXAR_TRGA     0x00    /* FIFO trigger table A */
  43 #define UART_FCTR_EXAR_TRGB     0x60    /* FIFO trigger table B */
  44 #define UART_FCTR_EXAR_TRGC     0x80    /* FIFO trigger table C */
  45 #define UART_FCTR_EXAR_TRGD     0xc0    /* FIFO trigger table D programmable */
  46
  47 #define UART_EXAR_TXTRG         0x0a    /* Tx FIFO trigger level write-only */
  48 #define UART_EXAR_RXTRG         0x0b    /* Rx FIFO trigger level write-only */
  49
  50 #define UART_EXAR_MPIOINT_7_0   0x8f    /* MPIOINT[7:0] */
  51 #define UART_EXAR_MPIOLVL_7_0   0x90    /* MPIOLVL[7:0] */
  52 #define UART_EXAR_MPIO3T_7_0    0x91    /* MPIO3T[7:0] */
  53 #define UART_EXAR_MPIOINV_7_0   0x92    /* MPIOINV[7:0] */
  54 #define UART_EXAR_MPIOSEL_7_0   0x93    /* MPIOSEL[7:0] */
  55 #define UART_EXAR_MPIOOD_7_0    0x94    /* MPIOOD[7:0] */
  56 #define UART_EXAR_MPIOINT_15_8  0x95    /* MPIOINT[15:8] */
  57 #define UART_EXAR_MPIOLVL_15_8  0x96    /* MPIOLVL[15:8] */
  58 #define UART_EXAR_MPIO3T_15_8   0x97    /* MPIO3T[15:8] */
  59 #define UART_EXAR_MPIOINV_15_8  0x98    /* MPIOINV[15:8] */
  60 #define UART_EXAR_MPIOSEL_15_8  0x99    /* MPIOSEL[15:8] */
  61 #define UART_EXAR_MPIOOD_15_8   0x9a    /* MPIOOD[15:8] */
  62
  63 struct exar8250;
  64
  65 /**
  66  * struct exar8250_board - board information
  67  * @num_ports: number of serial ports
  68  * @reg_shift: describes UART register mapping in PCI memory
  69  */
  70 struct exar8250_board {
  71         unsigned int num_ports;
  72         unsigned int reg_shift;
  73         bool has_slave;
  74         int     (*setup)(struct exar8250 *, struct pci_dev *,
  75                          struct uart_8250_port *, int);
  76         void    (*exit)(struct pci_dev *pcidev);
  77 };
  78
  79 struct exar8250 {
  80         unsigned int            nr;
  81         struct exar8250_board   *board;
  82         int                     line[0];
  83 };
  84
  85 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
  86                          int idx, unsigned int offset,
  87                          struct uart_8250_port *port)
  88 {
  89         const struct exar8250_board *board = priv->board;
  90         unsigned int bar = 0;
  91
  92         if (!pcim_iomap_table(pcidev)[bar] && !pcim_iomap(pcidev, bar, 0))
  93                 return -ENOMEM;
  94
  95         port->port.iotype = UPIO_MEM;
  96         port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
  97         port->port.membase = pcim_iomap_table(pcidev)[bar] + offset;
  98         port->port.regshift = board->reg_shift;
  99
 100         return 0;
 101 }
 102
 103 static int
 104 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 105                      struct uart_8250_port *port, int idx)
 106 {
 107         unsigned int offset = idx * 0x200;
 108         unsigned int baud = 1843200;
 109         u8 __iomem *p;
 110         int err;
 111
 112         port->port.uartclk = baud * 16;
 113
 114         err = default_setup(priv, pcidev, idx, offset, port);
 115         if (err)
 116                 return err;
 117
 118         p = port->port.membase;
 119
 120         writeb(0x00, p + UART_EXAR_8XMODE);
 121         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
 122         writeb(32, p + UART_EXAR_TXTRG);
 123         writeb(32, p + UART_EXAR_RXTRG);
 124
 125         /*
 126          * Setup Multipurpose Input/Output pins.
 127          */
 128         if (idx == 0) {
 129                 switch (pcidev->device) {
 130                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
 131                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
 132                         writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
 133                         writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
 134                         writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
 135                         break;
 136                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
 137                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
 138                         writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
 139                         writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
 140                         writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
 141                         break;
 142                 }
 143                 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 144                 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
 145                 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
 146         }
 147
 148         return 0;
 149 }
 150
 151 static int
 152 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 153                        struct uart_8250_port *port, int idx)
 154 {
 155         unsigned int offset = idx * 0x200;
 156         unsigned int baud = 1843200;
 157
 158         port->port.uartclk = baud * 16;
 159         return default_setup(priv, pcidev, idx, offset, port);
 160 }
 161
 162 static int
 163 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 164                    struct uart_8250_port *port, int idx)
 165 {
 166         unsigned int offset = idx * 0x200;
 167         unsigned int baud = 921600;
 168
 169         port->port.uartclk = baud * 16;
 170         return default_setup(priv, pcidev, idx, offset, port);
 171 }
 172
 173 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
 174 {
 175         /*
 176          * The Commtech adapters required the MPIOs to be driven low. The Exar
 177          * devices will export them as GPIOs, so we pre-configure them safely
 178          * as inputs.
 179          */
 180         u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
 181
 182         writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 183         writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
 184         writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
 185         writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
 186         writeb(dir,  p + UART_EXAR_MPIOSEL_7_0);
 187         writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
 188         writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
 189         writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
 190         writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
 191         writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
 192         writeb(dir,  p + UART_EXAR_MPIOSEL_15_8);
 193         writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
 194 }
 195
 196 static void *
 197 xr17v35x_register_gpio(struct pci_dev *pcidev)
 198 {
 199         struct platform_device *pdev;
 200
 201         pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
 202         if (!pdev)
 203                 return NULL;
 204
 205         platform_set_drvdata(pdev, pcidev);
 206         if (platform_device_add(pdev) < 0) {
 207                 platform_device_put(pdev);
 208                 return NULL;
 209         }
 210
 211         return pdev;
 212 }
 213
 214 static int
 215 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 216                    struct uart_8250_port *port, int idx)
 217 {
 218         const struct exar8250_board *board = priv->board;
 219         unsigned int offset = idx * 0x400;
 220         unsigned int baud = 7812500;
 221         u8 __iomem *p;
 222         int ret;
 223
 224         port->port.uartclk = baud * 16;
 225         /*
 226          * Setup the uart clock for the devices on expansion slot to
 227          * half the clock speed of the main chip (which is 125MHz)
 228          */
 229         if (board->has_slave && idx >= 8)
 230                 port->port.uartclk /= 2;
 231
 232         ret = default_setup(priv, pcidev, idx, offset, port);
 233         if (ret)
 234                 return ret;
 235
 236         p = port->port.membase;
 237
 238         writeb(0x00, p + UART_EXAR_8XMODE);
 239         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
 240         writeb(128, p + UART_EXAR_TXTRG);
 241         writeb(128, p + UART_EXAR_RXTRG);
 242
 243         if (idx == 0) {
 244                 /* Setup Multipurpose Input/Output pins. */
 245                 setup_gpio(pcidev, p);
 246
 247                 port->port.private_data = xr17v35x_register_gpio(pcidev);
 248         }
 249
 250         return 0;
 251 }
 252
 253 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
 254 {
 255         struct exar8250 *priv = pci_get_drvdata(pcidev);
 256         struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
 257         struct platform_device *pdev = port->port.private_data;
 258
 259         platform_device_unregister(pdev);
 260         port->port.private_data = NULL;
 261 }
 262
 263 static int
 264 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
 265 {
 266         unsigned int nr_ports, i, bar = 0, maxnr;
 267         struct exar8250_board *board;
 268         struct uart_8250_port uart;
 269         struct exar8250 *priv;
 270         int rc;
 271
 272         board = (struct exar8250_board *)ent->driver_data;
 273         if (!board)
 274                 return -EINVAL;
 275
 276         rc = pcim_enable_device(pcidev);
 277         if (rc)
 278                 return rc;
 279
 280         maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
 281
 282         nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
 283
 284         priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
 285                             sizeof(unsigned int) * nr_ports,
 286                             GFP_KERNEL);
 287         if (!priv)
 288                 return -ENOMEM;
 289
 290         priv->board = board;
 291
 292         pci_set_master(pcidev);
 293
 294         rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
 295         if (rc < 0)
 296                 return rc;
 297
 298         memset(&uart, 0, sizeof(uart));
 299         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
 300                           | UPF_EXAR_EFR;
 301         uart.port.irq = pci_irq_vector(pcidev, 0);
 302         uart.port.dev = &pcidev->dev;
 303
 304         for (i = 0; i < nr_ports && i < maxnr; i++) {
 305                 rc = board->setup(priv, pcidev, &uart, i);
 306                 if (rc) {
 307                         dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
 308                         break;
 309                 }
 310
 311                 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
 312                         uart.port.iobase, uart.port.irq, uart.port.iotype);
 313
 314                 priv->line[i] = serial8250_register_8250_port(&uart);
 315                 if (priv->line[i] < 0) {
 316                         dev_err(&pcidev->dev,
 317                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
 318                                 uart.port.iobase, uart.port.irq,
 319                                 uart.port.iotype, priv->line[i]);
 320                         break;
 321                 }
 322         }
 323         priv->nr = i;
 324         pci_set_drvdata(pcidev, priv);
 325         return 0;
 326 }
 327
 328 static void exar_pci_remove(struct pci_dev *pcidev)
 329 {
 330         struct exar8250 *priv = pci_get_drvdata(pcidev);
 331         unsigned int i;
 332
 333         for (i = 0; i < priv->nr; i++)
 334                 serial8250_unregister_port(priv->line[i]);
 335
 336         if (priv->board->exit)
 337                 priv->board->exit(pcidev);
 338 }
 339
 340 static int __maybe_unused exar_suspend(struct device *dev)
 341 {
 342         struct pci_dev *pcidev = to_pci_dev(dev);
 343         struct exar8250 *priv = pci_get_drvdata(pcidev);
 344         unsigned int i;
 345
 346         for (i = 0; i < priv->nr; i++)
 347                 if (priv->line[i] >= 0)
 348                         serial8250_suspend_port(priv->line[i]);
 349
 350         /* Ensure that every init quirk is properly torn down */
 351         if (priv->board->exit)
 352                 priv->board->exit(pcidev);
 353
 354         return 0;
 355 }
 356
 357 static int __maybe_unused exar_resume(struct device *dev)
 358 {
 359         struct pci_dev *pcidev = to_pci_dev(dev);
 360         struct exar8250 *priv = pci_get_drvdata(pcidev);
 361         unsigned int i;
 362
 363         for (i = 0; i < priv->nr; i++)
 364                 if (priv->line[i] >= 0)
 365                         serial8250_resume_port(priv->line[i]);
 366
 367         return 0;
 368 }
 369
 370 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
 371
 372 static const struct exar8250_board pbn_fastcom335_2 = {
 373         .num_ports      = 2,
 374         .setup          = pci_fastcom335_setup,
 375 };
 376
 377 static const struct exar8250_board pbn_fastcom335_4 = {
 378         .num_ports      = 4,
 379         .setup          = pci_fastcom335_setup,
 380 };
 381
 382 static const struct exar8250_board pbn_fastcom335_8 = {
 383         .num_ports      = 8,
 384         .setup          = pci_fastcom335_setup,
 385 };
 386
 387 static const struct exar8250_board pbn_connect = {
 388         .setup          = pci_connect_tech_setup,
 389 };
 390
 391 static const struct exar8250_board pbn_exar_ibm_saturn = {
 392         .num_ports      = 1,
 393         .setup          = pci_xr17c154_setup,
 394 };
 395
 396 static const struct exar8250_board pbn_exar_XR17C15x = {
 397         .setup          = pci_xr17c154_setup,
 398 };
 399
 400 static const struct exar8250_board pbn_exar_XR17V35x = {
 401         .setup          = pci_xr17v35x_setup,
 402         .exit           = pci_xr17v35x_exit,
 403 };
 404
 405 static const struct exar8250_board pbn_exar_XR17V4358 = {
 406         .num_ports      = 12,
 407         .has_slave      = true,
 408         .setup          = pci_xr17v35x_setup,
 409         .exit           = pci_xr17v35x_exit,
 410 };
 411
 412 static const struct exar8250_board pbn_exar_XR17V8358 = {
 413         .num_ports      = 16,
 414         .has_slave      = true,
 415         .setup          = pci_xr17v35x_setup,
 416         .exit           = pci_xr17v35x_exit,
 417 };
 418
 419 #define CONNECT_DEVICE(devid, sdevid, bd) {                             \
 420         PCI_DEVICE_SUB(                                                 \
 421                 PCI_VENDOR_ID_EXAR,                                     \
 422                 PCI_DEVICE_ID_EXAR_##devid,                             \
 423                 PCI_SUBVENDOR_ID_CONNECT_TECH,                          \
 424                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0,      \
 425                 (kernel_ulong_t)&bd                                     \
 426         }
 427
 428 #define EXAR_DEVICE(vend, devid, bd) {                                  \
 429         PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd   \
 430         }
 431
 432 #define IBM_DEVICE(devid, sdevid, bd) {                 \
 433         PCI_DEVICE_SUB(                                 \
 434                 PCI_VENDOR_ID_EXAR,                     \
 435                 PCI_DEVICE_ID_EXAR_##devid,             \
 436                 PCI_VENDOR_ID_IBM,                      \
 437                 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0,   \
 438                 (kernel_ulong_t)&bd                     \
 439         }
 440
 441 static struct pci_device_id exar_pci_tbl[] = {
 442         CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
 443         CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
 444         CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
 445         CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
 446         CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
 447         CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
 448         CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
 449         CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
 450         CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
 451         CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
 452         CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
 453         CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
 454
 455         IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
 456
 457         /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
 458         EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
 459         EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
 460         EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
 461
 462         /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
 463         EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
 464         EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
 465         EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
 466         EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
 467         EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
 468         EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
 469         EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
 470         EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
 471
 472         EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
 473         EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
 474         EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
 475         EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
 476         { 0, }
 477 };
 478 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
 479
 480 static struct pci_driver exar_pci_driver = {
 481         .name           = "exar_serial",
 482         .probe          = exar_pci_probe,
 483         .remove         = exar_pci_remove,
 484         .driver         = {
 485                 .pm     = &exar_pci_pm,
 486         },
 487         .id_table       = exar_pci_tbl,
 488 };
 489 module_pci_driver(exar_pci_driver);
 490
 491 MODULE_LICENSE("GPL");
 492 MODULE_DESCRIPTION("Exar Serial Driver");
 493 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");