1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Realtek PCI-Express card reader
5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
8 * Wei WANG (wei_wang@realsil.com.cn)
9 * Micky Ching (micky_ching@realsil.com.cn)
12 #include <linux/blkdev.h>
13 #include <linux/kthread.h>
14 #include <linux/sched.h>
19 #define SD_MAX_RETRY_COUNT 3
21 static u16 REG_SD_CFG1;
22 static u16 REG_SD_CFG2;
23 static u16 REG_SD_CFG3;
24 static u16 REG_SD_STAT1;
25 static u16 REG_SD_STAT2;
26 static u16 REG_SD_BUS_STAT;
27 static u16 REG_SD_PAD_CTL;
28 static u16 REG_SD_SAMPLE_POINT_CTL;
29 static u16 REG_SD_PUSH_POINT_CTL;
30 static u16 REG_SD_CMD0;
31 static u16 REG_SD_CMD1;
32 static u16 REG_SD_CMD2;
33 static u16 REG_SD_CMD3;
34 static u16 REG_SD_CMD4;
35 static u16 REG_SD_CMD5;
36 static u16 REG_SD_BYTE_CNT_L;
37 static u16 REG_SD_BYTE_CNT_H;
38 static u16 REG_SD_BLOCK_CNT_L;
39 static u16 REG_SD_BLOCK_CNT_H;
40 static u16 REG_SD_TRANSFER;
41 static u16 REG_SD_VPCLK0_CTL;
42 static u16 REG_SD_VPCLK1_CTL;
43 static u16 REG_SD_DCMPS0_CTL;
44 static u16 REG_SD_DCMPS1_CTL;
46 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
48 struct sd_info *sd_card = &chip->sd_card;
50 sd_card->err_code |= err_code;
53 static inline void sd_clr_err_code(struct rtsx_chip *chip)
55 struct sd_info *sd_card = &chip->sd_card;
57 sd_card->err_code = 0;
60 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
62 struct sd_info *sd_card = &chip->sd_card;
64 return sd_card->err_code & err_code;
67 static void sd_init_reg_addr(struct rtsx_chip *chip)
72 REG_SD_STAT1 = 0xFD30;
76 REG_SD_SAMPLE_POINT_CTL = 0;
77 REG_SD_PUSH_POINT_CTL = 0;
84 REG_SD_BYTE_CNT_L = 0xFD39;
85 REG_SD_BYTE_CNT_H = 0xFD3A;
86 REG_SD_BLOCK_CNT_L = 0xFD3B;
87 REG_SD_BLOCK_CNT_H = 0xFD3C;
88 REG_SD_TRANSFER = 0xFD32;
89 REG_SD_VPCLK0_CTL = 0;
90 REG_SD_VPCLK1_CTL = 0;
91 REG_SD_DCMPS0_CTL = 0;
92 REG_SD_DCMPS1_CTL = 0;
95 static int sd_check_data0_status(struct rtsx_chip *chip)
100 retval = rtsx_read_register(chip, REG_SD_STAT1, &stat);
104 if (!(stat & SD_DAT0_STATUS)) {
105 sd_set_err_code(chip, SD_BUSY);
109 return STATUS_SUCCESS;
112 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
113 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
115 struct sd_info *sd_card = &chip->sd_card;
123 sd_clr_err_code(chip);
125 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
127 if (rsp_type == SD_RSP_TYPE_R1b)
134 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
135 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
136 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
137 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
138 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
140 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
141 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
142 0x01, PINGPONG_BUFFER);
143 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
144 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
145 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
146 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END |
149 if (rsp_type == SD_RSP_TYPE_R2) {
150 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
152 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
155 } else if (rsp_type != SD_RSP_TYPE_R0) {
156 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
158 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
163 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
165 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
169 rtsx_read_register(chip, REG_SD_STAT1, &val);
170 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
172 rtsx_read_register(chip, REG_SD_CFG3, &val);
173 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
175 if (retval == -ETIMEDOUT) {
176 if (rsp_type & SD_WAIT_BUSY_END) {
177 retval = sd_check_data0_status(chip);
178 if (retval != STATUS_SUCCESS) {
179 rtsx_clear_sd_error(chip);
183 sd_set_err_code(chip, SD_TO_ERR);
185 retval = STATUS_TIMEDOUT;
187 retval = STATUS_FAIL;
189 rtsx_clear_sd_error(chip);
194 if (rsp_type == SD_RSP_TYPE_R0)
195 return STATUS_SUCCESS;
197 ptr = rtsx_get_cmd_data(chip) + 1;
199 if ((ptr[0] & 0xC0) != 0) {
200 sd_set_err_code(chip, SD_STS_ERR);
204 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
205 if (ptr[stat_idx] & SD_CRC7_ERR) {
206 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
207 sd_set_err_code(chip, SD_CRC_ERR);
210 if (rty_cnt < SD_MAX_RETRY_COUNT) {
215 sd_set_err_code(chip, SD_CRC_ERR);
221 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
222 if ((cmd_idx != SEND_RELATIVE_ADDR) &&
223 (cmd_idx != SEND_IF_COND)) {
224 if (cmd_idx != STOP_TRANSMISSION) {
228 #ifdef SUPPORT_SD_LOCK
233 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
238 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
243 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
248 sd_card->sd_data_buf_ready = 1;
250 sd_card->sd_data_buf_ready = 0;
255 memcpy(rsp, ptr, rsp_len);
257 return STATUS_SUCCESS;
260 static int sd_read_data(struct rtsx_chip *chip,
261 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
262 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
265 struct sd_info *sd_card = &chip->sd_card;
269 sd_clr_err_code(chip);
280 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
281 for (i = 0; i < (min(cmd_len, 6)); i++)
282 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
285 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
287 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
288 (u8)(byte_cnt >> 8));
289 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
291 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
294 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
296 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
297 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
298 SD_CHECK_CRC7 | SD_RSP_LEN_6);
299 if (trans_mode != SD_TM_AUTO_TUNING)
300 rtsx_add_cmd(chip, WRITE_REG_CMD,
301 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
303 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
304 trans_mode | SD_TRANSFER_START);
305 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
308 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
310 if (retval == -ETIMEDOUT) {
311 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
312 SD_RSP_TYPE_R1, NULL, 0);
318 if (buf && buf_len) {
319 retval = rtsx_read_ppbuf(chip, buf, buf_len);
320 if (retval != STATUS_SUCCESS)
324 return STATUS_SUCCESS;
327 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
328 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
329 u8 bus_width, u8 *buf, int buf_len, int timeout)
331 struct sd_info *sd_card = &chip->sd_card;
335 sd_clr_err_code(chip);
341 /* This function can't write data more than one page */
345 if (buf && buf_len) {
346 retval = rtsx_write_ppbuf(chip, buf, buf_len);
347 if (retval != STATUS_SUCCESS)
354 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
355 for (i = 0; i < (min(cmd_len, 6)); i++) {
356 rtsx_add_cmd(chip, WRITE_REG_CMD,
357 REG_SD_CMD0 + i, 0xFF, cmd[i]);
360 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
362 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
363 (u8)(byte_cnt >> 8));
364 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
366 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
369 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
371 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
372 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
373 SD_CHECK_CRC7 | SD_RSP_LEN_6);
375 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
376 trans_mode | SD_TRANSFER_START);
377 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
380 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
382 if (retval == -ETIMEDOUT) {
383 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
384 SD_RSP_TYPE_R1, NULL, 0);
390 return STATUS_SUCCESS;
393 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
395 struct sd_info *sd_card = &chip->sd_card;
398 u8 csd_ver, trans_speed;
401 for (i = 0; i < 6; i++) {
402 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
403 sd_set_err_code(chip, SD_NO_CARD);
407 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
408 SD_RSP_TYPE_R2, rsp, 16);
409 if (retval == STATUS_SUCCESS)
416 memcpy(sd_card->raw_csd, rsp + 1, 15);
418 dev_dbg(rtsx_dev(chip), "CSD Response:\n");
419 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd);
421 csd_ver = (rsp[1] & 0xc0) >> 6;
422 dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
424 trans_speed = rsp[4];
425 if ((trans_speed & 0x07) == 0x02) {
426 if ((trans_speed & 0xf8) >= 0x30) {
428 sd_card->sd_clock = 47;
430 sd_card->sd_clock = CLK_50;
432 } else if ((trans_speed & 0xf8) == 0x28) {
434 sd_card->sd_clock = 39;
436 sd_card->sd_clock = CLK_40;
438 } else if ((trans_speed & 0xf8) == 0x20) {
440 sd_card->sd_clock = 29;
442 sd_card->sd_clock = CLK_30;
444 } else if ((trans_speed & 0xf8) >= 0x10) {
446 sd_card->sd_clock = 23;
448 sd_card->sd_clock = CLK_20;
450 } else if ((trans_speed & 0x08) >= 0x08) {
452 sd_card->sd_clock = 19;
454 sd_card->sd_clock = CLK_20;
462 if (CHK_MMC_SECTOR_MODE(sd_card)) {
463 sd_card->capacity = 0;
465 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
466 u8 blk_size, c_size_mult;
469 blk_size = rsp[6] & 0x0F;
470 c_size = ((u16)(rsp[7] & 0x03) << 10)
472 + ((u16)(rsp[9] & 0xC0) >> 6);
473 c_size_mult = (u8)((rsp[10] & 0x03) << 1);
474 c_size_mult += (rsp[11] & 0x80) >> 7;
475 sd_card->capacity = (((u32)(c_size + 1)) *
476 (1 << (c_size_mult + 2)))
479 u32 total_sector = 0;
481 total_sector = (((u32)rsp[8] & 0x3f) << 16) |
482 ((u32)rsp[9] << 8) | (u32)rsp[10];
483 sd_card->capacity = (total_sector + 1) << 10;
489 chip->card_wp |= SD_CARD;
491 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
494 return STATUS_SUCCESS;
497 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
500 struct sd_info *sd_card = &chip->sd_card;
503 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
506 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
507 if (chip->asic_code) {
508 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
520 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
521 SD_SAMPLE_POINT_DELAY) {
528 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val);
532 return STATUS_SUCCESS;
535 static void sd_choose_proper_clock(struct rtsx_chip *chip)
537 struct sd_info *sd_card = &chip->sd_card;
539 if (CHK_SD_SDR104(sd_card)) {
541 sd_card->sd_clock = chip->asic_sd_sdr104_clk;
543 sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
545 } else if (CHK_SD_DDR50(sd_card)) {
547 sd_card->sd_clock = chip->asic_sd_ddr50_clk;
549 sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
551 } else if (CHK_SD_SDR50(sd_card)) {
553 sd_card->sd_clock = chip->asic_sd_sdr50_clk;
555 sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
557 } else if (CHK_SD_HS(sd_card)) {
559 sd_card->sd_clock = chip->asic_sd_hs_clk;
561 sd_card->sd_clock = chip->fpga_sd_hs_clk;
563 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
565 sd_card->sd_clock = chip->asic_mmc_52m_clk;
567 sd_card->sd_clock = chip->fpga_mmc_52m_clk;
569 } else if (CHK_MMC_26M(sd_card)) {
571 sd_card->sd_clock = 48;
573 sd_card->sd_clock = CLK_50;
577 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
580 u8 mask = 0, val = 0;
583 if (clk_div == SD_CLK_DIVIDE_0)
585 else if (clk_div == SD_CLK_DIVIDE_128)
587 else if (clk_div == SD_CLK_DIVIDE_256)
590 retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val);
594 return STATUS_SUCCESS;
597 static int sd_set_init_para(struct rtsx_chip *chip)
599 struct sd_info *sd_card = &chip->sd_card;
602 retval = sd_set_sample_push_timing(chip);
603 if (retval != STATUS_SUCCESS)
606 sd_choose_proper_clock(chip);
608 retval = switch_clock(chip, sd_card->sd_clock);
609 if (retval != STATUS_SUCCESS)
612 return STATUS_SUCCESS;
615 int sd_select_card(struct rtsx_chip *chip, int select)
617 struct sd_info *sd_card = &chip->sd_card;
619 u8 cmd_idx, cmd_type;
623 cmd_idx = SELECT_CARD;
624 cmd_type = SD_RSP_TYPE_R1;
625 addr = sd_card->sd_addr;
627 cmd_idx = DESELECT_CARD;
628 cmd_type = SD_RSP_TYPE_R0;
632 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
633 if (retval != STATUS_SUCCESS)
636 return STATUS_SUCCESS;
639 #ifdef SUPPORT_SD_LOCK
640 static int sd_update_lock_status(struct rtsx_chip *chip)
642 struct sd_info *sd_card = &chip->sd_card;
646 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
647 SD_RSP_TYPE_R1, rsp, 5);
648 if (retval != STATUS_SUCCESS)
652 sd_card->sd_lock_status |= SD_LOCKED;
654 sd_card->sd_lock_status &= ~SD_LOCKED;
656 dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
657 sd_card->sd_lock_status);
662 return STATUS_SUCCESS;
666 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
667 u8 data_ready, int polling_cnt)
669 struct sd_info *sd_card = &chip->sd_card;
673 for (i = 0; i < polling_cnt; i++) {
674 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
675 sd_card->sd_addr, SD_RSP_TYPE_R1,
677 if (retval != STATUS_SUCCESS)
680 if (((rsp[3] & 0x1E) == state) &&
681 ((rsp[3] & 0x01) == data_ready))
682 return STATUS_SUCCESS;
688 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
692 if (voltage == SD_IO_3V3) {
693 if (chip->asic_code) {
694 retval = rtsx_write_phy_register(chip, 0x08,
697 if (retval != STATUS_SUCCESS)
700 retval = rtsx_write_register(chip, SD_PAD_CTL,
705 } else if (voltage == SD_IO_1V8) {
706 if (chip->asic_code) {
707 retval = rtsx_write_phy_register(chip, 0x08,
710 if (retval != STATUS_SUCCESS)
713 retval = rtsx_write_register(chip, SD_PAD_CTL,
723 return STATUS_SUCCESS;
726 static int sd_voltage_switch(struct rtsx_chip *chip)
731 retval = rtsx_write_register(chip, SD_BUS_STAT,
732 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
737 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
739 if (retval != STATUS_SUCCESS)
742 udelay(chip->sd_voltage_switch_delay);
744 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
747 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
748 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
752 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
756 retval = sd_change_bank_voltage(chip, SD_IO_1V8);
757 if (retval != STATUS_SUCCESS)
762 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
768 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
771 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
772 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
773 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
774 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
775 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
776 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN |
777 SD_CLK_FORCE_STOP, 0);
778 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
782 retval = rtsx_write_register(chip, SD_BUS_STAT,
783 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
787 return STATUS_SUCCESS;
790 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
794 if (tune_dir == TUNE_RX) {
795 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
799 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
803 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
807 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
812 return STATUS_SUCCESS;
815 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
817 struct sd_info *sd_card = &chip->sd_card;
818 u16 SD_VP_CTL, SD_DCMPS_CTL;
823 dev_dbg(rtsx_dev(chip), "%s (sample_point = %d, tune_dir = %d)\n",
824 __func__, sample_point, tune_dir);
826 if (tune_dir == TUNE_RX) {
827 SD_VP_CTL = SD_VPRX_CTL;
828 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
829 if (CHK_SD_DDR50(sd_card))
832 SD_VP_CTL = SD_VPTX_CTL;
833 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
836 if (chip->asic_code) {
837 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK,
841 retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F,
845 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
849 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
850 PHASE_NOT_RESET, PHASE_NOT_RESET);
853 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0);
857 rtsx_read_register(chip, SD_VP_CTL, &val);
858 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
859 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
860 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
863 retval = rtsx_write_register(chip, SD_VP_CTL,
869 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
876 retval = rtsx_write_register(chip, CLK_CTL,
877 CHANGE_CLK, CHANGE_CLK);
881 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
890 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
892 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
893 DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
894 retval = rtsx_send_cmd(chip, SD_CARD, 100);
895 if (retval != STATUS_SUCCESS)
898 val = *rtsx_get_cmd_data(chip);
899 if (val & DCMPS_ERROR)
902 if ((val & DCMPS_CURRENT_PHASE) != sample_point)
905 retval = rtsx_write_register(chip, SD_DCMPS_CTL,
910 retval = rtsx_write_register(chip, SD_VP_CTL,
915 retval = rtsx_write_register(chip, CLK_CTL,
924 retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
928 return STATUS_SUCCESS;
931 rtsx_read_register(chip, SD_VP_CTL, &val);
932 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
933 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
934 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
936 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
937 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
939 sd_reset_dcm(chip, tune_dir);
943 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
945 struct sd_info *sd_card = &chip->sd_card;
949 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
950 SD_RSP_TYPE_R1, NULL, 0);
951 if (retval != STATUS_SUCCESS)
954 cmd[0] = 0x40 | SEND_SCR;
960 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
962 if (retval != STATUS_SUCCESS) {
963 rtsx_clear_sd_error(chip);
967 memcpy(sd_card->raw_scr, buf, 8);
969 if ((buf[0] & 0x0F) == 0)
972 return STATUS_SUCCESS;
975 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
976 u8 func_to_switch, u8 *buf, int buf_len)
978 u8 support_mask = 0, query_switch = 0, switch_busy = 0;
979 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
981 if (func_group == SD_FUNC_GROUP_1) {
982 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
983 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
984 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
986 switch (func_to_switch) {
988 support_mask = HS_SUPPORT_MASK;
989 query_switch = HS_QUERY_SWITCH_OK;
990 switch_busy = HS_SWITCH_BUSY;
994 support_mask = SDR50_SUPPORT_MASK;
995 query_switch = SDR50_QUERY_SWITCH_OK;
996 switch_busy = SDR50_SWITCH_BUSY;
1000 support_mask = SDR104_SUPPORT_MASK;
1001 query_switch = SDR104_QUERY_SWITCH_OK;
1002 switch_busy = SDR104_SWITCH_BUSY;
1006 support_mask = DDR50_SUPPORT_MASK;
1007 query_switch = DDR50_QUERY_SWITCH_OK;
1008 switch_busy = DDR50_SWITCH_BUSY;
1014 } else if (func_group == SD_FUNC_GROUP_3) {
1015 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1016 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1017 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1019 switch (func_to_switch) {
1020 case DRIVING_TYPE_A:
1021 support_mask = DRIVING_TYPE_A_MASK;
1022 query_switch = TYPE_A_QUERY_SWITCH_OK;
1023 switch_busy = TYPE_A_SWITCH_BUSY;
1026 case DRIVING_TYPE_C:
1027 support_mask = DRIVING_TYPE_C_MASK;
1028 query_switch = TYPE_C_QUERY_SWITCH_OK;
1029 switch_busy = TYPE_C_SWITCH_BUSY;
1032 case DRIVING_TYPE_D:
1033 support_mask = DRIVING_TYPE_D_MASK;
1034 query_switch = TYPE_D_QUERY_SWITCH_OK;
1035 switch_busy = TYPE_D_SWITCH_BUSY;
1041 } else if (func_group == SD_FUNC_GROUP_4) {
1042 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1043 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1044 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1046 switch (func_to_switch) {
1047 case CURRENT_LIMIT_400:
1048 support_mask = CURRENT_LIMIT_400_MASK;
1049 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1050 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1053 case CURRENT_LIMIT_600:
1054 support_mask = CURRENT_LIMIT_600_MASK;
1055 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1056 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1059 case CURRENT_LIMIT_800:
1060 support_mask = CURRENT_LIMIT_800_MASK;
1061 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1062 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1072 if (func_group == SD_FUNC_GROUP_1) {
1073 if (!(buf[support_offset] & support_mask) ||
1074 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1079 /* Check 'Busy Status' */
1080 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1081 ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1085 return STATUS_SUCCESS;
1088 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, u8 func_group,
1089 u8 func_to_switch, u8 bus_width)
1091 struct sd_info *sd_card = &chip->sd_card;
1095 dev_dbg(rtsx_dev(chip), "%s (mode = %d, func_group = %d, func_to_switch = %d)\n",
1096 __func__, mode, func_group, func_to_switch);
1098 cmd[0] = 0x40 | SWITCH;
1101 if (func_group == SD_FUNC_GROUP_1) {
1104 cmd[4] = 0xF0 + func_to_switch;
1105 } else if (func_group == SD_FUNC_GROUP_3) {
1107 cmd[3] = 0xF0 + func_to_switch;
1109 } else if (func_group == SD_FUNC_GROUP_4) {
1111 cmd[3] = 0x0F + (func_to_switch << 4);
1114 cmd[1] = SD_CHECK_MODE;
1120 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1122 if (retval != STATUS_SUCCESS) {
1123 rtsx_clear_sd_error(chip);
1127 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
1129 if (func_group == NO_ARGUMENT) {
1130 sd_card->func_group1_mask = buf[0x0D];
1131 sd_card->func_group2_mask = buf[0x0B];
1132 sd_card->func_group3_mask = buf[0x09];
1133 sd_card->func_group4_mask = buf[0x07];
1135 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1137 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1139 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1141 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1144 /* Maximum current consumption, check whether current is
1145 * acceptable; bit[511:496] = 0x0000 means some error happened.
1147 u16 cc = ((u16)buf[0] << 8) | buf[1];
1149 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1151 if ((cc == 0) || (cc > 800))
1154 retval = sd_query_switch_result(chip, func_group,
1155 func_to_switch, buf, 64);
1156 if (retval != STATUS_SUCCESS)
1159 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1160 retval = rtsx_write_register(chip, OCPPARA2,
1162 chip->sd_800mA_ocp_thd);
1165 retval = rtsx_write_register(chip, CARD_PWR_CTL,
1173 return STATUS_SUCCESS;
1176 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1178 if (func_group == SD_FUNC_GROUP_1) {
1179 if (func_to_switch > HS_SUPPORT)
1182 } else if (func_group == SD_FUNC_GROUP_4) {
1183 if (func_to_switch > CURRENT_LIMIT_200)
1187 return func_to_switch;
1190 static int sd_check_switch(struct rtsx_chip *chip,
1191 u8 func_group, u8 func_to_switch, u8 bus_width)
1195 bool switch_good = false;
1197 for (i = 0; i < 3; i++) {
1198 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1199 sd_set_err_code(chip, SD_NO_CARD);
1203 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1204 func_to_switch, bus_width);
1205 if (retval == STATUS_SUCCESS) {
1208 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1212 if (retval == STATUS_SUCCESS) {
1217 retval = rtsx_read_register(chip, SD_STAT1, &stat);
1220 if (stat & SD_CRC16_ERR) {
1221 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1226 func_to_switch = downgrade_switch_mode(func_group,
1235 return STATUS_SUCCESS;
1238 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1240 struct sd_info *sd_card = &chip->sd_card;
1243 u8 func_to_switch = 0;
1245 /* Get supported functions */
1246 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, NO_ARGUMENT,
1247 NO_ARGUMENT, bus_width);
1248 if (retval != STATUS_SUCCESS)
1251 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1253 /* Function Group 1: Access Mode */
1254 for (i = 0; i < 4; i++) {
1255 switch ((u8)(chip->sd_speed_prior >> (i * 8))) {
1256 case SDR104_SUPPORT:
1257 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) &&
1259 func_to_switch = SDR104_SUPPORT;
1264 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) &&
1266 func_to_switch = DDR50_SUPPORT;
1271 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) &&
1273 func_to_switch = SDR50_SUPPORT;
1278 if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1279 func_to_switch = HS_SUPPORT;
1290 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1293 #ifdef SUPPORT_SD_LOCK
1294 if ((sd_card->sd_lock_status & SD_SDR_RST) &&
1295 (func_to_switch == DDR50_SUPPORT) &&
1296 (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1297 func_to_switch = SDR50_SUPPORT;
1298 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1302 if (func_to_switch) {
1303 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1305 if (retval != STATUS_SUCCESS) {
1306 if (func_to_switch == SDR104_SUPPORT) {
1307 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1308 } else if (func_to_switch == DDR50_SUPPORT) {
1309 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1311 } else if (func_to_switch == SDR50_SUPPORT) {
1312 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1313 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1318 if (func_to_switch == SDR104_SUPPORT)
1319 SET_SD_SDR104(sd_card);
1320 else if (func_to_switch == DDR50_SUPPORT)
1321 SET_SD_DDR50(sd_card);
1322 else if (func_to_switch == SDR50_SUPPORT)
1323 SET_SD_SDR50(sd_card);
1328 if (CHK_SD_DDR50(sd_card)) {
1329 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06,
1333 retval = sd_set_sample_push_timing(chip);
1334 if (retval != STATUS_SUCCESS)
1338 if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1339 /* Do not try to switch current limit if the card doesn't
1340 * support UHS mode or we don't want it to support UHS mode
1342 return STATUS_SUCCESS;
1345 /* Function Group 4: Current Limit */
1346 func_to_switch = 0xFF;
1348 for (i = 0; i < 4; i++) {
1349 switch ((u8)(chip->sd_current_prior >> (i * 8))) {
1350 case CURRENT_LIMIT_800:
1351 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1352 func_to_switch = CURRENT_LIMIT_800;
1356 case CURRENT_LIMIT_600:
1357 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1358 func_to_switch = CURRENT_LIMIT_600;
1362 case CURRENT_LIMIT_400:
1363 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1364 func_to_switch = CURRENT_LIMIT_400;
1368 case CURRENT_LIMIT_200:
1369 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1370 func_to_switch = CURRENT_LIMIT_200;
1378 if (func_to_switch != 0xFF)
1382 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1385 if (func_to_switch <= CURRENT_LIMIT_800) {
1386 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1388 if (retval != STATUS_SUCCESS) {
1389 if (sd_check_err_code(chip, SD_NO_CARD))
1392 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1396 if (CHK_SD_DDR50(sd_card)) {
1397 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1402 return STATUS_SUCCESS;
1405 static int sd_wait_data_idle(struct rtsx_chip *chip)
1407 int retval = STATUS_TIMEDOUT;
1411 for (i = 0; i < 100; i++) {
1412 retval = rtsx_read_register(chip, SD_DATA_STATE, &val);
1415 if (val & SD_DATA_IDLE) {
1416 retval = STATUS_SUCCESS;
1421 dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1426 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1431 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1432 if (retval != STATUS_SUCCESS)
1435 cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1441 retval = sd_read_data(chip, SD_TM_AUTO_TUNING, cmd, 5, 0x40, 1,
1442 SD_BUS_WIDTH_4, NULL, 0, 100);
1443 if (retval != STATUS_SUCCESS) {
1444 (void)sd_wait_data_idle(chip);
1446 rtsx_clear_sd_error(chip);
1450 return STATUS_SUCCESS;
1453 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1455 struct sd_info *sd_card = &chip->sd_card;
1459 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1460 if (retval != STATUS_SUCCESS)
1463 dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1465 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1466 SD_RSP_TYPE_R1, NULL, 0);
1467 if (retval != STATUS_SUCCESS)
1470 cmd[0] = 0x40 | SD_STATUS;
1476 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
1477 SD_BUS_WIDTH_4, NULL, 0, 100);
1478 if (retval != STATUS_SUCCESS) {
1479 (void)sd_wait_data_idle(chip);
1481 rtsx_clear_sd_error(chip);
1485 return STATUS_SUCCESS;
1488 static int mmc_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1490 struct sd_info *sd_card = &chip->sd_card;
1492 u8 cmd[5], bus_width;
1494 if (CHK_MMC_8BIT(sd_card))
1495 bus_width = SD_BUS_WIDTH_8;
1496 else if (CHK_MMC_4BIT(sd_card))
1497 bus_width = SD_BUS_WIDTH_4;
1499 bus_width = SD_BUS_WIDTH_1;
1501 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1502 if (retval != STATUS_SUCCESS)
1505 dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1507 cmd[0] = 0x40 | SEND_EXT_CSD;
1513 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 0x200, 1,
1514 bus_width, NULL, 0, 100);
1515 if (retval != STATUS_SUCCESS) {
1516 (void)sd_wait_data_idle(chip);
1518 rtsx_clear_sd_error(chip);
1522 return STATUS_SUCCESS;
1525 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1527 struct sd_info *sd_card = &chip->sd_card;
1530 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1531 if (retval != STATUS_SUCCESS)
1534 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1535 SD_RSP_80CLK_TIMEOUT_EN);
1539 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1540 SD_RSP_TYPE_R1, NULL, 0);
1541 if (retval != STATUS_SUCCESS) {
1542 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1543 rtsx_write_register(chip, SD_CFG3,
1544 SD_RSP_80CLK_TIMEOUT_EN, 0);
1549 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1554 return STATUS_SUCCESS;
1557 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1559 struct sd_info *sd_card = &chip->sd_card;
1561 u8 cmd[5], bus_width;
1563 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1564 if (retval != STATUS_SUCCESS)
1567 if (CHK_SD(sd_card)) {
1568 bus_width = SD_BUS_WIDTH_4;
1570 if (CHK_MMC_8BIT(sd_card))
1571 bus_width = SD_BUS_WIDTH_8;
1572 else if (CHK_MMC_4BIT(sd_card))
1573 bus_width = SD_BUS_WIDTH_4;
1575 bus_width = SD_BUS_WIDTH_1;
1578 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1579 if (retval != STATUS_SUCCESS)
1582 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1583 SD_RSP_80CLK_TIMEOUT_EN);
1587 cmd[0] = 0x40 | PROGRAM_CSD;
1593 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, cmd, 5, 16, 1,
1594 bus_width, sd_card->raw_csd, 16, 100);
1595 if (retval != STATUS_SUCCESS) {
1596 rtsx_clear_sd_error(chip);
1597 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1601 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1606 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1609 return STATUS_SUCCESS;
1612 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1615 struct sd_info *sd_card = &chip->sd_card;
1616 struct timing_phase_path path[MAX_PHASE + 1];
1617 int i, j, cont_path_cnt;
1619 int max_len, final_path_idx;
1620 u8 final_phase = 0xFF;
1622 if (phase_map == 0xFFFFFFFF) {
1623 if (tune_dir == TUNE_RX)
1624 final_phase = (u8)chip->sd_default_rx_phase;
1626 final_phase = (u8)chip->sd_default_tx_phase;
1634 for (i = 0; i < MAX_PHASE + 1; i++) {
1635 if (phase_map & (1 << i)) {
1638 j = cont_path_cnt++;
1646 if (cont_path_cnt) {
1647 int idx = cont_path_cnt - 1;
1649 path[idx].len = path[idx].end -
1650 path[idx].start + 1;
1651 path[idx].mid = path[idx].start +
1657 if (cont_path_cnt == 0) {
1658 dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1661 int idx = cont_path_cnt - 1;
1663 path[idx].len = path[idx].end - path[idx].start + 1;
1664 path[idx].mid = path[idx].start + path[idx].len / 2;
1667 if ((path[0].start == 0) &&
1668 (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1669 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1670 path[0].len += path[cont_path_cnt - 1].len;
1671 path[0].mid = path[0].start + path[0].len / 2;
1672 if (path[0].mid < 0)
1673 path[0].mid += MAX_PHASE + 1;
1681 for (i = 0; i < cont_path_cnt; i++) {
1682 if (path[i].len > max_len) {
1683 max_len = path[i].len;
1684 final_phase = (u8)path[i].mid;
1688 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1690 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1691 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1692 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1693 dev_dbg(rtsx_dev(chip), "\n");
1696 if (tune_dir == TUNE_TX) {
1697 if (CHK_SD_SDR104(sd_card)) {
1699 int temp_mid = (max_len - 16) / 2;
1700 int temp_final_phase =
1701 path[final_path_idx].end -
1702 (max_len - (6 + temp_mid));
1704 if (temp_final_phase < 0)
1705 final_phase = (u8)(temp_final_phase +
1708 final_phase = (u8)temp_final_phase;
1710 } else if (CHK_SD_SDR50(sd_card)) {
1712 int temp_mid = (max_len - 13) / 2;
1713 int temp_final_phase =
1714 path[final_path_idx].end -
1715 (max_len - (3 + temp_mid));
1717 if (temp_final_phase < 0)
1718 final_phase = (u8)(temp_final_phase +
1721 final_phase = (u8)temp_final_phase;
1727 dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1731 static int sd_tuning_rx(struct rtsx_chip *chip)
1733 struct sd_info *sd_card = &chip->sd_card;
1736 u32 raw_phase_map[3], phase_map;
1738 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1740 if (CHK_SD(sd_card)) {
1741 if (CHK_SD_DDR50(sd_card))
1742 tuning_cmd = sd_ddr_tuning_rx_cmd;
1744 tuning_cmd = sd_sdr_tuning_rx_cmd;
1747 if (CHK_MMC_DDR52(sd_card))
1748 tuning_cmd = mmc_ddr_tuning_rx_cmd;
1753 for (i = 0; i < 3; i++) {
1754 raw_phase_map[i] = 0;
1755 for (j = MAX_PHASE; j >= 0; j--) {
1756 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1757 sd_set_err_code(chip, SD_NO_CARD);
1761 retval = tuning_cmd(chip, (u8)j);
1762 if (retval == STATUS_SUCCESS)
1763 raw_phase_map[i] |= 1 << j;
1767 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1768 for (i = 0; i < 3; i++)
1769 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1770 i, raw_phase_map[i]);
1772 dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1774 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1775 if (final_phase == 0xFF)
1778 retval = sd_change_phase(chip, final_phase, TUNE_RX);
1779 if (retval != STATUS_SUCCESS)
1782 return STATUS_SUCCESS;
1785 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1787 struct sd_info *sd_card = &chip->sd_card;
1793 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1794 SD_RSP_80CLK_TIMEOUT_EN);
1799 for (i = MAX_PHASE; i >= 0; i--) {
1800 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1801 sd_set_err_code(chip, SD_NO_CARD);
1802 rtsx_write_register(chip, SD_CFG3,
1803 SD_RSP_80CLK_TIMEOUT_EN, 0);
1807 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1808 if (retval != STATUS_SUCCESS)
1811 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
1812 sd_card->sd_addr, SD_RSP_TYPE_R1,
1814 if ((retval == STATUS_SUCCESS) ||
1815 !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1816 phase_map |= 1 << i;
1819 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1824 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
1827 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1828 if (final_phase == 0xFF)
1831 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1832 if (retval != STATUS_SUCCESS)
1835 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
1838 return STATUS_SUCCESS;
1841 static int sd_tuning_tx(struct rtsx_chip *chip)
1843 struct sd_info *sd_card = &chip->sd_card;
1846 u32 raw_phase_map[3], phase_map;
1848 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1850 if (CHK_SD(sd_card)) {
1851 if (CHK_SD_DDR50(sd_card))
1852 tuning_cmd = sd_ddr_tuning_tx_cmd;
1854 tuning_cmd = sd_sdr_tuning_tx_cmd;
1857 if (CHK_MMC_DDR52(sd_card))
1858 tuning_cmd = sd_ddr_tuning_tx_cmd;
1863 for (i = 0; i < 3; i++) {
1864 raw_phase_map[i] = 0;
1865 for (j = MAX_PHASE; j >= 0; j--) {
1866 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1867 sd_set_err_code(chip, SD_NO_CARD);
1868 rtsx_write_register(chip, SD_CFG3,
1869 SD_RSP_80CLK_TIMEOUT_EN, 0);
1873 retval = tuning_cmd(chip, (u8)j);
1874 if (retval == STATUS_SUCCESS)
1875 raw_phase_map[i] |= 1 << j;
1879 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1880 for (i = 0; i < 3; i++)
1881 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
1882 i, raw_phase_map[i]);
1884 dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
1886 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1887 if (final_phase == 0xFF)
1890 retval = sd_change_phase(chip, final_phase, TUNE_TX);
1891 if (retval != STATUS_SUCCESS)
1894 return STATUS_SUCCESS;
1897 static int sd_sdr_tuning(struct rtsx_chip *chip)
1901 retval = sd_tuning_tx(chip);
1902 if (retval != STATUS_SUCCESS)
1905 retval = sd_tuning_rx(chip);
1906 if (retval != STATUS_SUCCESS)
1909 return STATUS_SUCCESS;
1912 static int sd_ddr_tuning(struct rtsx_chip *chip)
1916 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1917 retval = sd_ddr_pre_tuning_tx(chip);
1918 if (retval != STATUS_SUCCESS)
1921 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
1923 if (retval != STATUS_SUCCESS)
1927 retval = sd_tuning_rx(chip);
1928 if (retval != STATUS_SUCCESS)
1931 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1932 retval = sd_tuning_tx(chip);
1933 if (retval != STATUS_SUCCESS)
1937 return STATUS_SUCCESS;
1940 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1944 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1945 retval = sd_ddr_pre_tuning_tx(chip);
1946 if (retval != STATUS_SUCCESS)
1949 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
1951 if (retval != STATUS_SUCCESS)
1955 retval = sd_tuning_rx(chip);
1956 if (retval != STATUS_SUCCESS)
1959 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1960 retval = sd_tuning_tx(chip);
1961 if (retval != STATUS_SUCCESS)
1965 return STATUS_SUCCESS;
1968 int sd_switch_clock(struct rtsx_chip *chip)
1970 struct sd_info *sd_card = &chip->sd_card;
1974 retval = select_card(chip, SD_CARD);
1975 if (retval != STATUS_SUCCESS)
1978 retval = switch_clock(chip, sd_card->sd_clock);
1979 if (retval != STATUS_SUCCESS)
1983 if (CHK_SD(sd_card)) {
1984 if (CHK_SD_DDR50(sd_card))
1985 retval = sd_ddr_tuning(chip);
1987 retval = sd_sdr_tuning(chip);
1989 if (CHK_MMC_DDR52(sd_card))
1990 retval = mmc_ddr_tuning(chip);
1993 if (retval != STATUS_SUCCESS)
1997 return STATUS_SUCCESS;
2000 static int sd_prepare_reset(struct rtsx_chip *chip)
2002 struct sd_info *sd_card = &chip->sd_card;
2005 if (chip->asic_code)
2006 sd_card->sd_clock = 29;
2008 sd_card->sd_clock = CLK_30;
2010 sd_card->sd_type = 0;
2011 sd_card->seq_mode = 0;
2012 sd_card->sd_data_buf_ready = 0;
2013 sd_card->capacity = 0;
2015 #ifdef SUPPORT_SD_LOCK
2016 sd_card->sd_lock_status = 0;
2017 sd_card->sd_erase_status = 0;
2020 chip->capacity[chip->card2lun[SD_CARD]] = 0;
2023 retval = sd_set_init_para(chip);
2024 if (retval != STATUS_SUCCESS)
2027 retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40);
2031 retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
2032 SD_STOP | SD_CLR_ERR);
2036 retval = select_card(chip, SD_CARD);
2037 if (retval != STATUS_SUCCESS)
2040 return STATUS_SUCCESS;
2043 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2047 if (CHECK_PID(chip, 0x5208)) {
2048 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
2049 XD_D3_PD | SD_D7_PD | SD_CLK_PD |
2053 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
2054 SD_D6_PD | SD_D0_PD | SD_D1_PD |
2058 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
2059 SD_D4_PD | XD_CE_PD | XD_CLE_PD |
2063 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
2064 XD_RDY_PD | SD_D3_PD | SD_D2_PD |
2068 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
2069 MS_INS_PU | SD_WP_PD | SD_CD_PU |
2073 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
2074 MS_D5_PD | MS_D4_PD);
2077 } else if (CHECK_PID(chip, 0x5288)) {
2078 if (CHECK_BARO_PKG(chip, QFN)) {
2079 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
2083 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
2087 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
2091 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
2098 return STATUS_SUCCESS;
2101 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2105 rtsx_init_cmd(chip);
2107 if (CHECK_PID(chip, 0x5208)) {
2108 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2109 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2110 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2111 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2112 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2113 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2114 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2115 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2116 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2117 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2118 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
2119 MS_D5_PD | MS_D4_PD);
2120 } else if (CHECK_PID(chip, 0x5288)) {
2121 if (CHECK_BARO_PKG(chip, QFN)) {
2122 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2124 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2126 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2128 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2133 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2137 return STATUS_SUCCESS;
2140 static int sd_init_power(struct rtsx_chip *chip)
2144 retval = sd_power_off_card3v3(chip);
2145 if (retval != STATUS_SUCCESS)
2148 if (!chip->ft2_fast_mode)
2151 retval = enable_card_clock(chip, SD_CARD);
2152 if (retval != STATUS_SUCCESS)
2155 if (chip->asic_code) {
2156 retval = sd_pull_ctl_enable(chip);
2157 if (retval != STATUS_SUCCESS)
2160 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2161 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2166 if (!chip->ft2_fast_mode) {
2167 retval = card_power_on(chip, SD_CARD);
2168 if (retval != STATUS_SUCCESS)
2174 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2175 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2182 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
2187 return STATUS_SUCCESS;
2190 static int sd_dummy_clock(struct rtsx_chip *chip)
2194 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01);
2198 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0);
2202 return STATUS_SUCCESS;
2205 static int sd_read_lba0(struct rtsx_chip *chip)
2207 struct sd_info *sd_card = &chip->sd_card;
2209 u8 cmd[5], bus_width;
2211 cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2217 if (CHK_SD(sd_card)) {
2218 bus_width = SD_BUS_WIDTH_4;
2220 if (CHK_MMC_8BIT(sd_card))
2221 bus_width = SD_BUS_WIDTH_8;
2222 else if (CHK_MMC_4BIT(sd_card))
2223 bus_width = SD_BUS_WIDTH_4;
2225 bus_width = SD_BUS_WIDTH_1;
2228 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512, 1,
2229 bus_width, NULL, 0, 100);
2230 if (retval != STATUS_SUCCESS) {
2231 rtsx_clear_sd_error(chip);
2235 return STATUS_SUCCESS;
2238 static int sd_check_wp_state(struct rtsx_chip *chip)
2240 struct sd_info *sd_card = &chip->sd_card;
2246 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2247 SD_RSP_TYPE_R1, NULL, 0);
2248 if (retval != STATUS_SUCCESS)
2251 cmd[0] = 0x40 | SD_STATUS;
2257 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2258 SD_BUS_WIDTH_4, buf, 64, 250);
2259 if (retval != STATUS_SUCCESS) {
2260 rtsx_clear_sd_error(chip);
2262 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2263 SD_RSP_TYPE_R1, NULL, 0);
2267 dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2268 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
2270 sd_card_type = ((u16)buf[2] << 8) | buf[3];
2271 dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2272 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2273 /* ROM card or OTP */
2274 chip->card_wp |= SD_CARD;
2277 /* Check SD Machanical Write-Protect Switch */
2278 val = rtsx_readl(chip, RTSX_BIPR);
2279 if (val & SD_WRITE_PROTECT)
2280 chip->card_wp |= SD_CARD;
2282 return STATUS_SUCCESS;
2285 static int reset_sd(struct rtsx_chip *chip)
2287 struct sd_info *sd_card = &chip->sd_card;
2288 bool hi_cap_flow = false;
2289 int retval, i = 0, j = 0, k = 0;
2290 bool sd_dont_switch = false;
2291 bool support_1v8 = false;
2292 bool try_sdio = true;
2294 u8 switch_bus_width;
2296 bool sd20_mode = false;
2305 hi_cap_flow = false;
2307 #ifdef SUPPORT_SD_LOCK
2308 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2309 goto SD_UNLOCK_ENTRY;
2312 retval = sd_prepare_reset(chip);
2313 if (retval != STATUS_SUCCESS)
2316 retval = sd_dummy_clock(chip);
2317 if (retval != STATUS_SUCCESS)
2320 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2323 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2324 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2325 sd_set_err_code(chip, SD_NO_CARD);
2329 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2330 SD_RSP_TYPE_R4, rsp, 5);
2331 if (retval == STATUS_SUCCESS) {
2332 int func_num = (rsp[1] >> 4) & 0x07;
2335 dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2344 sd_init_power(chip);
2346 sd_dummy_clock(chip);
2349 dev_dbg(rtsx_dev(chip), "Normal card!\n");
2352 /* Start Initialization Process of SD Card */
2354 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2356 if (retval != STATUS_SUCCESS)
2361 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2362 SD_RSP_TYPE_R7, rsp, 5);
2363 if (retval == STATUS_SUCCESS) {
2364 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2366 voltage = SUPPORT_VOLTAGE | 0x40000000;
2371 voltage = SUPPORT_VOLTAGE;
2373 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2374 SD_RSP_TYPE_R0, NULL, 0);
2375 if (retval != STATUS_SUCCESS)
2382 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2384 if (retval != STATUS_SUCCESS) {
2385 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2386 sd_set_err_code(chip, SD_NO_CARD);
2397 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2398 SD_RSP_TYPE_R3, rsp, 5);
2399 if (retval != STATUS_SUCCESS) {
2409 } while (!(rsp[1] & 0x80) && (i < 255));
2416 SET_SD_HCXC(sd_card);
2418 CLR_SD_HCXC(sd_card);
2420 support_1v8 = false;
2422 CLR_SD_HCXC(sd_card);
2423 support_1v8 = false;
2425 dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2428 retval = sd_voltage_switch(chip);
2429 if (retval != STATUS_SUCCESS)
2433 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2435 if (retval != STATUS_SUCCESS)
2438 for (i = 0; i < 3; i++) {
2439 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2440 SD_RSP_TYPE_R6, rsp, 5);
2441 if (retval != STATUS_SUCCESS)
2444 sd_card->sd_addr = (u32)rsp[1] << 24;
2445 sd_card->sd_addr += (u32)rsp[2] << 16;
2447 if (sd_card->sd_addr)
2451 retval = sd_check_csd(chip, 1);
2452 if (retval != STATUS_SUCCESS)
2455 retval = sd_select_card(chip, 1);
2456 if (retval != STATUS_SUCCESS)
2459 #ifdef SUPPORT_SD_LOCK
2461 retval = sd_update_lock_status(chip);
2462 if (retval != STATUS_SUCCESS)
2465 if (sd_card->sd_lock_status & SD_LOCKED) {
2466 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2467 return STATUS_SUCCESS;
2468 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2469 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2473 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2474 SD_RSP_TYPE_R1, NULL, 0);
2475 if (retval != STATUS_SUCCESS)
2478 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2479 SD_RSP_TYPE_R1, NULL, 0);
2480 if (retval != STATUS_SUCCESS)
2484 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2485 SD_RSP_TYPE_R1, NULL, 0);
2486 if (retval != STATUS_SUCCESS)
2489 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2490 SD_RSP_TYPE_R1, NULL, 0);
2491 if (retval != STATUS_SUCCESS)
2494 switch_bus_width = SD_BUS_WIDTH_4;
2496 switch_bus_width = SD_BUS_WIDTH_1;
2499 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2501 if (retval != STATUS_SUCCESS)
2504 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2505 if (retval != STATUS_SUCCESS)
2508 if (!(sd_card->raw_csd[4] & 0x40))
2509 sd_dont_switch = true;
2511 if (!sd_dont_switch) {
2513 /* Set sd_switch_fail here, because we needn't
2514 * switch to UHS mode
2516 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2517 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2520 /* Check the card whether follow SD1.1 spec or higher */
2521 retval = sd_check_spec(chip, switch_bus_width);
2522 if (retval == STATUS_SUCCESS) {
2523 retval = sd_switch_function(chip, switch_bus_width);
2524 if (retval != STATUS_SUCCESS) {
2525 sd_init_power(chip);
2526 sd_dont_switch = true;
2533 sd_init_power(chip);
2534 sd_dont_switch = true;
2543 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2544 SD_RSP_TYPE_R1, NULL, 0);
2545 if (retval != STATUS_SUCCESS)
2548 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2549 SD_RSP_TYPE_R1, NULL, 0);
2550 if (retval != STATUS_SUCCESS)
2554 #ifdef SUPPORT_SD_LOCK
2555 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2558 if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2561 retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07,
2562 chip->sd30_drive_sel_1v8);
2566 retval = sd_set_init_para(chip);
2567 if (retval != STATUS_SUCCESS)
2570 if (CHK_SD_DDR50(sd_card))
2571 retval = sd_ddr_tuning(chip);
2573 retval = sd_sdr_tuning(chip);
2575 if (retval != STATUS_SUCCESS) {
2579 retval = sd_init_power(chip);
2580 if (retval != STATUS_SUCCESS)
2589 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2590 SD_RSP_TYPE_R1, NULL, 0);
2592 if (CHK_SD_DDR50(sd_card)) {
2593 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2594 if (retval != STATUS_SUCCESS)
2599 retval = sd_read_lba0(chip);
2600 if (retval != STATUS_SUCCESS) {
2604 retval = sd_init_power(chip);
2605 if (retval != STATUS_SUCCESS)
2616 retval = sd_check_wp_state(chip);
2617 if (retval != STATUS_SUCCESS)
2620 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2622 #ifdef SUPPORT_SD_LOCK
2623 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2624 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
2628 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
2635 return STATUS_SUCCESS;
2641 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2643 struct sd_info *sd_card = &chip->sd_card;
2645 u8 buf[8] = {0}, bus_width, *ptr;
2649 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2651 if (retval != STATUS_SUCCESS)
2654 if (width == MMC_8BIT_BUS) {
2659 bus_width = SD_BUS_WIDTH_8;
2664 bus_width = SD_BUS_WIDTH_4;
2667 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2668 if (retval != STATUS_SUCCESS)
2671 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, NULL, 0, byte_cnt, 1,
2672 bus_width, buf, len, 100);
2673 if (retval != STATUS_SUCCESS) {
2674 rtsx_clear_sd_error(chip);
2675 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2679 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2680 if (retval != STATUS_SUCCESS)
2683 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
2685 rtsx_init_cmd(chip);
2687 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2689 if (width == MMC_8BIT_BUS)
2690 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2693 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2696 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2697 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2699 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, SD_CALCULATE_CRC7 |
2700 SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2701 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2702 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2704 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2705 SD_TM_NORMAL_READ | SD_TRANSFER_START);
2706 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2709 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2710 if (width == MMC_8BIT_BUS)
2711 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2713 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2715 rtsx_clear_sd_error(chip);
2719 ptr = rtsx_get_cmd_data(chip) + 1;
2721 if (width == MMC_8BIT_BUS) {
2722 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2724 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2728 if (CHK_MMC_DDR52(sd_card))
2733 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2734 SD_RSP_TYPE_R1b, rsp, 5);
2735 if ((retval == STATUS_SUCCESS) &&
2736 !(rsp[4] & MMC_SWITCH_ERR))
2737 return SWITCH_SUCCESS;
2740 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2741 if (ptr[0] == 0xA5) {
2745 if (CHK_MMC_DDR52(sd_card))
2750 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2751 SD_RSP_TYPE_R1b, rsp, 5);
2752 if ((retval == STATUS_SUCCESS) &&
2753 !(rsp[4] & MMC_SWITCH_ERR))
2754 return SWITCH_SUCCESS;
2761 static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr)
2763 struct sd_info *sd_card = &chip->sd_card;
2765 u8 *ptr, card_type, card_type_mask = 0;
2767 CLR_MMC_HS(sd_card);
2769 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
2771 rtsx_init_cmd(chip);
2773 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
2774 0x40 | SEND_EXT_CSD);
2775 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2776 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2777 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2778 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2780 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2781 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2782 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2783 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2785 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2786 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2787 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2788 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2790 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2791 SD_TM_NORMAL_READ | SD_TRANSFER_START);
2792 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2795 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2796 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2797 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2798 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2799 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2801 retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2803 if (retval == -ETIMEDOUT) {
2804 rtsx_clear_sd_error(chip);
2805 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2806 SD_RSP_TYPE_R1, NULL, 0);
2811 ptr = rtsx_get_cmd_data(chip);
2812 if (ptr[0] & SD_TRANSFER_ERR) {
2813 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2814 SD_RSP_TYPE_R1, NULL, 0);
2818 if (CHK_MMC_SECTOR_MODE(sd_card)) {
2819 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2820 ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2823 card_type_mask = 0x03;
2824 card_type = ptr[1] & card_type_mask;
2828 if (card_type & 0x04) {
2830 SET_MMC_DDR52(sd_card);
2832 SET_MMC_52M(sd_card);
2833 } else if (card_type & 0x02) {
2834 SET_MMC_52M(sd_card);
2836 SET_MMC_26M(sd_card);
2839 retval = sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100,
2840 SD_RSP_TYPE_R1b, rsp, 5);
2841 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2842 CLR_MMC_HS(sd_card);
2845 sd_choose_proper_clock(chip);
2846 retval = switch_clock(chip, sd_card->sd_clock);
2847 if (retval != STATUS_SUCCESS)
2850 /* Test Bus Procedure */
2851 retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2852 if (retval == SWITCH_SUCCESS) {
2853 SET_MMC_8BIT(sd_card);
2854 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2855 #ifdef SUPPORT_SD_LOCK
2856 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2858 } else if (retval == SWITCH_FAIL) {
2859 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2860 if (retval == SWITCH_SUCCESS) {
2861 SET_MMC_4BIT(sd_card);
2862 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2863 #ifdef SUPPORT_SD_LOCK
2864 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2866 } else if (retval == SWITCH_FAIL) {
2867 CLR_MMC_8BIT(sd_card);
2868 CLR_MMC_4BIT(sd_card);
2876 return STATUS_SUCCESS;
2879 static int reset_mmc(struct rtsx_chip *chip)
2881 struct sd_info *sd_card = &chip->sd_card;
2882 int retval, i = 0, j = 0, k = 0;
2883 bool switch_ddr = true;
2888 #ifdef SUPPORT_SD_LOCK
2889 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2890 goto MMC_UNLOCK_ENTRY;
2894 retval = sd_prepare_reset(chip);
2895 if (retval != STATUS_SUCCESS)
2901 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2903 if (retval != STATUS_SUCCESS)
2907 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2908 sd_set_err_code(chip, SD_NO_CARD);
2912 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2913 (SUPPORT_VOLTAGE | 0x40000000),
2914 SD_RSP_TYPE_R3, rsp, 5);
2915 if (retval != STATUS_SUCCESS) {
2916 if (sd_check_err_code(chip, SD_BUSY) ||
2917 sd_check_err_code(chip, SD_TO_ERR)) {
2920 sd_clr_err_code(chip);
2928 sd_clr_err_code(chip);
2938 } while (!(rsp[1] & 0x80) && (i < 255));
2943 if ((rsp[1] & 0x60) == 0x40)
2944 SET_MMC_SECTOR_MODE(sd_card);
2946 CLR_MMC_SECTOR_MODE(sd_card);
2948 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2950 if (retval != STATUS_SUCCESS)
2953 sd_card->sd_addr = 0x00100000;
2954 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2955 SD_RSP_TYPE_R6, rsp, 5);
2956 if (retval != STATUS_SUCCESS)
2959 retval = sd_check_csd(chip, 1);
2960 if (retval != STATUS_SUCCESS)
2963 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2965 retval = sd_select_card(chip, 1);
2966 if (retval != STATUS_SUCCESS)
2969 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2971 if (retval != STATUS_SUCCESS)
2974 #ifdef SUPPORT_SD_LOCK
2976 retval = sd_update_lock_status(chip);
2977 if (retval != STATUS_SUCCESS)
2981 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2982 if (retval != STATUS_SUCCESS)
2985 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2987 if (!sd_card->mmc_dont_switch_bus) {
2988 if (spec_ver == 4) {
2990 retval = mmc_switch_timing_bus(chip, switch_ddr);
2991 if (retval != STATUS_SUCCESS) {
2992 retval = sd_init_power(chip);
2993 if (retval != STATUS_SUCCESS)
2995 sd_card->mmc_dont_switch_bus = 1;
3000 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
3003 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3004 retval = sd_set_init_para(chip);
3005 if (retval != STATUS_SUCCESS)
3008 retval = mmc_ddr_tuning(chip);
3009 if (retval != STATUS_SUCCESS) {
3010 retval = sd_init_power(chip);
3011 if (retval != STATUS_SUCCESS)
3018 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3019 if (retval == STATUS_SUCCESS) {
3020 retval = sd_read_lba0(chip);
3021 if (retval != STATUS_SUCCESS) {
3022 retval = sd_init_power(chip);
3023 if (retval != STATUS_SUCCESS)
3033 #ifdef SUPPORT_SD_LOCK
3034 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3035 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
3039 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
3046 temp = rtsx_readl(chip, RTSX_BIPR);
3047 if (temp & SD_WRITE_PROTECT)
3048 chip->card_wp |= SD_CARD;
3050 return STATUS_SUCCESS;
3053 int reset_sd_card(struct rtsx_chip *chip)
3055 struct sd_info *sd_card = &chip->sd_card;
3058 sd_init_reg_addr(chip);
3060 memset(sd_card, 0, sizeof(struct sd_info));
3061 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3063 retval = enable_card_clock(chip, SD_CARD);
3064 if (retval != STATUS_SUCCESS)
3067 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
3068 !CHK_SDIO_IGNORED(chip)) {
3069 if (chip->asic_code) {
3070 retval = sd_pull_ctl_enable(chip);
3071 if (retval != STATUS_SUCCESS)
3074 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3075 FPGA_SD_PULL_CTL_BIT |
3077 if (retval != STATUS_SUCCESS)
3080 retval = card_share_mode(chip, SD_CARD);
3081 if (retval != STATUS_SUCCESS)
3088 retval = sd_init_power(chip);
3089 if (retval != STATUS_SUCCESS)
3092 if (chip->sd_ctl & RESET_MMC_FIRST) {
3093 retval = reset_mmc(chip);
3094 if (retval != STATUS_SUCCESS) {
3095 if (sd_check_err_code(chip, SD_NO_CARD))
3098 retval = reset_sd(chip);
3099 if (retval != STATUS_SUCCESS)
3103 retval = reset_sd(chip);
3104 if (retval != STATUS_SUCCESS) {
3105 if (sd_check_err_code(chip, SD_NO_CARD))
3110 retval = reset_mmc(chip);
3111 if (retval != STATUS_SUCCESS)
3116 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3117 if (retval != STATUS_SUCCESS)
3120 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3123 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3127 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3129 retval = sd_set_init_para(chip);
3130 if (retval != STATUS_SUCCESS)
3133 dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3135 return STATUS_SUCCESS;
3138 static int reset_mmc_only(struct rtsx_chip *chip)
3140 struct sd_info *sd_card = &chip->sd_card;
3143 sd_card->sd_type = 0;
3144 sd_card->seq_mode = 0;
3145 sd_card->sd_data_buf_ready = 0;
3146 sd_card->capacity = 0;
3147 sd_card->sd_switch_fail = 0;
3149 #ifdef SUPPORT_SD_LOCK
3150 sd_card->sd_lock_status = 0;
3151 sd_card->sd_erase_status = 0;
3154 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3156 retval = enable_card_clock(chip, SD_CARD);
3157 if (retval != STATUS_SUCCESS)
3160 retval = sd_init_power(chip);
3161 if (retval != STATUS_SUCCESS)
3164 retval = reset_mmc(chip);
3165 if (retval != STATUS_SUCCESS)
3168 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3169 if (retval != STATUS_SUCCESS)
3172 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3175 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3179 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3181 retval = sd_set_init_para(chip);
3182 if (retval != STATUS_SUCCESS)
3185 dev_dbg(rtsx_dev(chip), "In %s, sd_card->sd_type = 0x%x\n",
3186 __func__, sd_card->sd_type);
3188 return STATUS_SUCCESS;
3191 #define WAIT_DATA_READY_RTY_CNT 255
3193 static int wait_data_buf_ready(struct rtsx_chip *chip)
3195 struct sd_info *sd_card = &chip->sd_card;
3198 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3199 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3200 sd_set_err_code(chip, SD_NO_CARD);
3204 sd_card->sd_data_buf_ready = 0;
3206 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3207 sd_card->sd_addr, SD_RSP_TYPE_R1,
3209 if (retval != STATUS_SUCCESS)
3212 if (sd_card->sd_data_buf_ready) {
3213 return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3214 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3218 sd_set_err_code(chip, SD_TO_ERR);
3223 void sd_stop_seq_mode(struct rtsx_chip *chip)
3225 struct sd_info *sd_card = &chip->sd_card;
3228 if (sd_card->seq_mode) {
3229 retval = sd_switch_clock(chip);
3230 if (retval != STATUS_SUCCESS)
3233 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3234 SD_RSP_TYPE_R1b, NULL, 0);
3235 if (retval != STATUS_SUCCESS)
3236 sd_set_err_code(chip, SD_STS_ERR);
3238 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3239 if (retval != STATUS_SUCCESS)
3240 sd_set_err_code(chip, SD_STS_ERR);
3242 sd_card->seq_mode = 0;
3244 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3248 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3250 struct sd_info *sd_card = &chip->sd_card;
3253 if (chip->asic_code) {
3254 if (sd_card->sd_clock > 30)
3255 sd_card->sd_clock -= 20;
3257 switch (sd_card->sd_clock) {
3259 sd_card->sd_clock = CLK_150;
3263 sd_card->sd_clock = CLK_120;
3267 sd_card->sd_clock = CLK_100;
3271 sd_card->sd_clock = CLK_80;
3275 sd_card->sd_clock = CLK_60;
3279 sd_card->sd_clock = CLK_50;
3287 retval = sd_switch_clock(chip);
3288 if (retval != STATUS_SUCCESS)
3291 return STATUS_SUCCESS;
3294 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3297 struct sd_info *sd_card = &chip->sd_card;
3302 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3303 dev_dbg(rtsx_dev(chip), "%s: Read %d %s from 0x%x\n", __func__,
3304 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3307 dev_dbg(rtsx_dev(chip), "%s: Write %d %s to 0x%x\n", __func__,
3308 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3312 sd_card->cleanup_counter = 0;
3314 if (!(chip->card_ready & SD_CARD)) {
3315 sd_card->seq_mode = 0;
3317 retval = reset_sd_card(chip);
3318 if (retval == STATUS_SUCCESS) {
3319 chip->card_ready |= SD_CARD;
3320 chip->card_fail &= ~SD_CARD;
3322 chip->card_ready &= ~SD_CARD;
3323 chip->card_fail |= SD_CARD;
3324 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3325 chip->rw_need_retry = 1;
3330 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3331 data_addr = start_sector << 9;
3333 data_addr = start_sector;
3335 sd_clr_err_code(chip);
3337 retval = sd_switch_clock(chip);
3338 if (retval != STATUS_SUCCESS) {
3339 sd_set_err_code(chip, SD_IO_ERR);
3343 if (sd_card->seq_mode &&
3344 ((sd_card->pre_dir != srb->sc_data_direction) ||
3345 ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3347 if ((sd_card->pre_sec_cnt < 0x80) &&
3348 (sd_card->pre_dir == DMA_FROM_DEVICE) &&
3349 !CHK_SD30_SPEED(sd_card) &&
3350 !CHK_SD_HS(sd_card) &&
3351 !CHK_MMC_HS(sd_card)) {
3352 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3353 SD_RSP_TYPE_R1, NULL, 0);
3356 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3357 SD_RSP_TYPE_R1b, NULL, 0);
3358 if (retval != STATUS_SUCCESS) {
3359 chip->rw_need_retry = 1;
3360 sd_set_err_code(chip, SD_STS_ERR);
3364 sd_card->seq_mode = 0;
3366 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3367 if (retval != STATUS_SUCCESS) {
3368 sd_set_err_code(chip, SD_IO_ERR);
3372 if ((sd_card->pre_sec_cnt < 0x80) &&
3373 !CHK_SD30_SPEED(sd_card) &&
3374 !CHK_SD_HS(sd_card) &&
3375 !CHK_MMC_HS(sd_card)) {
3376 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3377 SD_RSP_TYPE_R1, NULL, 0);
3381 rtsx_init_cmd(chip);
3383 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3384 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3385 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3387 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3388 (u8)(sector_cnt >> 8));
3390 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3392 if (CHK_MMC_8BIT(sd_card))
3393 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3394 0x03, SD_BUS_WIDTH_8);
3395 else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3396 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3397 0x03, SD_BUS_WIDTH_4);
3399 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3400 0x03, SD_BUS_WIDTH_1);
3402 if (sd_card->seq_mode) {
3403 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3404 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3406 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3408 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3411 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3412 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3413 SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3415 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3416 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3419 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3420 SD_TRANSFER_END, SD_TRANSFER_END);
3422 rtsx_send_cmd_no_wait(chip);
3424 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3425 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3426 READ_MULTIPLE_BLOCK);
3427 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3428 0x40 | READ_MULTIPLE_BLOCK);
3429 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3430 (u8)(data_addr >> 24));
3431 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3432 (u8)(data_addr >> 16));
3433 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3434 (u8)(data_addr >> 8));
3435 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3438 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3439 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3441 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3444 trans_dma_enable(srb->sc_data_direction, chip,
3445 sector_cnt * 512, DMA_512);
3447 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3448 SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3449 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3450 SD_TRANSFER_END, SD_TRANSFER_END);
3452 rtsx_send_cmd_no_wait(chip);
3454 retval = rtsx_send_cmd(chip, SD_CARD, 50);
3456 rtsx_clear_sd_error(chip);
3458 chip->rw_need_retry = 1;
3459 sd_set_err_code(chip, SD_TO_ERR);
3463 retval = wait_data_buf_ready(chip);
3464 if (retval != STATUS_SUCCESS) {
3465 chip->rw_need_retry = 1;
3466 sd_set_err_code(chip, SD_TO_ERR);
3470 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3471 data_addr, SD_RSP_TYPE_R1,
3473 if (retval != STATUS_SUCCESS) {
3474 chip->rw_need_retry = 1;
3478 rtsx_init_cmd(chip);
3480 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3481 SD_NO_WAIT_BUSY_END |
3482 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3483 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3486 trans_dma_enable(srb->sc_data_direction, chip,
3487 sector_cnt * 512, DMA_512);
3489 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3490 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3491 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3492 SD_TRANSFER_END, SD_TRANSFER_END);
3494 rtsx_send_cmd_no_wait(chip);
3497 sd_card->seq_mode = 1;
3500 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3501 scsi_bufflen(srb), scsi_sg_count(srb),
3502 srb->sc_data_direction, chip->sd_timeout);
3507 sd_card->seq_mode = 0;
3509 if (retval == -ETIMEDOUT)
3510 err = STATUS_TIMEDOUT;
3514 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3515 rtsx_clear_sd_error(chip);
3516 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3517 chip->rw_need_retry = 0;
3518 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n",
3523 chip->rw_need_retry = 1;
3525 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3526 SD_RSP_TYPE_R1b, NULL, 0);
3527 if (retval != STATUS_SUCCESS) {
3528 sd_set_err_code(chip, SD_STS_ERR);
3532 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3533 dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3534 sd_set_err_code(chip, SD_CRC_ERR);
3538 if (err == STATUS_TIMEDOUT) {
3539 sd_set_err_code(chip, SD_TO_ERR);
3546 sd_card->pre_sec_addr = start_sector;
3547 sd_card->pre_sec_cnt = sector_cnt;
3548 sd_card->pre_dir = srb->sc_data_direction;
3550 return STATUS_SUCCESS;
3553 sd_card->seq_mode = 0;
3555 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3556 chip->rw_need_retry = 0;
3557 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", __func__);
3561 if (sd_check_err_code(chip, SD_CRC_ERR)) {
3562 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3563 sd_card->mmc_dont_switch_bus = 1;
3564 reset_mmc_only(chip);
3565 sd_card->mmc_dont_switch_bus = 0;
3567 sd_card->need_retune = 1;
3568 sd_auto_tune_clock(chip);
3570 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3571 retval = reset_sd_card(chip);
3572 if (retval != STATUS_SUCCESS) {
3573 chip->card_ready &= ~SD_CARD;
3574 chip->card_fail |= SD_CARD;
3575 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3583 int soft_reset_sd_card(struct rtsx_chip *chip)
3585 return reset_sd(chip);
3588 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg,
3589 u8 rsp_type, u8 *rsp, int rsp_len,
3599 dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
3601 if (rsp_type == SD_RSP_TYPE_R1b)
3606 rtsx_init_cmd(chip);
3608 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3609 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3610 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3611 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3612 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3614 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3615 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3616 0x01, PINGPONG_BUFFER);
3617 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3618 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3619 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3622 if (rsp_type == SD_RSP_TYPE_R2) {
3623 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3625 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3628 } else if (rsp_type != SD_RSP_TYPE_R0) {
3629 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3631 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3635 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3637 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3639 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3641 if (retval == -ETIMEDOUT) {
3642 rtsx_clear_sd_error(chip);
3644 if (rsp_type & SD_WAIT_BUSY_END) {
3645 retval = sd_check_data0_status(chip);
3646 if (retval != STATUS_SUCCESS)
3649 sd_set_err_code(chip, SD_TO_ERR);
3655 if (rsp_type == SD_RSP_TYPE_R0)
3656 return STATUS_SUCCESS;
3658 ptr = rtsx_get_cmd_data(chip) + 1;
3660 if ((ptr[0] & 0xC0) != 0) {
3661 sd_set_err_code(chip, SD_STS_ERR);
3665 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3666 if (ptr[stat_idx] & SD_CRC7_ERR) {
3667 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3668 sd_set_err_code(chip, SD_CRC_ERR);
3671 if (rty_cnt < SD_MAX_RETRY_COUNT) {
3676 sd_set_err_code(chip, SD_CRC_ERR);
3682 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3683 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3684 if ((cmd_idx != STOP_TRANSMISSION) && !special_check) {
3688 #ifdef SUPPORT_SD_LOCK
3689 if (ptr[1] & 0x7D) {
3691 if (ptr[1] & 0x7F) {
3698 if (cmd_idx == SELECT_CARD) {
3699 if (rsp_type == SD_RSP_TYPE_R2) {
3700 if ((ptr[3] & 0x1E) != 0x04)
3707 memcpy(rsp, ptr, rsp_len);
3709 return STATUS_SUCCESS;
3712 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3714 int retval, rsp_len;
3717 if (rsp_type == SD_RSP_TYPE_R0)
3718 return STATUS_SUCCESS;
3720 rtsx_init_cmd(chip);
3722 if (rsp_type == SD_RSP_TYPE_R2) {
3723 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3725 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3728 } else if (rsp_type != SD_RSP_TYPE_R0) {
3729 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3731 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3735 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3737 retval = rtsx_send_cmd(chip, SD_CARD, 100);
3738 if (retval != STATUS_SUCCESS)
3742 int min_len = (rsp_len < len) ? rsp_len : len;
3744 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3746 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
3747 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3748 rsp[0], rsp[1], rsp[2], rsp[3]);
3751 return STATUS_SUCCESS;
3754 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3756 struct sd_info *sd_card = &chip->sd_card;
3757 unsigned int lun = SCSI_LUN(srb);
3780 sd_card->pre_cmd_err = 0;
3782 if (!(CHK_BIT(chip->lun_mc, lun))) {
3783 SET_BIT(chip->lun_mc, lun);
3784 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3785 return TRANSPORT_FAILED;
3788 if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) ||
3789 (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) ||
3790 (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) ||
3791 (srb->cmnd[8] != 0x64)) {
3792 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3793 return TRANSPORT_FAILED;
3796 switch (srb->cmnd[1] & 0x0F) {
3798 sd_card->sd_pass_thru_en = 0;
3802 sd_card->sd_pass_thru_en = 1;
3806 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3807 return TRANSPORT_FAILED;
3810 buf[5] = (CHK_SD(sd_card) == 1) ? 0x01 : 0x02;
3811 if (chip->card_wp & SD_CARD)
3814 buf[6] = (u8)(sd_card->sd_addr >> 16);
3815 buf[7] = (u8)(sd_card->sd_addr >> 24);
3817 buf[15] = chip->max_lun;
3819 len = min_t(int, 18, scsi_bufflen(srb));
3820 rtsx_stor_set_xfer_buf(buf, len, srb);
3822 return TRANSPORT_GOOD;
3825 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
3828 if (!rsp_type || !rsp_len)
3831 switch (srb->cmnd[10]) {
3833 *rsp_type = SD_RSP_TYPE_R0;
3838 *rsp_type = SD_RSP_TYPE_R1;
3843 *rsp_type = SD_RSP_TYPE_R1b;
3848 *rsp_type = SD_RSP_TYPE_R2;
3853 *rsp_type = SD_RSP_TYPE_R3;
3861 return STATUS_SUCCESS;
3864 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3866 struct sd_info *sd_card = &chip->sd_card;
3867 unsigned int lun = SCSI_LUN(srb);
3868 int retval, rsp_len;
3869 u8 cmd_idx, rsp_type;
3870 bool standby = false, acmd = false;
3873 if (!sd_card->sd_pass_thru_en) {
3874 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3875 return TRANSPORT_FAILED;
3878 retval = sd_switch_clock(chip);
3879 if (retval != STATUS_SUCCESS)
3880 return TRANSPORT_FAILED;
3882 if (sd_card->pre_cmd_err) {
3883 sd_card->pre_cmd_err = 0;
3884 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3885 return TRANSPORT_FAILED;
3888 cmd_idx = srb->cmnd[2] & 0x3F;
3889 if (srb->cmnd[1] & 0x02)
3892 if (srb->cmnd[1] & 0x01)
3895 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3896 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3898 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3899 if (retval != STATUS_SUCCESS) {
3900 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3901 return TRANSPORT_FAILED;
3903 sd_card->last_rsp_type = rsp_type;
3905 retval = sd_switch_clock(chip);
3906 if (retval != STATUS_SUCCESS)
3907 return TRANSPORT_FAILED;
3909 #ifdef SUPPORT_SD_LOCK
3910 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3911 if (CHK_MMC_8BIT(sd_card)) {
3912 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3914 if (retval != STATUS_SUCCESS)
3915 return TRANSPORT_FAILED;
3917 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3918 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3920 if (retval != STATUS_SUCCESS)
3921 return TRANSPORT_FAILED;
3925 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3926 if (retval != STATUS_SUCCESS)
3927 return TRANSPORT_FAILED;
3931 retval = sd_select_card(chip, 0);
3932 if (retval != STATUS_SUCCESS)
3933 goto sd_execute_cmd_failed;
3937 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3939 SD_RSP_TYPE_R1, NULL, 0,
3941 if (retval != STATUS_SUCCESS)
3942 goto sd_execute_cmd_failed;
3945 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3946 sd_card->rsp, rsp_len, false);
3947 if (retval != STATUS_SUCCESS)
3948 goto sd_execute_cmd_failed;
3951 retval = sd_select_card(chip, 1);
3952 if (retval != STATUS_SUCCESS)
3953 goto sd_execute_cmd_failed;
3956 #ifdef SUPPORT_SD_LOCK
3957 retval = sd_update_lock_status(chip);
3958 if (retval != STATUS_SUCCESS)
3959 goto sd_execute_cmd_failed;
3962 scsi_set_resid(srb, 0);
3963 return TRANSPORT_GOOD;
3965 sd_execute_cmd_failed:
3966 sd_card->pre_cmd_err = 1;
3967 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3968 release_sd_card(chip);
3969 do_reset_sd_card(chip);
3970 if (!(chip->card_ready & SD_CARD))
3971 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3973 return TRANSPORT_FAILED;
3976 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3978 struct sd_info *sd_card = &chip->sd_card;
3979 unsigned int lun = SCSI_LUN(srb);
3980 int retval, rsp_len, i;
3981 bool read_err = false, cmd13_checkbit = false;
3982 u8 cmd_idx, rsp_type, bus_width;
3983 bool standby = false, send_cmd12 = false, acmd = false;
3986 if (!sd_card->sd_pass_thru_en) {
3987 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3988 return TRANSPORT_FAILED;
3991 if (sd_card->pre_cmd_err) {
3992 sd_card->pre_cmd_err = 0;
3993 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3994 return TRANSPORT_FAILED;
3997 retval = sd_switch_clock(chip);
3998 if (retval != STATUS_SUCCESS)
3999 return TRANSPORT_FAILED;
4001 cmd_idx = srb->cmnd[2] & 0x3F;
4002 if (srb->cmnd[1] & 0x04)
4005 if (srb->cmnd[1] & 0x02)
4008 if (srb->cmnd[1] & 0x01)
4011 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4012 << 8) | srb->cmnd[9];
4014 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4015 if (retval != STATUS_SUCCESS) {
4016 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4017 return TRANSPORT_FAILED;
4019 sd_card->last_rsp_type = rsp_type;
4021 retval = sd_switch_clock(chip);
4022 if (retval != STATUS_SUCCESS)
4023 return TRANSPORT_FAILED;
4025 #ifdef SUPPORT_SD_LOCK
4026 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4027 if (CHK_MMC_8BIT(sd_card))
4028 bus_width = SD_BUS_WIDTH_8;
4029 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
4030 bus_width = SD_BUS_WIDTH_4;
4032 bus_width = SD_BUS_WIDTH_1;
4034 bus_width = SD_BUS_WIDTH_4;
4036 dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
4038 bus_width = SD_BUS_WIDTH_4;
4041 if (data_len < 512) {
4042 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4043 SD_RSP_TYPE_R1, NULL, 0,
4045 if (retval != STATUS_SUCCESS)
4046 goto sd_execute_read_cmd_failed;
4050 retval = sd_select_card(chip, 0);
4051 if (retval != STATUS_SUCCESS)
4052 goto sd_execute_read_cmd_failed;
4056 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4058 SD_RSP_TYPE_R1, NULL, 0,
4060 if (retval != STATUS_SUCCESS)
4061 goto sd_execute_read_cmd_failed;
4064 if (data_len <= 512) {
4067 u16 byte_cnt, blk_cnt;
4070 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4073 cmd[0] = 0x40 | cmd_idx;
4074 cmd[1] = srb->cmnd[3];
4075 cmd[2] = srb->cmnd[4];
4076 cmd[3] = srb->cmnd[5];
4077 cmd[4] = srb->cmnd[6];
4079 buf = kmalloc(data_len, GFP_KERNEL);
4081 return TRANSPORT_ERROR;
4083 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4084 blk_cnt, bus_width, buf, data_len, 2000);
4085 if (retval != STATUS_SUCCESS) {
4088 rtsx_clear_sd_error(chip);
4089 goto sd_execute_read_cmd_failed;
4092 min_len = min(data_len, scsi_bufflen(srb));
4093 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4096 } else if (!(data_len & 0x1FF)) {
4097 rtsx_init_cmd(chip);
4099 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4101 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4103 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4105 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4106 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4107 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4108 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4110 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
4112 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
4114 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
4116 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
4118 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
4121 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4122 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4124 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4125 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4126 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4127 SD_TRANSFER_END, SD_TRANSFER_END);
4129 rtsx_send_cmd_no_wait(chip);
4131 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4134 DMA_FROM_DEVICE, 10000);
4137 rtsx_clear_sd_error(chip);
4138 goto sd_execute_read_cmd_failed;
4142 goto sd_execute_read_cmd_failed;
4145 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4146 if (retval != STATUS_SUCCESS)
4147 goto sd_execute_read_cmd_failed;
4150 retval = sd_select_card(chip, 1);
4151 if (retval != STATUS_SUCCESS)
4152 goto sd_execute_read_cmd_failed;
4156 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4157 SD_RSP_TYPE_R1b, NULL, 0,
4159 if (retval != STATUS_SUCCESS)
4160 goto sd_execute_read_cmd_failed;
4163 if (data_len < 512) {
4164 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4165 SD_RSP_TYPE_R1, NULL, 0,
4167 if (retval != STATUS_SUCCESS)
4168 goto sd_execute_read_cmd_failed;
4170 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4171 if (retval != STATUS_SUCCESS)
4172 goto sd_execute_read_cmd_failed;
4174 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4175 if (retval != STATUS_SUCCESS)
4176 goto sd_execute_read_cmd_failed;
4179 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4180 cmd13_checkbit = true;
4182 for (i = 0; i < 3; i++) {
4183 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4185 SD_RSP_TYPE_R1, NULL, 0,
4187 if (retval == STATUS_SUCCESS)
4190 if (retval != STATUS_SUCCESS)
4191 goto sd_execute_read_cmd_failed;
4193 scsi_set_resid(srb, 0);
4194 return TRANSPORT_GOOD;
4196 sd_execute_read_cmd_failed:
4197 sd_card->pre_cmd_err = 1;
4198 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4200 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4202 release_sd_card(chip);
4203 do_reset_sd_card(chip);
4204 if (!(chip->card_ready & SD_CARD))
4205 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4207 return TRANSPORT_FAILED;
4210 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4212 struct sd_info *sd_card = &chip->sd_card;
4213 unsigned int lun = SCSI_LUN(srb);
4214 int retval, rsp_len, i;
4215 bool write_err = false, cmd13_checkbit = false;
4216 u8 cmd_idx, rsp_type;
4217 bool standby = false, send_cmd12 = false, acmd = false;
4219 #ifdef SUPPORT_SD_LOCK
4220 int lock_cmd_fail = 0;
4221 u8 sd_lock_state = 0;
4222 u8 lock_cmd_type = 0;
4225 if (!sd_card->sd_pass_thru_en) {
4226 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4227 return TRANSPORT_FAILED;
4230 if (sd_card->pre_cmd_err) {
4231 sd_card->pre_cmd_err = 0;
4232 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4233 return TRANSPORT_FAILED;
4236 retval = sd_switch_clock(chip);
4237 if (retval != STATUS_SUCCESS)
4238 return TRANSPORT_FAILED;
4240 cmd_idx = srb->cmnd[2] & 0x3F;
4241 if (srb->cmnd[1] & 0x04)
4244 if (srb->cmnd[1] & 0x02)
4247 if (srb->cmnd[1] & 0x01)
4250 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4251 << 8) | srb->cmnd[9];
4252 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4253 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4255 #ifdef SUPPORT_SD_LOCK
4256 if (cmd_idx == LOCK_UNLOCK) {
4257 sd_lock_state = sd_card->sd_lock_status;
4258 sd_lock_state &= SD_LOCKED;
4262 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4263 if (retval != STATUS_SUCCESS) {
4264 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4265 return TRANSPORT_FAILED;
4267 sd_card->last_rsp_type = rsp_type;
4269 retval = sd_switch_clock(chip);
4270 if (retval != STATUS_SUCCESS)
4271 return TRANSPORT_FAILED;
4273 #ifdef SUPPORT_SD_LOCK
4274 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4275 if (CHK_MMC_8BIT(sd_card)) {
4276 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4278 if (retval != STATUS_SUCCESS)
4279 return TRANSPORT_FAILED;
4281 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4282 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4284 if (retval != STATUS_SUCCESS)
4285 return TRANSPORT_FAILED;
4289 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4290 if (retval != STATUS_SUCCESS)
4291 return TRANSPORT_FAILED;
4294 if (data_len < 512) {
4295 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4296 SD_RSP_TYPE_R1, NULL, 0,
4298 if (retval != STATUS_SUCCESS)
4299 goto sd_execute_write_cmd_failed;
4303 retval = sd_select_card(chip, 0);
4304 if (retval != STATUS_SUCCESS)
4305 goto sd_execute_write_cmd_failed;
4309 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4311 SD_RSP_TYPE_R1, NULL, 0,
4313 if (retval != STATUS_SUCCESS)
4314 goto sd_execute_write_cmd_failed;
4317 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4318 sd_card->rsp, rsp_len, false);
4319 if (retval != STATUS_SUCCESS)
4320 goto sd_execute_write_cmd_failed;
4322 if (data_len <= 512) {
4326 buf = kmalloc(data_len, GFP_KERNEL);
4328 return TRANSPORT_ERROR;
4330 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4332 #ifdef SUPPORT_SD_LOCK
4333 if (cmd_idx == LOCK_UNLOCK)
4334 lock_cmd_type = buf[0] & 0x0F;
4337 if (data_len > 256) {
4338 rtsx_init_cmd(chip);
4339 for (i = 0; i < 256; i++) {
4340 rtsx_add_cmd(chip, WRITE_REG_CMD,
4341 PPBUF_BASE2 + i, 0xFF, buf[i]);
4343 retval = rtsx_send_cmd(chip, 0, 250);
4344 if (retval != STATUS_SUCCESS) {
4346 goto sd_execute_write_cmd_failed;
4349 rtsx_init_cmd(chip);
4350 for (i = 256; i < data_len; i++) {
4351 rtsx_add_cmd(chip, WRITE_REG_CMD,
4352 PPBUF_BASE2 + i, 0xFF, buf[i]);
4354 retval = rtsx_send_cmd(chip, 0, 250);
4355 if (retval != STATUS_SUCCESS) {
4357 goto sd_execute_write_cmd_failed;
4360 rtsx_init_cmd(chip);
4361 for (i = 0; i < data_len; i++) {
4362 rtsx_add_cmd(chip, WRITE_REG_CMD,
4363 PPBUF_BASE2 + i, 0xFF, buf[i]);
4365 retval = rtsx_send_cmd(chip, 0, 250);
4366 if (retval != STATUS_SUCCESS) {
4368 goto sd_execute_write_cmd_failed;
4374 rtsx_init_cmd(chip);
4376 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4377 srb->cmnd[8] & 0x03);
4378 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4380 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4382 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4384 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4387 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4388 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4389 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4390 SD_TRANSFER_END, SD_TRANSFER_END);
4392 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4393 } else if (!(data_len & 0x1FF)) {
4394 rtsx_init_cmd(chip);
4396 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4398 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4400 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4402 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4403 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4404 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4405 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4407 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4408 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4409 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4410 SD_TRANSFER_END, SD_TRANSFER_END);
4412 rtsx_send_cmd_no_wait(chip);
4414 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4417 DMA_TO_DEVICE, 10000);
4420 goto sd_execute_write_cmd_failed;
4425 rtsx_clear_sd_error(chip);
4426 goto sd_execute_write_cmd_failed;
4429 #ifdef SUPPORT_SD_LOCK
4430 if (cmd_idx == LOCK_UNLOCK) {
4431 if (lock_cmd_type == SD_ERASE) {
4432 sd_card->sd_erase_status = SD_UNDER_ERASING;
4433 scsi_set_resid(srb, 0);
4434 return TRANSPORT_GOOD;
4437 rtsx_init_cmd(chip);
4438 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4440 rtsx_send_cmd(chip, SD_CARD, 250);
4442 retval = sd_update_lock_status(chip);
4443 if (retval != STATUS_SUCCESS) {
4444 dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
4448 #endif /* SUPPORT_SD_LOCK */
4451 retval = sd_select_card(chip, 1);
4452 if (retval != STATUS_SUCCESS)
4453 goto sd_execute_write_cmd_failed;
4457 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4458 SD_RSP_TYPE_R1b, NULL, 0,
4460 if (retval != STATUS_SUCCESS)
4461 goto sd_execute_write_cmd_failed;
4464 if (data_len < 512) {
4465 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4466 SD_RSP_TYPE_R1, NULL, 0,
4468 if (retval != STATUS_SUCCESS)
4469 goto sd_execute_write_cmd_failed;
4471 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4472 if (retval != STATUS_SUCCESS)
4473 goto sd_execute_write_cmd_failed;
4475 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4476 if (retval != STATUS_SUCCESS)
4477 goto sd_execute_write_cmd_failed;
4480 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4481 cmd13_checkbit = true;
4483 for (i = 0; i < 3; i++) {
4484 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4486 SD_RSP_TYPE_R1, NULL, 0,
4488 if (retval == STATUS_SUCCESS)
4491 if (retval != STATUS_SUCCESS)
4492 goto sd_execute_write_cmd_failed;
4494 #ifdef SUPPORT_SD_LOCK
4495 if (cmd_idx == LOCK_UNLOCK) {
4496 if (!lock_cmd_fail) {
4497 dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
4499 if (lock_cmd_type & SD_CLR_PWD)
4500 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4502 if (lock_cmd_type & SD_SET_PWD)
4503 sd_card->sd_lock_status |= SD_PWD_EXIST;
4506 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4507 sd_lock_state, sd_card->sd_lock_status);
4508 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4509 sd_card->sd_lock_notify = 1;
4510 if (sd_lock_state) {
4511 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4512 sd_card->sd_lock_status |= (
4513 SD_UNLOCK_POW_ON | SD_SDR_RST);
4514 if (CHK_SD(sd_card)) {
4515 retval = reset_sd(chip);
4516 if (retval != STATUS_SUCCESS) {
4517 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4518 goto sd_execute_write_cmd_failed;
4522 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4528 if (lock_cmd_fail) {
4529 scsi_set_resid(srb, 0);
4530 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4531 return TRANSPORT_FAILED;
4533 #endif /* SUPPORT_SD_LOCK */
4535 scsi_set_resid(srb, 0);
4536 return TRANSPORT_GOOD;
4538 sd_execute_write_cmd_failed:
4539 sd_card->pre_cmd_err = 1;
4540 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4542 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4544 release_sd_card(chip);
4545 do_reset_sd_card(chip);
4546 if (!(chip->card_ready & SD_CARD))
4547 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4549 return TRANSPORT_FAILED;
4552 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4554 struct sd_info *sd_card = &chip->sd_card;
4555 unsigned int lun = SCSI_LUN(srb);
4559 if (!sd_card->sd_pass_thru_en) {
4560 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4561 return TRANSPORT_FAILED;
4564 if (sd_card->pre_cmd_err) {
4565 sd_card->pre_cmd_err = 0;
4566 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4567 return TRANSPORT_FAILED;
4570 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4572 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4573 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4574 return TRANSPORT_FAILED;
4575 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4576 count = (data_len < 17) ? data_len : 17;
4578 count = (data_len < 6) ? data_len : 6;
4580 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4582 dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
4583 dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
4584 sd_card->rsp[0], sd_card->rsp[1],
4585 sd_card->rsp[2], sd_card->rsp[3]);
4587 scsi_set_resid(srb, 0);
4588 return TRANSPORT_GOOD;
4591 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4593 struct sd_info *sd_card = &chip->sd_card;
4594 unsigned int lun = SCSI_LUN(srb);
4597 if (!sd_card->sd_pass_thru_en) {
4598 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4599 return TRANSPORT_FAILED;
4602 if (sd_card->pre_cmd_err) {
4603 sd_card->pre_cmd_err = 0;
4604 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4605 return TRANSPORT_FAILED;
4608 if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) ||
4609 (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) ||
4610 (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) ||
4611 (srb->cmnd[8] != 0x64)) {
4612 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4613 return TRANSPORT_FAILED;
4616 switch (srb->cmnd[1] & 0x0F) {
4618 #ifdef SUPPORT_SD_LOCK
4619 if (srb->cmnd[9] == 0x64)
4620 sd_card->sd_lock_status |= SD_SDR_RST;
4622 retval = reset_sd_card(chip);
4623 if (retval != STATUS_SUCCESS) {
4624 #ifdef SUPPORT_SD_LOCK
4625 sd_card->sd_lock_status &= ~SD_SDR_RST;
4627 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4628 sd_card->pre_cmd_err = 1;
4629 return TRANSPORT_FAILED;
4631 #ifdef SUPPORT_SD_LOCK
4632 sd_card->sd_lock_status &= ~SD_SDR_RST;
4637 retval = soft_reset_sd_card(chip);
4638 if (retval != STATUS_SUCCESS) {
4639 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4640 sd_card->pre_cmd_err = 1;
4641 return TRANSPORT_FAILED;
4646 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4647 return TRANSPORT_FAILED;
4650 scsi_set_resid(srb, 0);
4651 return TRANSPORT_GOOD;
4655 void sd_cleanup_work(struct rtsx_chip *chip)
4657 struct sd_info *sd_card = &chip->sd_card;
4659 if (sd_card->seq_mode) {
4660 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
4661 sd_stop_seq_mode(chip);
4662 sd_card->cleanup_counter = 0;
4666 int sd_power_off_card3v3(struct rtsx_chip *chip)
4670 retval = disable_card_clock(chip, SD_CARD);
4671 if (retval != STATUS_SUCCESS)
4674 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
4678 if (!chip->ft2_fast_mode) {
4679 retval = card_power_off(chip, SD_CARD);
4680 if (retval != STATUS_SUCCESS)
4686 if (chip->asic_code) {
4687 retval = sd_pull_ctl_disable(chip);
4688 if (retval != STATUS_SUCCESS)
4691 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
4692 FPGA_SD_PULL_CTL_BIT | 0x20,
4693 FPGA_SD_PULL_CTL_BIT);
4698 return STATUS_SUCCESS;
4701 int release_sd_card(struct rtsx_chip *chip)
4703 struct sd_info *sd_card = &chip->sd_card;
4706 chip->card_ready &= ~SD_CARD;
4707 chip->card_fail &= ~SD_CARD;
4708 chip->card_wp &= ~SD_CARD;
4713 #ifdef SUPPORT_SD_LOCK
4714 sd_card->sd_lock_status = 0;
4715 sd_card->sd_erase_status = 0;
4718 memset(sd_card->raw_csd, 0, 16);
4719 memset(sd_card->raw_scr, 0, 8);
4721 retval = sd_power_off_card3v3(chip);
4722 if (retval != STATUS_SUCCESS)
4725 return STATUS_SUCCESS;