drivers/staging/rts5208/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "sd.h"
  31 #include "xd.h"
  32 #include "ms.h"
  33
  34 static void rtsx_calibration(struct rtsx_chip *chip)
  35 {
  36         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  37         wait_timeout(10);
  38         rtsx_write_phy_register(chip, 0x00, 0x0280);
  39         rtsx_write_phy_register(chip, 0x01, 0x7112);
  40         rtsx_write_phy_register(chip, 0x01, 0x7110);
  41         rtsx_write_phy_register(chip, 0x01, 0x7112);
  42         rtsx_write_phy_register(chip, 0x01, 0x7113);
  43         rtsx_write_phy_register(chip, 0x00, 0x0288);
  44 }
  45
  46 void rtsx_enable_card_int(struct rtsx_chip *chip)
  47 {
  48         u32 reg = rtsx_readl(chip, RTSX_BIER);
  49         int i;
  50
  51         for (i = 0; i <= chip->max_lun; i++) {
  52                 if (chip->lun2card[i] & XD_CARD)
  53                         reg |= XD_INT_EN;
  54                 if (chip->lun2card[i] & SD_CARD)
  55                         reg |= SD_INT_EN;
  56                 if (chip->lun2card[i] & MS_CARD)
  57                         reg |= MS_INT_EN;
  58         }
  59         if (chip->hw_bypass_sd)
  60                 reg &= ~((u32)SD_INT_EN);
  61
  62         rtsx_writel(chip, RTSX_BIER, reg);
  63 }
  64
  65 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  66 {
  67         u32 reg = 0;
  68 #ifndef DISABLE_CARD_INT
  69         int i;
  70 #endif
  71
  72         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  73
  74 #ifndef DISABLE_CARD_INT
  75         for (i = 0; i <= chip->max_lun; i++) {
  76                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  77                         i, chip->lun2card[i]);
  78
  79                 if (chip->lun2card[i] & XD_CARD)
  80                         reg |= XD_INT_EN;
  81                 if (chip->lun2card[i] & SD_CARD)
  82                         reg |= SD_INT_EN;
  83                 if (chip->lun2card[i] & MS_CARD)
  84                         reg |= MS_INT_EN;
  85         }
  86         if (chip->hw_bypass_sd)
  87                 reg &= ~((u32)SD_INT_EN);
  88 #endif
  89
  90         if (chip->ic_version >= IC_VER_C)
  91                 reg |= DELINK_INT_EN;
  92 #ifdef SUPPORT_OCP
  93         reg |= OC_INT_EN;
  94 #endif
  95         if (!chip->adma_mode)
  96                 reg |= DATA_DONE_INT_EN;
  97
  98         /* Enable Bus Interrupt */
  99         rtsx_writel(chip, RTSX_BIER, reg);
 100
 101         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
 102 }
 103
 104 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 105 {
 106         rtsx_writel(chip, RTSX_BIER, 0);
 107 }
 108
 109 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 110 {
 111         int retval;
 112
 113         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 114                 if (chip->asic_code) {
 115                         retval = rtsx_write_register(chip, CARD_PULL_CTL5,
 116                                                      0xFF,
 117                                                      MS_INS_PU | SD_WP_PU |
 118                                                      SD_CD_PU | SD_CMD_PU);
 119                         if (retval) {
 120                                 rtsx_trace(chip);
 121                                 return retval;
 122                         }
 123                 } else {
 124                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
 125                                                      0xFF,
 126                                                      FPGA_SD_PULL_CTL_EN);
 127                         if (retval) {
 128                                 rtsx_trace(chip);
 129                                 return retval;
 130                         }
 131                 }
 132                 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
 133                                              CARD_SHARE_48_SD);
 134                 if (retval) {
 135                         rtsx_trace(chip);
 136                         return retval;
 137                 }
 138
 139                 /* Enable SDIO internal clock */
 140                 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
 141                 if (retval) {
 142                         rtsx_trace(chip);
 143                         return retval;
 144                 }
 145
 146                 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
 147                                              SDIO_BUS_CTRL | SDIO_CD_CTRL);
 148                 if (retval) {
 149                         rtsx_trace(chip);
 150                         return retval;
 151                 }
 152
 153                 chip->sd_int = 1;
 154                 chip->sd_io = 1;
 155         } else {
 156                 chip->need_reset |= SD_CARD;
 157         }
 158
 159         return STATUS_SUCCESS;
 160 }
 161
 162 #ifdef HW_AUTO_SWITCH_SD_BUS
 163 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 164 {
 165         u8 tmp;
 166         bool sw_bypass_sd = false;
 167         int retval;
 168
 169         if (chip->driver_first_load) {
 170                 if (CHECK_PID(chip, 0x5288)) {
 171                         retval = rtsx_read_register(chip, 0xFE5A, &tmp);
 172                         if (retval) {
 173                                 rtsx_trace(chip);
 174                                 return retval;
 175                         }
 176                         if (tmp & 0x08)
 177                                 sw_bypass_sd = true;
 178                 } else if (CHECK_PID(chip, 0x5208)) {
 179                         retval = rtsx_read_register(chip, 0xFE70, &tmp);
 180                         if (retval) {
 181                                 rtsx_trace(chip);
 182                                 return retval;
 183                         }
 184                         if (tmp & 0x80)
 185                                 sw_bypass_sd = true;
 186                 }
 187         } else {
 188                 if (chip->sdio_in_charge)
 189                         sw_bypass_sd = true;
 190         }
 191         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 192                 chip->sdio_in_charge);
 193         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 194                 chip->driver_first_load);
 195         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 196                 sw_bypass_sd);
 197
 198         if (sw_bypass_sd) {
 199                 u8 cd_toggle_mask = 0;
 200
 201                 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
 202                 if (retval) {
 203                         rtsx_trace(chip);
 204                         return retval;
 205                 }
 206                 cd_toggle_mask = 0x08;
 207
 208                 if (tmp & cd_toggle_mask) {
 209                         /* Disable sdio_bus_auto_switch */
 210                         if (CHECK_PID(chip, 0x5288)) {
 211                                 retval = rtsx_write_register(chip, 0xFE5A,
 212                                                              0x08, 0x00);
 213                                 if (retval) {
 214                                         rtsx_trace(chip);
 215                                         return retval;
 216                                 }
 217                         } else if (CHECK_PID(chip, 0x5208)) {
 218                                 retval = rtsx_write_register(chip, 0xFE70,
 219                                                              0x80, 0x00);
 220                                 if (retval) {
 221                                         rtsx_trace(chip);
 222                                         return retval;
 223                                 }
 224                         }
 225
 226                         retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
 227                                                      tmp);
 228                         if (retval) {
 229                                 rtsx_trace(chip);
 230                                 return retval;
 231                         }
 232
 233                         chip->need_reset |= SD_CARD;
 234                 } else {
 235                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 236
 237                         if (chip->asic_code) {
 238                                 retval = sd_pull_ctl_enable(chip);
 239                                 if (retval != STATUS_SUCCESS) {
 240                                         rtsx_trace(chip);
 241                                         return STATUS_FAIL;
 242                                 }
 243                         } else {
 244                                 retval = rtsx_write_register
 245                                                 (chip, FPGA_PULL_CTL,
 246                                                  FPGA_SD_PULL_CTL_BIT | 0x20,
 247                                                  0);
 248                                 if (retval) {
 249                                         rtsx_trace(chip);
 250                                         return retval;
 251                                 }
 252                         }
 253                         retval = card_share_mode(chip, SD_CARD);
 254                         if (retval != STATUS_SUCCESS) {
 255                                 rtsx_trace(chip);
 256                                 return STATUS_FAIL;
 257                         }
 258
 259                         /* Enable sdio_bus_auto_switch */
 260                         if (CHECK_PID(chip, 0x5288)) {
 261                                 retval = rtsx_write_register(chip, 0xFE5A,
 262                                                              0x08, 0x08);
 263                                 if (retval) {
 264                                         rtsx_trace(chip);
 265                                         return retval;
 266                                 }
 267                         } else if (CHECK_PID(chip, 0x5208)) {
 268                                 retval = rtsx_write_register(chip, 0xFE70,
 269                                                              0x80, 0x80);
 270                                 if (retval) {
 271                                         rtsx_trace(chip);
 272                                         return retval;
 273                                 }
 274                         }
 275
 276                         chip->chip_insert_with_sdio = 1;
 277                         chip->sd_io = 1;
 278                 }
 279         } else {
 280                 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
 281                 if (retval) {
 282                         rtsx_trace(chip);
 283                         return retval;
 284                 }
 285
 286                 chip->need_reset |= SD_CARD;
 287         }
 288
 289         return STATUS_SUCCESS;
 290 }
 291 #endif
 292
 293 static int rtsx_reset_aspm(struct rtsx_chip *chip)
 294 {
 295         int ret;
 296
 297         if (chip->dynamic_aspm) {
 298                 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
 299                         return STATUS_SUCCESS;
 300
 301                 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
 302                                         chip->aspm_l0s_l1_en);
 303                 if (ret != STATUS_SUCCESS) {
 304                         rtsx_trace(chip);
 305                         return STATUS_FAIL;
 306                 }
 307
 308                 return STATUS_SUCCESS;
 309         }
 310
 311         if (CHECK_PID(chip, 0x5208)) {
 312                 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 313                 if (ret) {
 314                         rtsx_trace(chip);
 315                         return ret;
 316                 }
 317         }
 318         ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 319         if (ret != STATUS_SUCCESS) {
 320                 rtsx_trace(chip);
 321                 return STATUS_FAIL;
 322         }
 323
 324         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 325         if (CHK_SDIO_EXIST(chip)) {
 326                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 327                 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
 328                                         0xC0, 0xFF, chip->aspm_l0s_l1_en);
 329                 if (ret != STATUS_SUCCESS) {
 330                         rtsx_trace(chip);
 331                         return STATUS_FAIL;
 332                 }
 333         }
 334
 335         chip->aspm_enabled = 1;
 336
 337         return STATUS_SUCCESS;
 338 }
 339
 340 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
 341 {
 342         int ret;
 343
 344         if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
 345                 rtsx_enable_bus_int(chip);
 346                 return STATUS_SUCCESS;
 347         }
 348
 349         if (chip->phy_debug_mode) {
 350                 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
 351                 if (ret) {
 352                         rtsx_trace(chip);
 353                         return ret;
 354                 }
 355                 rtsx_disable_bus_int(chip);
 356         } else {
 357                 rtsx_enable_bus_int(chip);
 358         }
 359
 360         if (chip->ic_version >= IC_VER_D) {
 361                 u16 reg;
 362
 363                 ret = rtsx_read_phy_register(chip, 0x00, &reg);
 364                 if (ret != STATUS_SUCCESS) {
 365                         rtsx_trace(chip);
 366                         return STATUS_FAIL;
 367                 }
 368
 369                 reg &= 0xFE7F;
 370                 reg |= 0x80;
 371                 ret = rtsx_write_phy_register(chip, 0x00, reg);
 372                 if (ret != STATUS_SUCCESS) {
 373                         rtsx_trace(chip);
 374                         return STATUS_FAIL;
 375                 }
 376
 377                 ret = rtsx_read_phy_register(chip, 0x1C, &reg);
 378                 if (ret != STATUS_SUCCESS) {
 379                         rtsx_trace(chip);
 380                         return STATUS_FAIL;
 381                 }
 382
 383                 reg &= 0xFFF7;
 384                 ret = rtsx_write_phy_register(chip, 0x1C, reg);
 385                 if (ret != STATUS_SUCCESS) {
 386                         rtsx_trace(chip);
 387                         return STATUS_FAIL;
 388                 }
 389         }
 390
 391         if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
 392                 rtsx_calibration(chip);
 393
 394         return STATUS_SUCCESS;
 395 }
 396
 397 int rtsx_reset_chip(struct rtsx_chip *chip)
 398 {
 399         int retval;
 400
 401         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 402
 403         rtsx_disable_aspm(chip);
 404
 405         retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 406         if (retval) {
 407                 rtsx_trace(chip);
 408                 return retval;
 409         }
 410
 411         /* Disable card clock */
 412         retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
 413         if (retval) {
 414                 rtsx_trace(chip);
 415                 return retval;
 416         }
 417
 418 #ifdef SUPPORT_OCP
 419         /* SSC power on, OCD power on */
 420         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 421                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
 422                 if (retval) {
 423                         rtsx_trace(chip);
 424                         return retval;
 425                 }
 426         } else {
 427                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 428                                              MS_OC_POWER_DOWN);
 429                 if (retval) {
 430                         rtsx_trace(chip);
 431                         return retval;
 432                 }
 433         }
 434
 435         retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
 436                                      OCP_TIME_800);
 437         if (retval) {
 438                 rtsx_trace(chip);
 439                 return retval;
 440         }
 441         retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
 442                                      OCP_THD_244_946);
 443         if (retval) {
 444                 rtsx_trace(chip);
 445                 return retval;
 446         }
 447         retval = rtsx_write_register(chip, OCPCTL, 0xFF,
 448                                      CARD_OC_INT_EN | CARD_DETECT_EN);
 449         if (retval) {
 450                 rtsx_trace(chip);
 451                 return retval;
 452         }
 453 #else
 454         /* OC power down */
 455         retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 456                                      OC_POWER_DOWN);
 457         if (retval) {
 458                 rtsx_trace(chip);
 459                 return retval;
 460         }
 461 #endif
 462
 463         if (!CHECK_PID(chip, 0x5288)) {
 464                 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 465                 if (retval) {
 466                         rtsx_trace(chip);
 467                         return retval;
 468                 }
 469         }
 470
 471         /* Turn off LED */
 472         retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
 473         if (retval) {
 474                 rtsx_trace(chip);
 475                 return retval;
 476         }
 477
 478         /* Reset delink mode */
 479         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
 480         if (retval) {
 481                 rtsx_trace(chip);
 482                 return retval;
 483         }
 484
 485         /* Card driving select */
 486         retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
 487                                      chip->card_drive_sel);
 488         if (retval) {
 489                 rtsx_trace(chip);
 490                 return retval;
 491         }
 492
 493 #ifdef LED_AUTO_BLINK
 494         retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
 495                                      LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 496         if (retval) {
 497                 rtsx_trace(chip);
 498                 return retval;
 499         }
 500 #endif
 501
 502         if (chip->asic_code) {
 503                 /* Enable SSC Clock */
 504                 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
 505                                              SSC_8X_EN | SSC_SEL_4M);
 506                 if (retval) {
 507                         rtsx_trace(chip);
 508                         return retval;
 509                 }
 510                 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
 511                 if (retval) {
 512                         rtsx_trace(chip);
 513                         return retval;
 514                 }
 515         }
 516
 517         /*
 518          * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 519          *    0xFE5B
 520          *    bit[1]    u_cd_rst_core_en        rst_value = 0
 521          *    bit[2]    u_force_rst_core_en     rst_value = 0
 522          *    bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 523          *    bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 524          */
 525         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 526         if (retval) {
 527                 rtsx_trace(chip);
 528                 return retval;
 529         }
 530
 531         /* Enable ASPM */
 532         if (chip->aspm_l0s_l1_en) {
 533                 retval = rtsx_reset_aspm(chip);
 534                 if (retval != STATUS_SUCCESS) {
 535                         rtsx_trace(chip);
 536                         return STATUS_FAIL;
 537                 }
 538         } else {
 539                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 540                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 541                         if (retval != STATUS_SUCCESS) {
 542                                 rtsx_trace(chip);
 543                                 return STATUS_FAIL;
 544                         }
 545                 }
 546                 retval = rtsx_write_config_byte(chip, LCTLR,
 547                                                 chip->aspm_l0s_l1_en);
 548                 if (retval != STATUS_SUCCESS) {
 549                         rtsx_trace(chip);
 550                         return STATUS_FAIL;
 551                 }
 552         }
 553
 554         retval = rtsx_write_config_byte(chip, 0x81, 1);
 555         if (retval != STATUS_SUCCESS) {
 556                 rtsx_trace(chip);
 557                 return STATUS_FAIL;
 558         }
 559
 560         if (CHK_SDIO_EXIST(chip)) {
 561                 retval = rtsx_write_cfg_dw(chip,
 562                                            CHECK_PID(chip, 0x5288) ? 2 : 1,
 563                                            0xC0, 0xFF00, 0x0100);
 564
 565                 if (retval != STATUS_SUCCESS) {
 566                         rtsx_trace(chip);
 567                         return STATUS_FAIL;
 568                 }
 569         }
 570
 571         if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
 572                 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 573                 if (retval != STATUS_SUCCESS) {
 574                         rtsx_trace(chip);
 575                         return STATUS_FAIL;
 576                 }
 577
 578                 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 579                 if (retval != STATUS_SUCCESS) {
 580                         rtsx_trace(chip);
 581                         return STATUS_FAIL;
 582                 }
 583         }
 584
 585         retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
 586                                      LINK_RDY_INT);
 587         if (retval) {
 588                 rtsx_trace(chip);
 589                 return retval;
 590         }
 591
 592         retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 593         if (retval) {
 594                 rtsx_trace(chip);
 595                 return retval;
 596         }
 597
 598         retval = rtsx_enable_pcie_intr(chip);
 599         if (retval != STATUS_SUCCESS) {
 600                 rtsx_trace(chip);
 601                 return STATUS_FAIL;
 602         }
 603
 604         chip->need_reset = 0;
 605
 606         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 607
 608         if (chip->hw_bypass_sd)
 609                 goto nextcard;
 610         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 611                 chip->int_reg);
 612         if (chip->int_reg & SD_EXIST) {
 613 #ifdef HW_AUTO_SWITCH_SD_BUS
 614                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 615                         retval = rtsx_pre_handle_sdio_old(chip);
 616                 else
 617                         retval = rtsx_pre_handle_sdio_new(chip);
 618
 619                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (%s)\n",
 620                         (unsigned int)(chip->need_reset), __func__);
 621 #else  /* HW_AUTO_SWITCH_SD_BUS */
 622                 retval = rtsx_pre_handle_sdio_old(chip);
 623 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 624                 if (retval != STATUS_SUCCESS) {
 625                         rtsx_trace(chip);
 626                         return STATUS_FAIL;
 627                 }
 628
 629         } else {
 630                 chip->sd_io = 0;
 631                 retval = rtsx_write_register(chip, SDIO_CTRL,
 632                                              SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
 633                 if (retval) {
 634                         rtsx_trace(chip);
 635                         return retval;
 636                 }
 637         }
 638
 639 nextcard:
 640         if (chip->int_reg & XD_EXIST)
 641                 chip->need_reset |= XD_CARD;
 642         if (chip->int_reg & MS_EXIST)
 643                 chip->need_reset |= MS_CARD;
 644         if (chip->int_reg & CARD_EXIST) {
 645                 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
 646                                              SSC_RSTB);
 647                 if (retval) {
 648                         rtsx_trace(chip);
 649                         return retval;
 650                 }
 651         }
 652
 653         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 654                 (unsigned int)(chip->need_reset));
 655
 656         retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
 657         if (retval) {
 658                 rtsx_trace(chip);
 659                 return retval;
 660         }
 661
 662         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 663                 /* Turn off main power when entering S3/S4 state */
 664                 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
 665                                              0x03);
 666                 if (retval) {
 667                         rtsx_trace(chip);
 668                         return retval;
 669                 }
 670         }
 671
 672         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 673                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
 674                 if (retval) {
 675                         rtsx_trace(chip);
 676                         return retval;
 677                 }
 678                 if (chip->aux_pwr_exist) {
 679                         retval = rtsx_write_register(chip, PME_FORCE_CTL,
 680                                                      0xFF, 0x33);
 681                         if (retval) {
 682                                 rtsx_trace(chip);
 683                                 return retval;
 684                         }
 685                 }
 686         } else {
 687                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
 688                 if (retval) {
 689                         rtsx_trace(chip);
 690                         return retval;
 691                 }
 692                 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
 693                 if (retval) {
 694                         rtsx_trace(chip);
 695                         return retval;
 696                 }
 697         }
 698
 699         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
 700                 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
 701                 if (retval) {
 702                         rtsx_trace(chip);
 703                         return retval;
 704                 }
 705         }
 706
 707         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 708                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 709                 if (retval != STATUS_SUCCESS) {
 710                         rtsx_trace(chip);
 711                         return STATUS_FAIL;
 712                 }
 713         }
 714
 715         if (chip->ft2_fast_mode) {
 716                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 717                                              MS_PARTIAL_POWER_ON |
 718                                              SD_PARTIAL_POWER_ON);
 719                 if (retval) {
 720                         rtsx_trace(chip);
 721                         return retval;
 722                 }
 723                 udelay(chip->pmos_pwr_on_interval);
 724                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 725                                              MS_POWER_ON | SD_POWER_ON);
 726                 if (retval) {
 727                         rtsx_trace(chip);
 728                         return retval;
 729                 }
 730
 731                 wait_timeout(200);
 732         }
 733
 734         /* Reset card */
 735         rtsx_reset_detected_cards(chip, 0);
 736
 737         chip->driver_first_load = 0;
 738
 739         return STATUS_SUCCESS;
 740 }
 741
 742 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 743 {
 744         bool fake_para = false;
 745         int i;
 746
 747         for (i = 0; i < 4; i++) {
 748                 u8 tmp = (u8)(sd_speed_prior >> (i * 8));
 749
 750                 if ((tmp < 0x01) || (tmp > 0x04)) {
 751                         fake_para = true;
 752                         break;
 753                 }
 754         }
 755
 756         return !fake_para;
 757 }
 758
 759 static inline int check_sd_current_prior(u32 sd_current_prior)
 760 {
 761         bool fake_para = false;
 762         int i;
 763
 764         for (i = 0; i < 4; i++) {
 765                 u8 tmp = (u8)(sd_current_prior >> (i * 8));
 766
 767                 if (tmp > 0x03) {
 768                         fake_para = true;
 769                         break;
 770                 }
 771         }
 772
 773         return !fake_para;
 774 }
 775
 776 static int rts5208_init(struct rtsx_chip *chip)
 777 {
 778         int retval;
 779         u16 reg = 0;
 780         u8 val = 0;
 781
 782         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 783         if (retval) {
 784                 rtsx_trace(chip);
 785                 return retval;
 786         }
 787         retval = rtsx_read_register(chip, CLK_SEL, &val);
 788         if (retval) {
 789                 rtsx_trace(chip);
 790                 return retval;
 791         }
 792         chip->asic_code = val == 0 ? 1 : 0;
 793
 794         if (chip->asic_code) {
 795                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 796                 if (retval != STATUS_SUCCESS) {
 797                         rtsx_trace(chip);
 798                         return STATUS_FAIL;
 799                 }
 800
 801                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 802                         reg);
 803                 chip->ic_version = (reg >> 4) & 0x07;
 804                 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
 805
 806         } else {
 807                 retval = rtsx_read_register(chip, 0xFE80, &val);
 808                 if (retval) {
 809                         rtsx_trace(chip);
 810                         return retval;
 811                 }
 812                 chip->ic_version = val;
 813                 chip->phy_debug_mode = 0;
 814         }
 815
 816         retval = rtsx_read_register(chip, PDINFO, &val);
 817         if (retval) {
 818                 rtsx_trace(chip);
 819                 return retval;
 820         }
 821         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 822         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 823
 824         retval = rtsx_read_register(chip, 0xFE50, &val);
 825         if (retval) {
 826                 rtsx_trace(chip);
 827                 return retval;
 828         }
 829         chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
 830
 831         rtsx_read_config_byte(chip, 0x0E, &val);
 832         if (val & 0x80)
 833                 SET_SDIO_EXIST(chip);
 834         else
 835                 CLR_SDIO_EXIST(chip);
 836
 837         if (chip->use_hw_setting) {
 838                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 839                 if (retval) {
 840                         rtsx_trace(chip);
 841                         return retval;
 842                 }
 843                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 844         }
 845
 846         return STATUS_SUCCESS;
 847 }
 848
 849 static int rts5288_init(struct rtsx_chip *chip)
 850 {
 851         int retval;
 852         u8 val = 0, max_func;
 853         u32 lval = 0;
 854
 855         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 856         if (retval) {
 857                 rtsx_trace(chip);
 858                 return retval;
 859         }
 860         retval = rtsx_read_register(chip, CLK_SEL, &val);
 861         if (retval) {
 862                 rtsx_trace(chip);
 863                 return retval;
 864         }
 865         chip->asic_code = val == 0 ? 1 : 0;
 866
 867         chip->ic_version = 0;
 868         chip->phy_debug_mode = 0;
 869
 870         retval = rtsx_read_register(chip, PDINFO, &val);
 871         if (retval) {
 872                 rtsx_trace(chip);
 873                 return retval;
 874         }
 875         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 876         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 877
 878         retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
 879         if (retval) {
 880                 rtsx_trace(chip);
 881                 return retval;
 882         }
 883         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 884         chip->baro_pkg = val & 0x04 ? QFN : LQFP;
 885
 886         retval = rtsx_read_register(chip, 0xFE5A, &val);
 887         if (retval) {
 888                 rtsx_trace(chip);
 889                 return retval;
 890         }
 891         chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
 892
 893         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 894         if (retval != STATUS_SUCCESS) {
 895                 rtsx_trace(chip);
 896                 return STATUS_FAIL;
 897         }
 898
 899         max_func = (u8)((lval >> 29) & 0x07);
 900         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 901         if (max_func == 0x02)
 902                 SET_SDIO_EXIST(chip);
 903         else
 904                 CLR_SDIO_EXIST(chip);
 905
 906         if (chip->use_hw_setting) {
 907                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 908                 if (retval) {
 909                         rtsx_trace(chip);
 910                         return retval;
 911                 }
 912                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 913
 914                 if (CHECK_BARO_PKG(chip, LQFP))
 915                         chip->lun_mode = SD_MS_1LUN;
 916                 else
 917                         chip->lun_mode = DEFAULT_SINGLE;
 918         }
 919
 920         return STATUS_SUCCESS;
 921 }
 922
 923 int rtsx_init_chip(struct rtsx_chip *chip)
 924 {
 925         struct sd_info *sd_card = &chip->sd_card;
 926         struct xd_info *xd_card = &chip->xd_card;
 927         struct ms_info *ms_card = &chip->ms_card;
 928         int retval;
 929         unsigned int i;
 930
 931         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 932                 chip->vendor_id, chip->product_id);
 933
 934         chip->ic_version = 0;
 935
 936 #ifdef _MSG_TRACE
 937         chip->msg_idx = 0;
 938 #endif
 939
 940         memset(xd_card, 0, sizeof(struct xd_info));
 941         memset(sd_card, 0, sizeof(struct sd_info));
 942         memset(ms_card, 0, sizeof(struct ms_info));
 943
 944         chip->xd_reset_counter = 0;
 945         chip->sd_reset_counter = 0;
 946         chip->ms_reset_counter = 0;
 947
 948         chip->xd_show_cnt = MAX_SHOW_CNT;
 949         chip->sd_show_cnt = MAX_SHOW_CNT;
 950         chip->ms_show_cnt = MAX_SHOW_CNT;
 951
 952         chip->sd_io = 0;
 953         chip->auto_delink_cnt = 0;
 954         chip->auto_delink_allowed = 1;
 955         rtsx_set_stat(chip, RTSX_STAT_INIT);
 956
 957         chip->aspm_enabled = 0;
 958         chip->chip_insert_with_sdio = 0;
 959         chip->sdio_aspm = 0;
 960         chip->sdio_idle = 0;
 961         chip->sdio_counter = 0;
 962         chip->cur_card = 0;
 963         chip->phy_debug_mode = 0;
 964         chip->sdio_func_exist = 0;
 965         memset(chip->sdio_raw_data, 0, 12);
 966
 967         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 968                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 969                 chip->rw_fail_cnt[i] = 0;
 970         }
 971
 972         if (!check_sd_speed_prior(chip->sd_speed_prior))
 973                 chip->sd_speed_prior = 0x01040203;
 974
 975         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 976                 chip->sd_speed_prior);
 977
 978         if (!check_sd_current_prior(chip->sd_current_prior))
 979                 chip->sd_current_prior = 0x00010203;
 980
 981         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 982                 chip->sd_current_prior);
 983
 984         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 985                 chip->sd_ddr_tx_phase = 0;
 986
 987         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 988                 chip->mmc_ddr_tx_phase = 0;
 989
 990         retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
 991         if (retval) {
 992                 rtsx_trace(chip);
 993                 return retval;
 994         }
 995         wait_timeout(200);
 996         retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
 997         if (retval) {
 998                 rtsx_trace(chip);
 999                 return retval;
1000         }
1001         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
1002                 chip->use_hw_setting);
1003
1004         if (CHECK_PID(chip, 0x5208)) {
1005                 retval = rts5208_init(chip);
1006                 if (retval != STATUS_SUCCESS) {
1007                         rtsx_trace(chip);
1008                         return STATUS_FAIL;
1009                 }
1010
1011         } else if (CHECK_PID(chip, 0x5288)) {
1012                 retval = rts5288_init(chip);
1013                 if (retval != STATUS_SUCCESS) {
1014                         rtsx_trace(chip);
1015                         return STATUS_FAIL;
1016                 }
1017         }
1018
1019         if (chip->ss_en == 2)
1020                 chip->ss_en = 0;
1021
1022         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
1023         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
1024         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
1025                 chip->phy_debug_mode);
1026         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
1027                 chip->aux_pwr_exist);
1028         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
1029                 chip->sdio_func_exist);
1030         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
1031                 chip->hw_bypass_sd);
1032         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
1033                 chip->aspm_l0s_l1_en);
1034         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
1035         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
1036                 chip->auto_delink_en);
1037         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
1038         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
1039
1040         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1041                 chip->card2lun[SD_CARD] = 0;
1042                 chip->card2lun[MS_CARD] = 1;
1043                 chip->card2lun[XD_CARD] = 0xFF;
1044                 chip->lun2card[0] = SD_CARD;
1045                 chip->lun2card[1] = MS_CARD;
1046                 chip->max_lun = 1;
1047                 SET_SDIO_IGNORED(chip);
1048         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1049                 chip->card2lun[SD_CARD] = 0;
1050                 chip->card2lun[MS_CARD] = 0;
1051                 chip->card2lun[XD_CARD] = 0xFF;
1052                 chip->lun2card[0] = SD_CARD | MS_CARD;
1053                 chip->max_lun = 0;
1054         } else {
1055                 chip->card2lun[XD_CARD] = 0;
1056                 chip->card2lun[SD_CARD] = 0;
1057                 chip->card2lun[MS_CARD] = 0;
1058                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1059                 chip->max_lun = 0;
1060         }
1061
1062         retval = rtsx_reset_chip(chip);
1063         if (retval != STATUS_SUCCESS) {
1064                 rtsx_trace(chip);
1065                 return STATUS_FAIL;
1066         }
1067
1068         return STATUS_SUCCESS;
1069 }
1070
1071 void rtsx_release_chip(struct rtsx_chip *chip)
1072 {
1073         xd_free_l2p_tbl(chip);
1074         ms_free_l2p_tbl(chip);
1075         chip->card_exist = 0;
1076         chip->card_ready = 0;
1077 }
1078
1079 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1080 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1081 {
1082         if (chip->card_exist && chip->blink_led) {
1083                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1084                         chip->led_toggle_counter++;
1085                 } else {
1086                         chip->led_toggle_counter = 0;
1087                         toggle_gpio(chip, LED_GPIO);
1088                 }
1089         }
1090 }
1091 #endif
1092
1093 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1094 {
1095         bool reg_changed, maybe_support_aspm;
1096         u32 tmp = 0;
1097         u8 reg0 = 0, reg1 = 0;
1098
1099         maybe_support_aspm = false;
1100         reg_changed = false;
1101         rtsx_read_config_byte(chip, LCTLR, &reg0);
1102         if (chip->aspm_level[0] != reg0) {
1103                 reg_changed = true;
1104                 chip->aspm_level[0] = reg0;
1105         }
1106         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1107                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1108                 reg1 = (u8)tmp;
1109                 if (chip->aspm_level[1] != reg1) {
1110                         reg_changed = true;
1111                         chip->aspm_level[1] = reg1;
1112                 }
1113
1114                 if ((reg0 & 0x03) && (reg1 & 0x03))
1115                         maybe_support_aspm = true;
1116
1117         } else {
1118                 if (reg0 & 0x03)
1119                         maybe_support_aspm = true;
1120         }
1121
1122         if (reg_changed) {
1123                 if (maybe_support_aspm)
1124                         chip->aspm_l0s_l1_en = 0x03;
1125
1126                 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1127                         chip->aspm_level[0], chip->aspm_level[1]);
1128
1129                 if (chip->aspm_l0s_l1_en) {
1130                         chip->aspm_enabled = 1;
1131                 } else {
1132                         chip->aspm_enabled = 0;
1133                         chip->sdio_aspm = 0;
1134                 }
1135                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1136                                     0x30 | chip->aspm_level[0] |
1137                                     (chip->aspm_level[1] << 2));
1138         }
1139 }
1140
1141 static void rtsx_manage_ocp(struct rtsx_chip *chip)
1142 {
1143 #ifdef SUPPORT_OCP
1144         if (!chip->ocp_int)
1145                 return;
1146
1147         rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1148
1149         if (chip->card_exist & SD_CARD)
1150                 sd_power_off_card3v3(chip);
1151         else if (chip->card_exist & MS_CARD)
1152                 ms_power_off_card3v3(chip);
1153         else if (chip->card_exist & XD_CARD)
1154                 xd_power_off_card3v3(chip);
1155
1156         chip->ocp_int = 0;
1157 #endif
1158 }
1159
1160 static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
1161 {
1162 #ifdef SUPPORT_SD_LOCK
1163         struct sd_info *sd_card = &chip->sd_card;
1164         u8 val;
1165
1166         if (!sd_card->sd_erase_status)
1167                 return;
1168
1169         if (chip->card_exist & SD_CARD) {
1170                 rtsx_read_register(chip, 0xFD30, &val);
1171                 if (val & 0x02) {
1172                         sd_card->sd_erase_status = SD_NOT_ERASE;
1173                         sd_card->sd_lock_notify = 1;
1174                         chip->need_reinit |= SD_CARD;
1175                 }
1176         } else {
1177                 sd_card->sd_erase_status = SD_NOT_ERASE;
1178         }
1179 #endif
1180 }
1181
1182 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1183 {
1184         u32 val;
1185
1186         if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1187                 return false;
1188
1189         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1190                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1191                 if (val & 0x07)
1192                         return false;
1193         }
1194
1195         return true;
1196 }
1197
1198 static void rtsx_manage_ss(struct rtsx_chip *chip)
1199 {
1200         if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1201                 return;
1202
1203         if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1204                 chip->ss_counter = 0;
1205                 return;
1206         }
1207
1208         if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1209                 chip->ss_counter++;
1210         else
1211                 rtsx_exclusive_enter_ss(chip);
1212 }
1213
1214 static void rtsx_manage_aspm(struct rtsx_chip *chip)
1215 {
1216         u8 data;
1217
1218         if (!CHECK_PID(chip, 0x5208))
1219                 return;
1220
1221         rtsx_monitor_aspm_config(chip);
1222
1223 #ifdef SUPPORT_SDIO_ASPM
1224         if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1225             !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1226                 return;
1227
1228         if (chip->sd_io) {
1229                 dynamic_configure_sdio_aspm(chip);
1230                 return;
1231         }
1232
1233         if (chip->sdio_aspm)
1234                 return;
1235
1236         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1237         data = 0x30 | (chip->aspm_level[1] << 2);
1238         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1239         chip->sdio_aspm = 1;
1240 #endif
1241 }
1242
1243 static void rtsx_manage_idle(struct rtsx_chip *chip)
1244 {
1245         if (chip->idle_counter < IDLE_MAX_COUNT) {
1246                 chip->idle_counter++;
1247                 return;
1248         }
1249
1250         if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1251                 return;
1252
1253         dev_dbg(rtsx_dev(chip), "Idle state!\n");
1254         rtsx_set_stat(chip, RTSX_STAT_IDLE);
1255
1256 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1257         chip->led_toggle_counter = 0;
1258 #endif
1259         rtsx_force_power_on(chip, SSC_PDCTL);
1260
1261         turn_off_led(chip, LED_GPIO);
1262
1263         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1264                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1265 }
1266
1267 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1268 {
1269 #ifdef SUPPORT_OCP
1270         u8 sd_oc, ms_oc;
1271
1272         sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1273         ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1274
1275         if (sd_oc || ms_oc)
1276                 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1277                         chip->ocp_stat);
1278
1279         if (sd_oc && (chip->card_exist & SD_CARD)) {
1280                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1281                 card_power_off(chip, SD_CARD);
1282                 chip->card_fail |= SD_CARD;
1283         }
1284
1285         if (ms_oc && (chip->card_exist & MS_CARD)) {
1286                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1287                 card_power_off(chip, MS_CARD);
1288                 chip->card_fail |= MS_CARD;
1289         }
1290 #endif
1291 }
1292
1293 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1294 {
1295 #ifdef SUPPORT_OCP
1296         if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1297                 return;
1298
1299         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1300                 chip->ocp_stat);
1301
1302         if (chip->card_exist & SD_CARD) {
1303                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1304                 chip->card_fail |= SD_CARD;
1305         } else if (chip->card_exist & MS_CARD) {
1306                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1307                 chip->card_fail |= MS_CARD;
1308         } else if (chip->card_exist & XD_CARD) {
1309                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1310                 chip->card_fail |= XD_CARD;
1311         }
1312         card_power_off(chip, SD_CARD);
1313 #endif
1314 }
1315
1316 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1317                                int stage3_cnt)
1318 {
1319         u8 val;
1320
1321         rtsx_set_stat(chip, RTSX_STAT_DELINK);
1322
1323         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1324                 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1325
1326         if (chip->card_exist)
1327                 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1328         else
1329                 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1330
1331         if (enter_L1)
1332                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1333
1334         if (chip->card_exist)
1335                 val = 0x02;
1336         else
1337                 val = 0x0A;
1338
1339         rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1340
1341         if (enter_L1)
1342                 rtsx_enter_L1(chip);
1343
1344         if (chip->card_exist)
1345                 chip->auto_delink_cnt = stage3_cnt + 1;
1346 }
1347
1348 static void rtsx_delink_stage(struct rtsx_chip *chip)
1349 {
1350         int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1351         int enter_L1;
1352
1353         if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1354             chip->card_ready || chip->card_ejected || chip->sd_io) {
1355                 chip->auto_delink_cnt = 0;
1356                 return;
1357         }
1358
1359         enter_L1 = chip->auto_delink_in_L1 &&
1360                 (chip->aspm_l0s_l1_en || chip->ss_en);
1361
1362         delink_stage1_cnt = chip->delink_stage1_step;
1363         delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1364         delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1365
1366         if (chip->auto_delink_cnt > delink_stage3_cnt)
1367                 return;
1368
1369         if (chip->auto_delink_cnt == delink_stage1_cnt)
1370                 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1371
1372         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1373                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1374
1375                 if (enter_L1)
1376                         rtsx_exit_L1(chip);
1377
1378                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1379                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1380
1381                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1382         }
1383
1384         chip->auto_delink_cnt++;
1385 }
1386
1387 void rtsx_polling_func(struct rtsx_chip *chip)
1388 {
1389         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1390                 return;
1391
1392         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1393                 goto delink_stage;
1394
1395         if (chip->polling_config) {
1396                 u8 val;
1397
1398                 rtsx_read_config_byte(chip, 0, &val);
1399         }
1400
1401         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1402                 return;
1403
1404         rtsx_manage_ocp(chip);
1405
1406         rtsx_manage_sd_lock(chip);
1407
1408         rtsx_init_cards(chip);
1409
1410         rtsx_manage_ss(chip);
1411
1412         rtsx_manage_aspm(chip);
1413
1414         rtsx_manage_idle(chip);
1415
1416         switch (rtsx_get_stat(chip)) {
1417         case RTSX_STAT_RUN:
1418 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1419                 rtsx_blink_led(chip);
1420 #endif
1421                 do_remaining_work(chip);
1422                 break;
1423
1424         case RTSX_STAT_IDLE:
1425                 if (chip->sd_io && !chip->sd_int)
1426                         try_to_switch_sdio_ctrl(chip);
1427
1428                 rtsx_enable_aspm(chip);
1429                 break;
1430
1431         default:
1432                 break;
1433         }
1434
1435         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1436                 rtsx_manage_2lun_mode(chip);
1437         else
1438                 rtsx_manage_1lun_mode(chip);
1439
1440 delink_stage:
1441         rtsx_delink_stage(chip);
1442 }
1443
1444 /**
1445  * rtsx_stop_cmd - stop command transfer and DMA transfer
1446  * @chip: Realtek's card reader chip
1447  * @card: flash card type
1448  *
1449  * Stop command transfer and DMA transfer.
1450  * This function is called in error handler.
1451  */
1452 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1453 {
1454         int i;
1455
1456         for (i = 0; i <= 8; i++) {
1457                 int addr = RTSX_HCBAR + i * 4;
1458                 u32 reg;
1459
1460                 reg = rtsx_readl(chip, addr);
1461                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1462         }
1463         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1464         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1465
1466         for (i = 0; i < 16; i++) {
1467                 u16 addr = 0xFE20 + (u16)i;
1468                 u8 val;
1469
1470                 rtsx_read_register(chip, addr, &val);
1471                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1472         }
1473
1474         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1475         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1476 }
1477
1478 #define MAX_RW_REG_CNT          1024
1479
1480 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1481 {
1482         int i;
1483         u32 val = 3 << 30;
1484
1485         val |= (u32)(addr & 0x3FFF) << 16;
1486         val |= (u32)mask << 8;
1487         val |= (u32)data;
1488
1489         rtsx_writel(chip, RTSX_HAIMR, val);
1490
1491         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1492                 val = rtsx_readl(chip, RTSX_HAIMR);
1493                 if ((val & BIT(31)) == 0) {
1494                         if (data != (u8)val) {
1495                                 rtsx_trace(chip);
1496                                 return STATUS_FAIL;
1497                         }
1498
1499                         return STATUS_SUCCESS;
1500                 }
1501         }
1502
1503         rtsx_trace(chip);
1504         return STATUS_TIMEDOUT;
1505 }
1506
1507 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1508 {
1509         u32 val = 2 << 30;
1510         int i;
1511
1512         if (data)
1513                 *data = 0;
1514
1515         val |= (u32)(addr & 0x3FFF) << 16;
1516
1517         rtsx_writel(chip, RTSX_HAIMR, val);
1518
1519         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1520                 val = rtsx_readl(chip, RTSX_HAIMR);
1521                 if ((val & BIT(31)) == 0)
1522                         break;
1523         }
1524
1525         if (i >= MAX_RW_REG_CNT) {
1526                 rtsx_trace(chip);
1527                 return STATUS_TIMEDOUT;
1528         }
1529
1530         if (data)
1531                 *data = (u8)(val & 0xFF);
1532
1533         return STATUS_SUCCESS;
1534 }
1535
1536 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1537                       u32 val)
1538 {
1539         int retval;
1540         u8 mode = 0, tmp;
1541         int i;
1542
1543         for (i = 0; i < 4; i++) {
1544                 if (mask & 0xFF) {
1545                         retval = rtsx_write_register(chip, CFGDATA0 + i,
1546                                                      0xFF,
1547                                                      (u8)(val & mask & 0xFF));
1548                         if (retval) {
1549                                 rtsx_trace(chip);
1550                                 return retval;
1551                         }
1552                         mode |= (1 << i);
1553                 }
1554                 mask >>= 8;
1555                 val >>= 8;
1556         }
1557
1558         if (mode) {
1559                 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1560                 if (retval) {
1561                         rtsx_trace(chip);
1562                         return retval;
1563                 }
1564                 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1565                                              (u8)(addr >> 8));
1566                 if (retval) {
1567                         rtsx_trace(chip);
1568                         return retval;
1569                 }
1570
1571                 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1572                                              0x80 | mode |
1573                                              ((func_no & 0x03) << 4));
1574                 if (retval) {
1575                         rtsx_trace(chip);
1576                         return retval;
1577                 }
1578
1579                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1580                         retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1581                         if (retval) {
1582                                 rtsx_trace(chip);
1583                                 return retval;
1584                         }
1585                         if ((tmp & 0x80) == 0)
1586                                 break;
1587                 }
1588         }
1589
1590         return STATUS_SUCCESS;
1591 }
1592
1593 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1594 {
1595         int retval;
1596         int i;
1597         u8 tmp;
1598         u32 data = 0;
1599
1600         retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1601         if (retval) {
1602                 rtsx_trace(chip);
1603                 return retval;
1604         }
1605         retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1606         if (retval) {
1607                 rtsx_trace(chip);
1608                 return retval;
1609         }
1610         retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1611                                      0x80 | ((func_no & 0x03) << 4));
1612         if (retval) {
1613                 rtsx_trace(chip);
1614                 return retval;
1615         }
1616
1617         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1618                 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1619                 if (retval) {
1620                         rtsx_trace(chip);
1621                         return retval;
1622                 }
1623                 if ((tmp & 0x80) == 0)
1624                         break;
1625         }
1626
1627         for (i = 0; i < 4; i++) {
1628                 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1629                 if (retval) {
1630                         rtsx_trace(chip);
1631                         return retval;
1632                 }
1633                 data |= (u32)tmp << (i * 8);
1634         }
1635
1636         if (val)
1637                 *val = data;
1638
1639         return STATUS_SUCCESS;
1640 }
1641
1642 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1643                        int len)
1644 {
1645         u32 *data, *mask;
1646         u16 offset = addr % 4;
1647         u16 aligned_addr = addr - offset;
1648         int dw_len, i, j;
1649         int retval;
1650
1651         if (!buf) {
1652                 rtsx_trace(chip);
1653                 return STATUS_NOMEM;
1654         }
1655
1656         if ((len + offset) % 4)
1657                 dw_len = (len + offset) / 4 + 1;
1658         else
1659                 dw_len = (len + offset) / 4;
1660
1661         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1662
1663         data = vzalloc(dw_len * 4);
1664         if (!data) {
1665                 rtsx_trace(chip);
1666                 return STATUS_NOMEM;
1667         }
1668
1669         mask = vzalloc(dw_len * 4);
1670         if (!mask) {
1671                 vfree(data);
1672                 rtsx_trace(chip);
1673                 return STATUS_NOMEM;
1674         }
1675
1676         j = 0;
1677         for (i = 0; i < len; i++) {
1678                 mask[j] |= 0xFF << (offset * 8);
1679                 data[j] |= buf[i] << (offset * 8);
1680                 if (++offset == 4) {
1681                         j++;
1682                         offset = 0;
1683                 }
1684         }
1685
1686         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1687                              dw_len * 4);
1688         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1689                              dw_len * 4);
1690
1691         for (i = 0; i < dw_len; i++) {
1692                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1693                                            mask[i], data[i]);
1694                 if (retval != STATUS_SUCCESS) {
1695                         vfree(data);
1696                         vfree(mask);
1697                         rtsx_trace(chip);
1698                         return STATUS_FAIL;
1699                 }
1700         }
1701
1702         vfree(data);
1703         vfree(mask);
1704
1705         return STATUS_SUCCESS;
1706 }
1707
1708 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1709                       int len)
1710 {
1711         u32 *data;
1712         u16 offset = addr % 4;
1713         u16 aligned_addr = addr - offset;
1714         int dw_len, i, j;
1715         int retval;
1716
1717         if ((len + offset) % 4)
1718                 dw_len = (len + offset) / 4 + 1;
1719         else
1720                 dw_len = (len + offset) / 4;
1721
1722         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1723
1724         data = vmalloc(dw_len * 4);
1725         if (!data) {
1726                 rtsx_trace(chip);
1727                 return STATUS_NOMEM;
1728         }
1729
1730         for (i = 0; i < dw_len; i++) {
1731                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1732                                           data + i);
1733                 if (retval != STATUS_SUCCESS) {
1734                         vfree(data);
1735                         rtsx_trace(chip);
1736                         return STATUS_FAIL;
1737                 }
1738         }
1739
1740         if (buf) {
1741                 j = 0;
1742
1743                 for (i = 0; i < len; i++) {
1744                         buf[i] = (u8)(data[j] >> (offset * 8));
1745                         if (++offset == 4) {
1746                                 j++;
1747                                 offset = 0;
1748                         }
1749                 }
1750         }
1751
1752         vfree(data);
1753
1754         return STATUS_SUCCESS;
1755 }
1756
1757 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1758 {
1759         int retval;
1760         bool finished = false;
1761         int i;
1762         u8 tmp;
1763
1764         retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1765         if (retval) {
1766                 rtsx_trace(chip);
1767                 return retval;
1768         }
1769         retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1770         if (retval) {
1771                 rtsx_trace(chip);
1772                 return retval;
1773         }
1774         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1775         if (retval) {
1776                 rtsx_trace(chip);
1777                 return retval;
1778         }
1779         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1780         if (retval) {
1781                 rtsx_trace(chip);
1782                 return retval;
1783         }
1784
1785         for (i = 0; i < 100000; i++) {
1786                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1787                 if (retval) {
1788                         rtsx_trace(chip);
1789                         return retval;
1790                 }
1791                 if (!(tmp & 0x80)) {
1792                         finished = true;
1793                         break;
1794                 }
1795         }
1796
1797         if (!finished) {
1798                 rtsx_trace(chip);
1799                 return STATUS_FAIL;
1800         }
1801
1802         return STATUS_SUCCESS;
1803 }
1804
1805 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1806 {
1807         int retval;
1808         bool finished = false;
1809         int i;
1810         u16 data = 0;
1811         u8 tmp;
1812
1813         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1814         if (retval) {
1815                 rtsx_trace(chip);
1816                 return retval;
1817         }
1818         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1819         if (retval) {
1820                 rtsx_trace(chip);
1821                 return retval;
1822         }
1823
1824         for (i = 0; i < 100000; i++) {
1825                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1826                 if (retval) {
1827                         rtsx_trace(chip);
1828                         return retval;
1829                 }
1830                 if (!(tmp & 0x80)) {
1831                         finished = true;
1832                         break;
1833                 }
1834         }
1835
1836         if (!finished) {
1837                 rtsx_trace(chip);
1838                 return STATUS_FAIL;
1839         }
1840
1841         retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1842         if (retval) {
1843                 rtsx_trace(chip);
1844                 return retval;
1845         }
1846         data = tmp;
1847         retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1848         if (retval) {
1849                 rtsx_trace(chip);
1850                 return retval;
1851         }
1852         data |= (u16)tmp << 8;
1853
1854         if (val)
1855                 *val = data;
1856
1857         return STATUS_SUCCESS;
1858 }
1859
1860 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1861 {
1862         int retval;
1863         int i;
1864         u8 data = 0;
1865
1866         retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1867         if (retval) {
1868                 rtsx_trace(chip);
1869                 return retval;
1870         }
1871
1872         for (i = 0; i < 100; i++) {
1873                 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1874                 if (retval) {
1875                         rtsx_trace(chip);
1876                         return retval;
1877                 }
1878                 if (!(data & 0x80))
1879                         break;
1880                 udelay(1);
1881         }
1882
1883         if (data & 0x80) {
1884                 rtsx_trace(chip);
1885                 return STATUS_TIMEDOUT;
1886         }
1887
1888         retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1889         if (retval) {
1890                 rtsx_trace(chip);
1891                 return retval;
1892         }
1893         if (val)
1894                 *val = data;
1895
1896         return STATUS_SUCCESS;
1897 }
1898
1899 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1900 {
1901         int retval;
1902         int i, j;
1903         u8 data = 0, tmp = 0xFF;
1904
1905         for (i = 0; i < 8; i++) {
1906                 if (val & (u8)(1 << i))
1907                         continue;
1908
1909                 tmp &= (~(u8)(1 << i));
1910                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1911
1912                 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1913                 if (retval) {
1914                         rtsx_trace(chip);
1915                         return retval;
1916                 }
1917                 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1918                                              0xA0 | addr);
1919                 if (retval) {
1920                         rtsx_trace(chip);
1921                         return retval;
1922                 }
1923
1924                 for (j = 0; j < 100; j++) {
1925                         retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1926                         if (retval) {
1927                                 rtsx_trace(chip);
1928                                 return retval;
1929                         }
1930                         if (!(data & 0x80))
1931                                 break;
1932                         wait_timeout(3);
1933                 }
1934
1935                 if (data & 0x80) {
1936                         rtsx_trace(chip);
1937                         return STATUS_TIMEDOUT;
1938                 }
1939
1940                 wait_timeout(5);
1941         }
1942
1943         return STATUS_SUCCESS;
1944 }
1945
1946 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1947 {
1948         int retval;
1949         u16 value;
1950
1951         retval = rtsx_read_phy_register(chip, reg, &value);
1952         if (retval != STATUS_SUCCESS) {
1953                 rtsx_trace(chip);
1954                 return STATUS_FAIL;
1955         }
1956
1957         if (value & (1 << bit)) {
1958                 value &= ~(1 << bit);
1959                 retval = rtsx_write_phy_register(chip, reg, value);
1960                 if (retval != STATUS_SUCCESS) {
1961                         rtsx_trace(chip);
1962                         return STATUS_FAIL;
1963                 }
1964         }
1965
1966         return STATUS_SUCCESS;
1967 }
1968
1969 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1970 {
1971         int retval;
1972         u16 value;
1973
1974         retval = rtsx_read_phy_register(chip, reg, &value);
1975         if (retval != STATUS_SUCCESS) {
1976                 rtsx_trace(chip);
1977                 return STATUS_FAIL;
1978         }
1979
1980         if ((value & (1 << bit)) == 0) {
1981                 value |= (1 << bit);
1982                 retval = rtsx_write_phy_register(chip, reg, value);
1983                 if (retval != STATUS_SUCCESS) {
1984                         rtsx_trace(chip);
1985                         return STATUS_FAIL;
1986                 }
1987         }
1988
1989         return STATUS_SUCCESS;
1990 }
1991
1992 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1993 {
1994         u32 ultmp;
1995
1996         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1997                 chip->product_id, dstate);
1998
1999         if (CHK_SDIO_EXIST(chip)) {
2000                 u8 func_no;
2001
2002                 if (CHECK_PID(chip, 0x5288))
2003                         func_no = 2;
2004                 else
2005                         func_no = 1;
2006
2007                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
2008                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
2009                         (int)func_no, ultmp);
2010                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
2011         }
2012
2013         rtsx_write_config_byte(chip, 0x44, dstate);
2014         rtsx_write_config_byte(chip, 0x45, 0);
2015 }
2016
2017 void rtsx_enter_L1(struct rtsx_chip *chip)
2018 {
2019         rtsx_handle_pm_dstate(chip, 2);
2020 }
2021
2022 void rtsx_exit_L1(struct rtsx_chip *chip)
2023 {
2024         rtsx_write_config_byte(chip, 0x44, 0);
2025         rtsx_write_config_byte(chip, 0x45, 0);
2026 }
2027
2028 void rtsx_enter_ss(struct rtsx_chip *chip)
2029 {
2030         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
2031
2032         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2033
2034         if (chip->power_down_in_ss) {
2035                 rtsx_power_off_card(chip);
2036                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2037         }
2038
2039         if (CHK_SDIO_EXIST(chip))
2040                 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2041                                   0xC0, 0xFF00, 0x0100);
2042
2043         if (chip->auto_delink_en) {
2044                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
2045         } else {
2046                 if (!chip->phy_debug_mode) {
2047                         u32 tmp;
2048
2049                         tmp = rtsx_readl(chip, RTSX_BIER);
2050                         tmp |= CARD_INT;
2051                         rtsx_writel(chip, RTSX_BIER, tmp);
2052                 }
2053
2054                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
2055         }
2056
2057         rtsx_enter_L1(chip);
2058
2059         RTSX_CLR_DELINK(chip);
2060         rtsx_set_stat(chip, RTSX_STAT_SS);
2061 }
2062
2063 void rtsx_exit_ss(struct rtsx_chip *chip)
2064 {
2065         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
2066
2067         rtsx_exit_L1(chip);
2068
2069         if (chip->power_down_in_ss) {
2070                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
2071                 udelay(1000);
2072         }
2073
2074         if (RTSX_TST_DELINK(chip)) {
2075                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2076                 rtsx_reinit_cards(chip, 1);
2077                 RTSX_CLR_DELINK(chip);
2078         } else if (chip->power_down_in_ss) {
2079                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2080                 rtsx_reinit_cards(chip, 0);
2081         }
2082 }
2083
2084 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
2085 {
2086         u32 status, int_enable;
2087         bool exit_ss = false;
2088 #ifdef SUPPORT_OCP
2089         u32 ocp_int = 0;
2090
2091         ocp_int = OC_INT;
2092 #endif
2093
2094         if (chip->ss_en) {
2095                 chip->ss_counter = 0;
2096                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
2097                         exit_ss = true;
2098                         rtsx_exit_L1(chip);
2099                         rtsx_set_stat(chip, RTSX_STAT_RUN);
2100                 }
2101         }
2102
2103         int_enable = rtsx_readl(chip, RTSX_BIER);
2104         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
2105
2106         if (((chip->int_reg & int_enable) == 0) ||
2107             (chip->int_reg == 0xFFFFFFFF))
2108                 return STATUS_FAIL;
2109
2110         status = chip->int_reg &= (int_enable | 0x7FFFFF);
2111
2112         if (status & CARD_INT) {
2113                 chip->auto_delink_cnt = 0;
2114
2115                 if (status & SD_INT) {
2116                         if (status & SD_EXIST) {
2117                                 set_bit(SD_NR, &chip->need_reset);
2118                         } else {
2119                                 set_bit(SD_NR, &chip->need_release);
2120                                 chip->sd_reset_counter = 0;
2121                                 chip->sd_show_cnt = 0;
2122                                 clear_bit(SD_NR, &chip->need_reset);
2123                         }
2124                 } else {
2125                         /*
2126                          * If multi-luns, it's possible that
2127                          * when plugging/unplugging one card
2128                          * there is another card which still
2129                          * exists in the slot. In this case,
2130                          * all existed cards should be reset.
2131                          */
2132                         if (exit_ss && (status & SD_EXIST))
2133                                 set_bit(SD_NR, &chip->need_reinit);
2134                 }
2135                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2136                         if (status & XD_INT) {
2137                                 if (status & XD_EXIST) {
2138                                         set_bit(XD_NR, &chip->need_reset);
2139                                 } else {
2140                                         set_bit(XD_NR, &chip->need_release);
2141                                         chip->xd_reset_counter = 0;
2142                                         chip->xd_show_cnt = 0;
2143                                         clear_bit(XD_NR, &chip->need_reset);
2144                                 }
2145                         } else {
2146                                 if (exit_ss && (status & XD_EXIST))
2147                                         set_bit(XD_NR, &chip->need_reinit);
2148                         }
2149                 }
2150                 if (status & MS_INT) {
2151                         if (status & MS_EXIST) {
2152                                 set_bit(MS_NR, &chip->need_reset);
2153                         } else {
2154                                 set_bit(MS_NR, &chip->need_release);
2155                                 chip->ms_reset_counter = 0;
2156                                 chip->ms_show_cnt = 0;
2157                                 clear_bit(MS_NR, &chip->need_reset);
2158                         }
2159                 } else {
2160                         if (exit_ss && (status & MS_EXIST))
2161                                 set_bit(MS_NR, &chip->need_reinit);
2162                 }
2163         }
2164
2165 #ifdef SUPPORT_OCP
2166         chip->ocp_int = ocp_int & status;
2167 #endif
2168
2169         if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2170                 chip->int_reg &= ~(u32)DATA_DONE_INT;
2171
2172         return STATUS_SUCCESS;
2173 }
2174
2175 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2176 {
2177         int retval;
2178
2179         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2180
2181         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2182
2183         retval = rtsx_force_power_on(chip, SSC_PDCTL);
2184         if (retval != STATUS_SUCCESS)
2185                 return;
2186
2187         rtsx_release_cards(chip);
2188         rtsx_disable_bus_int(chip);
2189         turn_off_led(chip, LED_GPIO);
2190
2191 #ifdef HW_AUTO_SWITCH_SD_BUS
2192         if (chip->sd_io) {
2193                 chip->sdio_in_charge = 1;
2194                 if (CHECK_PID(chip, 0x5208)) {
2195                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2196                         /* Enable sdio_bus_auto_switch */
2197                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2198                 } else if (CHECK_PID(chip, 0x5288)) {
2199                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2200                         /* Enable sdio_bus_auto_switch */
2201                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2202                 }
2203         }
2204 #endif
2205
2206         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2207                 /* u_force_clkreq_0 */
2208                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2209         }
2210
2211         if (pm_stat == PM_S1) {
2212                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2213                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2214                                     HOST_ENTER_S1);
2215         } else if (pm_stat == PM_S3) {
2216                 if (chip->s3_pwr_off_delay > 0)
2217                         wait_timeout(chip->s3_pwr_off_delay);
2218
2219                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2220                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2221                                     HOST_ENTER_S3);
2222         }
2223
2224         if (chip->do_delink_before_power_down && chip->auto_delink_en)
2225                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2226
2227         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2228
2229         chip->cur_clk = 0;
2230         chip->cur_card = 0;
2231         chip->card_exist = 0;
2232 }
2233
2234 void rtsx_enable_aspm(struct rtsx_chip *chip)
2235 {
2236         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2237                 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2238                 chip->aspm_enabled = 1;
2239
2240                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2241                         rtsx_write_phy_register(chip, 0x07, 0);
2242                 if (CHECK_PID(chip, 0x5208)) {
2243                         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2244                                             0x30 | chip->aspm_level[0]);
2245                 } else {
2246                         rtsx_write_config_byte(chip, LCTLR,
2247                                                chip->aspm_l0s_l1_en);
2248                 }
2249
2250                 if (CHK_SDIO_EXIST(chip)) {
2251                         u16 val = chip->aspm_l0s_l1_en | 0x0100;
2252
2253                         rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2254                                           0xC0, 0xFFF, val);
2255                 }
2256         }
2257 }
2258
2259 void rtsx_disable_aspm(struct rtsx_chip *chip)
2260 {
2261         if (CHECK_PID(chip, 0x5208))
2262                 rtsx_monitor_aspm_config(chip);
2263
2264         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2265                 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2266                 chip->aspm_enabled = 0;
2267
2268                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2269                         rtsx_write_phy_register(chip, 0x07, 0x0129);
2270                 if (CHECK_PID(chip, 0x5208))
2271                         rtsx_write_register(chip, ASPM_FORCE_CTL,
2272                                             0xF3, 0x30);
2273                 else
2274                         rtsx_write_config_byte(chip, LCTLR, 0x00);
2275
2276                 wait_timeout(1);
2277         }
2278 }
2279
2280 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2281 {
2282         int retval;
2283         int i, j;
2284         u16 reg_addr;
2285         u8 *ptr;
2286
2287         if (!buf) {
2288                 rtsx_trace(chip);
2289                 return STATUS_ERROR;
2290         }
2291
2292         ptr = buf;
2293         reg_addr = PPBUF_BASE2;
2294         for (i = 0; i < buf_len / 256; i++) {
2295                 rtsx_init_cmd(chip);
2296
2297                 for (j = 0; j < 256; j++)
2298                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2299
2300                 retval = rtsx_send_cmd(chip, 0, 250);
2301                 if (retval < 0) {
2302                         rtsx_trace(chip);
2303                         return STATUS_FAIL;
2304                 }
2305
2306                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2307                 ptr += 256;
2308         }
2309
2310         if (buf_len % 256) {
2311                 rtsx_init_cmd(chip);
2312
2313                 for (j = 0; j < buf_len % 256; j++)
2314                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2315
2316                 retval = rtsx_send_cmd(chip, 0, 250);
2317                 if (retval < 0) {
2318                         rtsx_trace(chip);
2319                         return STATUS_FAIL;
2320                 }
2321         }
2322
2323         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256);
2324
2325         return STATUS_SUCCESS;
2326 }
2327
2328 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2329 {
2330         int retval;
2331         int i, j;
2332         u16 reg_addr;
2333         u8 *ptr;
2334
2335         if (!buf) {
2336                 rtsx_trace(chip);
2337                 return STATUS_ERROR;
2338         }
2339
2340         ptr = buf;
2341         reg_addr = PPBUF_BASE2;
2342         for (i = 0; i < buf_len / 256; i++) {
2343                 rtsx_init_cmd(chip);
2344
2345                 for (j = 0; j < 256; j++) {
2346                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2347                                      *ptr);
2348                         ptr++;
2349                 }
2350
2351                 retval = rtsx_send_cmd(chip, 0, 250);
2352                 if (retval < 0) {
2353                         rtsx_trace(chip);
2354                         return STATUS_FAIL;
2355                 }
2356         }
2357
2358         if (buf_len % 256) {
2359                 rtsx_init_cmd(chip);
2360
2361                 for (j = 0; j < buf_len % 256; j++) {
2362                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2363                                      *ptr);
2364                         ptr++;
2365                 }
2366
2367                 retval = rtsx_send_cmd(chip, 0, 250);
2368                 if (retval < 0) {
2369                         rtsx_trace(chip);
2370                         return STATUS_FAIL;
2371                 }
2372         }
2373
2374         return STATUS_SUCCESS;
2375 }
2376
2377 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2378 {
2379         if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2380                 rtsx_trace(chip);
2381                 return STATUS_FAIL;
2382         }
2383
2384         return STATUS_SUCCESS;
2385 }
2386
2387 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2388 {
2389         int retval;
2390         u8 mask = 0;
2391
2392         if (ctl & SSC_PDCTL)
2393                 mask |= SSC_POWER_DOWN;
2394
2395 #ifdef SUPPORT_OCP
2396         if (ctl & OC_PDCTL) {
2397                 mask |= SD_OC_POWER_DOWN;
2398                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2399                         mask |= MS_OC_POWER_DOWN;
2400         }
2401 #endif
2402
2403         if (mask) {
2404                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2405                 if (retval != STATUS_SUCCESS) {
2406                         rtsx_trace(chip);
2407                         return STATUS_FAIL;
2408                 }
2409
2410                 if (CHECK_PID(chip, 0x5288))
2411                         wait_timeout(200);
2412         }
2413
2414         return STATUS_SUCCESS;
2415 }
2416
2417 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2418 {
2419         int retval;
2420         u8 mask = 0, val = 0;
2421
2422         if (ctl & SSC_PDCTL)
2423                 mask |= SSC_POWER_DOWN;
2424
2425 #ifdef SUPPORT_OCP
2426         if (ctl & OC_PDCTL) {
2427                 mask |= SD_OC_POWER_DOWN;
2428                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2429                         mask |= MS_OC_POWER_DOWN;
2430         }
2431 #endif
2432
2433         if (mask) {
2434                 val = mask;
2435                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2436                 if (retval != STATUS_SUCCESS) {
2437                         rtsx_trace(chip);
2438                         return STATUS_FAIL;
2439                 }
2440         }
2441
2442         return STATUS_SUCCESS;
2443 }