1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
11 * Larry Finger <Larry.Finger@lwfinger.net>
13 *****************************************************************************/
15 #ifndef __HALHWOUTSRC_H__
16 #define __HALHWOUTSRC_H__
18 /*--------------------------Define -------------------------------------------*/
19 #define CCK_RSSI_INIT_COUNT 5
21 #define RA_RSSI_STATE_INIT 0
22 #define RA_RSSI_STATE_SEND 1
23 #define RA_RSSI_STATE_HOLD 2
25 #define CFO_HW_RPT_2_MHZ(val) ((val << 1) + (val >> 1))
26 /* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */
28 #define AGC_DIFF_CONFIG_MP(ic, band) \
29 (odm_read_and_config_mp_##ic##_agc_tab_diff( \
30 dm, array_mp_##ic##_agc_tab_diff_##band, \
31 sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
32 #define AGC_DIFF_CONFIG_TC(ic, band) \
33 (odm_read_and_config_tc_##ic##_agc_tab_diff( \
34 dm, array_tc_##ic##_agc_tab_diff_##band, \
35 sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
37 #define AGC_DIFF_CONFIG(ic, band) \
40 AGC_DIFF_CONFIG_MP(ic, band); \
42 AGC_DIFF_CONFIG_TC(ic, band); \
45 /* ************************************************************
46 * structure and define
47 * *************************************************************/
49 struct phy_rx_agc_info {
50 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
51 u8 gain : 7, trsw : 1;
53 u8 trsw : 1, gain : 7;
57 struct phy_status_rpt_8192cd {
58 struct phy_rx_agc_info path_agc[2];
60 u8 cck_sig_qual_ofdm_pwdb_all;
61 u8 cck_agc_rpt_ofdm_cfosho_a;
62 u8 cck_rpt_b_ofdm_cfosho_b;
63 u8 rsvd_1; /*ch_corr_msb;*/
64 u8 noise_power_db_msb;
69 u8 noise_power_db_lsb;
72 u8 stream_target_csi[2];
76 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
77 u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
81 u8 r_ant_train_en : 1;
84 #else /*_BIG_ENDIAN_ */
87 u8 r_ant_train_en : 1;
91 u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
95 struct phy_status_rpt_8812 {
97 u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
98 u8 chl_num_LSB; /*channel number[7:0]*/
99 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
100 u8 chl_num_MSB : 2; /*channel number[9:8]*/
101 u8 sub_chnl : 4; /*sub-channel location[3:0]*/
102 u8 r_RFMOD : 2; /*RF mode[1:0]*/
103 #else /*_BIG_ENDIAN_ */
110 u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
111 s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 */
112 /*CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
113 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
114 /*this should be checked again
115 *because the definition of 8812 and 8814 is different
118 u8 bt_RF_ch_MSB : 2; /*8812A:2'b0, 8814A: bt rf channel keep[7:6]*/
119 #else /*_BIG_ENDIAN_*/
125 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
126 u8 ant_div_sw_a : 1; /*8812A: ant_div_sw_a, 8814A: 1'b0*/
127 u8 ant_div_sw_b : 1; /*8812A: ant_div_sw_b, 8814A: 1'b0*/
128 u8 bt_RF_ch_LSB : 6; /*8812A: 6'b0, 8814A: bt rf channel keep[5:0]*/
129 #else /*_BIG_ENDIAN_ */
134 s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
135 u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
136 u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
139 s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
140 s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
143 u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
144 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
145 u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
146 u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
147 u8 resvd_1 : 1; /*1'b0*/
148 #else /*_BIG_ENDIAN_*/
150 u8 pcts_rpt_valid : 1;
151 u8 PCTS_MSK_RPT_3 : 6;
153 s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 */
154 /* 8812A: 16'b0, 8814A: stream 3 and stream 4 RX EVM*/
157 u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 */
158 /* 8812A: stream 1 and 2 CSI, 8814A: path-C and path-D RX SNR*/
159 u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 */
160 /* path-C and path-D {TRSW, gain[6:0] }*/
163 s8 sigevm; /*signal field EVM*/
164 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
165 u8 antidx_antc : 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
166 u8 antidx_antd : 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
167 u8 dpdt_ctrl_keep : 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
168 u8 GNT_BT_keep : 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
169 #else /*_BIG_ENDIAN_*/
171 u8 dpdt_ctrl_keep : 1;
175 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
176 u8 antidx_anta : 3; /*antidx_anta[2:0]*/
177 u8 antidx_antb : 3; /*antidx_antb[2:0]*/
178 u8 hw_antsw_occur : 2; /*1'b0*/
179 #else /*_BIG_ENDIAN_*/
180 u8 hw_antsw_occur : 2;
186 void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id);
188 void odm_init_rssi_for_dm(struct phy_dm_struct *dm);
190 void odm_phy_status_query(struct phy_dm_struct *dm,
191 struct dm_phy_status_info *phy_info, u8 *phy_status,
192 struct dm_per_pkt_info *pktinfo);
194 void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
195 bool is_packet_match_bssid, bool is_packet_to_self,
196 bool is_packet_beacon);
199 odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm);
202 odm_config_rf_with_header_file(struct phy_dm_struct *dm,
203 enum odm_rf_config_type config_type,
204 enum odm_rf_radio_path e_rf_path);
207 odm_config_bb_with_header_file(struct phy_dm_struct *dm,
208 enum odm_bb_config_type config_type);
210 enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm);
213 odm_config_fw_with_header_file(struct phy_dm_struct *dm,
214 enum odm_fw_config_type config_type,
215 u8 *p_firmware, u32 *size);
217 u32 odm_get_hw_img_version(struct phy_dm_struct *dm);
219 /*For 8822B only!! need to move to FW finally */
220 /*==============================================*/
221 void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
222 struct dm_per_pkt_info *pktinfo,
223 struct dm_phy_status_info *phy_info);
225 bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
226 u8 *p_data_rate, u8 *p_gid);
228 struct phy_status_rpt_jaguar2_type0 {
232 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
245 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
257 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
275 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
300 struct phy_status_rpt_jaguar2_type1 {
304 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
312 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
315 u8 hw_antsw_occu : 1;
325 u8 hw_antsw_occu : 1;
332 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
350 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
360 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
375 s8 rxevm[4]; /* s(8,1) */
378 s8 cfo_tail[4]; /* s(8,7) */
381 s8 rxsnr[4]; /* s(8,1) */
384 struct phy_status_rpt_jaguar2_type2 {
388 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
396 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
399 u8 hw_antsw_occu : 1;
409 u8 hw_antsw_occu : 1;
415 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
423 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
437 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
474 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
487 #endif /*#ifndef __HALHWOUTSRC_H__*/