drivers/staging/media/hantro/hantro_g1_h264_dec.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Rockchip RK3288 VPU codec driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co., Ltd.
   6  *      Hertz Wong <hertz.wong@rock-chips.com>
   7  *      Herman Chen <herman.chen@rock-chips.com>
   8  *
   9  * Copyright (C) 2014 Google, Inc.
  10  *      Tomasz Figa <tfiga@chromium.org>
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/sort.h>
  15
  16 #include <media/v4l2-mem2mem.h>
  17
  18 #include "hantro_g1_regs.h"
  19 #include "hantro_hw.h"
  20 #include "hantro_v4l2.h"
  21
  22 static void set_params(struct hantro_ctx *ctx)
  23 {
  24         const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
  25         const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
  26         const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
  27         const struct v4l2_ctrl_h264_sps *sps = ctrls->sps;
  28         const struct v4l2_ctrl_h264_pps *pps = ctrls->pps;
  29         struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx);
  30         struct hantro_dev *vpu = ctx->dev;
  31         u32 reg;
  32
  33         /* Decoder control register 0. */
  34         reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0);
  35         if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)
  36                 reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E;
  37         if (sps->profile_idc > 66) {
  38                 reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E;
  39                 if (dec_param->nal_ref_idc)
  40                         reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E;
  41         }
  42
  43         if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) &&
  44             (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD ||
  45              slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
  46                 reg |= G1_REG_DEC_CTRL0_PIC_INTERLACE_E;
  47         if (slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)
  48                 reg |= G1_REG_DEC_CTRL0_PIC_FIELDMODE_E;
  49         if (!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD))
  50                 reg |= G1_REG_DEC_CTRL0_PIC_TOPFIELD_E;
  51         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);
  52
  53         /* Decoder control register 1. */
  54         reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)) |
  55               G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |
  56               G1_REG_DEC_CTRL1_REF_FRAMES(sps->max_num_ref_frames);
  57         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);
  58
  59         /* Decoder control register 2. */
  60         reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) |
  61               G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset);
  62
  63         /* always use the matrix sent from userspace */
  64         reg |= G1_REG_DEC_CTRL2_TYPE1_QUANT_E;
  65
  66         if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
  67                 reg |= G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E;
  68         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);
  69
  70         /* Decoder control register 3. */
  71         reg = G1_REG_DEC_CTRL3_START_CODE_E |
  72               G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) |
  73               G1_REG_DEC_CTRL3_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
  74         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3);
  75
  76         /* Decoder control register 4. */
  77         reg = G1_REG_DEC_CTRL4_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) |
  78               G1_REG_DEC_CTRL4_FRAMENUM(slices[0].frame_num) |
  79               G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc);
  80         if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)
  81                 reg |= G1_REG_DEC_CTRL4_CABAC_E;
  82         if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE)
  83                 reg |= G1_REG_DEC_CTRL4_DIR_8X8_INFER_E;
  84         if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0)
  85                 reg |= G1_REG_DEC_CTRL4_BLACKWHITE_E;
  86         if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED)
  87                 reg |= G1_REG_DEC_CTRL4_WEIGHT_PRED_E;
  88         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);
  89
  90         /* Decoder control register 5. */
  91         reg = G1_REG_DEC_CTRL5_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) |
  92               G1_REG_DEC_CTRL5_IDR_PIC_ID(slices[0].idr_pic_id);
  93         if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)
  94                 reg |= G1_REG_DEC_CTRL5_CONST_INTRA_E;
  95         if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT)
  96                 reg |= G1_REG_DEC_CTRL5_FILT_CTRL_PRES;
  97         if (pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT)
  98                 reg |= G1_REG_DEC_CTRL5_RDPIC_CNT_PRES;
  99         if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE)
 100                 reg |= G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E;
 101         if (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC)
 102                 reg |= G1_REG_DEC_CTRL5_IDR_PIC_E;
 103         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5);
 104
 105         /* Decoder control register 6. */
 106         reg = G1_REG_DEC_CTRL6_PPS_ID(slices[0].pic_parameter_set_id) |
 107               G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |
 108               G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |
 109               G1_REG_DEC_CTRL6_POC_LENGTH(slices[0].pic_order_cnt_bit_size);
 110         vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6);
 111
 112         /* Error concealment register. */
 113         vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC);
 114
 115         /* Prediction filter tap register. */
 116         vdpu_write_relaxed(vpu,
 117                            G1_REG_PRED_FLT_PRED_BC_TAP_0_0(1) |
 118                            G1_REG_PRED_FLT_PRED_BC_TAP_0_1(-5 & 0x3ff) |
 119                            G1_REG_PRED_FLT_PRED_BC_TAP_0_2(20),
 120                            G1_REG_PRED_FLT);
 121
 122         /* Reference picture buffer control register. */
 123         vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL);
 124
 125         /* Reference picture buffer control register 2. */
 126         vdpu_write_relaxed(vpu, G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(8),
 127                            G1_REG_REF_BUF_CTRL2);
 128 }
 129
 130 static void set_ref(struct hantro_ctx *ctx)
 131 {
 132         struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
 133         const u8 *b0_reflist, *b1_reflist, *p_reflist;
 134         struct hantro_dev *vpu = ctx->dev;
 135         u32 dpb_longterm = 0;
 136         u32 dpb_valid = 0;
 137         int reg_num;
 138         u32 reg;
 139         int i;
 140
 141         /*
 142          * Set up bit maps of valid and long term DPBs.
 143          * NOTE: The bits are reversed, i.e. MSb is DPB 0.
 144          */
 145         for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
 146                 if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
 147                         dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
 148
 149                 if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
 150                         dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
 151         }
 152         vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
 153         vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
 154
 155         /*
 156          * Set up reference frame picture numbers.
 157          *
 158          * Each G1_REG_REF_PIC(x) register contains numbers of two
 159          * subsequential reference pictures.
 160          */
 161         for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) {
 162                 reg = 0;
 163                 if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
 164                         reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num);
 165                 else
 166                         reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num);
 167
 168                 if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
 169                         reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num);
 170                 else
 171                         reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num);
 172
 173                 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2));
 174         }
 175
 176         b0_reflist = ctx->h264_dec.reflists.b0;
 177         b1_reflist = ctx->h264_dec.reflists.b1;
 178         p_reflist = ctx->h264_dec.reflists.p;
 179
 180         /*
 181          * Each G1_REG_BD_REF_PIC(x) register contains three entries
 182          * of each forward and backward picture list.
 183          */
 184         reg_num = 0;
 185         for (i = 0; i < 15; i += 3) {
 186                 reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i]) |
 187                       G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1]) |
 188                       G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2]) |
 189                       G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i]) |
 190                       G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1]) |
 191                       G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2]);
 192                 vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));
 193         }
 194
 195         /*
 196          * G1_REG_BD_P_REF_PIC register contains last entries (index 15)
 197          * of forward and backward reference picture lists and first 4 entries
 198          * of P forward picture list.
 199          */
 200         reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15]) |
 201               G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15]) |
 202               G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0]) |
 203               G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1]) |
 204               G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2]) |
 205               G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3]);
 206         vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC);
 207
 208         /*
 209          * Each G1_REG_FWD_PIC(x) register contains six consecutive
 210          * entries of P forward picture list, starting from index 4.
 211          */
 212         reg_num = 0;
 213         for (i = 4; i < HANTRO_H264_DPB_SIZE; i += 6) {
 214                 reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i]) |
 215                       G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1]) |
 216                       G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2]) |
 217                       G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3]) |
 218                       G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4]) |
 219                       G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5]);
 220                 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++));
 221         }
 222
 223         /* Set up addresses of DPB buffers. */
 224         for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) {
 225                 dma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i);
 226
 227                 vdpu_write_relaxed(vpu, dma_addr, G1_REG_ADDR_REF(i));
 228         }
 229 }
 230
 231 static void set_buffers(struct hantro_ctx *ctx)
 232 {
 233         const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
 234         struct vb2_v4l2_buffer *src_buf, *dst_buf;
 235         struct hantro_dev *vpu = ctx->dev;
 236         dma_addr_t src_dma, dst_dma;
 237         size_t offset = 0;
 238
 239         src_buf = hantro_get_src_buf(ctx);
 240         dst_buf = hantro_get_dst_buf(ctx);
 241
 242         /* Source (stream) buffer. */
 243         src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
 244         vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR);
 245
 246         /* Destination (decoded frame) buffer. */
 247         dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
 248         /* Adjust dma addr to start at second line for bottom field */
 249         if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
 250                 offset = ALIGN(ctx->src_fmt.width, MB_DIM);
 251         vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DST);
 252
 253         /* Higher profiles require DMV buffer appended to reference frames. */
 254         if (ctrls->sps->profile_idc > 66 && ctrls->decode->nal_ref_idc) {
 255                 unsigned int bytes_per_mb = 384;
 256
 257                 /* DMV buffer for monochrome start directly after Y-plane */
 258                 if (ctrls->sps->profile_idc >= 100 &&
 259                     ctrls->sps->chroma_format_idc == 0)
 260                         bytes_per_mb = 256;
 261                 offset = bytes_per_mb * MB_WIDTH(ctx->src_fmt.width) *
 262                          MB_HEIGHT(ctx->src_fmt.height);
 263
 264                 /*
 265                  * DMV buffer is split in two for field encoded frames,
 266                  * adjust offset for bottom field
 267                  */
 268                 if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
 269                         offset += 32 * MB_WIDTH(ctx->src_fmt.width) *
 270                                   MB_HEIGHT(ctx->src_fmt.height);
 271                 vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV);
 272         }
 273
 274         /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */
 275         vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);
 276 }
 277
 278 void hantro_g1_h264_dec_run(struct hantro_ctx *ctx)
 279 {
 280         struct hantro_dev *vpu = ctx->dev;
 281
 282         /* Prepare the H264 decoder context. */
 283         if (hantro_h264_dec_prepare_run(ctx))
 284                 return;
 285
 286         /* Configure hardware registers. */
 287         set_params(ctx);
 288         set_ref(ctx);
 289         set_buffers(ctx);
 290
 291         hantro_finish_run(ctx);
 292
 293         /* Start decoding! */
 294         vdpu_write_relaxed(vpu,
 295                            G1_REG_CONFIG_DEC_AXI_RD_ID(0xffu) |
 296                            G1_REG_CONFIG_DEC_TIMEOUT_E |
 297                            G1_REG_CONFIG_DEC_OUT_ENDIAN |
 298                            G1_REG_CONFIG_DEC_STRENDIAN_E |
 299                            G1_REG_CONFIG_DEC_MAX_BURST(16) |
 300                            G1_REG_CONFIG_DEC_OUTSWAP32_E |
 301                            G1_REG_CONFIG_DEC_INSWAP32_E |
 302                            G1_REG_CONFIG_DEC_STRSWAP32_E |
 303                            G1_REG_CONFIG_DEC_CLK_GATE_E,
 304                            G1_REG_CONFIG);
 305         vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
 306 }