drivers/staging/media/davinci_vpfe/dm365_isif_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Inc
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * Contributors:
  15  *      Manjunath Hadli <manjunath.hadli@ti.com>
  16  *      Prabhakar Lad <prabhakar.lad@ti.com>
  17  */
  18
  19 #ifndef _DAVINCI_VPFE_DM365_ISIF_REGS_H
  20 #define _DAVINCI_VPFE_DM365_ISIF_REGS_H
  21
  22 /* ISIF registers relative offsets */
  23 #define SYNCEN                                  0x00
  24 #define MODESET                                 0x04
  25 #define HDW                                     0x08
  26 #define VDW                                     0x0c
  27 #define PPLN                                    0x10
  28 #define LPFR                                    0x14
  29 #define SPH                                     0x18
  30 #define LNH                                     0x1c
  31 #define SLV0                                    0x20
  32 #define SLV1                                    0x24
  33 #define LNV                                     0x28
  34 #define CULH                                    0x2c
  35 #define CULV                                    0x30
  36 #define HSIZE                                   0x34
  37 #define SDOFST                                  0x38
  38 #define CADU                                    0x3c
  39 #define CADL                                    0x40
  40 #define LINCFG0                                 0x44
  41 #define LINCFG1                                 0x48
  42 #define CCOLP                                   0x4c
  43 #define CRGAIN                                  0x50
  44 #define CGRGAIN                                 0x54
  45 #define CGBGAIN                                 0x58
  46 #define CBGAIN                                  0x5c
  47 #define COFSTA                                  0x60
  48 #define FLSHCFG0                                0x64
  49 #define FLSHCFG1                                0x68
  50 #define FLSHCFG2                                0x6c
  51 #define VDINT0                                  0x70
  52 #define VDINT1                                  0x74
  53 #define VDINT2                                  0x78
  54 #define MISC                                    0x7c
  55 #define CGAMMAWD                                0x80
  56 #define REC656IF                                0x84
  57 #define CCDCFG                                  0x88
  58 /*****************************************************
  59  * Defect Correction registers
  60  *****************************************************/
  61 #define DFCCTL                                  0x8c
  62 #define VDFSATLV                                0x90
  63 #define DFCMEMCTL                               0x94
  64 #define DFCMEM0                                 0x98
  65 #define DFCMEM1                                 0x9c
  66 #define DFCMEM2                                 0xa0
  67 #define DFCMEM3                                 0xa4
  68 #define DFCMEM4                                 0xa8
  69 /****************************************************
  70  * Black Clamp registers
  71  ****************************************************/
  72 #define CLAMPCFG                                0xac
  73 #define CLDCOFST                                0xb0
  74 #define CLSV                                    0xb4
  75 #define CLHWIN0                                 0xb8
  76 #define CLHWIN1                                 0xbc
  77 #define CLHWIN2                                 0xc0
  78 #define CLVRV                                   0xc4
  79 #define CLVWIN0                                 0xc8
  80 #define CLVWIN1                                 0xcc
  81 #define CLVWIN2                                 0xd0
  82 #define CLVWIN3                                 0xd4
  83 /****************************************************
  84  * Lense Shading Correction
  85  ****************************************************/
  86 #define DATAHOFST                               0xd8
  87 #define DATAVOFST                               0xdc
  88 #define LSCHVAL                                 0xe0
  89 #define LSCVVAL                                 0xe4
  90 #define TWODLSCCFG                              0xe8
  91 #define TWODLSCOFST                             0xec
  92 #define TWODLSCINI                              0xf0
  93 #define TWODLSCGRBU                             0xf4
  94 #define TWODLSCGRBL                             0xf8
  95 #define TWODLSCGROF                             0xfc
  96 #define TWODLSCORBU                             0x100
  97 #define TWODLSCORBL                             0x104
  98 #define TWODLSCOROF                             0x108
  99 #define TWODLSCIRQEN                            0x10c
 100 #define TWODLSCIRQST                            0x110
 101 /****************************************************
 102  * Data formatter
 103  ****************************************************/
 104 #define FMTCFG                                  0x114
 105 #define FMTPLEN                                 0x118
 106 #define FMTSPH                                  0x11c
 107 #define FMTLNH                                  0x120
 108 #define FMTSLV                                  0x124
 109 #define FMTLNV                                  0x128
 110 #define FMTRLEN                                 0x12c
 111 #define FMTHCNT                                 0x130
 112 #define FMTAPTR_BASE                            0x134
 113 /* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
 114 #define FMTAPTR(i)                      (FMTAPTR_BASE + (i * 4))
 115 #define FMTPGMVF0                               0x174
 116 #define FMTPGMVF1                               0x178
 117 #define FMTPGMAPU0                              0x17c
 118 #define FMTPGMAPU1                              0x180
 119 #define FMTPGMAPS0                              0x184
 120 #define FMTPGMAPS1                              0x188
 121 #define FMTPGMAPS2                              0x18c
 122 #define FMTPGMAPS3                              0x190
 123 #define FMTPGMAPS4                              0x194
 124 #define FMTPGMAPS5                              0x198
 125 #define FMTPGMAPS6                              0x19c
 126 #define FMTPGMAPS7                              0x1a0
 127 /************************************************
 128  * Color Space Converter
 129  ************************************************/
 130 #define CSCCTL                                  0x1a4
 131 #define CSCM0                                   0x1a8
 132 #define CSCM1                                   0x1ac
 133 #define CSCM2                                   0x1b0
 134 #define CSCM3                                   0x1b4
 135 #define CSCM4                                   0x1b8
 136 #define CSCM5                                   0x1bc
 137 #define CSCM6                                   0x1c0
 138 #define CSCM7                                   0x1c4
 139 #define OBWIN0                                  0x1c8
 140 #define OBWIN1                                  0x1cc
 141 #define OBWIN2                                  0x1d0
 142 #define OBWIN3                                  0x1d4
 143 #define OBVAL0                                  0x1d8
 144 #define OBVAL1                                  0x1dc
 145 #define OBVAL2                                  0x1e0
 146 #define OBVAL3                                  0x1e4
 147 #define OBVAL4                                  0x1e8
 148 #define OBVAL5                                  0x1ec
 149 #define OBVAL6                                  0x1f0
 150 #define OBVAL7                                  0x1f4
 151 #define CLKCTL                                  0x1f8
 152
 153 /* Masks & Shifts below */
 154 #define START_PX_HOR_MASK                       0x7fff
 155 #define NUM_PX_HOR_MASK                         0x7fff
 156 #define START_VER_ONE_MASK                      0x7fff
 157 #define START_VER_TWO_MASK                      0x7fff
 158 #define NUM_LINES_VER                           0x7fff
 159
 160 /* gain - offset masks */
 161 #define OFFSET_MASK                             0xfff
 162 #define GAIN_SDRAM_EN_SHIFT                     12
 163 #define GAIN_IPIPE_EN_SHIFT                     13
 164 #define GAIN_H3A_EN_SHIFT                       14
 165 #define OFST_SDRAM_EN_SHIFT                     8
 166 #define OFST_IPIPE_EN_SHIFT                     9
 167 #define OFST_H3A_EN_SHIFT                       10
 168 #define GAIN_OFFSET_EN_MASK                     0x7700
 169
 170 /* Culling */
 171 #define CULL_PAT_EVEN_LINE_SHIFT                8
 172
 173 /* CCDCFG register */
 174 #define ISIF_YCINSWP_RAW                        (0x00 << 4)
 175 #define ISIF_YCINSWP_YCBCR                      (0x01 << 4)
 176 #define ISIF_CCDCFG_FIDMD_LATCH_VSYNC           (0x00 << 6)
 177 #define ISIF_CCDCFG_WENLOG_AND                  (0x00 << 8)
 178 #define ISIF_CCDCFG_TRGSEL_WEN                  (0x00 << 9)
 179 #define ISIF_CCDCFG_EXTRG_DISABLE               (0x00 << 10)
 180 #define ISIF_LATCH_ON_VSYNC_DISABLE             (0x01 << 15)
 181 #define ISIF_LATCH_ON_VSYNC_ENABLE              (0x00 << 15)
 182 #define ISIF_DATA_PACK_MASK                     0x03
 183 #define ISIF_PIX_ORDER_SHIFT                    11
 184 #define ISIF_PIX_ORDER_MASK                     0x01
 185 #define ISIF_BW656_ENABLE                       (0x01 << 5)
 186
 187 /* MODESET registers */
 188 #define ISIF_VDHDOUT_INPUT                      (0x00 << 0)
 189 #define ISIF_INPUT_MASK                         0x03
 190 #define ISIF_INPUT_SHIFT                        12
 191 #define ISIF_FID_POL_MASK                       0x01
 192 #define ISIF_FID_POL_SHIFT                      4
 193 #define ISIF_HD_POL_MASK                        0x01
 194 #define ISIF_HD_POL_SHIFT                       3
 195 #define ISIF_VD_POL_MASK                        0x01
 196 #define ISIF_VD_POL_SHIFT                       2
 197 #define ISIF_DATAPOL_NORMAL                     0x00
 198 #define ISIF_DATAPOL_MASK                       0x01
 199 #define ISIF_DATAPOL_SHIFT                      6
 200 #define ISIF_EXWEN_DISABLE                      0x00
 201 #define ISIF_EXWEN_MASK                         0x01
 202 #define ISIF_EXWEN_SHIFT                        5
 203 #define ISIF_FRM_FMT_MASK                       0x01
 204 #define ISIF_FRM_FMT_SHIFT                      7
 205 #define ISIF_DATASFT_MASK                       0x07
 206 #define ISIF_DATASFT_SHIFT                      8
 207 #define ISIF_LPF_SHIFT                          14
 208 #define ISIF_LPF_MASK                           0x1
 209
 210 /* GAMMAWD registers */
 211 #define ISIF_ALAW_GAMA_WD_MASK                  0xf
 212 #define ISIF_ALAW_GAMA_WD_SHIFT                 1
 213 #define ISIF_ALAW_ENABLE                        0x01
 214 #define ISIF_GAMMAWD_CFA_MASK                   0x01
 215 #define ISIF_GAMMAWD_CFA_SHIFT                  5
 216
 217 /* HSIZE registers */
 218 #define ISIF_HSIZE_FLIP_MASK                    0x01
 219 #define ISIF_HSIZE_FLIP_SHIFT                   12
 220 #define ISIF_LINEOFST_MASK                      0xfff
 221
 222 /* MISC registers */
 223 #define ISIF_DPCM_EN_SHIFT                      12
 224 #define ISIF_DPCM_PREDICTOR_SHIFT               13
 225 #define ISIF_DPCM_PREDICTOR_MASK                1
 226
 227 /* Black clamp related */
 228 #define ISIF_BC_DCOFFSET_MASK                   0x1fff
 229 #define ISIF_BC_MODE_COLOR_MASK                 1
 230 #define ISIF_BC_MODE_COLOR_SHIFT                4
 231 #define ISIF_HORZ_BC_MODE_MASK                  3
 232 #define ISIF_HORZ_BC_MODE_SHIFT                 1
 233 #define ISIF_HORZ_BC_WIN_COUNT_MASK             0x1f
 234 #define ISIF_HORZ_BC_WIN_SEL_SHIFT              5
 235 #define ISIF_HORZ_BC_PIX_LIMIT_SHIFT            6
 236 #define ISIF_HORZ_BC_WIN_H_SIZE_MASK            3
 237 #define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT           8
 238 #define ISIF_HORZ_BC_WIN_V_SIZE_MASK            3
 239 #define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT           12
 240 #define ISIF_HORZ_BC_WIN_START_H_MASK           0x1fff
 241 #define ISIF_HORZ_BC_WIN_START_V_MASK           0x1fff
 242 #define ISIF_VERT_BC_OB_H_SZ_MASK               7
 243 #define ISIF_VERT_BC_RST_VAL_SEL_MASK           3
 244 #define ISIF_VERT_BC_RST_VAL_SEL_SHIFT          4
 245 #define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT        8
 246 #define ISIF_VERT_BC_OB_START_HORZ_MASK         0x1fff
 247 #define ISIF_VERT_BC_OB_START_VERT_MASK         0x1fff
 248 #define ISIF_VERT_BC_OB_VERT_SZ_MASK            0x1fff
 249 #define ISIF_VERT_BC_RST_VAL_MASK               0xfff
 250 #define ISIF_BC_VERT_START_SUB_V_MASK           0x1fff
 251
 252 /* VDFC registers */
 253 #define ISIF_VDFC_EN_SHIFT                      4
 254 #define ISIF_VDFC_CORR_MOD_MASK                 3
 255 #define ISIF_VDFC_CORR_MOD_SHIFT                5
 256 #define ISIF_VDFC_CORR_WHOLE_LN_SHIFT           7
 257 #define ISIF_VDFC_LEVEL_SHFT_MASK               7
 258 #define ISIF_VDFC_LEVEL_SHFT_SHIFT              8
 259 #define ISIF_VDFC_SAT_LEVEL_MASK                0xfff
 260 #define ISIF_VDFC_POS_MASK                      0x1fff
 261 #define ISIF_DFCMEMCTL_DFCMARST_SHIFT           2
 262
 263 /* CSC registers */
 264 #define ISIF_CSC_COEF_INTEG_MASK                7
 265 #define ISIF_CSC_COEF_DECIMAL_MASK              0x1f
 266 #define ISIF_CSC_COEF_INTEG_SHIFT               5
 267 #define ISIF_CSCM_MSB_SHIFT                     8
 268 #define ISIF_DF_CSC_SPH_MASK                    0x1fff
 269 #define ISIF_DF_CSC_LNH_MASK                    0x1fff
 270 #define ISIF_DF_CSC_SLV_MASK                    0x1fff
 271 #define ISIF_DF_CSC_LNV_MASK                    0x1fff
 272 #define ISIF_DF_NUMLINES                        0x7fff
 273 #define ISIF_DF_NUMPIX                          0x1fff
 274
 275 /* Offsets for LSC/DFC/Gain */
 276 #define ISIF_DATA_H_OFFSET_MASK                 0x1fff
 277 #define ISIF_DATA_V_OFFSET_MASK                 0x1fff
 278
 279 /* Linearization */
 280 #define ISIF_LIN_CORRSFT_MASK                   7
 281 #define ISIF_LIN_CORRSFT_SHIFT                  4
 282 #define ISIF_LIN_SCALE_FACT_INTEG_SHIFT         10
 283 #define ISIF_LIN_SCALE_FACT_DECIMAL_MASK        0x3ff
 284 #define ISIF_LIN_ENTRY_MASK                     0x3ff
 285
 286 /* masks and shifts*/
 287 #define ISIF_SYNCEN_VDHDEN_MASK                 (1 << 0)
 288 #define ISIF_SYNCEN_WEN_MASK                    (1 << 1)
 289 #define ISIF_SYNCEN_WEN_SHIFT                   1
 290
 291 #endif          /* _DAVINCI_VPFE_DM365_ISIF_REGS_H */