1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for DAQ-STC based boards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
11 * This file is meant to be included by another file, e.g.,
12 * ni_atmio.c or ni_pcimio.c.
14 * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
16 * References (ftp://ftp.natinst.com/support/manuals):
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
18 * 341079b.pdf PCI E Series RLPM
19 * 340934b.pdf DAQ-STC reference manual
21 * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
25 * Other possibly relevant info:
26 * 320517c.pdf User manual (obsolete)
27 * 320517f.pdf User manual (new)
29 * 320906c.pdf maximum signal ratings
30 * 321066a.pdf about 16x
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
34 * 321838a.pdf about at-mio-16de-10 rev N
37 * - the interrupt routine needs to be cleaned up
39 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
40 * fully tested as yet. Terry Barnaby, BEAM Ltd.
43 #include <linux/interrupt.h>
44 #include <linux/sched.h>
45 #include <linux/delay.h>
50 #define NI_TIMEOUT 1000
52 /* Note: this table must match the ai_gain_* definitions */
53 static const short ni_gainlkup[][16] = {
54 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
55 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
56 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
57 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
58 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
59 [ai_gain_4] = {0, 1, 4, 7},
60 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
61 0x003, 0x004, 0x005, 0x006},
62 [ai_gain_622x] = {0, 1, 4, 5},
63 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
64 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
67 static const struct comedi_lrange range_ni_E_ai = {
88 static const struct comedi_lrange range_ni_E_ai_limited = {
101 static const struct comedi_lrange range_ni_E_ai_limited14 = {
120 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
129 static const struct comedi_lrange range_ni_E_ai_611x = {
142 static const struct comedi_lrange range_ni_M_ai_622x = {
151 static const struct comedi_lrange range_ni_M_ai_628x = {
163 static const struct comedi_lrange range_ni_E_ao_ext = {
172 static const struct comedi_lrange *const ni_range_lkup[] = {
173 [ai_gain_16] = &range_ni_E_ai,
174 [ai_gain_8] = &range_ni_E_ai_limited,
175 [ai_gain_14] = &range_ni_E_ai_limited14,
176 [ai_gain_4] = &range_ni_E_ai_bipolar4,
177 [ai_gain_611x] = &range_ni_E_ai_611x,
178 [ai_gain_622x] = &range_ni_M_ai_622x,
179 [ai_gain_628x] = &range_ni_M_ai_628x,
180 [ai_gain_6143] = &range_bipolar5
185 AIMODE_HALF_FULL = 1,
190 enum ni_common_subdevices {
196 NI_CALIBRATION_SUBDEV,
199 NI_CS5529_CALIBRATION_SUBDEV,
208 #define NI_GPCT_SUBDEV(x) (NI_GPCT0_SUBDEV + (x))
210 enum timebase_nanoseconds {
212 TIMEBASE_2_NS = 10000
215 #define SERIAL_DISABLED 0
216 #define SERIAL_600NS 600
217 #define SERIAL_1_2US 1200
218 #define SERIAL_10US 10000
220 static const int num_adc_stages_611x = 3;
222 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
225 writel(data, dev->mmio + reg);
227 outl(data, dev->iobase + reg);
230 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
233 writew(data, dev->mmio + reg);
235 outw(data, dev->iobase + reg);
238 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
241 writeb(data, dev->mmio + reg);
243 outb(data, dev->iobase + reg);
246 static unsigned int ni_readl(struct comedi_device *dev, int reg)
249 return readl(dev->mmio + reg);
251 return inl(dev->iobase + reg);
254 static unsigned int ni_readw(struct comedi_device *dev, int reg)
257 return readw(dev->mmio + reg);
259 return inw(dev->iobase + reg);
262 static unsigned int ni_readb(struct comedi_device *dev, int reg)
265 return readb(dev->mmio + reg);
267 return inb(dev->iobase + reg);
271 * We automatically take advantage of STC registers that can be
272 * read/written directly in the I/O space of the board.
274 * The AT-MIO and DAQCard devices map the low 8 STC registers to
277 * Most PCIMIO devices also map the low 8 STC registers but the
278 * 611x devices map the read registers to iobase+(addr-1)*2.
279 * For now non-windowed STC access is disabled if a PCIMIO device
280 * is detected (devpriv->mite has been initialized).
282 * The M series devices do not used windowed registers for the
283 * STC registers. The functions below handle the mapping of the
284 * windowed STC registers to the m series register offsets.
288 unsigned int mio_reg;
292 static const struct mio_regmap m_series_stc_write_regmap[] = {
293 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
294 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
295 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
296 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
297 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
298 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
299 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
300 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
302 * NISTC_DIO_OUT_REG maps to:
303 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
305 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
306 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
307 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
308 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
309 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
310 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
311 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
312 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
313 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
314 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
315 [NISTC_G0_MODE_REG] = { 0x134, 2 },
316 [NISTC_G1_MODE_REG] = { 0x136, 2 },
317 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
318 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
319 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
320 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
321 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
322 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
323 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
324 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
325 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
326 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
327 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
328 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
329 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
330 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
331 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
332 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
333 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
334 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
335 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
336 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
337 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
338 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
339 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
340 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
341 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
342 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
343 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
344 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
345 [NISTC_RESET_REG] = { 0x190, 2 },
346 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
347 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
348 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
349 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
350 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
351 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
352 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
353 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
354 /* doc for following line: mhddk/nimseries/ChipObjects/tMSeries.h */
355 [NISTC_RTSI_BOARD_REG] = { 0x1a2, 2 },
356 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
357 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
358 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
359 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
360 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
363 static void m_series_stc_write(struct comedi_device *dev,
364 unsigned int data, unsigned int reg)
366 const struct mio_regmap *regmap;
368 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
369 regmap = &m_series_stc_write_regmap[reg];
371 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
376 switch (regmap->size) {
378 ni_writel(dev, data, regmap->mio_reg);
381 ni_writew(dev, data, regmap->mio_reg);
384 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
390 static const struct mio_regmap m_series_stc_read_regmap[] = {
391 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
392 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
393 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
394 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
395 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
396 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
397 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
398 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
399 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
400 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
401 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
402 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
403 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
404 [NISTC_STATUS1_REG] = { 0x136, 2 },
405 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
406 [NISTC_STATUS2_REG] = { 0x13a, 2 },
407 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
408 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
411 static unsigned int m_series_stc_read(struct comedi_device *dev,
414 const struct mio_regmap *regmap;
416 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
417 regmap = &m_series_stc_read_regmap[reg];
419 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
424 switch (regmap->size) {
426 return ni_readl(dev, regmap->mio_reg);
428 return ni_readw(dev, regmap->mio_reg);
430 return ni_readb(dev, regmap->mio_reg);
432 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
438 static void ni_stc_writew(struct comedi_device *dev,
439 unsigned int data, int reg)
441 struct ni_private *devpriv = dev->private;
444 if (devpriv->is_m_series) {
445 m_series_stc_write(dev, data, reg);
447 spin_lock_irqsave(&devpriv->window_lock, flags);
448 if (!devpriv->mite && reg < 8) {
449 ni_writew(dev, data, reg * 2);
451 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
452 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
454 spin_unlock_irqrestore(&devpriv->window_lock, flags);
458 static void ni_stc_writel(struct comedi_device *dev,
459 unsigned int data, int reg)
461 struct ni_private *devpriv = dev->private;
463 if (devpriv->is_m_series) {
464 m_series_stc_write(dev, data, reg);
466 ni_stc_writew(dev, data >> 16, reg);
467 ni_stc_writew(dev, data & 0xffff, reg + 1);
471 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
473 struct ni_private *devpriv = dev->private;
477 if (devpriv->is_m_series) {
478 val = m_series_stc_read(dev, reg);
480 spin_lock_irqsave(&devpriv->window_lock, flags);
481 if (!devpriv->mite && reg < 8) {
482 val = ni_readw(dev, reg * 2);
484 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
485 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
487 spin_unlock_irqrestore(&devpriv->window_lock, flags);
492 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
494 struct ni_private *devpriv = dev->private;
497 if (devpriv->is_m_series) {
498 val = m_series_stc_read(dev, reg);
500 val = ni_stc_readw(dev, reg) << 16;
501 val |= ni_stc_readw(dev, reg + 1);
506 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
507 unsigned int bit_mask,
508 unsigned int bit_values)
510 struct ni_private *devpriv = dev->private;
513 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
515 case NISTC_INTA_ENA_REG:
516 devpriv->int_a_enable_reg &= ~bit_mask;
517 devpriv->int_a_enable_reg |= bit_values & bit_mask;
518 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
520 case NISTC_INTB_ENA_REG:
521 devpriv->int_b_enable_reg &= ~bit_mask;
522 devpriv->int_b_enable_reg |= bit_values & bit_mask;
523 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
525 case NISTC_IO_BIDIR_PIN_REG:
526 devpriv->io_bidirection_pin_reg &= ~bit_mask;
527 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
528 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
530 case NI_E_DMA_AI_AO_SEL_REG:
531 devpriv->ai_ao_select_reg &= ~bit_mask;
532 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
533 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
535 case NI_E_DMA_G0_G1_SEL_REG:
536 devpriv->g0_g1_select_reg &= ~bit_mask;
537 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
538 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
540 case NI_M_CDIO_DMA_SEL_REG:
541 devpriv->cdio_dma_select_reg &= ~bit_mask;
542 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
543 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
546 dev_err(dev->class_dev, "called with invalid register %d\n",
551 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
556 /* selects the MITE channel to use for DMA */
557 #define NI_STC_DMA_CHAN_SEL(x) (((x) < 4) ? BIT(x) : \
559 ((x) == 5) ? 0x5 : 0x0)
561 /* DMA channel setup */
562 static int ni_request_ai_mite_channel(struct comedi_device *dev)
564 struct ni_private *devpriv = dev->private;
565 struct mite_channel *mite_chan;
569 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
570 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
572 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
573 dev_err(dev->class_dev,
574 "failed to reserve mite dma channel for analog input\n");
577 mite_chan->dir = COMEDI_INPUT;
578 devpriv->ai_mite_chan = mite_chan;
580 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
581 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
582 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
584 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
588 static int ni_request_ao_mite_channel(struct comedi_device *dev)
590 struct ni_private *devpriv = dev->private;
591 struct mite_channel *mite_chan;
595 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
596 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
598 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
599 dev_err(dev->class_dev,
600 "failed to reserve mite dma channel for analog outut\n");
603 mite_chan->dir = COMEDI_OUTPUT;
604 devpriv->ao_mite_chan = mite_chan;
606 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
607 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
608 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
610 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
614 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
615 unsigned int gpct_index,
616 enum comedi_io_direction direction)
618 struct ni_private *devpriv = dev->private;
619 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
620 struct mite_channel *mite_chan;
624 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
625 mite_chan = mite_request_channel(devpriv->mite,
626 devpriv->gpct_mite_ring[gpct_index]);
628 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
629 dev_err(dev->class_dev,
630 "failed to reserve mite dma channel for counter\n");
633 mite_chan->dir = direction;
634 ni_tio_set_mite_channel(counter, mite_chan);
636 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
637 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
638 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
639 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
641 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
645 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
647 struct ni_private *devpriv = dev->private;
648 struct mite_channel *mite_chan;
652 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
653 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
655 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
656 dev_err(dev->class_dev,
657 "failed to reserve mite dma channel for correlated digital output\n");
660 mite_chan->dir = COMEDI_OUTPUT;
661 devpriv->cdo_mite_chan = mite_chan;
664 * XXX just guessing NI_STC_DMA_CHAN_SEL()
665 * returns the right bits, under the assumption the cdio dma
666 * selection works just like ai/ao/gpct.
667 * Definitely works for dma channels 0 and 1.
669 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
670 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
671 NI_M_CDIO_DMA_SEL_CDO_MASK,
672 NI_M_CDIO_DMA_SEL_CDO(bits));
674 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
679 static void ni_release_ai_mite_channel(struct comedi_device *dev)
682 struct ni_private *devpriv = dev->private;
685 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
686 if (devpriv->ai_mite_chan) {
687 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
688 NI_E_DMA_AI_SEL_MASK, 0);
689 mite_release_channel(devpriv->ai_mite_chan);
690 devpriv->ai_mite_chan = NULL;
692 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
696 static void ni_release_ao_mite_channel(struct comedi_device *dev)
699 struct ni_private *devpriv = dev->private;
702 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
703 if (devpriv->ao_mite_chan) {
704 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
705 NI_E_DMA_AO_SEL_MASK, 0);
706 mite_release_channel(devpriv->ao_mite_chan);
707 devpriv->ao_mite_chan = NULL;
709 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
714 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
715 unsigned int gpct_index)
717 struct ni_private *devpriv = dev->private;
720 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
721 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
722 struct mite_channel *mite_chan =
723 devpriv->counter_dev->counters[gpct_index].mite_chan;
725 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
726 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
727 ni_tio_set_mite_channel(&devpriv->
728 counter_dev->counters[gpct_index],
730 mite_release_channel(mite_chan);
732 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
735 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
737 struct ni_private *devpriv = dev->private;
740 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
741 if (devpriv->cdo_mite_chan) {
742 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
743 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
744 mite_release_channel(devpriv->cdo_mite_chan);
745 devpriv->cdo_mite_chan = NULL;
747 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
750 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
751 unsigned int gpct_index, short enable)
753 struct ni_private *devpriv = dev->private;
754 unsigned int val = 0;
757 if (devpriv->is_m_series || gpct_index > 1)
761 * e-series boards use the second irq signals to generate
762 * dma requests for their counters
764 if (gpct_index == 0) {
765 reg = NISTC_INTA2_ENA_REG;
767 val = NISTC_INTA_ENA_G0_GATE;
769 reg = NISTC_INTB2_ENA_REG;
771 val = NISTC_INTB_ENA_G1_GATE;
773 ni_stc_writew(dev, val, reg);
777 static void ni_clear_ai_fifo(struct comedi_device *dev)
779 struct ni_private *devpriv = dev->private;
780 static const int timeout = 10000;
783 if (devpriv->is_6143) {
784 /* Flush the 6143 data FIFO */
785 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
786 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
787 /* Wait for complete */
788 for (i = 0; i < timeout; i++) {
789 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
794 dev_err(dev->class_dev, "FIFO flush timeout\n");
796 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
797 if (devpriv->is_625x) {
798 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
799 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
802 * The NI example code does 3 convert pulses for 625x
803 * boards, But that appears to be wrong in practice.
805 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
807 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
809 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
816 static inline void ni_ao_win_outw(struct comedi_device *dev,
817 unsigned int data, int addr)
819 struct ni_private *devpriv = dev->private;
822 spin_lock_irqsave(&devpriv->window_lock, flags);
823 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
824 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
825 spin_unlock_irqrestore(&devpriv->window_lock, flags);
828 static inline void ni_ao_win_outl(struct comedi_device *dev,
829 unsigned int data, int addr)
831 struct ni_private *devpriv = dev->private;
834 spin_lock_irqsave(&devpriv->window_lock, flags);
835 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
836 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
837 spin_unlock_irqrestore(&devpriv->window_lock, flags);
840 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
842 struct ni_private *devpriv = dev->private;
846 spin_lock_irqsave(&devpriv->window_lock, flags);
847 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
848 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
849 spin_unlock_irqrestore(&devpriv->window_lock, flags);
854 * ni_set_bits( ) allows different parts of the ni_mio_common driver to
855 * share registers (such as Interrupt_A_Register) without interfering with
858 * NOTE: the switch/case statements are optimized out for a constant argument
859 * so this is actually quite fast--- If you must wrap another function around
860 * this make it inline to avoid a large speed penalty.
862 * value should only be 1 or 0.
864 static inline void ni_set_bits(struct comedi_device *dev, int reg,
865 unsigned int bits, unsigned int value)
867 unsigned int bit_values;
873 ni_set_bitfield(dev, reg, bits, bit_values);
877 static void ni_sync_ai_dma(struct comedi_device *dev)
879 struct ni_private *devpriv = dev->private;
880 struct comedi_subdevice *s = dev->read_subdev;
883 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
884 if (devpriv->ai_mite_chan)
885 mite_sync_dma(devpriv->ai_mite_chan, s);
886 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
889 static int ni_ai_drain_dma(struct comedi_device *dev)
891 struct ni_private *devpriv = dev->private;
893 static const int timeout = 10000;
897 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
898 if (devpriv->ai_mite_chan) {
899 for (i = 0; i < timeout; i++) {
900 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
901 NISTC_AI_STATUS1_FIFO_E) &&
902 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
907 dev_err(dev->class_dev, "timed out\n");
908 dev_err(dev->class_dev,
909 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
910 mite_bytes_in_transit(devpriv->ai_mite_chan),
911 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
915 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
922 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
924 static const int timeout = 10000;
927 for (i = 0; i < timeout; i++) {
928 unsigned short b_status;
930 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
931 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
934 * If we poll too often, the pci bus activity seems
935 * to slow the dma transfer down.
937 usleep_range(10, 100);
940 dev_err(dev->class_dev, "timed out waiting for dma load\n");
949 static void ni_ao_fifo_load(struct comedi_device *dev,
950 struct comedi_subdevice *s, int n)
952 struct ni_private *devpriv = dev->private;
955 unsigned int packed_data;
957 for (i = 0; i < n; i++) {
958 comedi_buf_read_samples(s, &d, 1);
960 if (devpriv->is_6xxx) {
961 packed_data = d & 0xffff;
962 /* 6711 only has 16 bit wide ao fifo */
963 if (!devpriv->is_6711) {
964 comedi_buf_read_samples(s, &d, 1);
966 packed_data |= (d << 16) & 0xffff0000;
968 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
970 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
976 * There's a small problem if the FIFO gets really low and we
977 * don't have the data to fill it. Basically, if after we fill
978 * the FIFO with all the data available, the FIFO is _still_
979 * less than half full, we never clear the interrupt. If the
980 * IRQ is in edge mode, we never get another interrupt, because
981 * this one wasn't cleared. If in level mode, we get flooded
982 * with interrupts that we can't fulfill, because nothing ever
983 * gets put into the buffer.
985 * This kind of situation is recoverable, but it is easier to
986 * just pretend we had a FIFO underrun, since there is a good
987 * chance it will happen anyway. This is _not_ the case for
988 * RT code, as RT code might purposely be running close to the
989 * metal. Needs to be fixed eventually.
991 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
992 struct comedi_subdevice *s)
994 const struct ni_board_struct *board = dev->board_ptr;
996 unsigned int nsamples;
998 nbytes = comedi_buf_read_n_available(s);
1000 s->async->events |= COMEDI_CB_OVERFLOW;
1004 nsamples = comedi_bytes_to_samples(s, nbytes);
1005 if (nsamples > board->ao_fifo_depth / 2)
1006 nsamples = board->ao_fifo_depth / 2;
1008 ni_ao_fifo_load(dev, s, nsamples);
1013 static int ni_ao_prep_fifo(struct comedi_device *dev,
1014 struct comedi_subdevice *s)
1016 const struct ni_board_struct *board = dev->board_ptr;
1017 struct ni_private *devpriv = dev->private;
1018 unsigned int nbytes;
1019 unsigned int nsamples;
1022 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1023 if (devpriv->is_6xxx)
1024 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1026 /* load some data */
1027 nbytes = comedi_buf_read_n_available(s);
1031 nsamples = comedi_bytes_to_samples(s, nbytes);
1032 if (nsamples > board->ao_fifo_depth)
1033 nsamples = board->ao_fifo_depth;
1035 ni_ao_fifo_load(dev, s, nsamples);
1040 static void ni_ai_fifo_read(struct comedi_device *dev,
1041 struct comedi_subdevice *s, int n)
1043 struct ni_private *devpriv = dev->private;
1044 struct comedi_async *async = s->async;
1046 unsigned short data;
1049 if (devpriv->is_611x) {
1050 for (i = 0; i < n / 2; i++) {
1051 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1052 /* This may get the hi/lo data in the wrong order */
1053 data = (dl >> 16) & 0xffff;
1054 comedi_buf_write_samples(s, &data, 1);
1056 comedi_buf_write_samples(s, &data, 1);
1058 /* Check if there's a single sample stuck in the FIFO */
1060 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1062 comedi_buf_write_samples(s, &data, 1);
1064 } else if (devpriv->is_6143) {
1066 * This just reads the FIFO assuming the data is present,
1067 * no checks on the FIFO status are performed.
1069 for (i = 0; i < n / 2; i++) {
1070 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1072 data = (dl >> 16) & 0xffff;
1073 comedi_buf_write_samples(s, &data, 1);
1075 comedi_buf_write_samples(s, &data, 1);
1078 /* Assume there is a single sample stuck in the FIFO */
1079 /* Get stranded sample into FIFO */
1080 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1081 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1082 data = (dl >> 16) & 0xffff;
1083 comedi_buf_write_samples(s, &data, 1);
1086 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1087 dev_err(dev->class_dev,
1088 "bug! ai_fifo_buffer too small\n");
1089 async->events |= COMEDI_CB_ERROR;
1092 for (i = 0; i < n; i++) {
1093 devpriv->ai_fifo_buffer[i] =
1094 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1096 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1100 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1102 const struct ni_board_struct *board = dev->board_ptr;
1103 struct comedi_subdevice *s = dev->read_subdev;
1106 n = board->ai_fifo_depth / 2;
1108 ni_ai_fifo_read(dev, s, n);
1112 /* Empties the AI fifo */
1113 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1115 struct ni_private *devpriv = dev->private;
1116 struct comedi_subdevice *s = dev->read_subdev;
1118 unsigned short data;
1121 if (devpriv->is_611x) {
1122 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1123 NISTC_AI_STATUS1_FIFO_E) == 0) {
1124 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1126 /* This may get the hi/lo data in the wrong order */
1128 comedi_buf_write_samples(s, &data, 1);
1130 comedi_buf_write_samples(s, &data, 1);
1132 } else if (devpriv->is_6143) {
1134 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1135 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1137 /* This may get the hi/lo data in the wrong order */
1139 comedi_buf_write_samples(s, &data, 1);
1141 comedi_buf_write_samples(s, &data, 1);
1144 /* Check if stranded sample is present */
1145 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1146 /* Get stranded sample into FIFO */
1147 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1148 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1149 data = (dl >> 16) & 0xffff;
1150 comedi_buf_write_samples(s, &data, 1);
1154 unsigned short fe; /* fifo empty */
1156 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1157 NISTC_AI_STATUS1_FIFO_E;
1160 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1161 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1162 NISTC_AI_STATUS1_FIFO_E;
1165 devpriv->ai_fifo_buffer[i] =
1166 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1168 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1173 static void get_last_sample_611x(struct comedi_device *dev)
1175 struct ni_private *devpriv = dev->private;
1176 struct comedi_subdevice *s = dev->read_subdev;
1177 unsigned short data;
1180 if (!devpriv->is_611x)
1183 /* Check if there's a single sample stuck in the FIFO */
1184 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1185 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1187 comedi_buf_write_samples(s, &data, 1);
1191 static void get_last_sample_6143(struct comedi_device *dev)
1193 struct ni_private *devpriv = dev->private;
1194 struct comedi_subdevice *s = dev->read_subdev;
1195 unsigned short data;
1198 if (!devpriv->is_6143)
1201 /* Check if there's a single sample stuck in the FIFO */
1202 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1203 /* Get stranded sample into FIFO */
1204 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1205 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1207 /* This may get the hi/lo data in the wrong order */
1208 data = (dl >> 16) & 0xffff;
1209 comedi_buf_write_samples(s, &data, 1);
1213 static void shutdown_ai_command(struct comedi_device *dev)
1215 struct comedi_subdevice *s = dev->read_subdev;
1218 ni_ai_drain_dma(dev);
1220 ni_handle_fifo_dregs(dev);
1221 get_last_sample_611x(dev);
1222 get_last_sample_6143(dev);
1224 s->async->events |= COMEDI_CB_EOA;
1227 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1229 struct ni_private *devpriv = dev->private;
1231 if (devpriv->aimode == AIMODE_SCAN) {
1233 static const int timeout = 10;
1236 for (i = 0; i < timeout; i++) {
1237 ni_sync_ai_dma(dev);
1238 if ((s->async->events & COMEDI_CB_EOS))
1243 ni_handle_fifo_dregs(dev);
1244 s->async->events |= COMEDI_CB_EOS;
1247 /* handle special case of single scan */
1248 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1249 shutdown_ai_command(dev);
1252 static void handle_gpct_interrupt(struct comedi_device *dev,
1253 unsigned short counter_index)
1256 struct ni_private *devpriv = dev->private;
1257 struct comedi_subdevice *s;
1259 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1261 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1263 comedi_handle_events(dev, s);
1267 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1269 unsigned short ack = 0;
1271 if (a_status & NISTC_AI_STATUS1_SC_TC)
1272 ack |= NISTC_INTA_ACK_AI_SC_TC;
1273 if (a_status & NISTC_AI_STATUS1_START1)
1274 ack |= NISTC_INTA_ACK_AI_START1;
1275 if (a_status & NISTC_AI_STATUS1_START)
1276 ack |= NISTC_INTA_ACK_AI_START;
1277 if (a_status & NISTC_AI_STATUS1_STOP)
1278 ack |= NISTC_INTA_ACK_AI_STOP;
1279 if (a_status & NISTC_AI_STATUS1_OVER)
1280 ack |= NISTC_INTA_ACK_AI_ERR;
1282 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1285 static void handle_a_interrupt(struct comedi_device *dev,
1286 struct comedi_subdevice *s,
1287 unsigned short status)
1289 struct comedi_cmd *cmd = &s->async->cmd;
1291 /* test for all uncommon interrupt events at the same time */
1292 if (status & (NISTC_AI_STATUS1_ERR |
1293 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1294 if (status == 0xffff) {
1295 dev_err(dev->class_dev, "Card removed?\n");
1297 * We probably aren't even running a command now,
1298 * so it's a good idea to be careful.
1300 if (comedi_is_subdevice_running(s))
1301 s->async->events |= COMEDI_CB_ERROR;
1304 if (status & NISTC_AI_STATUS1_ERR) {
1305 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1308 shutdown_ai_command(dev);
1310 s->async->events |= COMEDI_CB_ERROR;
1311 if (status & NISTC_AI_STATUS1_OVER)
1312 s->async->events |= COMEDI_CB_OVERFLOW;
1315 if (status & NISTC_AI_STATUS1_SC_TC) {
1316 if (cmd->stop_src == TRIG_COUNT)
1317 shutdown_ai_command(dev);
1321 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1323 static const int timeout = 10;
1325 * PCMCIA cards (at least 6036) seem to stop producing
1326 * interrupts if we fail to get the fifo less than half
1327 * full, so loop to be sure.
1329 for (i = 0; i < timeout; ++i) {
1330 ni_handle_fifo_half_full(dev);
1331 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1332 NISTC_AI_STATUS1_FIFO_HF) == 0)
1336 #endif /* !PCIDMA */
1338 if (status & NISTC_AI_STATUS1_STOP)
1339 ni_handle_eos(dev, s);
1342 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1344 unsigned short ack = 0;
1346 if (b_status & NISTC_AO_STATUS1_BC_TC)
1347 ack |= NISTC_INTB_ACK_AO_BC_TC;
1348 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1349 ack |= NISTC_INTB_ACK_AO_ERR;
1350 if (b_status & NISTC_AO_STATUS1_START)
1351 ack |= NISTC_INTB_ACK_AO_START;
1352 if (b_status & NISTC_AO_STATUS1_START1)
1353 ack |= NISTC_INTB_ACK_AO_START1;
1354 if (b_status & NISTC_AO_STATUS1_UC_TC)
1355 ack |= NISTC_INTB_ACK_AO_UC_TC;
1356 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1357 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1358 if (b_status & NISTC_AO_STATUS1_UPDATE)
1359 ack |= NISTC_INTB_ACK_AO_UPDATE;
1361 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1364 static void handle_b_interrupt(struct comedi_device *dev,
1365 struct comedi_subdevice *s,
1366 unsigned short b_status)
1368 if (b_status == 0xffff)
1370 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1371 dev_err(dev->class_dev,
1372 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1373 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1374 s->async->events |= COMEDI_CB_OVERFLOW;
1377 if (s->async->cmd.stop_src != TRIG_NONE &&
1378 b_status & NISTC_AO_STATUS1_BC_TC)
1379 s->async->events |= COMEDI_CB_EOA;
1382 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1385 ret = ni_ao_fifo_half_empty(dev, s);
1387 dev_err(dev->class_dev, "AO buffer underrun\n");
1388 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1389 NISTC_INTB_ENA_AO_FIFO |
1390 NISTC_INTB_ENA_AO_ERR, 0);
1391 s->async->events |= COMEDI_CB_OVERFLOW;
1397 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1398 void *data, unsigned int num_bytes,
1399 unsigned int chan_index)
1401 struct ni_private *devpriv = dev->private;
1402 struct comedi_async *async = s->async;
1403 struct comedi_cmd *cmd = &async->cmd;
1404 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1405 unsigned short *array = data;
1406 unsigned int *larray = data;
1409 __le16 *barray = data;
1410 __le32 *blarray = data;
1413 for (i = 0; i < nsamples; i++) {
1415 if (s->subdev_flags & SDF_LSAMPL)
1416 larray[i] = le32_to_cpu(blarray[i]);
1418 array[i] = le16_to_cpu(barray[i]);
1420 if (s->subdev_flags & SDF_LSAMPL)
1421 larray[i] += devpriv->ai_offset[chan_index];
1423 array[i] += devpriv->ai_offset[chan_index];
1425 chan_index %= cmd->chanlist_len;
1431 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1433 struct ni_private *devpriv = dev->private;
1434 struct comedi_subdevice *s = dev->read_subdev;
1436 unsigned long flags;
1438 retval = ni_request_ai_mite_channel(dev);
1442 /* write alloc the entire buffer */
1443 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1445 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1446 if (!devpriv->ai_mite_chan) {
1447 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1451 if (devpriv->is_611x || devpriv->is_6143)
1452 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1453 else if (devpriv->is_628x)
1454 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1456 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1459 mite_dma_arm(devpriv->ai_mite_chan);
1460 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1465 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1467 struct ni_private *devpriv = dev->private;
1468 struct comedi_subdevice *s = dev->write_subdev;
1470 unsigned long flags;
1472 retval = ni_request_ao_mite_channel(dev);
1476 /* read alloc the entire buffer */
1477 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1479 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1480 if (devpriv->ao_mite_chan) {
1481 if (devpriv->is_611x || devpriv->is_6713) {
1482 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1485 * Doing 32 instead of 16 bit wide transfers from
1486 * memory makes the mite do 32 bit pci transfers,
1487 * doubling pci bandwidth.
1489 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1491 mite_dma_arm(devpriv->ao_mite_chan);
1495 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1503 * used for both cancel ioctl and board initialization
1505 * this is pretty harsh for a cancel, but it works...
1507 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1509 struct ni_private *devpriv = dev->private;
1510 unsigned int ai_personal;
1511 unsigned int ai_out_ctrl;
1513 ni_release_ai_mite_channel(dev);
1514 /* ai configuration */
1515 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1518 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1520 ni_clear_ai_fifo(dev);
1522 if (!devpriv->is_6143)
1523 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1525 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1526 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1528 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1529 NISTC_AI_MODE1_REG);
1530 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1531 /* generate FIFO interrupts on non-empty */
1532 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1533 NISTC_AI_MODE3_REG);
1535 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1536 NISTC_AI_PERSONAL_SOC_POLARITY |
1537 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1538 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1539 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1540 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1541 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1542 if (devpriv->is_611x) {
1543 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1544 } else if (devpriv->is_6143) {
1545 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1547 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1548 if (devpriv->is_622x)
1549 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1551 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1553 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1554 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1556 /* the following registers should not be changed, because there
1557 * are no backup registers in devpriv. If you want to change
1558 * any of these, add a backup register and other appropriate code:
1559 * NISTC_AI_MODE1_REG
1560 * NISTC_AI_MODE3_REG
1561 * NISTC_AI_PERSONAL_REG
1562 * NISTC_AI_OUT_CTRL_REG
1565 /* clear interrupts */
1566 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1568 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1573 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1575 unsigned long flags;
1578 /* lock to avoid race with interrupt handler */
1579 spin_lock_irqsave(&dev->spinlock, flags);
1581 ni_handle_fifo_dregs(dev);
1583 ni_sync_ai_dma(dev);
1585 count = comedi_buf_n_bytes_ready(s);
1586 spin_unlock_irqrestore(&dev->spinlock, flags);
1591 static void ni_prime_channelgain_list(struct comedi_device *dev)
1595 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1596 for (i = 0; i < NI_TIMEOUT; ++i) {
1597 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1598 NISTC_AI_STATUS1_FIFO_E)) {
1599 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1604 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1607 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1608 unsigned int n_chan,
1611 const struct ni_board_struct *board = dev->board_ptr;
1612 struct ni_private *devpriv = dev->private;
1613 unsigned int chan, range, aref;
1615 unsigned int dither;
1616 unsigned int range_code;
1618 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1620 if ((list[0] & CR_ALT_SOURCE)) {
1621 unsigned int bypass_bits;
1623 chan = CR_CHAN(list[0]);
1624 range = CR_RANGE(list[0]);
1625 range_code = ni_gainlkup[board->gainlkup][range];
1626 dither = (list[0] & CR_ALT_FILTER) != 0;
1627 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1628 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1629 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1630 devpriv->ai_calib_source;
1632 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1633 /* don't use 2's complement encoding */
1634 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1635 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1637 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1639 for (i = 0; i < n_chan; i++) {
1640 unsigned int config_bits = 0;
1642 chan = CR_CHAN(list[i]);
1643 aref = CR_AREF(list[i]);
1644 range = CR_RANGE(list[i]);
1645 dither = (list[i] & CR_ALT_FILTER) != 0;
1647 range_code = ni_gainlkup[board->gainlkup][range];
1648 devpriv->ai_offset[i] = 0;
1651 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1654 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1657 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1662 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1663 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1664 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1665 if (i == n_chan - 1)
1666 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1668 config_bits |= NI_M_AI_CFG_DITHER;
1669 /* don't use 2's complement encoding */
1670 config_bits |= NI_M_AI_CFG_POLARITY;
1671 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1673 ni_prime_channelgain_list(dev);
1677 * Notes on the 6110 and 6111:
1678 * These boards a slightly different than the rest of the series, since
1679 * they have multiple A/D converters.
1680 * From the driver side, the configuration memory is a
1682 * Configuration Memory Low:
1684 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1685 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1686 * 1001 gain=0.1 (+/- 50)
1695 * Configuration Memory High:
1696 * bits 12-14: Channel Type
1697 * 001 for differential
1698 * 000 for calibration
1699 * bit 11: coupling (this is not currently handled)
1703 * valid channels are 0-3
1705 static void ni_load_channelgain_list(struct comedi_device *dev,
1706 struct comedi_subdevice *s,
1707 unsigned int n_chan, unsigned int *list)
1709 const struct ni_board_struct *board = dev->board_ptr;
1710 struct ni_private *devpriv = dev->private;
1711 unsigned int offset = (s->maxdata + 1) >> 1;
1712 unsigned int chan, range, aref;
1714 unsigned int hi, lo;
1715 unsigned int dither;
1717 if (devpriv->is_m_series) {
1718 ni_m_series_load_channelgain_list(dev, n_chan, list);
1721 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1722 if (devpriv->changain_state &&
1723 devpriv->changain_spec == list[0]) {
1727 devpriv->changain_state = 1;
1728 devpriv->changain_spec = list[0];
1730 devpriv->changain_state = 0;
1733 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1735 /* Set up Calibration mode if required */
1736 if (devpriv->is_6143) {
1737 if ((list[0] & CR_ALT_SOURCE) &&
1738 !devpriv->ai_calib_source_enabled) {
1739 /* Strobe Relay enable bit */
1740 ni_writew(dev, devpriv->ai_calib_source |
1741 NI6143_CALIB_CHAN_RELAY_ON,
1742 NI6143_CALIB_CHAN_REG);
1743 ni_writew(dev, devpriv->ai_calib_source,
1744 NI6143_CALIB_CHAN_REG);
1745 devpriv->ai_calib_source_enabled = 1;
1746 /* Allow relays to change */
1747 msleep_interruptible(100);
1748 } else if (!(list[0] & CR_ALT_SOURCE) &&
1749 devpriv->ai_calib_source_enabled) {
1750 /* Strobe Relay disable bit */
1751 ni_writew(dev, devpriv->ai_calib_source |
1752 NI6143_CALIB_CHAN_RELAY_OFF,
1753 NI6143_CALIB_CHAN_REG);
1754 ni_writew(dev, devpriv->ai_calib_source,
1755 NI6143_CALIB_CHAN_REG);
1756 devpriv->ai_calib_source_enabled = 0;
1757 /* Allow relays to change */
1758 msleep_interruptible(100);
1762 for (i = 0; i < n_chan; i++) {
1763 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1764 chan = devpriv->ai_calib_source;
1766 chan = CR_CHAN(list[i]);
1767 aref = CR_AREF(list[i]);
1768 range = CR_RANGE(list[i]);
1769 dither = (list[i] & CR_ALT_FILTER) != 0;
1771 /* fix the external/internal range differences */
1772 range = ni_gainlkup[board->gainlkup][range];
1773 if (devpriv->is_611x)
1774 devpriv->ai_offset[i] = offset;
1776 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1779 if ((list[i] & CR_ALT_SOURCE)) {
1780 if (devpriv->is_611x)
1781 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1782 NI611X_CALIB_CHAN_SEL_REG);
1784 if (devpriv->is_611x)
1786 else if (devpriv->is_6143)
1790 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1793 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1796 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1802 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1804 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1806 if (!devpriv->is_6143) {
1807 lo = NI_E_AI_CFG_LO_GAIN(range);
1809 if (i == n_chan - 1)
1810 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1812 lo |= NI_E_AI_CFG_LO_DITHER;
1814 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1818 /* prime the channel/gain list */
1819 if (!devpriv->is_611x && !devpriv->is_6143)
1820 ni_prime_channelgain_list(dev);
1823 static int ni_ai_insn_read(struct comedi_device *dev,
1824 struct comedi_subdevice *s,
1825 struct comedi_insn *insn,
1828 struct ni_private *devpriv = dev->private;
1829 unsigned int mask = s->maxdata;
1831 unsigned int signbits;
1834 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1836 ni_clear_ai_fifo(dev);
1838 signbits = devpriv->ai_offset[0];
1839 if (devpriv->is_611x) {
1840 for (n = 0; n < num_adc_stages_611x; n++) {
1841 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1845 for (n = 0; n < insn->n; n++) {
1846 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1848 /* The 611x has screwy 32-bit FIFOs. */
1850 for (i = 0; i < NI_TIMEOUT; i++) {
1851 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1853 NI611X_AI_FIFO_DATA_REG);
1858 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1859 NISTC_AI_STATUS1_FIFO_E)) {
1861 NI611X_AI_FIFO_DATA_REG);
1866 if (i == NI_TIMEOUT) {
1867 dev_err(dev->class_dev, "timeout\n");
1871 data[n] = d & 0xffff;
1873 } else if (devpriv->is_6143) {
1874 for (n = 0; n < insn->n; n++) {
1875 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1879 * The 6143 has 32-bit FIFOs. You need to strobe a
1880 * bit to move a single 16bit stranded sample into
1884 for (i = 0; i < NI_TIMEOUT; i++) {
1885 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1887 /* Get stranded sample into FIFO */
1888 ni_writel(dev, 0x01,
1889 NI6143_AI_FIFO_CTRL_REG);
1891 NI6143_AI_FIFO_DATA_REG);
1895 if (i == NI_TIMEOUT) {
1896 dev_err(dev->class_dev, "timeout\n");
1899 data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1902 for (n = 0; n < insn->n; n++) {
1903 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1905 for (i = 0; i < NI_TIMEOUT; i++) {
1906 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1907 NISTC_AI_STATUS1_FIFO_E))
1910 if (i == NI_TIMEOUT) {
1911 dev_err(dev->class_dev, "timeout\n");
1914 if (devpriv->is_m_series) {
1915 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1919 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1921 data[n] = d & 0xffff;
1928 static int ni_ns_to_timer(const struct comedi_device *dev,
1929 unsigned int nanosec, unsigned int flags)
1931 struct ni_private *devpriv = dev->private;
1934 switch (flags & CMDF_ROUND_MASK) {
1935 case CMDF_ROUND_NEAREST:
1937 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1939 case CMDF_ROUND_DOWN:
1940 divider = (nanosec) / devpriv->clock_ns;
1943 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1949 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1951 struct ni_private *devpriv = dev->private;
1953 return devpriv->clock_ns * (timer + 1);
1956 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1957 struct comedi_subdevice *sdev,
1958 const struct comedi_cmd *cmd,
1959 unsigned int max_count)
1962 unsigned int nbytes = max_count;
1964 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1965 nbytes = cmd->stop_arg;
1966 nbytes *= comedi_bytes_per_scan(sdev);
1968 if (nbytes > sdev->async->prealloc_bufsz) {
1969 if (cmd->stop_arg > 0)
1970 dev_err(sdev->device->class_dev,
1971 "%s: tried exact data transfer limits greater than buffer size\n",
1975 * we can only transfer up to the size of the buffer. In this
1976 * case, the user is expected to continue to write into the
1977 * comedi buffer (already implemented as a ring buffer).
1979 nbytes = sdev->async->prealloc_bufsz;
1982 mite_init_ring_descriptors(ring, sdev, nbytes);
1984 dev_err(sdev->device->class_dev,
1985 "%s: exact data transfer limits not implemented yet without DMA\n",
1990 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1991 unsigned int num_channels)
1993 const struct ni_board_struct *board = dev->board_ptr;
1994 struct ni_private *devpriv = dev->private;
1996 /* simultaneously-sampled inputs */
1997 if (devpriv->is_611x || devpriv->is_6143)
1998 return board->ai_speed;
2000 /* multiplexed inputs */
2001 return board->ai_speed * num_channels;
2004 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2005 struct comedi_cmd *cmd)
2007 const struct ni_board_struct *board = dev->board_ptr;
2008 struct ni_private *devpriv = dev->private;
2010 unsigned int sources;
2012 /* Step 1 : check if triggers are trivially valid */
2014 err |= comedi_check_trigger_src(&cmd->start_src,
2015 TRIG_NOW | TRIG_INT | TRIG_EXT);
2016 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2017 TRIG_TIMER | TRIG_EXT);
2019 sources = TRIG_TIMER | TRIG_EXT;
2020 if (devpriv->is_611x || devpriv->is_6143)
2021 sources |= TRIG_NOW;
2022 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2024 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2025 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2030 /* Step 2a : make sure trigger sources are unique */
2032 err |= comedi_check_trigger_is_unique(cmd->start_src);
2033 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2034 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2035 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2037 /* Step 2b : and mutually compatible */
2042 /* Step 3: check if arguments are trivially valid */
2044 switch (cmd->start_src) {
2047 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2050 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
2052 &devpriv->routing_tables, 1);
2056 if (cmd->scan_begin_src == TRIG_TIMER) {
2057 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2058 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2059 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2062 } else if (cmd->scan_begin_src == TRIG_EXT) {
2063 /* external trigger */
2064 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg),
2066 &devpriv->routing_tables, 1);
2067 } else { /* TRIG_OTHER */
2068 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2071 if (cmd->convert_src == TRIG_TIMER) {
2072 if (devpriv->is_611x || devpriv->is_6143) {
2073 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2076 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2078 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2082 } else if (cmd->convert_src == TRIG_EXT) {
2083 /* external trigger */
2084 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg),
2086 &devpriv->routing_tables, 1);
2087 } else if (cmd->convert_src == TRIG_NOW) {
2088 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2091 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2094 if (cmd->stop_src == TRIG_COUNT) {
2095 unsigned int max_count = 0x01000000;
2097 if (devpriv->is_611x)
2098 max_count -= num_adc_stages_611x;
2099 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2100 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2103 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2109 /* step 4: fix up any arguments */
2111 if (cmd->scan_begin_src == TRIG_TIMER) {
2112 unsigned int tmp = cmd->scan_begin_arg;
2113 cmd->scan_begin_arg =
2114 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2115 cmd->scan_begin_arg,
2117 if (tmp != cmd->scan_begin_arg)
2120 if (cmd->convert_src == TRIG_TIMER) {
2121 if (!devpriv->is_611x && !devpriv->is_6143) {
2122 unsigned int tmp = cmd->convert_arg;
2124 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2127 if (tmp != cmd->convert_arg)
2129 if (cmd->scan_begin_src == TRIG_TIMER &&
2130 cmd->scan_begin_arg <
2131 cmd->convert_arg * cmd->scan_end_arg) {
2132 cmd->scan_begin_arg =
2133 cmd->convert_arg * cmd->scan_end_arg;
2145 static int ni_ai_inttrig(struct comedi_device *dev,
2146 struct comedi_subdevice *s,
2147 unsigned int trig_num)
2149 struct ni_private *devpriv = dev->private;
2150 struct comedi_cmd *cmd = &s->async->cmd;
2152 if (trig_num != cmd->start_arg)
2155 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2157 s->async->inttrig = NULL;
2162 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2164 struct ni_private *devpriv = dev->private;
2165 const struct comedi_cmd *cmd = &s->async->cmd;
2167 int mode1 = 0; /* mode1 is needed for both stop and convert */
2169 int start_stop_select = 0;
2170 unsigned int stop_count;
2171 int interrupt_a_enable = 0;
2172 unsigned int ai_trig;
2174 if (dev->irq == 0) {
2175 dev_err(dev->class_dev, "cannot run command without an irq\n");
2178 ni_clear_ai_fifo(dev);
2180 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2182 /* start configuration */
2183 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2186 * Disable analog triggering for now, since it interferes
2187 * with the use of pfi0.
2189 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2190 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2192 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2193 switch (cmd->start_src) {
2196 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2197 NISTC_AI_TRIG_START1_SEL(0);
2200 ai_trig |= NISTC_AI_TRIG_START1_SEL(
2201 ni_get_reg_value_roffs(CR_CHAN(cmd->start_arg),
2203 &devpriv->routing_tables, 1));
2205 if (cmd->start_arg & CR_INVERT)
2206 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2207 if (cmd->start_arg & CR_EDGE)
2208 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2211 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2213 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2214 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2215 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2216 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2218 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2220 start_stop_select |= NISTC_AI_STOP_POLARITY |
2221 NISTC_AI_STOP_SEL(31) |
2224 /* ai configuration memory */
2225 start_stop_select |= NISTC_AI_STOP_SEL(19);
2227 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2229 devpriv->ai_cmd2 = 0;
2230 switch (cmd->stop_src) {
2232 stop_count = cmd->stop_arg - 1;
2234 if (devpriv->is_611x) {
2235 /* have to take 3 stage adc pipeline into account */
2236 stop_count += num_adc_stages_611x;
2238 /* stage number of scans */
2239 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2241 mode1 |= NISTC_AI_MODE1_START_STOP |
2242 NISTC_AI_MODE1_RSVD |
2243 NISTC_AI_MODE1_TRIGGER_ONCE;
2244 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2245 /* load SC (Scan Count) */
2246 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2248 if (stop_count == 0) {
2249 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2250 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2252 * This is required to get the last sample for
2253 * chanlist_len > 1, not sure why.
2255 if (cmd->chanlist_len > 1)
2256 start_stop_select |= NISTC_AI_STOP_POLARITY |
2261 /* stage number of scans */
2262 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2264 mode1 |= NISTC_AI_MODE1_START_STOP |
2265 NISTC_AI_MODE1_RSVD |
2266 NISTC_AI_MODE1_CONTINUOUS;
2267 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2269 /* load SC (Scan Count) */
2270 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2274 switch (cmd->scan_begin_src) {
2277 * stop bits for non 611x boards
2278 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2279 * NISTC_AI_MODE2_PRE_TRIGGER=0
2280 * NISTC_AI_START_STOP_REG:
2281 * NISTC_AI_START_POLARITY=0 (?) rising edge
2282 * NISTC_AI_START_EDGE=1 edge triggered
2283 * NISTC_AI_START_SYNC=1 (?)
2284 * NISTC_AI_START_SEL=0 SI_TC
2285 * NISTC_AI_STOP_POLARITY=0 rising edge
2286 * NISTC_AI_STOP_EDGE=0 level
2287 * NISTC_AI_STOP_SYNC=1
2288 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2290 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2291 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2293 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2294 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2295 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2296 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2299 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2300 CMDF_ROUND_NEAREST);
2301 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2302 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2305 if (cmd->scan_begin_arg & CR_EDGE)
2306 start_stop_select |= NISTC_AI_START_EDGE;
2307 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2308 start_stop_select |= NISTC_AI_START_POLARITY;
2309 if (cmd->scan_begin_src != cmd->convert_src ||
2310 (cmd->scan_begin_arg & ~CR_EDGE) !=
2311 (cmd->convert_arg & ~CR_EDGE))
2312 start_stop_select |= NISTC_AI_START_SYNC;
2313 start_stop_select |= NISTC_AI_START_SEL(
2314 ni_get_reg_value_roffs(CR_CHAN(cmd->scan_begin_arg),
2316 &devpriv->routing_tables, 1));
2317 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2321 switch (cmd->convert_src) {
2324 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2327 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2328 CMDF_ROUND_NEAREST);
2329 /* 0,0 does not work */
2330 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2331 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2333 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2334 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2335 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2337 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2339 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2340 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2341 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2344 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(
2345 ni_get_reg_value_roffs(CR_CHAN(cmd->convert_arg),
2347 &devpriv->routing_tables, 1));
2348 if ((cmd->convert_arg & CR_INVERT) == 0)
2349 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2350 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2352 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2353 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2354 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2360 /* interrupt on FIFO, errors, SC_TC */
2361 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2362 NISTC_INTA_ENA_AI_SC_TC;
2365 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2368 if ((cmd->flags & CMDF_WAKE_EOS) ||
2369 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2370 /* wake on end-of-scan */
2371 devpriv->aimode = AIMODE_SCAN;
2373 devpriv->aimode = AIMODE_HALF_FULL;
2376 switch (devpriv->aimode) {
2377 case AIMODE_HALF_FULL:
2378 /* FIFO interrupts and DMA requests on half-full */
2380 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2381 NISTC_AI_MODE3_REG);
2383 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2384 NISTC_AI_MODE3_REG);
2388 /*generate FIFO interrupts on non-empty */
2389 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2390 NISTC_AI_MODE3_REG);
2394 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2395 NISTC_AI_MODE3_REG);
2397 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2398 NISTC_AI_MODE3_REG);
2400 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2406 /* clear interrupts */
2407 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2409 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2411 /* interrupt on nothing */
2412 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2414 /* XXX start polling if necessary */
2417 /* end configuration */
2418 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2420 switch (cmd->scan_begin_src) {
2422 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2423 NISTC_AI_CMD1_SI_ARM |
2424 NISTC_AI_CMD1_DIV_ARM |
2425 NISTC_AI_CMD1_SC_ARM,
2429 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2430 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2431 NISTC_AI_CMD1_DIV_ARM |
2432 NISTC_AI_CMD1_SC_ARM,
2439 int retval = ni_ai_setup_MITE_dma(dev);
2446 if (cmd->start_src == TRIG_NOW) {
2447 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2450 s->async->inttrig = NULL;
2451 } else if (cmd->start_src == TRIG_EXT) {
2452 s->async->inttrig = NULL;
2453 } else { /* TRIG_INT */
2454 s->async->inttrig = ni_ai_inttrig;
2460 static int ni_ai_insn_config(struct comedi_device *dev,
2461 struct comedi_subdevice *s,
2462 struct comedi_insn *insn, unsigned int *data)
2464 const struct ni_board_struct *board = dev->board_ptr;
2465 struct ni_private *devpriv = dev->private;
2471 case INSN_CONFIG_ALT_SOURCE:
2472 if (devpriv->is_m_series) {
2473 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2475 devpriv->ai_calib_source = data[1];
2476 } else if (devpriv->is_6143) {
2477 unsigned int calib_source;
2479 calib_source = data[1] & 0xf;
2481 devpriv->ai_calib_source = calib_source;
2482 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2484 unsigned int calib_source;
2485 unsigned int calib_source_adjust;
2487 calib_source = data[1] & 0xf;
2488 calib_source_adjust = (data[1] >> 4) & 0xff;
2490 if (calib_source >= 8)
2492 devpriv->ai_calib_source = calib_source;
2493 if (devpriv->is_611x) {
2494 ni_writeb(dev, calib_source_adjust,
2495 NI611X_CAL_GAIN_SEL_REG);
2499 case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2500 /* we don't care about actual channels */
2501 /* data[3] : chanlist_len */
2502 data[1] = ni_min_ai_scan_period_ns(dev, data[3]);
2503 if (devpriv->is_611x || devpriv->is_6143)
2504 data[2] = 0; /* simultaneous output */
2506 data[2] = board->ai_speed;
2515 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2516 void *data, unsigned int num_bytes,
2517 unsigned int chan_index)
2519 struct comedi_cmd *cmd = &s->async->cmd;
2520 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2521 unsigned short *array = data;
2524 __le16 buf, *barray = data;
2527 for (i = 0; i < nsamples; i++) {
2528 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2529 unsigned short val = array[i];
2532 * Munge data from unsigned to two's complement for
2535 if (comedi_range_is_bipolar(s, range))
2536 val = comedi_offset_munge(s, val);
2538 buf = cpu_to_le16(val);
2544 chan_index %= cmd->chanlist_len;
2548 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2549 struct comedi_subdevice *s,
2550 unsigned int chanspec[],
2551 unsigned int n_chans, int timed)
2553 struct ni_private *devpriv = dev->private;
2561 for (i = 0; i < s->n_chan; ++i) {
2562 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2563 ni_writeb(dev, devpriv->ao_conf[i],
2564 NI_M_AO_CFG_BANK_REG(i));
2565 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2568 for (i = 0; i < n_chans; i++) {
2569 const struct comedi_krange *krange;
2571 chan = CR_CHAN(chanspec[i]);
2572 range = CR_RANGE(chanspec[i]);
2573 krange = s->range_table->range + range;
2576 switch (krange->max - krange->min) {
2578 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2579 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2582 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2583 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2586 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2587 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2588 NI_M_AO_REF_ATTENUATION_REG(chan));
2591 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2592 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2593 NI_M_AO_REF_ATTENUATION_REG(chan));
2596 dev_err(dev->class_dev,
2597 "bug! unhandled ao reference voltage\n");
2600 switch (krange->max + krange->min) {
2602 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2605 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2608 dev_err(dev->class_dev,
2609 "bug! unhandled ao offset voltage\n");
2613 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2614 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2615 devpriv->ao_conf[chan] = conf;
2616 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2621 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2622 struct comedi_subdevice *s,
2623 unsigned int chanspec[],
2624 unsigned int n_chans)
2626 struct ni_private *devpriv = dev->private;
2633 for (i = 0; i < n_chans; i++) {
2634 chan = CR_CHAN(chanspec[i]);
2635 range = CR_RANGE(chanspec[i]);
2636 conf = NI_E_AO_DACSEL(chan);
2638 if (comedi_range_is_bipolar(s, range)) {
2639 conf |= NI_E_AO_CFG_BIP;
2640 invert = (s->maxdata + 1) >> 1;
2644 if (comedi_range_is_external(s, range))
2645 conf |= NI_E_AO_EXT_REF;
2647 /* not all boards can deglitch, but this shouldn't hurt */
2648 if (chanspec[i] & CR_DEGLITCH)
2649 conf |= NI_E_AO_DEGLITCH;
2651 /* analog reference */
2652 /* AREF_OTHER connects AO ground to AI ground, i think */
2653 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2654 conf |= NI_E_AO_GROUND_REF;
2656 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2657 devpriv->ao_conf[chan] = conf;
2662 static int ni_ao_config_chanlist(struct comedi_device *dev,
2663 struct comedi_subdevice *s,
2664 unsigned int chanspec[], unsigned int n_chans,
2667 struct ni_private *devpriv = dev->private;
2669 if (devpriv->is_m_series)
2670 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2673 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2676 static int ni_ao_insn_write(struct comedi_device *dev,
2677 struct comedi_subdevice *s,
2678 struct comedi_insn *insn,
2681 struct ni_private *devpriv = dev->private;
2682 unsigned int chan = CR_CHAN(insn->chanspec);
2683 unsigned int range = CR_RANGE(insn->chanspec);
2687 if (devpriv->is_6xxx) {
2688 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2690 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2691 } else if (devpriv->is_m_series) {
2692 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2694 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2697 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2699 for (i = 0; i < insn->n; i++) {
2700 unsigned int val = data[i];
2702 s->readback[chan] = val;
2704 if (devpriv->is_6xxx) {
2706 * 6xxx boards have bipolar outputs, munge the
2707 * unsigned comedi values to 2's complement
2709 val = comedi_offset_munge(s, val);
2711 ni_ao_win_outw(dev, val, reg);
2712 } else if (devpriv->is_m_series) {
2714 * M-series boards use offset binary values for
2715 * bipolar and uinpolar outputs
2717 ni_writew(dev, val, reg);
2720 * Non-M series boards need two's complement values
2721 * for bipolar ranges.
2723 if (comedi_range_is_bipolar(s, range))
2724 val = comedi_offset_munge(s, val);
2726 ni_writew(dev, val, reg);
2734 * Arms the AO device in preparation for a trigger event.
2735 * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2736 * not used). As a part of this preparation, this function preloads the DAC
2737 * registers with the first values of the output stream. This ensures that the
2738 * first clock cycle after the trigger can be used for output.
2740 * Note that this function _must_ happen after a user has written data to the
2741 * output buffers via either mmap or write(fileno,...).
2743 static int ni_ao_arm(struct comedi_device *dev,
2744 struct comedi_subdevice *s)
2746 struct ni_private *devpriv = dev->private;
2748 int interrupt_b_bits;
2750 static const int timeout = 1000;
2753 * Prevent ao from doing things like trying to allocate the ao dma
2754 * channel multiple times.
2756 if (!devpriv->ao_needs_arming) {
2757 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2762 devpriv->ao_needs_arming = 0;
2764 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2765 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2766 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2768 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2769 if (devpriv->is_6xxx)
2770 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2771 ret = ni_ao_setup_MITE_dma(dev);
2774 ret = ni_ao_wait_for_dma_load(dev);
2778 ret = ni_ao_prep_fifo(dev, s);
2782 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2785 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2786 NISTC_AO_MODE3_REG);
2787 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2788 /* wait for DACs to be loaded */
2789 for (i = 0; i < timeout; i++) {
2791 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2792 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2796 dev_err(dev->class_dev,
2797 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2801 * stc manual says we are need to clear error interrupt after
2802 * AO_TMRDACWRs_In_Progress_St clears
2804 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2806 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2808 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2809 NISTC_AO_CMD1_UC_ARM |
2810 NISTC_AO_CMD1_BC_ARM |
2817 static int ni_ao_insn_config(struct comedi_device *dev,
2818 struct comedi_subdevice *s,
2819 struct comedi_insn *insn, unsigned int *data)
2821 const struct ni_board_struct *board = dev->board_ptr;
2822 struct ni_private *devpriv = dev->private;
2823 unsigned int nbytes;
2826 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2829 nbytes = comedi_samples_to_bytes(s,
2830 board->ao_fifo_depth);
2831 data[2] = 1 + nbytes;
2833 data[2] += devpriv->mite->fifo_size;
2842 case INSN_CONFIG_ARM:
2843 return ni_ao_arm(dev, s);
2844 case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2845 /* we don't care about actual channels */
2846 /* data[3] : chanlist_len */
2847 data[1] = board->ao_speed * data[3];
2857 static int ni_ao_inttrig(struct comedi_device *dev,
2858 struct comedi_subdevice *s,
2859 unsigned int trig_num)
2861 struct ni_private *devpriv = dev->private;
2862 struct comedi_cmd *cmd = &s->async->cmd;
2866 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2867 * For backwards compatibility, also allow trig_num == 0 when
2868 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2869 * in that case, the internal trigger is being used as a pre-trigger
2870 * before the external trigger.
2872 if (!(trig_num == cmd->start_arg ||
2873 (trig_num == 0 && cmd->start_src != TRIG_INT)))
2877 * Null trig at beginning prevent ao start trigger from executing more
2878 * than once per command.
2880 s->async->inttrig = NULL;
2882 if (devpriv->ao_needs_arming) {
2883 /* only arm this device if it still needs arming */
2884 ret = ni_ao_arm(dev, s);
2889 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2897 * Organized similar to NI-STC and MHDDK examples.
2898 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2901 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2902 const struct comedi_cmd *cmd)
2904 const struct ni_board_struct *board = dev->board_ptr;
2907 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2910 /* fast CPU interface--only eseries */
2911 /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2912 NISTC_AO_PERSONAL_BC_SRC_SEL |
2913 0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2915 * FIXME: start setting following bit when appropriate. Need to
2916 * determine whether board is E4 or E1.
2918 * if board is E4 or E1
2919 * Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2923 NISTC_AO_PERSONAL_UPDATE_PW |
2924 /* FIXME: when should we set following bit to zero? */
2925 NISTC_AO_PERSONAL_TMRDACWR_PW |
2926 (board->ao_fifo_depth ?
2927 NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2932 * add something like ".has_individual_dacs = 0" to ni_board_struct
2933 * since, as F Hess pointed out, not all in m series have singles. not
2934 * sure if e-series all have duals...
2938 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2939 * 6281, verified with bus analyzer.
2941 if (devpriv->is_m_series)
2942 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2944 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2946 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2949 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2950 const struct comedi_cmd *cmd)
2952 struct ni_private *devpriv = dev->private;
2953 unsigned int trigsel;
2955 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2958 if (cmd->stop_src == TRIG_NONE) {
2959 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2960 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2962 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2963 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2965 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2967 if (cmd->start_src == TRIG_INT) {
2968 trigsel = NISTC_AO_TRIG_START1_EDGE |
2969 NISTC_AO_TRIG_START1_SYNC;
2970 } else { /* TRIG_EXT */
2971 trigsel = NISTC_AO_TRIG_START1_SEL(
2972 ni_get_reg_value_roffs(CR_CHAN(cmd->start_arg),
2974 &devpriv->routing_tables, 1));
2975 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2976 if (cmd->start_arg & CR_INVERT)
2977 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2978 /* 0=edge detection disabled, 1=enabled */
2979 if (cmd->start_arg & CR_EDGE)
2980 trigsel |= NISTC_AO_TRIG_START1_EDGE;
2982 ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2984 /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2987 /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2988 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2989 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2991 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2994 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
2995 const struct comedi_cmd *cmd)
2997 struct ni_private *devpriv = dev->private;
2998 /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3000 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3002 * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3003 * set_trigger above. It is unclear whether we really need to re-write
3004 * this register with these values. The mhddk examples for e-series
3005 * show writing this in both places, but the examples for m-series show
3006 * a single write in the set_counters function (here).
3008 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3010 /* sync (upload number of buffer iterations -1) */
3011 /* indicate that we want to use BC_Load_A_Register as the source */
3012 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3013 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3016 * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3017 * ignoring BC_TC, then we will need to find a way to ignore that
3018 * interrupt in continuous mode.
3020 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3022 /* sync (issue command to load number of buffer iterations -1) */
3023 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3025 /* sync (upload number of updates in buffer) */
3026 /* indicate that we want to use UC_Load_A_Register as the source */
3027 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3028 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3031 * if a user specifies '0', this automatically assumes the entire 24bit
3032 * address space is available for the (multiple iterations of single
3033 * buffer) MISB. Otherwise, stop_arg specifies the MISB length that
3034 * will be used, regardless of whether we are in continuous mode or not.
3035 * In continuous mode, the output will just iterate indefinitely over
3039 unsigned int stop_arg = cmd->stop_arg > 0 ?
3040 (cmd->stop_arg & 0xffffff) : 0xffffff;
3042 if (devpriv->is_m_series) {
3044 * this is how the NI example code does it for m-series
3045 * boards, verified correct with 6259
3047 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3049 /* sync (issue cmd to load number of updates in MISB) */
3050 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3053 ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3055 /* sync (issue cmd to load number of updates in MISB) */
3056 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3060 * sync (upload number of updates-1 in MISB)
3063 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3067 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3070 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3071 const struct comedi_cmd *cmd)
3073 struct ni_private *devpriv = dev->private;
3075 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3078 * zero out these bit fields to be set below. Does an ao-reset do this
3081 devpriv->ao_mode1 &= ~(
3082 NISTC_AO_MODE1_UI_SRC_MASK |
3083 NISTC_AO_MODE1_UI_SRC_POLARITY |
3084 NISTC_AO_MODE1_UPDATE_SRC_MASK |
3085 NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3088 if (cmd->scan_begin_src == TRIG_TIMER) {
3089 unsigned int trigvar;
3091 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3094 * NOTE: there are several other ways of configuring internal
3095 * updates, but we'll only support one for now: using
3096 * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3097 * START1 and first update, and also w/o local buffer mode w/
3102 * This is already done above:
3103 * devpriv->ao_mode1 &= ~(
3104 * // set UPDATE_Source to UI_TC:
3105 * NISTC_AO_MODE1_UPDATE_SRC_MASK |
3106 * // set UPDATE_Source_Polarity to rising (required?)
3107 * NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3108 * // set UI_Source to AO_IN_TIMEBASE1:
3109 * NISTC_AO_MODE1_UI_SRC_MASK |
3110 * // set UI_Source_Polarity to rising (required?)
3111 * NISTC_AO_MODE1_UI_SRC_POLARITY
3116 * TODO: use ao_ui_clock_source to allow all possible signals
3117 * to be routed to UI_Source_Select. See tSTC.h for
3118 * eseries/ni67xx and tMSeries.h for mseries.
3121 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3122 CMDF_ROUND_NEAREST);
3125 * Wait N TB3 ticks after the start trigger before
3126 * clocking (N must be >=2).
3128 /* following line: 2-1 per STC */
3129 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3130 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3131 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3132 } else { /* TRIG_EXT */
3133 /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */
3134 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3135 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3136 ni_get_reg_value(CR_CHAN(cmd->scan_begin_arg),
3138 &devpriv->routing_tables));
3139 if (cmd->scan_begin_arg & CR_INVERT)
3140 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3143 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3144 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3145 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3146 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3147 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3149 /* Configure DAQ-STC for Timed update mode */
3150 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3151 NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3152 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3153 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3155 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3158 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3159 struct comedi_subdevice *s)
3161 struct ni_private *devpriv = dev->private;
3162 const struct comedi_cmd *cmd = &s->async->cmd;
3163 unsigned int bits = 0;
3165 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3167 if (devpriv->is_6xxx) {
3171 for (i = 0; i < cmd->chanlist_len; ++i) {
3172 int chan = CR_CHAN(cmd->chanlist[i]);
3175 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3177 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3180 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3182 if (cmd->scan_end_arg > 1) {
3183 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3184 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3185 | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3188 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3189 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3190 if (devpriv->is_m_series | devpriv->is_6xxx)
3191 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3193 bits |= NISTC_AO_OUT_CTRL_CHANS(
3194 CR_CHAN(cmd->chanlist[0]));
3197 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3198 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3200 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3203 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3204 const struct comedi_cmd *cmd)
3206 struct ni_private *devpriv = dev->private;
3208 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3210 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3211 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3214 * Since we are not supporting waveform staging, we ignore these errors:
3215 * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3216 * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3219 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3222 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3224 struct ni_private *devpriv = dev->private;
3226 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3228 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3230 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3232 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3234 /* NOTE: this is where use_onboard_memory=True would be implemented */
3235 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3236 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3238 /* enable sending of ao fifo requests (dma request) */
3239 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3241 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3243 /* we are not supporting boards with virtual fifos */
3246 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3247 struct comedi_subdevice *s)
3249 if (s->async->cmd.stop_src == TRIG_COUNT)
3250 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3251 NISTC_INTB_ENA_AO_BC_TC, 1);
3253 s->async->inttrig = ni_ao_inttrig;
3256 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3258 struct ni_private *devpriv = dev->private;
3259 const struct comedi_cmd *cmd = &s->async->cmd;
3261 if (dev->irq == 0) {
3262 dev_err(dev->class_dev, "cannot run command without an irq");
3266 /* ni_ao_reset should have already been done */
3267 ni_ao_cmd_personalize(dev, cmd);
3268 /* clearing fifo and preload happens elsewhere */
3270 ni_ao_cmd_set_trigger(dev, cmd);
3271 ni_ao_cmd_set_counters(dev, cmd);
3272 ni_ao_cmd_set_update(dev, cmd);
3273 ni_ao_cmd_set_channels(dev, s);
3274 ni_ao_cmd_set_stop_conditions(dev, cmd);
3275 ni_ao_cmd_set_fifo_mode(dev);
3276 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3277 ni_ao_cmd_set_interrupts(dev, s);
3280 * arm(ing) must happen later so that DMA can be setup and DACs
3281 * preloaded with the actual output buffer before starting.
3283 * start(ing) must happen _after_ arming is completed. Starting can be
3284 * done either via ni_ao_inttrig, or via an external trigger.
3286 * **Currently, ni_ao_inttrig will automatically attempt a call to
3287 * ni_ao_arm if the device still needs arming at that point. This
3288 * allows backwards compatibility.
3290 devpriv->ao_needs_arming = 1;
3296 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3297 struct comedi_cmd *cmd)
3299 const struct ni_board_struct *board = dev->board_ptr;
3300 struct ni_private *devpriv = dev->private;
3304 /* Step 1 : check if triggers are trivially valid */
3306 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3307 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3308 TRIG_TIMER | TRIG_EXT);
3309 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3310 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3311 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3316 /* Step 2a : make sure trigger sources are unique */
3318 err |= comedi_check_trigger_is_unique(cmd->start_src);
3319 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3320 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3322 /* Step 2b : and mutually compatible */
3327 /* Step 3: check if arguments are trivially valid */
3329 switch (cmd->start_src) {
3331 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3334 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
3336 &devpriv->routing_tables, 1);
3340 if (cmd->scan_begin_src == TRIG_TIMER) {
3341 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3343 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3346 } else { /* TRIG_EXT */
3347 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3349 &devpriv->routing_tables);
3352 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3353 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3355 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3360 /* step 4: fix up any arguments */
3361 if (cmd->scan_begin_src == TRIG_TIMER) {
3362 tmp = cmd->scan_begin_arg;
3363 cmd->scan_begin_arg =
3364 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3365 cmd->scan_begin_arg,
3367 if (tmp != cmd->scan_begin_arg)
3376 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3378 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3381 * In the following, the "--sync" comments are meant to denote
3382 * asynchronous boundaries for setting the registers as described in the
3383 * DAQ-STC mostly in the order also described in the DAQ-STC.
3386 struct ni_private *devpriv = dev->private;
3388 ni_release_ao_mite_channel(dev);
3390 /* --sync (reset AO) */
3391 if (devpriv->is_m_series)
3392 /* following example in mhddk for m-series */
3393 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3395 /*--sync (start config) */
3396 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3398 /*--sync (Disarm) */
3399 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3403 * (clear bunch of registers--mseries mhddk examples do not include
3406 devpriv->ao_cmd1 = 0;
3407 devpriv->ao_cmd2 = 0;
3408 devpriv->ao_mode1 = 0;
3409 devpriv->ao_mode2 = 0;
3410 if (devpriv->is_m_series)
3411 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3413 devpriv->ao_mode3 = 0;
3415 ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3416 ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3417 ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3418 ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3419 ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3420 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3421 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3422 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3423 ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3425 /*--sync (disable interrupts) */
3426 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3429 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3430 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3432 /*--not in DAQ-STC. which doc? */
3433 if (devpriv->is_6xxx) {
3434 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3435 NI671X_AO_IMMEDIATE_REG);
3436 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3437 NI611X_AO_MISC_REG);
3439 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3447 static int ni_dio_insn_config(struct comedi_device *dev,
3448 struct comedi_subdevice *s,
3449 struct comedi_insn *insn,
3452 struct ni_private *devpriv = dev->private;
3455 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3459 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3460 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3461 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3466 static int ni_dio_insn_bits(struct comedi_device *dev,
3467 struct comedi_subdevice *s,
3468 struct comedi_insn *insn,
3471 struct ni_private *devpriv = dev->private;
3473 /* Make sure we're not using the serial part of the dio */
3474 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3475 devpriv->serial_interval_ns)
3478 if (comedi_dio_update_state(s, data)) {
3479 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3480 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3481 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3484 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3490 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3491 struct comedi_subdevice *s,
3492 struct comedi_insn *insn,
3497 if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
3498 const struct ni_board_struct *board = dev->board_ptr;
3500 /* we don't care about actual channels */
3501 data[1] = board->dio_speed;
3506 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3510 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3515 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3516 struct comedi_subdevice *s,
3517 struct comedi_insn *insn,
3520 if (comedi_dio_update_state(s, data))
3521 ni_writel(dev, s->state, NI_M_DIO_REG);
3523 data[1] = ni_readl(dev, NI_M_DIO_REG);
3528 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3529 struct comedi_subdevice *s,
3530 struct comedi_cmd *cmd)
3534 for (i = 0; i < cmd->chanlist_len; ++i) {
3535 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3544 static int ni_cdio_cmdtest(struct comedi_device *dev,
3545 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3547 struct ni_private *devpriv = dev->private;
3550 /* Step 1 : check if triggers are trivially valid */
3552 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3553 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3554 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3555 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3556 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3561 /* Step 2a : make sure trigger sources are unique */
3562 /* Step 2b : and mutually compatible */
3564 /* Step 3: check if arguments are trivially valid */
3566 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3569 * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3570 * for completeness, test whether the cmd is output or input?
3572 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3574 &devpriv->routing_tables);
3575 if (CR_RANGE(cmd->scan_begin_arg) != 0 ||
3576 CR_AREF(cmd->scan_begin_arg) != 0)
3579 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3580 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3582 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3583 s->async->prealloc_bufsz /
3584 comedi_bytes_per_scan(s));
3589 /* Step 4: fix up any arguments */
3591 /* Step 5: check channel list if it exists */
3593 if (cmd->chanlist && cmd->chanlist_len > 0)
3594 err |= ni_cdio_check_chanlist(dev, s, cmd);
3602 static int ni_cdo_inttrig(struct comedi_device *dev,
3603 struct comedi_subdevice *s,
3604 unsigned int trig_num)
3606 struct comedi_cmd *cmd = &s->async->cmd;
3607 const unsigned int timeout = 1000;
3610 struct ni_private *devpriv = dev->private;
3611 unsigned long flags;
3613 if (trig_num != cmd->start_arg)
3616 s->async->inttrig = NULL;
3618 /* read alloc the entire buffer */
3619 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3621 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3622 if (devpriv->cdo_mite_chan) {
3623 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3624 mite_dma_arm(devpriv->cdo_mite_chan);
3626 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3629 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3634 * XXX not sure what interrupt C group does
3635 * wait for dma to fill output fifo
3636 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3638 for (i = 0; i < timeout; ++i) {
3639 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3640 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3642 usleep_range(10, 100);
3645 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3649 ni_writel(dev, NI_M_CDO_CMD_ARM |
3650 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3651 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3656 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3658 struct ni_private *devpriv = dev->private;
3659 const struct comedi_cmd *cmd = &s->async->cmd;
3660 unsigned int cdo_mode_bits;
3663 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3665 * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3666 * for completeness, test whether the cmd is output or input(?)
3668 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3669 NI_M_CDO_MODE_HALT_ON_ERROR |
3670 NI_M_CDO_MODE_SAMPLE_SRC(
3671 ni_get_reg_value(CR_CHAN(cmd->scan_begin_arg),
3673 &devpriv->routing_tables));
3674 if (cmd->scan_begin_arg & CR_INVERT)
3675 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3676 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3678 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3679 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3680 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3682 dev_err(dev->class_dev,
3683 "attempted to run digital output command with no lines configured as outputs\n");
3686 retval = ni_request_cdo_mite_channel(dev);
3690 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3691 s->async->prealloc_bufsz /
3692 comedi_bytes_per_scan(s));
3694 s->async->inttrig = ni_cdo_inttrig;
3699 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3701 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3702 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3703 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3704 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3707 * XXX not sure what interrupt C group does
3708 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3710 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3711 ni_release_cdo_mite_channel(dev);
3715 static void handle_cdio_interrupt(struct comedi_device *dev)
3717 struct ni_private *devpriv = dev->private;
3718 unsigned int cdio_status;
3719 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3720 unsigned long flags;
3722 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3723 if (devpriv->cdo_mite_chan)
3724 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3725 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3727 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3728 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3729 /* XXX just guessing this is needed and does something useful */
3730 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3732 s->async->events |= COMEDI_CB_OVERFLOW;
3734 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3735 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3737 /* s->async->events |= COMEDI_CB_EOA; */
3739 comedi_handle_events(dev, s);
3743 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3744 struct comedi_subdevice *s,
3745 unsigned char data_out,
3746 unsigned char *data_in)
3748 struct ni_private *devpriv = dev->private;
3749 unsigned int status1;
3750 int err = 0, count = 20;
3752 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3753 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3754 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3756 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3757 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3762 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3763 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3764 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3766 /* Wait until STC says we're done, but don't loop infinitely. */
3767 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3768 NISTC_STATUS1_SERIO_IN_PROG) {
3769 /* Delay one bit per loop */
3770 udelay((devpriv->serial_interval_ns + 999) / 1000);
3772 dev_err(dev->class_dev,
3773 "SPI serial I/O didn't finish in time!\n");
3780 * Delay for last bit. This delay is absolutely necessary, because
3781 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3783 udelay((devpriv->serial_interval_ns + 999) / 1000);
3786 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3789 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3794 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3795 struct comedi_subdevice *s,
3796 unsigned char data_out,
3797 unsigned char *data_in)
3799 struct ni_private *devpriv = dev->private;
3800 unsigned char mask, input = 0;
3802 /* Wait for one bit before transfer */
3803 udelay((devpriv->serial_interval_ns + 999) / 1000);
3805 for (mask = 0x80; mask; mask >>= 1) {
3807 * Output current bit; note that we cannot touch s->state
3808 * because it is a per-subdevice field, and serial is
3809 * a separate subdevice from DIO.
3811 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3812 if (data_out & mask)
3813 devpriv->dio_output |= NISTC_DIO_SDOUT;
3814 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3817 * Assert SDCLK (active low, inverted), wait for half of
3818 * the delay, deassert SDCLK, and wait for the other half.
3820 devpriv->dio_control |= NISTC_DIO_SDCLK;
3821 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3823 udelay((devpriv->serial_interval_ns + 999) / 2000);
3825 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3826 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3828 udelay((devpriv->serial_interval_ns + 999) / 2000);
3830 /* Input current bit */
3831 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3841 static int ni_serial_insn_config(struct comedi_device *dev,
3842 struct comedi_subdevice *s,
3843 struct comedi_insn *insn,
3846 struct ni_private *devpriv = dev->private;
3847 unsigned int clk_fout = devpriv->clock_and_fout;
3849 unsigned char byte_out, byte_in = 0;
3855 case INSN_CONFIG_SERIAL_CLOCK:
3856 devpriv->serial_hw_mode = 1;
3857 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3859 if (data[1] == SERIAL_DISABLED) {
3860 devpriv->serial_hw_mode = 0;
3861 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3863 data[1] = SERIAL_DISABLED;
3864 devpriv->serial_interval_ns = data[1];
3865 } else if (data[1] <= SERIAL_600NS) {
3867 * Warning: this clock speed is too fast to reliably
3870 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3871 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3872 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3873 data[1] = SERIAL_600NS;
3874 devpriv->serial_interval_ns = data[1];
3875 } else if (data[1] <= SERIAL_1_2US) {
3876 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3877 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3878 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3879 data[1] = SERIAL_1_2US;
3880 devpriv->serial_interval_ns = data[1];
3881 } else if (data[1] <= SERIAL_10US) {
3882 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3883 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3884 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3886 * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3887 * 600ns/1.2us. If you turn divide_by_2 off with the
3888 * slow clock, you will still get 10us, except then
3889 * all your delays are wrong.
3891 data[1] = SERIAL_10US;
3892 devpriv->serial_interval_ns = data[1];
3894 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3896 devpriv->serial_hw_mode = 0;
3897 data[1] = (data[1] / 1000) * 1000;
3898 devpriv->serial_interval_ns = data[1];
3900 devpriv->clock_and_fout = clk_fout;
3902 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3903 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3906 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3908 if (devpriv->serial_interval_ns == 0)
3911 byte_out = data[1] & 0xFF;
3913 if (devpriv->serial_hw_mode) {
3914 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3916 } else if (devpriv->serial_interval_ns > 0) {
3917 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3920 dev_err(dev->class_dev, "serial disabled!\n");
3925 data[1] = byte_in & 0xFF;
3934 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3938 for (i = 0; i < s->n_chan; i++) {
3939 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3940 NI67XX_AO_CFG2_REG);
3942 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3945 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3946 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3947 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3948 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3949 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3950 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3951 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3952 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3953 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3954 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3955 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3956 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3957 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3958 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3959 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3960 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3961 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3962 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3963 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3964 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3965 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3966 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3967 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3968 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3969 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3970 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3971 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3972 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3973 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3974 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3975 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3976 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3977 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3978 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3979 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3980 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3981 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3984 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3985 enum ni_gpct_register reg)
3987 const struct mio_regmap *regmap;
3989 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3990 regmap = &ni_gpct_to_stc_regmap[reg];
3992 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3997 return regmap->mio_reg;
4000 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
4001 enum ni_gpct_register reg)
4003 struct comedi_device *dev = counter->counter_dev->dev;
4004 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4006 if (stc_register == 0)
4010 /* m-series only registers */
4011 case NITIO_G0_CNT_MODE:
4012 case NITIO_G1_CNT_MODE:
4013 case NITIO_G0_GATE2:
4014 case NITIO_G1_GATE2:
4015 case NITIO_G0_DMA_CFG:
4016 case NITIO_G1_DMA_CFG:
4019 ni_writew(dev, bits, stc_register);
4022 /* 32 bit registers */
4023 case NITIO_G0_LOADA:
4024 case NITIO_G1_LOADA:
4025 case NITIO_G0_LOADB:
4026 case NITIO_G1_LOADB:
4027 ni_stc_writel(dev, bits, stc_register);
4030 /* 16 bit registers */
4031 case NITIO_G0_INT_ENA:
4032 ni_set_bitfield(dev, stc_register,
4033 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
4036 case NITIO_G1_INT_ENA:
4037 ni_set_bitfield(dev, stc_register,
4038 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4042 ni_stc_writew(dev, bits, stc_register);
4046 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4047 enum ni_gpct_register reg)
4049 struct comedi_device *dev = counter->counter_dev->dev;
4050 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4052 if (stc_register == 0)
4056 /* m-series only registers */
4057 case NITIO_G0_DMA_STATUS:
4058 case NITIO_G1_DMA_STATUS:
4059 return ni_readw(dev, stc_register);
4061 /* 32 bit registers */
4062 case NITIO_G0_HW_SAVE:
4063 case NITIO_G1_HW_SAVE:
4064 case NITIO_G0_SW_SAVE:
4065 case NITIO_G1_SW_SAVE:
4066 return ni_stc_readl(dev, stc_register);
4068 /* 16 bit registers */
4070 return ni_stc_readw(dev, stc_register);
4074 static int ni_freq_out_insn_read(struct comedi_device *dev,
4075 struct comedi_subdevice *s,
4076 struct comedi_insn *insn,
4079 struct ni_private *devpriv = dev->private;
4080 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4083 for (i = 0; i < insn->n; i++)
4089 static int ni_freq_out_insn_write(struct comedi_device *dev,
4090 struct comedi_subdevice *s,
4091 struct comedi_insn *insn,
4094 struct ni_private *devpriv = dev->private;
4097 unsigned int val = data[insn->n - 1];
4099 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4100 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4101 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4103 /* use the last data value to set the fout divider */
4104 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4106 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4107 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4112 static int ni_freq_out_insn_config(struct comedi_device *dev,
4113 struct comedi_subdevice *s,
4114 struct comedi_insn *insn,
4117 struct ni_private *devpriv = dev->private;
4120 case INSN_CONFIG_SET_CLOCK_SRC:
4122 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4123 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4125 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4126 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4131 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4133 case INSN_CONFIG_GET_CLOCK_SRC:
4134 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4135 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4136 data[2] = TIMEBASE_2_NS;
4138 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4139 data[2] = TIMEBASE_1_NS * 2;
4148 static int ni_8255_callback(struct comedi_device *dev,
4149 int dir, int port, int data, unsigned long iobase)
4152 ni_writeb(dev, data, iobase + 2 * port);
4156 return ni_readb(dev, iobase + 2 * port);
4159 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4161 struct ni_private *devpriv = dev->private;
4163 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4164 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4168 static int ni_m_series_pwm_config(struct comedi_device *dev,
4169 struct comedi_subdevice *s,
4170 struct comedi_insn *insn,
4173 struct ni_private *devpriv = dev->private;
4174 unsigned int up_count, down_count;
4177 case INSN_CONFIG_PWM_OUTPUT:
4179 case CMDF_ROUND_NEAREST:
4180 up_count = DIV_ROUND_CLOSEST(data[2],
4183 case CMDF_ROUND_DOWN:
4184 up_count = data[2] / devpriv->clock_ns;
4188 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4194 case CMDF_ROUND_NEAREST:
4195 down_count = DIV_ROUND_CLOSEST(data[4],
4198 case CMDF_ROUND_DOWN:
4199 down_count = data[4] / devpriv->clock_ns;
4203 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4208 if (up_count * devpriv->clock_ns != data[2] ||
4209 down_count * devpriv->clock_ns != data[4]) {
4210 data[2] = up_count * devpriv->clock_ns;
4211 data[4] = down_count * devpriv->clock_ns;
4214 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4215 NI_M_CAL_PWM_LOW_TIME(down_count),
4217 devpriv->pwm_up_count = up_count;
4218 devpriv->pwm_down_count = down_count;
4220 case INSN_CONFIG_GET_PWM_OUTPUT:
4221 return ni_get_pwm_config(dev, data);
4228 static int ni_6143_pwm_config(struct comedi_device *dev,
4229 struct comedi_subdevice *s,
4230 struct comedi_insn *insn,
4233 struct ni_private *devpriv = dev->private;
4234 unsigned int up_count, down_count;
4237 case INSN_CONFIG_PWM_OUTPUT:
4239 case CMDF_ROUND_NEAREST:
4240 up_count = DIV_ROUND_CLOSEST(data[2],
4243 case CMDF_ROUND_DOWN:
4244 up_count = data[2] / devpriv->clock_ns;
4248 DIV_ROUND_UP(data[2], devpriv->clock_ns);
4254 case CMDF_ROUND_NEAREST:
4255 down_count = DIV_ROUND_CLOSEST(data[4],
4258 case CMDF_ROUND_DOWN:
4259 down_count = data[4] / devpriv->clock_ns;
4263 DIV_ROUND_UP(data[4], devpriv->clock_ns);
4268 if (up_count * devpriv->clock_ns != data[2] ||
4269 down_count * devpriv->clock_ns != data[4]) {
4270 data[2] = up_count * devpriv->clock_ns;
4271 data[4] = down_count * devpriv->clock_ns;
4274 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4275 devpriv->pwm_up_count = up_count;
4276 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4277 devpriv->pwm_down_count = down_count;
4279 case INSN_CONFIG_GET_PWM_OUTPUT:
4280 return ni_get_pwm_config(dev, data);
4287 static int pack_mb88341(int addr, int val, int *bitstring)
4291 * Note that address bits are reversed. Thanks to
4292 * Ingo Keen for noticing this.
4294 * Note also that the 88341 expects address values from
4295 * 1-12, whereas we use channel numbers 0-11. The NI
4296 * docs use 1-12, also, so be careful here.
4299 *bitstring = ((addr & 0x1) << 11) |
4300 ((addr & 0x2) << 9) |
4301 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4305 static int pack_dac8800(int addr, int val, int *bitstring)
4307 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4311 static int pack_dac8043(int addr, int val, int *bitstring)
4313 *bitstring = val & 0xfff;
4317 static int pack_ad8522(int addr, int val, int *bitstring)
4319 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4323 static int pack_ad8804(int addr, int val, int *bitstring)
4325 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4329 static int pack_ad8842(int addr, int val, int *bitstring)
4331 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4335 struct caldac_struct {
4338 int (*packbits)(int address, int value, int *bitstring);
4341 static struct caldac_struct caldacs[] = {
4342 [mb88341] = {12, 8, pack_mb88341},
4343 [dac8800] = {8, 8, pack_dac8800},
4344 [dac8043] = {1, 12, pack_dac8043},
4345 [ad8522] = {2, 12, pack_ad8522},
4346 [ad8804] = {12, 8, pack_ad8804},
4347 [ad8842] = {8, 8, pack_ad8842},
4348 [ad8804_debug] = {16, 8, pack_ad8804},
4351 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4353 const struct ni_board_struct *board = dev->board_ptr;
4354 struct ni_private *devpriv = dev->private;
4355 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4360 if (devpriv->caldacs[addr] == val)
4362 devpriv->caldacs[addr] = val;
4364 for (i = 0; i < 3; i++) {
4365 type = board->caldac[i];
4366 if (type == caldac_none)
4368 if (addr < caldacs[type].n_chans) {
4369 bits = caldacs[type].packbits(addr, val, &bitstring);
4370 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4373 addr -= caldacs[type].n_chans;
4376 /* bits will be 0 if there is no caldac for the given addr */
4380 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4381 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4382 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4384 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4387 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4389 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4392 static int ni_calib_insn_write(struct comedi_device *dev,
4393 struct comedi_subdevice *s,
4394 struct comedi_insn *insn,
4397 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4402 static int ni_calib_insn_read(struct comedi_device *dev,
4403 struct comedi_subdevice *s,
4404 struct comedi_insn *insn,
4407 struct ni_private *devpriv = dev->private;
4409 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4414 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4416 const struct ni_board_struct *board = dev->board_ptr;
4417 struct ni_private *devpriv = dev->private;
4426 type = board->caldac[0];
4427 if (type == caldac_none)
4429 n_bits = caldacs[type].n_bits;
4430 for (i = 0; i < 3; i++) {
4431 type = board->caldac[i];
4432 if (type == caldac_none)
4434 if (caldacs[type].n_bits != n_bits)
4436 n_chans += caldacs[type].n_chans;
4439 s->n_chan = n_chans;
4442 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4444 if (n_chans > MAX_N_CALDACS)
4445 dev_err(dev->class_dev,
4446 "BUG! MAX_N_CALDACS too small\n");
4447 s->maxdata_list = maxdata_list;
4449 for (i = 0; i < n_dacs; i++) {
4450 type = board->caldac[i];
4451 for (j = 0; j < caldacs[type].n_chans; j++) {
4452 maxdata_list[chan] =
4453 (1 << caldacs[type].n_bits) - 1;
4458 for (chan = 0; chan < s->n_chan; chan++)
4459 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4461 type = board->caldac[0];
4462 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4464 for (chan = 0; chan < s->n_chan; chan++)
4465 ni_write_caldac(dev, i, s->maxdata / 2);
4469 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4471 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4475 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4476 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4477 for (bit = 0x8000; bit; bit >>= 1) {
4478 if (bit & bitstring)
4479 cmd |= NI_E_SERIAL_CMD_SDATA;
4481 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4483 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4484 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4486 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4488 for (bit = 0x80; bit; bit >>= 1) {
4489 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4490 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4491 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4494 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4499 static int ni_eeprom_insn_read(struct comedi_device *dev,
4500 struct comedi_subdevice *s,
4501 struct comedi_insn *insn,
4504 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4509 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4510 struct comedi_subdevice *s,
4511 struct comedi_insn *insn,
4514 struct ni_private *devpriv = dev->private;
4516 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4521 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4524 /* pre-m-series boards have fixed signals on pfi pins */
4527 return NI_PFI_OUTPUT_AI_START1;
4529 return NI_PFI_OUTPUT_AI_START2;
4531 return NI_PFI_OUTPUT_AI_CONVERT;
4533 return NI_PFI_OUTPUT_G_SRC1;
4535 return NI_PFI_OUTPUT_G_GATE1;
4537 return NI_PFI_OUTPUT_AO_UPDATE_N;
4539 return NI_PFI_OUTPUT_AO_START1;
4541 return NI_PFI_OUTPUT_AI_START_PULSE;
4543 return NI_PFI_OUTPUT_G_SRC0;
4545 return NI_PFI_OUTPUT_G_GATE0;
4547 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4553 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4554 unsigned int chan, unsigned int source)
4556 /* pre-m-series boards have fixed signals on pfi pins */
4557 if (source != ni_old_get_pfi_routing(dev, chan))
4562 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4565 struct ni_private *devpriv = dev->private;
4566 const unsigned int array_offset = chan / 3;
4568 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4569 devpriv->pfi_output_select_reg[array_offset]);
4572 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4573 unsigned int chan, unsigned int source)
4575 struct ni_private *devpriv = dev->private;
4576 unsigned int index = chan / 3;
4577 unsigned short val = devpriv->pfi_output_select_reg[index];
4579 if ((source & 0x1f) != source)
4582 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4583 val |= NI_M_PFI_OUT_SEL(chan, source);
4584 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4585 devpriv->pfi_output_select_reg[index] = val;
4590 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4593 struct ni_private *devpriv = dev->private;
4595 if (chan >= NI_PFI(0)) {
4596 /* allow new and old names of pfi channels to work. */
4599 return (devpriv->is_m_series)
4600 ? ni_m_series_get_pfi_routing(dev, chan)
4601 : ni_old_get_pfi_routing(dev, chan);
4604 /* Sets the output mux for the specified PFI channel. */
4605 static int ni_set_pfi_routing(struct comedi_device *dev,
4606 unsigned int chan, unsigned int source)
4608 struct ni_private *devpriv = dev->private;
4610 if (chan >= NI_PFI(0)) {
4611 /* allow new and old names of pfi channels to work. */
4614 return (devpriv->is_m_series)
4615 ? ni_m_series_set_pfi_routing(dev, chan, source)
4616 : ni_old_set_pfi_routing(dev, chan, source);
4619 static int ni_config_pfi_filter(struct comedi_device *dev,
4621 enum ni_pfi_filter_select filter)
4623 struct ni_private *devpriv = dev->private;
4626 if (!devpriv->is_m_series)
4629 if (chan >= NI_PFI(0)) {
4630 /* allow new and old names of pfi channels to work. */
4634 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4635 bits &= ~NI_M_PFI_FILTER_SEL_MASK(chan);
4636 bits |= NI_M_PFI_FILTER_SEL(chan, filter);
4637 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4641 static void ni_set_pfi_direction(struct comedi_device *dev, int chan,
4642 unsigned int direction)
4644 if (chan >= NI_PFI(0)) {
4645 /* allow new and old names of pfi channels to work. */
4648 direction = (direction == COMEDI_OUTPUT) ? 1u : 0u;
4649 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, direction);
4652 static int ni_get_pfi_direction(struct comedi_device *dev, int chan)
4654 struct ni_private *devpriv = dev->private;
4656 if (chan >= NI_PFI(0)) {
4657 /* allow new and old names of pfi channels to work. */
4660 return devpriv->io_bidirection_pin_reg & (1 << chan) ?
4661 COMEDI_OUTPUT : COMEDI_INPUT;
4664 static int ni_pfi_insn_config(struct comedi_device *dev,
4665 struct comedi_subdevice *s,
4666 struct comedi_insn *insn,
4674 chan = CR_CHAN(insn->chanspec);
4679 ni_set_pfi_direction(dev, chan, data[0]);
4681 case INSN_CONFIG_DIO_QUERY:
4682 data[1] = ni_get_pfi_direction(dev, chan);
4684 case INSN_CONFIG_SET_ROUTING:
4685 return ni_set_pfi_routing(dev, chan, data[1]);
4686 case INSN_CONFIG_GET_ROUTING:
4687 data[1] = ni_get_pfi_routing(dev, chan);
4689 case INSN_CONFIG_FILTER:
4690 return ni_config_pfi_filter(dev, chan, data[1]);
4697 static int ni_pfi_insn_bits(struct comedi_device *dev,
4698 struct comedi_subdevice *s,
4699 struct comedi_insn *insn,
4702 struct ni_private *devpriv = dev->private;
4704 if (!devpriv->is_m_series)
4707 if (comedi_dio_update_state(s, data))
4708 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4710 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4715 static int cs5529_wait_for_idle(struct comedi_device *dev)
4717 unsigned short status;
4718 const int timeout = HZ;
4721 for (i = 0; i < timeout; i++) {
4722 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4723 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4725 set_current_state(TASK_INTERRUPTIBLE);
4726 if (schedule_timeout(1))
4730 dev_err(dev->class_dev, "timeout\n");
4736 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4738 static const int timeout = 100;
4741 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4742 /* give time for command to start being serially clocked into cs5529.
4743 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4744 * set before we exit this function.
4746 for (i = 0; i < timeout; i++) {
4747 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4748 NI67XX_CAL_STATUS_BUSY)
4753 dev_err(dev->class_dev,
4754 "possible problem - never saw adc go busy?\n");
4757 static int cs5529_do_conversion(struct comedi_device *dev,
4758 unsigned short *data)
4761 unsigned short status;
4763 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4764 retval = cs5529_wait_for_idle(dev);
4766 dev_err(dev->class_dev,
4767 "timeout or signal in %s()\n", __func__);
4770 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4771 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4772 dev_err(dev->class_dev,
4773 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4776 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4777 dev_err(dev->class_dev,
4778 "cs5529 conversion error, overrange (ignoring)\n");
4781 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4782 /* cs5529 returns 16 bit signed data in bipolar mode */
4788 static int cs5529_ai_insn_read(struct comedi_device *dev,
4789 struct comedi_subdevice *s,
4790 struct comedi_insn *insn,
4794 unsigned short sample;
4795 unsigned int channel_select;
4796 const unsigned int INTERNAL_REF = 0x1000;
4799 * Set calibration adc source. Docs lie, reference select bits 8 to 11
4800 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4801 * 13 causes the adc input to go overrange (maybe reads external
4804 if (insn->chanspec & CR_ALT_SOURCE)
4805 channel_select = INTERNAL_REF;
4807 channel_select = CR_CHAN(insn->chanspec);
4808 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4810 for (n = 0; n < insn->n; n++) {
4811 retval = cs5529_do_conversion(dev, &sample);
4819 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4820 unsigned int reg_select_bits)
4822 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4823 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4824 reg_select_bits &= CS5529_CMD_REG_MASK;
4825 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4826 if (cs5529_wait_for_idle(dev))
4827 dev_err(dev->class_dev,
4828 "timeout or signal in %s\n", __func__);
4831 static int init_cs5529(struct comedi_device *dev)
4833 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4834 CS5529_CFG_WORD_RATE_2180;
4837 /* do self-calibration */
4838 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4840 /* need to force a conversion for calibration to run */
4841 cs5529_do_conversion(dev, NULL);
4843 /* force gain calibration to 1 */
4844 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4845 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4847 if (cs5529_wait_for_idle(dev))
4848 dev_err(dev->class_dev,
4849 "timeout or signal in %s\n", __func__);
4855 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4856 * given an arbitrary frequency input clock.
4858 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4859 unsigned int *freq_divider,
4860 unsigned int *freq_multiplier,
4861 unsigned int *actual_period_ns)
4864 unsigned int best_div = 1;
4866 unsigned int best_mult = 1;
4867 static const unsigned int pico_per_nano = 1000;
4868 const unsigned int reference_picosec = reference_period_ns *
4871 * m-series wants the phased-locked loop to output 80MHz, which is
4872 * divided by 4 to 20 MHz for most timing clocks
4874 static const unsigned int target_picosec = 12500;
4875 int best_period_picosec = 0;
4877 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4878 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4879 unsigned int new_period_ps =
4880 (reference_picosec * div) / mult;
4881 if (abs(new_period_ps - target_picosec) <
4882 abs(best_period_picosec - target_picosec)) {
4883 best_period_picosec = new_period_ps;
4889 if (best_period_picosec == 0)
4892 *freq_divider = best_div;
4893 *freq_multiplier = best_mult;
4894 /* return the actual period (* fudge factor for 80 to 20 MHz) */
4895 *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4900 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4901 unsigned int source,
4902 unsigned int period_ns)
4904 struct ni_private *devpriv = dev->private;
4905 static const unsigned int min_period_ns = 50;
4906 static const unsigned int max_period_ns = 1000;
4907 static const unsigned int timeout = 1000;
4908 unsigned int pll_control_bits;
4909 unsigned int freq_divider;
4910 unsigned int freq_multiplier;
4915 if (source == NI_MIO_PLL_PXI10_CLOCK)
4918 * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4919 * range so we'll use that.
4921 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4922 dev_err(dev->class_dev,
4923 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4924 __func__, min_period_ns, max_period_ns);
4927 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4928 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4929 NISTC_RTSI_TRIG_DIR_REG);
4930 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4931 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4932 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4933 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4935 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4936 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4938 case NI_MIO_PLL_PXI10_CLOCK:
4939 /* pxi clock is 10MHz */
4940 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4943 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4944 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4945 devpriv->clock_and_fout2 |=
4946 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4950 if (rtsi > NI_M_MAX_RTSI_CHAN)
4954 retval = ni_mseries_get_pll_parameters(period_ns,
4957 &devpriv->clock_ns);
4959 dev_err(dev->class_dev,
4960 "bug, failed to find pll parameters\n");
4964 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4965 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4966 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4968 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4969 devpriv->clock_source = source;
4970 /* it takes a few hundred microseconds for PLL to lock */
4971 for (i = 0; i < timeout; ++i) {
4972 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4977 dev_err(dev->class_dev,
4978 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4979 __func__, source, period_ns);
4985 static int ni_set_master_clock(struct comedi_device *dev,
4986 unsigned int source, unsigned int period_ns)
4988 struct ni_private *devpriv = dev->private;
4990 if (source == NI_MIO_INTERNAL_CLOCK) {
4991 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4992 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4993 NISTC_RTSI_TRIG_DIR_REG);
4994 devpriv->clock_ns = TIMEBASE_1_NS;
4995 if (devpriv->is_m_series) {
4996 devpriv->clock_and_fout2 &=
4997 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4998 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4999 ni_writew(dev, devpriv->clock_and_fout2,
5000 NI_M_CLK_FOUT2_REG);
5001 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5003 devpriv->clock_source = source;
5005 if (devpriv->is_m_series) {
5006 return ni_mseries_set_pll_master_clock(dev, source,
5009 if (source == NI_MIO_RTSI_CLOCK) {
5010 devpriv->rtsi_trig_direction_reg |=
5011 NISTC_RTSI_TRIG_USE_CLK;
5013 devpriv->rtsi_trig_direction_reg,
5014 NISTC_RTSI_TRIG_DIR_REG);
5015 if (period_ns == 0) {
5016 dev_err(dev->class_dev,
5017 "we don't handle an unspecified clock period correctly yet, returning error\n");
5020 devpriv->clock_ns = period_ns;
5021 devpriv->clock_source = source;
5030 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5031 unsigned int chan, unsigned int source)
5033 struct ni_private *devpriv = dev->private;
5035 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5036 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5037 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5040 dev_err(dev->class_dev,
5041 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5042 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5048 case NI_RTSI_OUTPUT_ADR_START1:
5049 case NI_RTSI_OUTPUT_ADR_START2:
5050 case NI_RTSI_OUTPUT_SCLKG:
5051 case NI_RTSI_OUTPUT_DACUPDN:
5052 case NI_RTSI_OUTPUT_DA_START1:
5053 case NI_RTSI_OUTPUT_G_SRC0:
5054 case NI_RTSI_OUTPUT_G_GATE0:
5055 case NI_RTSI_OUTPUT_RGOUT0:
5056 case NI_RTSI_OUTPUT_RTSI_BRD(0):
5057 case NI_RTSI_OUTPUT_RTSI_BRD(1):
5058 case NI_RTSI_OUTPUT_RTSI_BRD(2):
5059 case NI_RTSI_OUTPUT_RTSI_BRD(3):
5061 case NI_RTSI_OUTPUT_RTSI_OSC:
5062 return (devpriv->is_m_series) ? 1 : 0;
5068 static int ni_set_rtsi_routing(struct comedi_device *dev,
5069 unsigned int chan, unsigned int src)
5071 struct ni_private *devpriv = dev->private;
5073 if (chan >= TRIGGER_LINE(0))
5074 /* allow new and old names of rtsi channels to work. */
5075 chan -= TRIGGER_LINE(0);
5077 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5080 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5081 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5082 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5083 NISTC_RTSI_TRIGA_OUT_REG);
5084 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5085 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5086 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5087 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5088 NISTC_RTSI_TRIGB_OUT_REG);
5089 } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5090 /* probably should never reach this, since the
5091 * ni_valid_rtsi_output_source above errors out if chan is too
5094 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5100 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5103 struct ni_private *devpriv = dev->private;
5105 if (chan >= TRIGGER_LINE(0))
5106 /* allow new and old names of rtsi channels to work. */
5107 chan -= TRIGGER_LINE(0);
5110 return NISTC_RTSI_TRIG_TO_SRC(chan,
5111 devpriv->rtsi_trig_a_output_reg);
5112 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5113 return NISTC_RTSI_TRIG_TO_SRC(chan,
5114 devpriv->rtsi_trig_b_output_reg);
5115 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5116 return NI_RTSI_OUTPUT_RTSI_OSC;
5119 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5123 static void ni_set_rtsi_direction(struct comedi_device *dev, int chan,
5124 unsigned int direction)
5126 struct ni_private *devpriv = dev->private;
5127 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5129 if (chan >= TRIGGER_LINE(0))
5130 /* allow new and old names of rtsi channels to work. */
5131 chan -= TRIGGER_LINE(0);
5133 if (direction == COMEDI_OUTPUT) {
5134 if (chan < max_chan) {
5135 devpriv->rtsi_trig_direction_reg |=
5136 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5137 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5138 devpriv->rtsi_trig_direction_reg |=
5139 NISTC_RTSI_TRIG_DRV_CLK;
5142 if (chan < max_chan) {
5143 devpriv->rtsi_trig_direction_reg &=
5144 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5145 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5146 devpriv->rtsi_trig_direction_reg &=
5147 ~NISTC_RTSI_TRIG_DRV_CLK;
5150 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5151 NISTC_RTSI_TRIG_DIR_REG);
5154 static int ni_get_rtsi_direction(struct comedi_device *dev, int chan)
5156 struct ni_private *devpriv = dev->private;
5157 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5159 if (chan >= TRIGGER_LINE(0))
5160 /* allow new and old names of rtsi channels to work. */
5161 chan -= TRIGGER_LINE(0);
5163 if (chan < max_chan) {
5164 return (devpriv->rtsi_trig_direction_reg &
5165 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5166 ? COMEDI_OUTPUT : COMEDI_INPUT;
5167 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5168 return (devpriv->rtsi_trig_direction_reg &
5169 NISTC_RTSI_TRIG_DRV_CLK)
5170 ? COMEDI_OUTPUT : COMEDI_INPUT;
5175 static int ni_rtsi_insn_config(struct comedi_device *dev,
5176 struct comedi_subdevice *s,
5177 struct comedi_insn *insn,
5180 struct ni_private *devpriv = dev->private;
5181 unsigned int chan = CR_CHAN(insn->chanspec);
5186 ni_set_rtsi_direction(dev, chan, data[0]);
5188 case INSN_CONFIG_DIO_QUERY: {
5189 int ret = ni_get_rtsi_direction(dev, chan);
5196 case INSN_CONFIG_SET_CLOCK_SRC:
5197 return ni_set_master_clock(dev, data[1], data[2]);
5198 case INSN_CONFIG_GET_CLOCK_SRC:
5199 data[1] = devpriv->clock_source;
5200 data[2] = devpriv->clock_ns;
5202 case INSN_CONFIG_SET_ROUTING:
5203 return ni_set_rtsi_routing(dev, chan, data[1]);
5204 case INSN_CONFIG_GET_ROUTING: {
5205 int ret = ni_get_rtsi_routing(dev, chan);
5218 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5219 struct comedi_subdevice *s,
5220 struct comedi_insn *insn,
5229 * Default routing for RTSI trigger lines.
5231 * These values are used here in the init function, as well as in the
5232 * disconnect_route function, after a RTSI route has been disconnected.
5234 static const int default_rtsi_routing[] = {
5235 [0] = NI_RTSI_OUTPUT_ADR_START1,
5236 [1] = NI_RTSI_OUTPUT_ADR_START2,
5237 [2] = NI_RTSI_OUTPUT_SCLKG,
5238 [3] = NI_RTSI_OUTPUT_DACUPDN,
5239 [4] = NI_RTSI_OUTPUT_DA_START1,
5240 [5] = NI_RTSI_OUTPUT_G_SRC0,
5241 [6] = NI_RTSI_OUTPUT_G_GATE0,
5242 [7] = NI_RTSI_OUTPUT_RTSI_OSC,
5246 * Route signals through RGOUT0 terminal.
5247 * @reg: raw register value of RGOUT0 bits (only bit0 is important).
5248 * @dev: comedi device handle.
5250 static void set_rgout0_reg(int reg, struct comedi_device *dev)
5252 struct ni_private *devpriv = dev->private;
5254 if (devpriv->is_m_series) {
5255 devpriv->rtsi_trig_direction_reg &=
5256 ~NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5257 devpriv->rtsi_trig_direction_reg |=
5258 (reg << NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT) &
5259 NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5260 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5261 NISTC_RTSI_TRIG_DIR_REG);
5263 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1;
5264 devpriv->rtsi_trig_b_output_reg |=
5265 (reg << NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT) &
5266 NISTC_RTSI_TRIGB_SUB_SEL1;
5267 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5268 NISTC_RTSI_TRIGB_OUT_REG);
5272 static int get_rgout0_reg(struct comedi_device *dev)
5274 struct ni_private *devpriv = dev->private;
5277 if (devpriv->is_m_series)
5278 reg = (devpriv->rtsi_trig_direction_reg &
5279 NISTC_RTSI_TRIG_DIR_SUB_SEL1)
5280 >> NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT;
5282 reg = (devpriv->rtsi_trig_b_output_reg &
5283 NISTC_RTSI_TRIGB_SUB_SEL1)
5284 >> NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT;
5288 static inline int get_rgout0_src(struct comedi_device *dev)
5290 struct ni_private *devpriv = dev->private;
5291 int reg = get_rgout0_reg(dev);
5293 return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables);
5297 * Route signals through RGOUT0 terminal and increment the RGOUT0 use for this
5299 * @src: device-global signal name
5300 * @dev: comedi device handle
5302 * Return: -EINVAL if the source is not valid to route to RGOUT0;
5303 * -EBUSY if the RGOUT0 is already used;
5306 static int incr_rgout0_src_use(int src, struct comedi_device *dev)
5308 struct ni_private *devpriv = dev->private;
5309 s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5310 &devpriv->routing_tables);
5315 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg)
5318 ++devpriv->rgout0_usage;
5319 set_rgout0_reg(reg, dev);
5324 * Unroute signals through RGOUT0 terminal and deccrement the RGOUT0 use for
5325 * this particular source. This function does not actually unroute anything
5326 * with respect to RGOUT0. It does, on the other hand, decrement the usage
5327 * counter for the current src->RGOUT0 mapping.
5329 * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5330 * already at zero); 0 if successful.
5332 static int decr_rgout0_src_use(int src, struct comedi_device *dev)
5334 struct ni_private *devpriv = dev->private;
5335 s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5336 &devpriv->routing_tables);
5338 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) {
5339 --devpriv->rgout0_usage;
5340 if (!devpriv->rgout0_usage)
5341 set_rgout0_reg(0, dev); /* ok default? */
5348 * Route signals through given NI_RTSI_BRD mux.
5349 * @i: index of mux to route
5350 * @reg: raw register value of RTSI_BRD bits
5351 * @dev: comedi device handle
5353 static void set_ith_rtsi_brd_reg(int i, int reg, struct comedi_device *dev)
5355 struct ni_private *devpriv = dev->private;
5356 int reg_i_sz = 3; /* value for e-series */
5360 if (devpriv->is_m_series)
5362 reg_i_mask = ~((~0) << reg_i_sz);
5363 reg_i_shift = i * reg_i_sz;
5365 /* clear out the current reg_i for ith brd */
5366 devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask << reg_i_shift);
5367 /* (softcopy) write the new reg_i for ith brd */
5368 devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift;
5369 /* (hardcopy) write the new reg_i for ith brd */
5370 ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG);
5373 static int get_ith_rtsi_brd_reg(int i, struct comedi_device *dev)
5375 struct ni_private *devpriv = dev->private;
5376 int reg_i_sz = 3; /* value for e-series */
5380 if (devpriv->is_m_series)
5382 reg_i_mask = ~((~0) << reg_i_sz);
5383 reg_i_shift = i * reg_i_sz;
5385 return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask;
5388 static inline int get_rtsi_brd_src(int brd, struct comedi_device *dev)
5390 struct ni_private *devpriv = dev->private;
5391 int brd_index = brd;
5394 if (brd >= NI_RTSI_BRD(0))
5395 brd_index = brd - NI_RTSI_BRD(0);
5397 brd = NI_RTSI_BRD(brd);
5400 * brd : device-global name
5401 * brd_index : index number of RTSI_BRD mux
5404 reg = get_ith_rtsi_brd_reg(brd_index, dev);
5406 return ni_find_route_source(reg, brd, &devpriv->routing_tables);
5410 * Route signals through NI_RTSI_BRD mux and increment the use counter for this
5413 * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5414 * -EBUSY if all NI_RTSI_BRD muxes are already used;
5415 * NI_RTSI_BRD(i) of allocated ith mux if successful.
5417 static int incr_rtsi_brd_src_use(int src, struct comedi_device *dev)
5419 struct ni_private *devpriv = dev->private;
5420 int first_available = -1;
5425 /* first look for a mux that is already configured to provide src */
5426 for (i = 0; i < NUM_RTSI_SHARED_MUXS; ++i) {
5427 reg = ni_lookup_route_register(CR_CHAN(src), NI_RTSI_BRD(i),
5428 &devpriv->routing_tables);
5431 continue; /* invalid route */
5433 if (!devpriv->rtsi_shared_mux_usage[i]) {
5434 if (first_available < 0)
5435 /* found the first unused, but usable mux */
5436 first_available = i;
5439 * we've seen at least one possible route, so change the
5440 * final error to -EBUSY in case there are no muxes
5445 if (get_ith_rtsi_brd_reg(i, dev) == reg) {
5447 * we've found a mux that is already being used
5448 * to provide the requested signal. Reuse it.
5455 if (first_available < 0)
5458 /* we did not find a mux to reuse, but there is at least one usable */
5459 i = first_available;
5462 ++devpriv->rtsi_shared_mux_usage[i];
5463 set_ith_rtsi_brd_reg(i, reg, dev);
5464 return NI_RTSI_BRD(i);
5468 * Unroute signals through NI_RTSI_BRD mux and decrement the user counter for
5469 * this particular route.
5471 * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5472 * is already at zero); 0 if successful.
5474 static int decr_rtsi_brd_src_use(int src, int rtsi_brd,
5475 struct comedi_device *dev)
5477 struct ni_private *devpriv = dev->private;
5478 s8 reg = ni_lookup_route_register(CR_CHAN(src), rtsi_brd,
5479 &devpriv->routing_tables);
5480 const int i = rtsi_brd - NI_RTSI_BRD(0);
5482 if (devpriv->rtsi_shared_mux_usage[i] > 0 &&
5483 get_ith_rtsi_brd_reg(i, dev) == reg) {
5484 --devpriv->rtsi_shared_mux_usage[i];
5485 if (!devpriv->rtsi_shared_mux_usage[i])
5486 set_ith_rtsi_brd_reg(i, 0, dev); /* ok default? */
5493 static void ni_rtsi_init(struct comedi_device *dev)
5495 struct ni_private *devpriv = dev->private;
5498 /* Initialises the RTSI bus signal switch to a default state */
5501 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5502 * to have no effect, at least on pxi-6281, which always uses
5503 * 20MHz rtsi clock frequency
5505 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5506 /* Set clock mode to internal */
5507 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5508 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5510 /* default internal lines routing to RTSI bus lines */
5511 for (i = 0; i < 8; ++i) {
5512 ni_set_rtsi_direction(dev, i, COMEDI_INPUT);
5513 ni_set_rtsi_routing(dev, i, default_rtsi_routing[i]);
5517 * Sets the source and direction of the 4 on board lines.
5518 * This configures all board lines to be:
5520 * 1) inputs (not sure what "output" would mean)
5521 * 2) copying TRIGGER_LINE(0) (or RTSI0) output
5523 * copying NI_PFI(0) output
5525 devpriv->rtsi_shared_mux_reg = 0;
5526 for (i = 0; i < 4; ++i)
5527 set_ith_rtsi_brd_reg(i, 0, dev);
5528 memset(devpriv->rtsi_shared_mux_usage, 0,
5529 sizeof(devpriv->rtsi_shared_mux_usage));
5531 /* initialize rgout0 pin as unused. */
5532 devpriv->rgout0_usage = 0;
5533 set_rgout0_reg(0, dev);
5536 /* Get route of GPFO_i/CtrOut pins */
5537 static inline int ni_get_gout_routing(unsigned int dest,
5538 struct comedi_device *dev)
5540 struct ni_private *devpriv = dev->private;
5541 unsigned int reg = devpriv->an_trig_etc_reg;
5545 if (reg & NISTC_ATRIG_ETC_GPFO_0_ENA)
5546 return NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(reg);
5549 if (reg & NISTC_ATRIG_ETC_GPFO_1_ENA)
5550 return NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(reg);
5557 /* Set route of GPFO_i/CtrOut pins */
5558 static inline int ni_disable_gout_routing(unsigned int dest,
5559 struct comedi_device *dev)
5561 struct ni_private *devpriv = dev->private;
5565 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA;
5568 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA;
5574 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5578 /* Set route of GPFO_i/CtrOut pins */
5579 static inline int ni_set_gout_routing(unsigned int src, unsigned int dest,
5580 struct comedi_device *dev)
5582 struct ni_private *devpriv = dev->private;
5587 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1);
5589 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA
5590 | NISTC_ATRIG_ETC_GPFO_0_SEL(src);
5594 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL;
5595 src = src ? NISTC_ATRIG_ETC_GPFO_1_SEL : 0;
5597 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src;
5603 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5608 * Retrieves the current source of the output selector for the given
5609 * destination. If the terminal for the destination is not already configured
5610 * as an output, this function returns -EINVAL as error.
5612 * Return: the register value of the destination output selector;
5613 * -EINVAL if terminal is not configured for output.
5615 static int get_output_select_source(int dest, struct comedi_device *dev)
5617 struct ni_private *devpriv = dev->private;
5620 if (channel_is_pfi(dest)) {
5621 if (ni_get_pfi_direction(dev, dest) == COMEDI_OUTPUT)
5622 reg = ni_get_pfi_routing(dev, dest);
5623 } else if (channel_is_rtsi(dest)) {
5624 if (ni_get_rtsi_direction(dev, dest) == COMEDI_OUTPUT) {
5625 reg = ni_get_rtsi_routing(dev, dest);
5627 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5628 dest = NI_RGOUT0; /* prepare for lookup below */
5629 reg = get_rgout0_reg(dev);
5630 } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) &&
5631 reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) {
5632 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0);
5634 dest = NI_RTSI_BRD(i); /* prepare for lookup */
5635 reg = get_ith_rtsi_brd_reg(i, dev);
5638 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5640 * not handled by ni_tio. Only available for GPFO registers in
5643 dest -= NI_CtrOut(0);
5645 /* there are only two g_out outputs. */
5647 reg = ni_get_gout_routing(dest, dev);
5648 } else if (channel_is_ctr(dest)) {
5649 reg = ni_tio_get_routing(devpriv->counter_dev, dest);
5651 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n",
5656 return ni_find_route_source(CR_CHAN(reg), dest,
5657 &devpriv->routing_tables);
5664 * Return: -1 if not connectible;
5665 * 0 if connectible and not connected;
5666 * 1 if connectible and connected.
5668 static int test_route(unsigned int src, unsigned int dest,
5669 struct comedi_device *dev)
5671 struct ni_private *devpriv = dev->private;
5672 s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5673 &devpriv->routing_tables);
5677 if (get_output_select_source(dest, dev) != CR_CHAN(src))
5682 /* Connect the actual route. */
5683 static int connect_route(unsigned int src, unsigned int dest,
5684 struct comedi_device *dev)
5686 struct ni_private *devpriv = dev->private;
5687 s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5688 &devpriv->routing_tables);
5692 /* route is not valid */
5695 current_src = get_output_select_source(dest, dev);
5696 if (current_src == CR_CHAN(src))
5698 if (current_src >= 0)
5699 /* destination mux is already busy. complain, don't overwrite */
5702 /* The route is valid and available. Now connect... */
5703 if (channel_is_pfi(dest)) {
5704 /* set routing source, then open output */
5705 ni_set_pfi_routing(dev, dest, reg);
5706 ni_set_pfi_direction(dev, dest, COMEDI_OUTPUT);
5707 } else if (channel_is_rtsi(dest)) {
5708 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5709 int ret = incr_rgout0_src_use(src, dev);
5713 } else if (ni_rtsi_route_requires_mux(reg)) {
5714 /* Attempt to allocate and route (src->brd) */
5715 int brd = incr_rtsi_brd_src_use(src, dev);
5720 /* Now lookup the register value for (brd->dest) */
5721 reg = ni_lookup_route_register(
5722 brd, dest, &devpriv->routing_tables);
5725 ni_set_rtsi_direction(dev, dest, COMEDI_OUTPUT);
5726 ni_set_rtsi_routing(dev, dest, reg);
5727 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5729 * not handled by ni_tio. Only available for GPFO registers in
5732 dest -= NI_CtrOut(0);
5734 /* there are only two g_out outputs. */
5736 if (ni_set_gout_routing(src, dest, dev))
5738 } else if (channel_is_ctr(dest)) {
5740 * we are adding back the channel modifier info to set
5741 * invert/edge info passed by the user
5743 ni_tio_set_routing(devpriv->counter_dev, dest,
5744 reg | (src & ~CR_CHAN(-1)));
5751 static int disconnect_route(unsigned int src, unsigned int dest,
5752 struct comedi_device *dev)
5754 struct ni_private *devpriv = dev->private;
5755 s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5756 &devpriv->routing_tables);
5759 /* route is not valid */
5761 if (get_output_select_source(dest, dev) != src)
5762 /* cannot disconnect something not connected */
5765 /* The route is valid and is connected. Now disconnect... */
5766 if (channel_is_pfi(dest)) {
5767 /* set the pfi to high impedance, and disconnect */
5768 ni_set_pfi_direction(dev, dest, COMEDI_INPUT);
5769 ni_set_pfi_routing(dev, dest, NI_PFI_OUTPUT_PFI_DEFAULT);
5770 } else if (channel_is_rtsi(dest)) {
5771 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5772 int ret = decr_rgout0_src_use(src, dev);
5776 } else if (ni_rtsi_route_requires_mux(reg)) {
5777 /* find which RTSI_BRD line is source for rtsi pin */
5778 int brd = ni_find_route_source(
5779 ni_get_rtsi_routing(dev, dest), dest,
5780 &devpriv->routing_tables);
5785 /* decrement/disconnect RTSI_BRD line from source */
5786 decr_rtsi_brd_src_use(src, brd, dev);
5789 /* set rtsi output selector to default state */
5790 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)];
5791 ni_set_rtsi_direction(dev, dest, COMEDI_INPUT);
5792 ni_set_rtsi_routing(dev, dest, reg);
5793 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5795 * not handled by ni_tio. Only available for GPFO registers in
5798 dest -= NI_CtrOut(0);
5800 /* there are only two g_out outputs. */
5802 reg = ni_disable_gout_routing(dest, dev);
5803 } else if (channel_is_ctr(dest)) {
5804 ni_tio_unset_routing(devpriv->counter_dev, dest);
5811 static int ni_global_insn_config(struct comedi_device *dev,
5812 struct comedi_insn *insn,
5816 case INSN_DEVICE_CONFIG_TEST_ROUTE:
5817 data[0] = test_route(data[1], data[2], dev);
5819 case INSN_DEVICE_CONFIG_CONNECT_ROUTE:
5820 return connect_route(data[1], data[2], dev);
5821 case INSN_DEVICE_CONFIG_DISCONNECT_ROUTE:
5822 return disconnect_route(data[1], data[2], dev);
5824 * This case is already handled one level up.
5825 * case INSN_DEVICE_CONFIG_GET_ROUTES:
5834 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5836 struct ni_gpct *counter = s->private;
5839 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5842 dev_err(dev->class_dev,
5843 "no dma channel available for use by counter\n");
5846 ni_tio_acknowledge(counter);
5847 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5849 return ni_tio_cmd(dev, s);
5852 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5854 struct ni_gpct *counter = s->private;
5857 retval = ni_tio_cancel(counter);
5858 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5859 ni_release_gpct_mite_channel(dev, counter->counter_index);
5864 static irqreturn_t ni_E_interrupt(int irq, void *d)
5866 struct comedi_device *dev = d;
5867 struct comedi_subdevice *s_ai = dev->read_subdev;
5868 struct comedi_subdevice *s_ao = dev->write_subdev;
5869 unsigned short a_status;
5870 unsigned short b_status;
5871 unsigned long flags;
5873 struct ni_private *devpriv = dev->private;
5878 smp_mb(); /* make sure dev->attached is checked */
5880 /* lock to avoid race with comedi_poll */
5881 spin_lock_irqsave(&dev->spinlock, flags);
5882 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5883 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5885 if (devpriv->mite) {
5886 unsigned long flags_too;
5888 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5889 if (s_ai && devpriv->ai_mite_chan)
5890 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5891 if (s_ao && devpriv->ao_mite_chan)
5892 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5893 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5896 ack_a_interrupt(dev, a_status);
5897 ack_b_interrupt(dev, b_status);
5899 if (a_status & NISTC_AI_STATUS1_INTA)
5900 handle_a_interrupt(dev, s_ai, a_status);
5901 /* handle any interrupt or dma events */
5902 comedi_handle_events(dev, s_ai);
5905 if (b_status & NISTC_AO_STATUS1_INTB)
5906 handle_b_interrupt(dev, s_ao, b_status);
5907 /* handle any interrupt or dma events */
5908 comedi_handle_events(dev, s_ao);
5910 handle_gpct_interrupt(dev, 0);
5911 handle_gpct_interrupt(dev, 1);
5913 if (devpriv->is_m_series)
5914 handle_cdio_interrupt(dev);
5917 spin_unlock_irqrestore(&dev->spinlock, flags);
5921 static int ni_alloc_private(struct comedi_device *dev)
5923 struct ni_private *devpriv;
5925 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5929 spin_lock_init(&devpriv->window_lock);
5930 spin_lock_init(&devpriv->soft_reg_copy_lock);
5931 spin_lock_init(&devpriv->mite_channel_lock);
5936 static unsigned int _ni_get_valid_routes(struct comedi_device *dev,
5937 unsigned int n_pairs,
5938 unsigned int *pair_data)
5940 struct ni_private *devpriv = dev->private;
5942 return ni_get_valid_routes(&devpriv->routing_tables, n_pairs,
5946 static int ni_E_init(struct comedi_device *dev,
5947 unsigned int interrupt_pin, unsigned int irq_polarity)
5949 const struct ni_board_struct *board = dev->board_ptr;
5950 struct ni_private *devpriv = dev->private;
5951 struct comedi_subdevice *s;
5954 const char *dev_family = devpriv->is_m_series ? "ni_mseries"
5957 /* prepare the device for globally-named routes. */
5958 if (ni_assign_device_routes(dev_family, board->name,
5959 &devpriv->routing_tables) < 0) {
5960 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n",
5961 __func__, board->name);
5962 dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\n",
5963 __func__, board->name);
5966 * only(?) assign insn_device_config if we have global names for
5969 dev->insn_device_config = ni_global_insn_config;
5970 dev->get_valid_routes = _ni_get_valid_routes;
5973 if (board->n_aochan > MAX_N_AO_CHAN) {
5974 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5978 /* initialize clock dividers */
5979 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5980 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5981 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5982 NISTC_CLK_FOUT_TO_BOARD;
5983 if (!devpriv->is_6xxx) {
5984 /* BEAM is this needed for PCI-6143 ?? */
5985 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5986 NISTC_CLK_FOUT_AO_OUT_DIV2);
5988 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5990 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5994 /* Analog Input subdevice */
5995 s = &dev->subdevices[NI_AI_SUBDEV];
5996 if (board->n_adchan) {
5997 s->type = COMEDI_SUBD_AI;
5998 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5999 if (!devpriv->is_611x)
6000 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
6001 if (board->ai_maxdata > 0xffff)
6002 s->subdev_flags |= SDF_LSAMPL;
6003 if (devpriv->is_m_series)
6004 s->subdev_flags |= SDF_SOFT_CALIBRATED;
6005 s->n_chan = board->n_adchan;
6006 s->maxdata = board->ai_maxdata;
6007 s->range_table = ni_range_lkup[board->gainlkup];
6008 s->insn_read = ni_ai_insn_read;
6009 s->insn_config = ni_ai_insn_config;
6011 dev->read_subdev = s;
6012 s->subdev_flags |= SDF_CMD_READ;
6013 s->len_chanlist = 512;
6014 s->do_cmdtest = ni_ai_cmdtest;
6015 s->do_cmd = ni_ai_cmd;
6016 s->cancel = ni_ai_reset;
6017 s->poll = ni_ai_poll;
6018 s->munge = ni_ai_munge;
6021 s->async_dma_dir = DMA_FROM_DEVICE;
6024 /* reset the analog input configuration */
6025 ni_ai_reset(dev, s);
6027 s->type = COMEDI_SUBD_UNUSED;
6030 /* Analog Output subdevice */
6031 s = &dev->subdevices[NI_AO_SUBDEV];
6032 if (board->n_aochan) {
6033 s->type = COMEDI_SUBD_AO;
6034 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
6035 if (devpriv->is_m_series)
6036 s->subdev_flags |= SDF_SOFT_CALIBRATED;
6037 s->n_chan = board->n_aochan;
6038 s->maxdata = board->ao_maxdata;
6039 s->range_table = board->ao_range_table;
6040 s->insn_config = ni_ao_insn_config;
6041 s->insn_write = ni_ao_insn_write;
6043 ret = comedi_alloc_subdev_readback(s);
6048 * Along with the IRQ we need either a FIFO or DMA for
6049 * async command support.
6051 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
6052 dev->write_subdev = s;
6053 s->subdev_flags |= SDF_CMD_WRITE;
6054 s->len_chanlist = s->n_chan;
6055 s->do_cmdtest = ni_ao_cmdtest;
6056 s->do_cmd = ni_ao_cmd;
6057 s->cancel = ni_ao_reset;
6058 if (!devpriv->is_m_series)
6059 s->munge = ni_ao_munge;
6062 s->async_dma_dir = DMA_TO_DEVICE;
6065 if (devpriv->is_67xx)
6066 init_ao_67xx(dev, s);
6068 /* reset the analog output configuration */
6069 ni_ao_reset(dev, s);
6071 s->type = COMEDI_SUBD_UNUSED;
6074 /* Digital I/O subdevice */
6075 s = &dev->subdevices[NI_DIO_SUBDEV];
6076 s->type = COMEDI_SUBD_DIO;
6077 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
6078 s->n_chan = board->has_32dio_chan ? 32 : 8;
6080 s->range_table = &range_digital;
6081 if (devpriv->is_m_series) {
6083 s->subdev_flags |= SDF_LSAMPL;
6084 s->insn_bits = ni_m_series_dio_insn_bits;
6085 s->insn_config = ni_m_series_dio_insn_config;
6087 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
6088 s->len_chanlist = s->n_chan;
6089 s->do_cmdtest = ni_cdio_cmdtest;
6090 s->do_cmd = ni_cdio_cmd;
6091 s->cancel = ni_cdio_cancel;
6093 /* M-series boards use DMA */
6094 s->async_dma_dir = DMA_BIDIRECTIONAL;
6097 /* reset DIO and set all channels to inputs */
6098 ni_writel(dev, NI_M_CDO_CMD_RESET |
6101 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
6104 s->insn_bits = ni_dio_insn_bits;
6105 s->insn_config = ni_dio_insn_config;
6107 /* set all channels to inputs */
6108 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
6109 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
6113 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
6114 if (board->has_8255) {
6115 ret = subdev_8255_init(dev, s, ni_8255_callback,
6120 s->type = COMEDI_SUBD_UNUSED;
6123 /* formerly general purpose counter/timer device, but no longer used */
6124 s = &dev->subdevices[NI_UNUSED_SUBDEV];
6125 s->type = COMEDI_SUBD_UNUSED;
6127 /* Calibration subdevice */
6128 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
6129 s->type = COMEDI_SUBD_CALIB;
6130 s->subdev_flags = SDF_INTERNAL;
6133 if (devpriv->is_m_series) {
6134 /* internal PWM output used for AI nonlinearity calibration */
6135 s->insn_config = ni_m_series_pwm_config;
6137 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
6138 } else if (devpriv->is_6143) {
6139 /* internal PWM output used for AI nonlinearity calibration */
6140 s->insn_config = ni_6143_pwm_config;
6142 s->subdev_flags |= SDF_WRITABLE;
6143 s->insn_read = ni_calib_insn_read;
6144 s->insn_write = ni_calib_insn_write;
6146 /* setup the caldacs and find the real n_chan and maxdata */
6147 caldac_setup(dev, s);
6150 /* EEPROM subdevice */
6151 s = &dev->subdevices[NI_EEPROM_SUBDEV];
6152 s->type = COMEDI_SUBD_MEMORY;
6153 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
6155 if (devpriv->is_m_series) {
6156 s->n_chan = M_SERIES_EEPROM_SIZE;
6157 s->insn_read = ni_m_series_eeprom_insn_read;
6160 s->insn_read = ni_eeprom_insn_read;
6163 /* Digital I/O (PFI) subdevice */
6164 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
6165 s->type = COMEDI_SUBD_DIO;
6167 if (devpriv->is_m_series) {
6169 s->insn_bits = ni_pfi_insn_bits;
6170 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6172 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
6173 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
6174 ni_writew(dev, devpriv->pfi_output_select_reg[i],
6175 NI_M_PFI_OUT_SEL_REG(i));
6179 s->subdev_flags = SDF_INTERNAL;
6181 s->insn_config = ni_pfi_insn_config;
6183 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
6185 /* cs5529 calibration adc */
6186 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
6187 if (devpriv->is_67xx) {
6188 s->type = COMEDI_SUBD_AI;
6189 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
6190 /* one channel for each analog output channel */
6191 s->n_chan = board->n_aochan;
6192 s->maxdata = (1 << 16) - 1;
6193 s->range_table = &range_unknown; /* XXX */
6194 s->insn_read = cs5529_ai_insn_read;
6195 s->insn_config = NULL;
6198 s->type = COMEDI_SUBD_UNUSED;
6202 s = &dev->subdevices[NI_SERIAL_SUBDEV];
6203 s->type = COMEDI_SUBD_SERIAL;
6204 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6207 s->insn_config = ni_serial_insn_config;
6208 devpriv->serial_interval_ns = 0;
6209 devpriv->serial_hw_mode = 0;
6212 s = &dev->subdevices[NI_RTSI_SUBDEV];
6213 s->type = COMEDI_SUBD_DIO;
6214 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6217 s->insn_bits = ni_rtsi_insn_bits;
6218 s->insn_config = ni_rtsi_insn_config;
6221 /* allocate and initialize the gpct counter device */
6222 devpriv->counter_dev = ni_gpct_device_construct(dev,
6223 ni_gpct_write_register,
6224 ni_gpct_read_register,
6225 (devpriv->is_m_series)
6226 ? ni_gpct_variant_m_series
6227 : ni_gpct_variant_e_series,
6230 &devpriv->routing_tables);
6231 if (!devpriv->counter_dev)
6234 /* Counter (gpct) subdevices */
6235 for (i = 0; i < NUM_GPCT; ++i) {
6236 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
6238 /* setup and initialize the counter */
6239 ni_tio_init_counter(gpct);
6241 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
6242 s->type = COMEDI_SUBD_COUNTER;
6243 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
6245 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
6247 s->insn_read = ni_tio_insn_read;
6248 s->insn_write = ni_tio_insn_write;
6249 s->insn_config = ni_tio_insn_config;
6251 if (dev->irq && devpriv->mite) {
6252 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
6253 s->len_chanlist = 1;
6254 s->do_cmdtest = ni_tio_cmdtest;
6255 s->do_cmd = ni_gpct_cmd;
6256 s->cancel = ni_gpct_cancel;
6258 s->async_dma_dir = DMA_BIDIRECTIONAL;
6264 /* Initialize GPFO_{0,1} to produce output of counters */
6265 ni_set_gout_routing(0, 0, dev); /* output of counter 0; DAQ STC, p338 */
6266 ni_set_gout_routing(0, 1, dev); /* output of counter 1; DAQ STC, p338 */
6268 /* Frequency output subdevice */
6269 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
6270 s->type = COMEDI_SUBD_COUNTER;
6271 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
6274 s->insn_read = ni_freq_out_insn_read;
6275 s->insn_write = ni_freq_out_insn_write;
6276 s->insn_config = ni_freq_out_insn_config;
6280 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
6281 (NISTC_INT_CTRL_3PIN_INT & 0) |
6282 NISTC_INT_CTRL_INTA_ENA |
6283 NISTC_INT_CTRL_INTB_ENA |
6284 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
6285 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
6286 NISTC_INT_CTRL_REG);
6290 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
6291 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
6293 if (devpriv->is_6xxx) {
6294 ni_writeb(dev, 0, NI611X_MAGIC_REG);
6295 } else if (devpriv->is_m_series) {
6298 for (channel = 0; channel < board->n_aochan; ++channel) {
6300 NI_M_AO_WAVEFORM_ORDER_REG(channel));
6302 NI_M_AO_REF_ATTENUATION_REG(channel));
6304 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
6310 static void mio_common_detach(struct comedi_device *dev)
6312 struct ni_private *devpriv = dev->private;
6315 ni_gpct_device_destroy(devpriv->counter_dev);