Merge remote-tracking branches 'spi/topic/rockchip', 'spi/topic/rspi', 'spi/topic...
[sfrench/cifs-2.6.git] / drivers / spi / spi-s3c64xx.c
1 /*
2  * Copyright (C) 2009 Samsung Electronics Ltd.
3  *      Jaswinder Singh <jassi.brar@samsung.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/gpio.h>
27 #include <linux/of.h>
28 #include <linux/of_gpio.h>
29
30 #include <linux/platform_data/spi-s3c64xx.h>
31
32 #define MAX_SPI_PORTS           6
33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
35 #define AUTOSUSPEND_TIMEOUT     2000
36
37 /* Registers and bit-fields */
38
39 #define S3C64XX_SPI_CH_CFG              0x00
40 #define S3C64XX_SPI_CLK_CFG             0x04
41 #define S3C64XX_SPI_MODE_CFG    0x08
42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
43 #define S3C64XX_SPI_INT_EN              0x10
44 #define S3C64XX_SPI_STATUS              0x14
45 #define S3C64XX_SPI_TX_DATA             0x18
46 #define S3C64XX_SPI_RX_DATA             0x1C
47 #define S3C64XX_SPI_PACKET_CNT  0x20
48 #define S3C64XX_SPI_PENDING_CLR 0x24
49 #define S3C64XX_SPI_SWAP_CFG    0x28
50 #define S3C64XX_SPI_FB_CLK              0x2C
51
52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
55 #define S3C64XX_SPI_CPOL_L              (1<<3)
56 #define S3C64XX_SPI_CPHA_B              (1<<2)
57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
59
60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
63 #define S3C64XX_SPI_PSR_MASK            0xff
64
65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
76
77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
80
81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
88
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
95
96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
97
98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
103
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
112
113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
114
115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
120                                         FIFO_LVL_MASK(i))
121
122 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF        19
124
125 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
126
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
129
130 #define RXBUSY    (1<<2)
131 #define TXBUSY    (1<<3)
132
133 struct s3c64xx_spi_dma_data {
134         struct dma_chan *ch;
135         enum dma_transfer_direction direction;
136 };
137
138 /**
139  * struct s3c64xx_spi_info - SPI Controller hardware info
140  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
141  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
142  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
143  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
144  * @clk_from_cmu: True, if the controller does not include a clock mux and
145  *      prescaler unit.
146  *
147  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
148  * differ in some aspects such as the size of the fifo and spi bus clock
149  * setup. Such differences are specified to the driver using this structure
150  * which is provided as driver data to the driver.
151  */
152 struct s3c64xx_spi_port_config {
153         int     fifo_lvl_mask[MAX_SPI_PORTS];
154         int     rx_lvl_offset;
155         int     tx_st_done;
156         int     quirks;
157         bool    high_speed;
158         bool    clk_from_cmu;
159         bool    clk_ioclk;
160 };
161
162 /**
163  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164  * @clk: Pointer to the spi clock.
165  * @src_clk: Pointer to the clock used to generate SPI signals.
166  * @ioclk: Pointer to the i/o clock between master and slave
167  * @master: Pointer to the SPI Protocol master.
168  * @cntrlr_info: Platform specific data for the controller this driver manages.
169  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
170  * @lock: Controller specific lock.
171  * @state: Set of FLAGS to indicate status.
172  * @rx_dmach: Controller's DMA channel for Rx.
173  * @tx_dmach: Controller's DMA channel for Tx.
174  * @sfr_start: BUS address of SPI controller regs.
175  * @regs: Pointer to ioremap'ed controller registers.
176  * @irq: interrupt
177  * @xfer_completion: To indicate completion of xfer task.
178  * @cur_mode: Stores the active configuration of the controller.
179  * @cur_bpw: Stores the active bits per word settings.
180  * @cur_speed: Stores the active xfer clock speed.
181  */
182 struct s3c64xx_spi_driver_data {
183         void __iomem                    *regs;
184         struct clk                      *clk;
185         struct clk                      *src_clk;
186         struct clk                      *ioclk;
187         struct platform_device          *pdev;
188         struct spi_master               *master;
189         struct s3c64xx_spi_info  *cntrlr_info;
190         struct spi_device               *tgl_spi;
191         spinlock_t                      lock;
192         unsigned long                   sfr_start;
193         struct completion               xfer_completion;
194         unsigned                        state;
195         unsigned                        cur_mode, cur_bpw;
196         unsigned                        cur_speed;
197         struct s3c64xx_spi_dma_data     rx_dma;
198         struct s3c64xx_spi_dma_data     tx_dma;
199         struct s3c64xx_spi_port_config  *port_conf;
200         unsigned int                    port_id;
201 };
202
203 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
204 {
205         void __iomem *regs = sdd->regs;
206         unsigned long loops;
207         u32 val;
208
209         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
210
211         val = readl(regs + S3C64XX_SPI_CH_CFG);
212         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
213         writel(val, regs + S3C64XX_SPI_CH_CFG);
214
215         val = readl(regs + S3C64XX_SPI_CH_CFG);
216         val |= S3C64XX_SPI_CH_SW_RST;
217         val &= ~S3C64XX_SPI_CH_HS_EN;
218         writel(val, regs + S3C64XX_SPI_CH_CFG);
219
220         /* Flush TxFIFO*/
221         loops = msecs_to_loops(1);
222         do {
223                 val = readl(regs + S3C64XX_SPI_STATUS);
224         } while (TX_FIFO_LVL(val, sdd) && loops--);
225
226         if (loops == 0)
227                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
228
229         /* Flush RxFIFO*/
230         loops = msecs_to_loops(1);
231         do {
232                 val = readl(regs + S3C64XX_SPI_STATUS);
233                 if (RX_FIFO_LVL(val, sdd))
234                         readl(regs + S3C64XX_SPI_RX_DATA);
235                 else
236                         break;
237         } while (loops--);
238
239         if (loops == 0)
240                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
241
242         val = readl(regs + S3C64XX_SPI_CH_CFG);
243         val &= ~S3C64XX_SPI_CH_SW_RST;
244         writel(val, regs + S3C64XX_SPI_CH_CFG);
245
246         val = readl(regs + S3C64XX_SPI_MODE_CFG);
247         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
248         writel(val, regs + S3C64XX_SPI_MODE_CFG);
249 }
250
251 static void s3c64xx_spi_dmacb(void *data)
252 {
253         struct s3c64xx_spi_driver_data *sdd;
254         struct s3c64xx_spi_dma_data *dma = data;
255         unsigned long flags;
256
257         if (dma->direction == DMA_DEV_TO_MEM)
258                 sdd = container_of(data,
259                         struct s3c64xx_spi_driver_data, rx_dma);
260         else
261                 sdd = container_of(data,
262                         struct s3c64xx_spi_driver_data, tx_dma);
263
264         spin_lock_irqsave(&sdd->lock, flags);
265
266         if (dma->direction == DMA_DEV_TO_MEM) {
267                 sdd->state &= ~RXBUSY;
268                 if (!(sdd->state & TXBUSY))
269                         complete(&sdd->xfer_completion);
270         } else {
271                 sdd->state &= ~TXBUSY;
272                 if (!(sdd->state & RXBUSY))
273                         complete(&sdd->xfer_completion);
274         }
275
276         spin_unlock_irqrestore(&sdd->lock, flags);
277 }
278
279 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
280                         struct sg_table *sgt)
281 {
282         struct s3c64xx_spi_driver_data *sdd;
283         struct dma_slave_config config;
284         struct dma_async_tx_descriptor *desc;
285
286         memset(&config, 0, sizeof(config));
287
288         if (dma->direction == DMA_DEV_TO_MEM) {
289                 sdd = container_of((void *)dma,
290                         struct s3c64xx_spi_driver_data, rx_dma);
291                 config.direction = dma->direction;
292                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
293                 config.src_addr_width = sdd->cur_bpw / 8;
294                 config.src_maxburst = 1;
295                 dmaengine_slave_config(dma->ch, &config);
296         } else {
297                 sdd = container_of((void *)dma,
298                         struct s3c64xx_spi_driver_data, tx_dma);
299                 config.direction = dma->direction;
300                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
301                 config.dst_addr_width = sdd->cur_bpw / 8;
302                 config.dst_maxburst = 1;
303                 dmaengine_slave_config(dma->ch, &config);
304         }
305
306         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
307                                        dma->direction, DMA_PREP_INTERRUPT);
308
309         desc->callback = s3c64xx_spi_dmacb;
310         desc->callback_param = dma;
311
312         dmaengine_submit(desc);
313         dma_async_issue_pending(dma->ch);
314 }
315
316 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
317 {
318         struct s3c64xx_spi_driver_data *sdd =
319                                         spi_master_get_devdata(spi->master);
320
321         if (sdd->cntrlr_info->no_cs)
322                 return;
323
324         if (enable) {
325                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
326                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
327                 } else {
328                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
329
330                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
331                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
332                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
333                 }
334         } else {
335                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
336                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
337                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
338         }
339 }
340
341 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
342 {
343         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
344
345         if (is_polling(sdd))
346                 return 0;
347
348         spi->dma_rx = sdd->rx_dma.ch;
349         spi->dma_tx = sdd->tx_dma.ch;
350
351         return 0;
352 }
353
354 static bool s3c64xx_spi_can_dma(struct spi_master *master,
355                                 struct spi_device *spi,
356                                 struct spi_transfer *xfer)
357 {
358         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
359
360         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
361 }
362
363 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
364                                 struct spi_device *spi,
365                                 struct spi_transfer *xfer, int dma_mode)
366 {
367         void __iomem *regs = sdd->regs;
368         u32 modecfg, chcfg;
369
370         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
371         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
372
373         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
374         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
375
376         if (dma_mode) {
377                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
378         } else {
379                 /* Always shift in data in FIFO, even if xfer is Tx only,
380                  * this helps setting PCKT_CNT value for generating clocks
381                  * as exactly needed.
382                  */
383                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
384                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
385                                         | S3C64XX_SPI_PACKET_CNT_EN,
386                                         regs + S3C64XX_SPI_PACKET_CNT);
387         }
388
389         if (xfer->tx_buf != NULL) {
390                 sdd->state |= TXBUSY;
391                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
392                 if (dma_mode) {
393                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
394                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
395                 } else {
396                         switch (sdd->cur_bpw) {
397                         case 32:
398                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
399                                         xfer->tx_buf, xfer->len / 4);
400                                 break;
401                         case 16:
402                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
403                                         xfer->tx_buf, xfer->len / 2);
404                                 break;
405                         default:
406                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
407                                         xfer->tx_buf, xfer->len);
408                                 break;
409                         }
410                 }
411         }
412
413         if (xfer->rx_buf != NULL) {
414                 sdd->state |= RXBUSY;
415
416                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
417                                         && !(sdd->cur_mode & SPI_CPHA))
418                         chcfg |= S3C64XX_SPI_CH_HS_EN;
419
420                 if (dma_mode) {
421                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
422                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
423                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
424                                         | S3C64XX_SPI_PACKET_CNT_EN,
425                                         regs + S3C64XX_SPI_PACKET_CNT);
426                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
427                 }
428         }
429
430         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
431         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
432 }
433
434 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
435                                         int timeout_ms)
436 {
437         void __iomem *regs = sdd->regs;
438         unsigned long val = 1;
439         u32 status;
440
441         /* max fifo depth available */
442         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
443
444         if (timeout_ms)
445                 val = msecs_to_loops(timeout_ms);
446
447         do {
448                 status = readl(regs + S3C64XX_SPI_STATUS);
449         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
450
451         /* return the actual received data length */
452         return RX_FIFO_LVL(status, sdd);
453 }
454
455 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
456                         struct spi_transfer *xfer)
457 {
458         void __iomem *regs = sdd->regs;
459         unsigned long val;
460         u32 status;
461         int ms;
462
463         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
464         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
465         ms += 10; /* some tolerance */
466
467         val = msecs_to_jiffies(ms) + 10;
468         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
469
470         /*
471          * If the previous xfer was completed within timeout, then
472          * proceed further else return -EIO.
473          * DmaTx returns after simply writing data in the FIFO,
474          * w/o waiting for real transmission on the bus to finish.
475          * DmaRx returns only after Dma read data from FIFO which
476          * needs bus transmission to finish, so we don't worry if
477          * Xfer involved Rx(with or without Tx).
478          */
479         if (val && !xfer->rx_buf) {
480                 val = msecs_to_loops(10);
481                 status = readl(regs + S3C64XX_SPI_STATUS);
482                 while ((TX_FIFO_LVL(status, sdd)
483                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
484                        && --val) {
485                         cpu_relax();
486                         status = readl(regs + S3C64XX_SPI_STATUS);
487                 }
488
489         }
490
491         /* If timed out while checking rx/tx status return error */
492         if (!val)
493                 return -EIO;
494
495         return 0;
496 }
497
498 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
499                         struct spi_transfer *xfer)
500 {
501         void __iomem *regs = sdd->regs;
502         unsigned long val;
503         u32 status;
504         int loops;
505         u32 cpy_len;
506         u8 *buf;
507         int ms;
508
509         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
510         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
511         ms += 10; /* some tolerance */
512
513         val = msecs_to_loops(ms);
514         do {
515                 status = readl(regs + S3C64XX_SPI_STATUS);
516         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
517
518
519         /* If it was only Tx */
520         if (!xfer->rx_buf) {
521                 sdd->state &= ~TXBUSY;
522                 return 0;
523         }
524
525         /*
526          * If the receive length is bigger than the controller fifo
527          * size, calculate the loops and read the fifo as many times.
528          * loops = length / max fifo size (calculated by using the
529          * fifo mask).
530          * For any size less than the fifo size the below code is
531          * executed atleast once.
532          */
533         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
534         buf = xfer->rx_buf;
535         do {
536                 /* wait for data to be received in the fifo */
537                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
538                                                        (loops ? ms : 0));
539
540                 switch (sdd->cur_bpw) {
541                 case 32:
542                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
543                                      buf, cpy_len / 4);
544                         break;
545                 case 16:
546                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
547                                      buf, cpy_len / 2);
548                         break;
549                 default:
550                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
551                                     buf, cpy_len);
552                         break;
553                 }
554
555                 buf = buf + cpy_len;
556         } while (loops--);
557         sdd->state &= ~RXBUSY;
558
559         return 0;
560 }
561
562 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
563 {
564         void __iomem *regs = sdd->regs;
565         u32 val;
566
567         /* Disable Clock */
568         if (!sdd->port_conf->clk_from_cmu) {
569                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
570                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
571                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
572         }
573
574         /* Set Polarity and Phase */
575         val = readl(regs + S3C64XX_SPI_CH_CFG);
576         val &= ~(S3C64XX_SPI_CH_SLAVE |
577                         S3C64XX_SPI_CPOL_L |
578                         S3C64XX_SPI_CPHA_B);
579
580         if (sdd->cur_mode & SPI_CPOL)
581                 val |= S3C64XX_SPI_CPOL_L;
582
583         if (sdd->cur_mode & SPI_CPHA)
584                 val |= S3C64XX_SPI_CPHA_B;
585
586         writel(val, regs + S3C64XX_SPI_CH_CFG);
587
588         /* Set Channel & DMA Mode */
589         val = readl(regs + S3C64XX_SPI_MODE_CFG);
590         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
591                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
592
593         switch (sdd->cur_bpw) {
594         case 32:
595                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
596                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
597                 break;
598         case 16:
599                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
600                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
601                 break;
602         default:
603                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
604                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
605                 break;
606         }
607
608         writel(val, regs + S3C64XX_SPI_MODE_CFG);
609
610         if (sdd->port_conf->clk_from_cmu) {
611                 /* The src_clk clock is divided internally by 2 */
612                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
613         } else {
614                 /* Configure Clock */
615                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
616                 val &= ~S3C64XX_SPI_PSR_MASK;
617                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
618                                 & S3C64XX_SPI_PSR_MASK);
619                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
620
621                 /* Enable Clock */
622                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
623                 val |= S3C64XX_SPI_ENCLK_ENABLE;
624                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
625         }
626 }
627
628 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
629
630 static int s3c64xx_spi_prepare_message(struct spi_master *master,
631                                        struct spi_message *msg)
632 {
633         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
634         struct spi_device *spi = msg->spi;
635         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
636
637         /* Configure feedback delay */
638         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
639
640         return 0;
641 }
642
643 static int s3c64xx_spi_transfer_one(struct spi_master *master,
644                                     struct spi_device *spi,
645                                     struct spi_transfer *xfer)
646 {
647         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
648         int status;
649         u32 speed;
650         u8 bpw;
651         unsigned long flags;
652         int use_dma;
653
654         reinit_completion(&sdd->xfer_completion);
655
656         /* Only BPW and Speed may change across transfers */
657         bpw = xfer->bits_per_word;
658         speed = xfer->speed_hz;
659
660         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
661                 sdd->cur_bpw = bpw;
662                 sdd->cur_speed = speed;
663                 sdd->cur_mode = spi->mode;
664                 s3c64xx_spi_config(sdd);
665         }
666
667         /* Polling method for xfers not bigger than FIFO capacity */
668         use_dma = 0;
669         if (!is_polling(sdd) &&
670             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
671              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
672                 use_dma = 1;
673
674         spin_lock_irqsave(&sdd->lock, flags);
675
676         /* Pending only which is to be done */
677         sdd->state &= ~RXBUSY;
678         sdd->state &= ~TXBUSY;
679
680         enable_datapath(sdd, spi, xfer, use_dma);
681
682         /* Start the signals */
683         s3c64xx_spi_set_cs(spi, true);
684
685         spin_unlock_irqrestore(&sdd->lock, flags);
686
687         if (use_dma)
688                 status = wait_for_dma(sdd, xfer);
689         else
690                 status = wait_for_pio(sdd, xfer);
691
692         if (status) {
693                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
694                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
695                         (sdd->state & RXBUSY) ? 'f' : 'p',
696                         (sdd->state & TXBUSY) ? 'f' : 'p',
697                         xfer->len);
698
699                 if (use_dma) {
700                         if (xfer->tx_buf != NULL
701                             && (sdd->state & TXBUSY))
702                                 dmaengine_terminate_all(sdd->tx_dma.ch);
703                         if (xfer->rx_buf != NULL
704                             && (sdd->state & RXBUSY))
705                                 dmaengine_terminate_all(sdd->rx_dma.ch);
706                 }
707         } else {
708                 flush_fifo(sdd);
709         }
710
711         return status;
712 }
713
714 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
715                                 struct spi_device *spi)
716 {
717         struct s3c64xx_spi_csinfo *cs;
718         struct device_node *slave_np, *data_np = NULL;
719         u32 fb_delay = 0;
720
721         slave_np = spi->dev.of_node;
722         if (!slave_np) {
723                 dev_err(&spi->dev, "device node not found\n");
724                 return ERR_PTR(-EINVAL);
725         }
726
727         data_np = of_get_child_by_name(slave_np, "controller-data");
728         if (!data_np) {
729                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
730                 return ERR_PTR(-EINVAL);
731         }
732
733         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
734         if (!cs) {
735                 of_node_put(data_np);
736                 return ERR_PTR(-ENOMEM);
737         }
738
739         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
740         cs->fb_delay = fb_delay;
741         of_node_put(data_np);
742         return cs;
743 }
744
745 /*
746  * Here we only check the validity of requested configuration
747  * and save the configuration in a local data-structure.
748  * The controller is actually configured only just before we
749  * get a message to transfer.
750  */
751 static int s3c64xx_spi_setup(struct spi_device *spi)
752 {
753         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
754         struct s3c64xx_spi_driver_data *sdd;
755         struct s3c64xx_spi_info *sci;
756         int err;
757
758         sdd = spi_master_get_devdata(spi->master);
759         if (spi->dev.of_node) {
760                 cs = s3c64xx_get_slave_ctrldata(spi);
761                 spi->controller_data = cs;
762         } else if (cs) {
763                 /* On non-DT platforms the SPI core will set spi->cs_gpio
764                  * to -ENOENT. The GPIO pin used to drive the chip select
765                  * is defined by using platform data so spi->cs_gpio value
766                  * has to be override to have the proper GPIO pin number.
767                  */
768                 spi->cs_gpio = cs->line;
769         }
770
771         if (IS_ERR_OR_NULL(cs)) {
772                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
773                 return -ENODEV;
774         }
775
776         if (!spi_get_ctldata(spi)) {
777                 if (gpio_is_valid(spi->cs_gpio)) {
778                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
779                                                dev_name(&spi->dev));
780                         if (err) {
781                                 dev_err(&spi->dev,
782                                         "Failed to get /CS gpio [%d]: %d\n",
783                                         spi->cs_gpio, err);
784                                 goto err_gpio_req;
785                         }
786                 }
787
788                 spi_set_ctldata(spi, cs);
789         }
790
791         sci = sdd->cntrlr_info;
792
793         pm_runtime_get_sync(&sdd->pdev->dev);
794
795         /* Check if we can provide the requested rate */
796         if (!sdd->port_conf->clk_from_cmu) {
797                 u32 psr, speed;
798
799                 /* Max possible */
800                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
801
802                 if (spi->max_speed_hz > speed)
803                         spi->max_speed_hz = speed;
804
805                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
806                 psr &= S3C64XX_SPI_PSR_MASK;
807                 if (psr == S3C64XX_SPI_PSR_MASK)
808                         psr--;
809
810                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
811                 if (spi->max_speed_hz < speed) {
812                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
813                                 psr++;
814                         } else {
815                                 err = -EINVAL;
816                                 goto setup_exit;
817                         }
818                 }
819
820                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
821                 if (spi->max_speed_hz >= speed) {
822                         spi->max_speed_hz = speed;
823                 } else {
824                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
825                                 spi->max_speed_hz);
826                         err = -EINVAL;
827                         goto setup_exit;
828                 }
829         }
830
831         pm_runtime_mark_last_busy(&sdd->pdev->dev);
832         pm_runtime_put_autosuspend(&sdd->pdev->dev);
833         s3c64xx_spi_set_cs(spi, false);
834
835         return 0;
836
837 setup_exit:
838         pm_runtime_mark_last_busy(&sdd->pdev->dev);
839         pm_runtime_put_autosuspend(&sdd->pdev->dev);
840         /* setup() returns with device de-selected */
841         s3c64xx_spi_set_cs(spi, false);
842
843         if (gpio_is_valid(spi->cs_gpio))
844                 gpio_free(spi->cs_gpio);
845         spi_set_ctldata(spi, NULL);
846
847 err_gpio_req:
848         if (spi->dev.of_node)
849                 kfree(cs);
850
851         return err;
852 }
853
854 static void s3c64xx_spi_cleanup(struct spi_device *spi)
855 {
856         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
857
858         if (gpio_is_valid(spi->cs_gpio)) {
859                 gpio_free(spi->cs_gpio);
860                 if (spi->dev.of_node)
861                         kfree(cs);
862                 else {
863                         /* On non-DT platforms, the SPI core sets
864                          * spi->cs_gpio to -ENOENT and .setup()
865                          * overrides it with the GPIO pin value
866                          * passed using platform data.
867                          */
868                         spi->cs_gpio = -ENOENT;
869                 }
870         }
871
872         spi_set_ctldata(spi, NULL);
873 }
874
875 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
876 {
877         struct s3c64xx_spi_driver_data *sdd = data;
878         struct spi_master *spi = sdd->master;
879         unsigned int val, clr = 0;
880
881         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
882
883         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
884                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
885                 dev_err(&spi->dev, "RX overrun\n");
886         }
887         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
888                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
889                 dev_err(&spi->dev, "RX underrun\n");
890         }
891         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
892                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
893                 dev_err(&spi->dev, "TX overrun\n");
894         }
895         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
896                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
897                 dev_err(&spi->dev, "TX underrun\n");
898         }
899
900         /* Clear the pending irq by setting and then clearing it */
901         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
902         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
903
904         return IRQ_HANDLED;
905 }
906
907 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
908 {
909         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
910         void __iomem *regs = sdd->regs;
911         unsigned int val;
912
913         sdd->cur_speed = 0;
914
915         if (sci->no_cs)
916                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
917         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
918                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
919
920         /* Disable Interrupts - we use Polling if not DMA mode */
921         writel(0, regs + S3C64XX_SPI_INT_EN);
922
923         if (!sdd->port_conf->clk_from_cmu)
924                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
925                                 regs + S3C64XX_SPI_CLK_CFG);
926         writel(0, regs + S3C64XX_SPI_MODE_CFG);
927         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
928
929         /* Clear any irq pending bits, should set and clear the bits */
930         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
931                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
932                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
933                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
934         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
935         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
936
937         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
938
939         val = readl(regs + S3C64XX_SPI_MODE_CFG);
940         val &= ~S3C64XX_SPI_MODE_4BURST;
941         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
942         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
943         writel(val, regs + S3C64XX_SPI_MODE_CFG);
944
945         flush_fifo(sdd);
946 }
947
948 #ifdef CONFIG_OF
949 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
950 {
951         struct s3c64xx_spi_info *sci;
952         u32 temp;
953
954         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
955         if (!sci)
956                 return ERR_PTR(-ENOMEM);
957
958         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
959                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
960                 sci->src_clk_nr = 0;
961         } else {
962                 sci->src_clk_nr = temp;
963         }
964
965         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
966                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
967                 sci->num_cs = 1;
968         } else {
969                 sci->num_cs = temp;
970         }
971
972         sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
973
974         return sci;
975 }
976 #else
977 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
978 {
979         return dev_get_platdata(dev);
980 }
981 #endif
982
983 static const struct of_device_id s3c64xx_spi_dt_match[];
984
985 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
986                                                 struct platform_device *pdev)
987 {
988 #ifdef CONFIG_OF
989         if (pdev->dev.of_node) {
990                 const struct of_device_id *match;
991                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
992                 return (struct s3c64xx_spi_port_config *)match->data;
993         }
994 #endif
995         return (struct s3c64xx_spi_port_config *)
996                          platform_get_device_id(pdev)->driver_data;
997 }
998
999 static int s3c64xx_spi_probe(struct platform_device *pdev)
1000 {
1001         struct resource *mem_res;
1002         struct s3c64xx_spi_driver_data *sdd;
1003         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1004         struct spi_master *master;
1005         int ret, irq;
1006         char clk_name[16];
1007
1008         if (!sci && pdev->dev.of_node) {
1009                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1010                 if (IS_ERR(sci))
1011                         return PTR_ERR(sci);
1012         }
1013
1014         if (!sci) {
1015                 dev_err(&pdev->dev, "platform_data missing!\n");
1016                 return -ENODEV;
1017         }
1018
1019         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1020         if (mem_res == NULL) {
1021                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1022                 return -ENXIO;
1023         }
1024
1025         irq = platform_get_irq(pdev, 0);
1026         if (irq < 0) {
1027                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1028                 return irq;
1029         }
1030
1031         master = spi_alloc_master(&pdev->dev,
1032                                 sizeof(struct s3c64xx_spi_driver_data));
1033         if (master == NULL) {
1034                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1035                 return -ENOMEM;
1036         }
1037
1038         platform_set_drvdata(pdev, master);
1039
1040         sdd = spi_master_get_devdata(master);
1041         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1042         sdd->master = master;
1043         sdd->cntrlr_info = sci;
1044         sdd->pdev = pdev;
1045         sdd->sfr_start = mem_res->start;
1046         if (pdev->dev.of_node) {
1047                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1048                 if (ret < 0) {
1049                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1050                                 ret);
1051                         goto err_deref_master;
1052                 }
1053                 sdd->port_id = ret;
1054         } else {
1055                 sdd->port_id = pdev->id;
1056         }
1057
1058         sdd->cur_bpw = 8;
1059
1060         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1061         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1062
1063         master->dev.of_node = pdev->dev.of_node;
1064         master->bus_num = sdd->port_id;
1065         master->setup = s3c64xx_spi_setup;
1066         master->cleanup = s3c64xx_spi_cleanup;
1067         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1068         master->prepare_message = s3c64xx_spi_prepare_message;
1069         master->transfer_one = s3c64xx_spi_transfer_one;
1070         master->num_chipselect = sci->num_cs;
1071         master->dma_alignment = 8;
1072         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1073                                         SPI_BPW_MASK(8);
1074         /* the spi->mode bits understood by this driver: */
1075         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1076         master->auto_runtime_pm = true;
1077         if (!is_polling(sdd))
1078                 master->can_dma = s3c64xx_spi_can_dma;
1079
1080         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1081         if (IS_ERR(sdd->regs)) {
1082                 ret = PTR_ERR(sdd->regs);
1083                 goto err_deref_master;
1084         }
1085
1086         if (sci->cfg_gpio && sci->cfg_gpio()) {
1087                 dev_err(&pdev->dev, "Unable to config gpio\n");
1088                 ret = -EBUSY;
1089                 goto err_deref_master;
1090         }
1091
1092         /* Setup clocks */
1093         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1094         if (IS_ERR(sdd->clk)) {
1095                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1096                 ret = PTR_ERR(sdd->clk);
1097                 goto err_deref_master;
1098         }
1099
1100         ret = clk_prepare_enable(sdd->clk);
1101         if (ret) {
1102                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1103                 goto err_deref_master;
1104         }
1105
1106         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1107         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1108         if (IS_ERR(sdd->src_clk)) {
1109                 dev_err(&pdev->dev,
1110                         "Unable to acquire clock '%s'\n", clk_name);
1111                 ret = PTR_ERR(sdd->src_clk);
1112                 goto err_disable_clk;
1113         }
1114
1115         ret = clk_prepare_enable(sdd->src_clk);
1116         if (ret) {
1117                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1118                 goto err_disable_clk;
1119         }
1120
1121         if (sdd->port_conf->clk_ioclk) {
1122                 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1123                 if (IS_ERR(sdd->ioclk)) {
1124                         dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1125                         ret = PTR_ERR(sdd->ioclk);
1126                         goto err_disable_src_clk;
1127                 }
1128
1129                 ret = clk_prepare_enable(sdd->ioclk);
1130                 if (ret) {
1131                         dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1132                         goto err_disable_src_clk;
1133                 }
1134         }
1135
1136         if (!is_polling(sdd)) {
1137                 /* Acquire DMA channels */
1138                 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1139                                                                   "rx");
1140                 if (IS_ERR(sdd->rx_dma.ch)) {
1141                         dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1142                         ret = PTR_ERR(sdd->rx_dma.ch);
1143                         goto err_disable_io_clk;
1144                 }
1145                 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1146                                                                   "tx");
1147                 if (IS_ERR(sdd->tx_dma.ch)) {
1148                         dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1149                         ret = PTR_ERR(sdd->tx_dma.ch);
1150                         goto err_release_rx_dma;
1151                 }
1152         }
1153
1154         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1155         pm_runtime_use_autosuspend(&pdev->dev);
1156         pm_runtime_set_active(&pdev->dev);
1157         pm_runtime_enable(&pdev->dev);
1158         pm_runtime_get_sync(&pdev->dev);
1159
1160         /* Setup Deufult Mode */
1161         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1162
1163         spin_lock_init(&sdd->lock);
1164         init_completion(&sdd->xfer_completion);
1165
1166         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1167                                 "spi-s3c64xx", sdd);
1168         if (ret != 0) {
1169                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1170                         irq, ret);
1171                 goto err_pm_put;
1172         }
1173
1174         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1175                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1176                sdd->regs + S3C64XX_SPI_INT_EN);
1177
1178         ret = devm_spi_register_master(&pdev->dev, master);
1179         if (ret != 0) {
1180                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1181                 goto err_pm_put;
1182         }
1183
1184         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1185                                         sdd->port_id, master->num_chipselect);
1186         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1187                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1188
1189         pm_runtime_mark_last_busy(&pdev->dev);
1190         pm_runtime_put_autosuspend(&pdev->dev);
1191
1192         return 0;
1193
1194 err_pm_put:
1195         pm_runtime_put_noidle(&pdev->dev);
1196         pm_runtime_disable(&pdev->dev);
1197         pm_runtime_set_suspended(&pdev->dev);
1198
1199         if (!is_polling(sdd))
1200                 dma_release_channel(sdd->tx_dma.ch);
1201 err_release_rx_dma:
1202         if (!is_polling(sdd))
1203                 dma_release_channel(sdd->rx_dma.ch);
1204 err_disable_io_clk:
1205         clk_disable_unprepare(sdd->ioclk);
1206 err_disable_src_clk:
1207         clk_disable_unprepare(sdd->src_clk);
1208 err_disable_clk:
1209         clk_disable_unprepare(sdd->clk);
1210 err_deref_master:
1211         spi_master_put(master);
1212
1213         return ret;
1214 }
1215
1216 static int s3c64xx_spi_remove(struct platform_device *pdev)
1217 {
1218         struct spi_master *master = platform_get_drvdata(pdev);
1219         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1220
1221         pm_runtime_get_sync(&pdev->dev);
1222
1223         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1224
1225         if (!is_polling(sdd)) {
1226                 dma_release_channel(sdd->rx_dma.ch);
1227                 dma_release_channel(sdd->tx_dma.ch);
1228         }
1229
1230         clk_disable_unprepare(sdd->ioclk);
1231
1232         clk_disable_unprepare(sdd->src_clk);
1233
1234         clk_disable_unprepare(sdd->clk);
1235
1236         pm_runtime_put_noidle(&pdev->dev);
1237         pm_runtime_disable(&pdev->dev);
1238         pm_runtime_set_suspended(&pdev->dev);
1239
1240         return 0;
1241 }
1242
1243 #ifdef CONFIG_PM_SLEEP
1244 static int s3c64xx_spi_suspend(struct device *dev)
1245 {
1246         struct spi_master *master = dev_get_drvdata(dev);
1247         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1248
1249         int ret = spi_master_suspend(master);
1250         if (ret)
1251                 return ret;
1252
1253         ret = pm_runtime_force_suspend(dev);
1254         if (ret < 0)
1255                 return ret;
1256
1257         sdd->cur_speed = 0; /* Output Clock is stopped */
1258
1259         return 0;
1260 }
1261
1262 static int s3c64xx_spi_resume(struct device *dev)
1263 {
1264         struct spi_master *master = dev_get_drvdata(dev);
1265         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1266         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1267         int ret;
1268
1269         if (sci->cfg_gpio)
1270                 sci->cfg_gpio();
1271
1272         ret = pm_runtime_force_resume(dev);
1273         if (ret < 0)
1274                 return ret;
1275
1276         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1277
1278         return spi_master_resume(master);
1279 }
1280 #endif /* CONFIG_PM_SLEEP */
1281
1282 #ifdef CONFIG_PM
1283 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1284 {
1285         struct spi_master *master = dev_get_drvdata(dev);
1286         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1287
1288         clk_disable_unprepare(sdd->clk);
1289         clk_disable_unprepare(sdd->src_clk);
1290         clk_disable_unprepare(sdd->ioclk);
1291
1292         return 0;
1293 }
1294
1295 static int s3c64xx_spi_runtime_resume(struct device *dev)
1296 {
1297         struct spi_master *master = dev_get_drvdata(dev);
1298         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1299         int ret;
1300
1301         if (sdd->port_conf->clk_ioclk) {
1302                 ret = clk_prepare_enable(sdd->ioclk);
1303                 if (ret != 0)
1304                         return ret;
1305         }
1306
1307         ret = clk_prepare_enable(sdd->src_clk);
1308         if (ret != 0)
1309                 goto err_disable_ioclk;
1310
1311         ret = clk_prepare_enable(sdd->clk);
1312         if (ret != 0)
1313                 goto err_disable_src_clk;
1314
1315         return 0;
1316
1317 err_disable_src_clk:
1318         clk_disable_unprepare(sdd->src_clk);
1319 err_disable_ioclk:
1320         clk_disable_unprepare(sdd->ioclk);
1321
1322         return ret;
1323 }
1324 #endif /* CONFIG_PM */
1325
1326 static const struct dev_pm_ops s3c64xx_spi_pm = {
1327         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1328         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1329                            s3c64xx_spi_runtime_resume, NULL)
1330 };
1331
1332 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1333         .fifo_lvl_mask  = { 0x7f },
1334         .rx_lvl_offset  = 13,
1335         .tx_st_done     = 21,
1336         .high_speed     = true,
1337 };
1338
1339 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1340         .fifo_lvl_mask  = { 0x7f, 0x7F },
1341         .rx_lvl_offset  = 13,
1342         .tx_st_done     = 21,
1343 };
1344
1345 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1346         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1347         .rx_lvl_offset  = 15,
1348         .tx_st_done     = 25,
1349         .high_speed     = true,
1350 };
1351
1352 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1353         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1354         .rx_lvl_offset  = 15,
1355         .tx_st_done     = 25,
1356         .high_speed     = true,
1357         .clk_from_cmu   = true,
1358 };
1359
1360 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1361         .fifo_lvl_mask  = { 0x1ff },
1362         .rx_lvl_offset  = 15,
1363         .tx_st_done     = 25,
1364         .high_speed     = true,
1365         .clk_from_cmu   = true,
1366         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1367 };
1368
1369 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1370         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1371         .rx_lvl_offset  = 15,
1372         .tx_st_done     = 25,
1373         .high_speed     = true,
1374         .clk_from_cmu   = true,
1375         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1376 };
1377
1378 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1379         .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1380         .rx_lvl_offset  = 15,
1381         .tx_st_done     = 25,
1382         .high_speed     = true,
1383         .clk_from_cmu   = true,
1384         .clk_ioclk      = true,
1385         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1386 };
1387
1388 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1389         {
1390                 .name           = "s3c2443-spi",
1391                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1392         }, {
1393                 .name           = "s3c6410-spi",
1394                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1395         },
1396         { },
1397 };
1398
1399 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1400         { .compatible = "samsung,s3c2443-spi",
1401                         .data = (void *)&s3c2443_spi_port_config,
1402         },
1403         { .compatible = "samsung,s3c6410-spi",
1404                         .data = (void *)&s3c6410_spi_port_config,
1405         },
1406         { .compatible = "samsung,s5pv210-spi",
1407                         .data = (void *)&s5pv210_spi_port_config,
1408         },
1409         { .compatible = "samsung,exynos4210-spi",
1410                         .data = (void *)&exynos4_spi_port_config,
1411         },
1412         { .compatible = "samsung,exynos5440-spi",
1413                         .data = (void *)&exynos5440_spi_port_config,
1414         },
1415         { .compatible = "samsung,exynos7-spi",
1416                         .data = (void *)&exynos7_spi_port_config,
1417         },
1418         { .compatible = "samsung,exynos5433-spi",
1419                         .data = (void *)&exynos5433_spi_port_config,
1420         },
1421         { },
1422 };
1423 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1424
1425 static struct platform_driver s3c64xx_spi_driver = {
1426         .driver = {
1427                 .name   = "s3c64xx-spi",
1428                 .pm = &s3c64xx_spi_pm,
1429                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1430         },
1431         .probe = s3c64xx_spi_probe,
1432         .remove = s3c64xx_spi_remove,
1433         .id_table = s3c64xx_spi_driver_ids,
1434 };
1435 MODULE_ALIAS("platform:s3c64xx-spi");
1436
1437 module_platform_driver(s3c64xx_spi_driver);
1438
1439 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1440 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1441 MODULE_LICENSE("GPL");