drivers/spi/spi-pxa2xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/gpio.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/of.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/property.h>
  27 #include <linux/slab.h>
  28 #include <linux/spi/pxa2xx_spi.h>
  29 #include <linux/spi/spi.h>
  30
  31 #include "spi-pxa2xx.h"
  32
  33 MODULE_AUTHOR("Stephen Street");
  34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  35 MODULE_LICENSE("GPL");
  36 MODULE_ALIAS("platform:pxa2xx-spi");
  37
  38 #define TIMOUT_DFLT             1000
  39
  40 /*
  41  * for testing SSCR1 changes that require SSP restart, basically
  42  * everything except the service and interrupt enables, the pxa270 developer
  43  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  44  * list, but the PXA255 dev man says all bits without really meaning the
  45  * service and interrupt enables
  46  */
  47 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  48                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  49                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  50                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  51                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  52                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  53
  54 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  55                                 | QUARK_X1000_SSCR1_EFWR        \
  56                                 | QUARK_X1000_SSCR1_RFT         \
  57                                 | QUARK_X1000_SSCR1_TFT         \
  58                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  61                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  62                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  63                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  64                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  65                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  66
  67 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  68 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  69 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  70 #define LPSS_CAPS_CS_EN_SHIFT                   9
  71 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  72
  73 struct lpss_config {
  74         /* LPSS offset from drv_data->ioaddr */
  75         unsigned offset;
  76         /* Register offsets from drv_data->lpss_base or -1 */
  77         int reg_general;
  78         int reg_ssp;
  79         int reg_cs_ctrl;
  80         int reg_capabilities;
  81         /* FIFO thresholds */
  82         u32 rx_threshold;
  83         u32 tx_threshold_lo;
  84         u32 tx_threshold_hi;
  85         /* Chip select control */
  86         unsigned cs_sel_shift;
  87         unsigned cs_sel_mask;
  88         unsigned cs_num;
  89 };
  90
  91 /* Keep these sorted with enum pxa_ssp_type */
  92 static const struct lpss_config lpss_platforms[] = {
  93         {       /* LPSS_LPT_SSP */
  94                 .offset = 0x800,
  95                 .reg_general = 0x08,
  96                 .reg_ssp = 0x0c,
  97                 .reg_cs_ctrl = 0x18,
  98                 .reg_capabilities = -1,
  99                 .rx_threshold = 64,
 100                 .tx_threshold_lo = 160,
 101                 .tx_threshold_hi = 224,
 102         },
 103         {       /* LPSS_BYT_SSP */
 104                 .offset = 0x400,
 105                 .reg_general = 0x08,
 106                 .reg_ssp = 0x0c,
 107                 .reg_cs_ctrl = 0x18,
 108                 .reg_capabilities = -1,
 109                 .rx_threshold = 64,
 110                 .tx_threshold_lo = 160,
 111                 .tx_threshold_hi = 224,
 112         },
 113         {       /* LPSS_BSW_SSP */
 114                 .offset = 0x400,
 115                 .reg_general = 0x08,
 116                 .reg_ssp = 0x0c,
 117                 .reg_cs_ctrl = 0x18,
 118                 .reg_capabilities = -1,
 119                 .rx_threshold = 64,
 120                 .tx_threshold_lo = 160,
 121                 .tx_threshold_hi = 224,
 122                 .cs_sel_shift = 2,
 123                 .cs_sel_mask = 1 << 2,
 124                 .cs_num = 2,
 125         },
 126         {       /* LPSS_SPT_SSP */
 127                 .offset = 0x200,
 128                 .reg_general = -1,
 129                 .reg_ssp = 0x20,
 130                 .reg_cs_ctrl = 0x24,
 131                 .reg_capabilities = -1,
 132                 .rx_threshold = 1,
 133                 .tx_threshold_lo = 32,
 134                 .tx_threshold_hi = 56,
 135         },
 136         {       /* LPSS_BXT_SSP */
 137                 .offset = 0x200,
 138                 .reg_general = -1,
 139                 .reg_ssp = 0x20,
 140                 .reg_cs_ctrl = 0x24,
 141                 .reg_capabilities = 0xfc,
 142                 .rx_threshold = 1,
 143                 .tx_threshold_lo = 16,
 144                 .tx_threshold_hi = 48,
 145                 .cs_sel_shift = 8,
 146                 .cs_sel_mask = 3 << 8,
 147         },
 148         {       /* LPSS_CNL_SSP */
 149                 .offset = 0x200,
 150                 .reg_general = -1,
 151                 .reg_ssp = 0x20,
 152                 .reg_cs_ctrl = 0x24,
 153                 .reg_capabilities = 0xfc,
 154                 .rx_threshold = 1,
 155                 .tx_threshold_lo = 32,
 156                 .tx_threshold_hi = 56,
 157                 .cs_sel_shift = 8,
 158                 .cs_sel_mask = 3 << 8,
 159         },
 160 };
 161
 162 static inline const struct lpss_config
 163 *lpss_get_config(const struct driver_data *drv_data)
 164 {
 165         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 166 }
 167
 168 static bool is_lpss_ssp(const struct driver_data *drv_data)
 169 {
 170         switch (drv_data->ssp_type) {
 171         case LPSS_LPT_SSP:
 172         case LPSS_BYT_SSP:
 173         case LPSS_BSW_SSP:
 174         case LPSS_SPT_SSP:
 175         case LPSS_BXT_SSP:
 176         case LPSS_CNL_SSP:
 177                 return true;
 178         default:
 179                 return false;
 180         }
 181 }
 182
 183 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 184 {
 185         return drv_data->ssp_type == QUARK_X1000_SSP;
 186 }
 187
 188 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 189 {
 190         switch (drv_data->ssp_type) {
 191         case QUARK_X1000_SSP:
 192                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 193         case CE4100_SSP:
 194                 return CE4100_SSCR1_CHANGE_MASK;
 195         default:
 196                 return SSCR1_CHANGE_MASK;
 197         }
 198 }
 199
 200 static u32
 201 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 202 {
 203         switch (drv_data->ssp_type) {
 204         case QUARK_X1000_SSP:
 205                 return RX_THRESH_QUARK_X1000_DFLT;
 206         case CE4100_SSP:
 207                 return RX_THRESH_CE4100_DFLT;
 208         default:
 209                 return RX_THRESH_DFLT;
 210         }
 211 }
 212
 213 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 214 {
 215         u32 mask;
 216
 217         switch (drv_data->ssp_type) {
 218         case QUARK_X1000_SSP:
 219                 mask = QUARK_X1000_SSSR_TFL_MASK;
 220                 break;
 221         case CE4100_SSP:
 222                 mask = CE4100_SSSR_TFL_MASK;
 223                 break;
 224         default:
 225                 mask = SSSR_TFL_MASK;
 226                 break;
 227         }
 228
 229         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 230 }
 231
 232 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 233                                      u32 *sccr1_reg)
 234 {
 235         u32 mask;
 236
 237         switch (drv_data->ssp_type) {
 238         case QUARK_X1000_SSP:
 239                 mask = QUARK_X1000_SSCR1_RFT;
 240                 break;
 241         case CE4100_SSP:
 242                 mask = CE4100_SSCR1_RFT;
 243                 break;
 244         default:
 245                 mask = SSCR1_RFT;
 246                 break;
 247         }
 248         *sccr1_reg &= ~mask;
 249 }
 250
 251 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 252                                    u32 *sccr1_reg, u32 threshold)
 253 {
 254         switch (drv_data->ssp_type) {
 255         case QUARK_X1000_SSP:
 256                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 257                 break;
 258         case CE4100_SSP:
 259                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 260                 break;
 261         default:
 262                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 263                 break;
 264         }
 265 }
 266
 267 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 268                                   u32 clk_div, u8 bits)
 269 {
 270         switch (drv_data->ssp_type) {
 271         case QUARK_X1000_SSP:
 272                 return clk_div
 273                         | QUARK_X1000_SSCR0_Motorola
 274                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 275                         | SSCR0_SSE;
 276         default:
 277                 return clk_div
 278                         | SSCR0_Motorola
 279                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 280                         | SSCR0_SSE
 281                         | (bits > 16 ? SSCR0_EDSS : 0);
 282         }
 283 }
 284
 285 /*
 286  * Read and write LPSS SSP private registers. Caller must first check that
 287  * is_lpss_ssp() returns true before these can be called.
 288  */
 289 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 290 {
 291         WARN_ON(!drv_data->lpss_base);
 292         return readl(drv_data->lpss_base + offset);
 293 }
 294
 295 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 296                                   unsigned offset, u32 value)
 297 {
 298         WARN_ON(!drv_data->lpss_base);
 299         writel(value, drv_data->lpss_base + offset);
 300 }
 301
 302 /*
 303  * lpss_ssp_setup - perform LPSS SSP specific setup
 304  * @drv_data: pointer to the driver private data
 305  *
 306  * Perform LPSS SSP specific setup. This function must be called first if
 307  * one is going to use LPSS SSP private registers.
 308  */
 309 static void lpss_ssp_setup(struct driver_data *drv_data)
 310 {
 311         const struct lpss_config *config;
 312         u32 value;
 313
 314         config = lpss_get_config(drv_data);
 315         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 316
 317         /* Enable software chip select control */
 318         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 319         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 320         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 321         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 322
 323         /* Enable multiblock DMA transfers */
 324         if (drv_data->controller_info->enable_dma) {
 325                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 326
 327                 if (config->reg_general >= 0) {
 328                         value = __lpss_ssp_read_priv(drv_data,
 329                                                      config->reg_general);
 330                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 331                         __lpss_ssp_write_priv(drv_data,
 332                                               config->reg_general, value);
 333                 }
 334         }
 335 }
 336
 337 static void lpss_ssp_select_cs(struct spi_device *spi,
 338                                const struct lpss_config *config)
 339 {
 340         struct driver_data *drv_data =
 341                 spi_controller_get_devdata(spi->controller);
 342         u32 value, cs;
 343
 344         if (!config->cs_sel_mask)
 345                 return;
 346
 347         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 348
 349         cs = spi->chip_select;
 350         cs <<= config->cs_sel_shift;
 351         if (cs != (value & config->cs_sel_mask)) {
 352                 /*
 353                  * When switching another chip select output active the
 354                  * output must be selected first and wait 2 ssp_clk cycles
 355                  * before changing state to active. Otherwise a short
 356                  * glitch will occur on the previous chip select since
 357                  * output select is latched but state control is not.
 358                  */
 359                 value &= ~config->cs_sel_mask;
 360                 value |= cs;
 361                 __lpss_ssp_write_priv(drv_data,
 362                                       config->reg_cs_ctrl, value);
 363                 ndelay(1000000000 /
 364                        (drv_data->controller->max_speed_hz / 2));
 365         }
 366 }
 367
 368 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 369 {
 370         struct driver_data *drv_data =
 371                 spi_controller_get_devdata(spi->controller);
 372         const struct lpss_config *config;
 373         u32 value;
 374
 375         config = lpss_get_config(drv_data);
 376
 377         if (enable)
 378                 lpss_ssp_select_cs(spi, config);
 379
 380         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 381         if (enable)
 382                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 383         else
 384                 value |= LPSS_CS_CONTROL_CS_HIGH;
 385         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 386 }
 387
 388 static void cs_assert(struct spi_device *spi)
 389 {
 390         struct chip_data *chip = spi_get_ctldata(spi);
 391         struct driver_data *drv_data =
 392                 spi_controller_get_devdata(spi->controller);
 393
 394         if (drv_data->ssp_type == CE4100_SSP) {
 395                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 396                 return;
 397         }
 398
 399         if (chip->cs_control) {
 400                 chip->cs_control(PXA2XX_CS_ASSERT);
 401                 return;
 402         }
 403
 404         if (chip->gpiod_cs) {
 405                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 406                 return;
 407         }
 408
 409         if (is_lpss_ssp(drv_data))
 410                 lpss_ssp_cs_control(spi, true);
 411 }
 412
 413 static void cs_deassert(struct spi_device *spi)
 414 {
 415         struct chip_data *chip = spi_get_ctldata(spi);
 416         struct driver_data *drv_data =
 417                 spi_controller_get_devdata(spi->controller);
 418         unsigned long timeout;
 419
 420         if (drv_data->ssp_type == CE4100_SSP)
 421                 return;
 422
 423         /* Wait until SSP becomes idle before deasserting the CS */
 424         timeout = jiffies + msecs_to_jiffies(10);
 425         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 426                !time_after(jiffies, timeout))
 427                 cpu_relax();
 428
 429         if (chip->cs_control) {
 430                 chip->cs_control(PXA2XX_CS_DEASSERT);
 431                 return;
 432         }
 433
 434         if (chip->gpiod_cs) {
 435                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 436                 return;
 437         }
 438
 439         if (is_lpss_ssp(drv_data))
 440                 lpss_ssp_cs_control(spi, false);
 441 }
 442
 443 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 444 {
 445         if (level)
 446                 cs_deassert(spi);
 447         else
 448                 cs_assert(spi);
 449 }
 450
 451 int pxa2xx_spi_flush(struct driver_data *drv_data)
 452 {
 453         unsigned long limit = loops_per_jiffy << 1;
 454
 455         do {
 456                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 457                         pxa2xx_spi_read(drv_data, SSDR);
 458         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 459         write_SSSR_CS(drv_data, SSSR_ROR);
 460
 461         return limit;
 462 }
 463
 464 static int null_writer(struct driver_data *drv_data)
 465 {
 466         u8 n_bytes = drv_data->n_bytes;
 467
 468         if (pxa2xx_spi_txfifo_full(drv_data)
 469                 || (drv_data->tx == drv_data->tx_end))
 470                 return 0;
 471
 472         pxa2xx_spi_write(drv_data, SSDR, 0);
 473         drv_data->tx += n_bytes;
 474
 475         return 1;
 476 }
 477
 478 static int null_reader(struct driver_data *drv_data)
 479 {
 480         u8 n_bytes = drv_data->n_bytes;
 481
 482         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 483                && (drv_data->rx < drv_data->rx_end)) {
 484                 pxa2xx_spi_read(drv_data, SSDR);
 485                 drv_data->rx += n_bytes;
 486         }
 487
 488         return drv_data->rx == drv_data->rx_end;
 489 }
 490
 491 static int u8_writer(struct driver_data *drv_data)
 492 {
 493         if (pxa2xx_spi_txfifo_full(drv_data)
 494                 || (drv_data->tx == drv_data->tx_end))
 495                 return 0;
 496
 497         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 498         ++drv_data->tx;
 499
 500         return 1;
 501 }
 502
 503 static int u8_reader(struct driver_data *drv_data)
 504 {
 505         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 506                && (drv_data->rx < drv_data->rx_end)) {
 507                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 508                 ++drv_data->rx;
 509         }
 510
 511         return drv_data->rx == drv_data->rx_end;
 512 }
 513
 514 static int u16_writer(struct driver_data *drv_data)
 515 {
 516         if (pxa2xx_spi_txfifo_full(drv_data)
 517                 || (drv_data->tx == drv_data->tx_end))
 518                 return 0;
 519
 520         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 521         drv_data->tx += 2;
 522
 523         return 1;
 524 }
 525
 526 static int u16_reader(struct driver_data *drv_data)
 527 {
 528         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 529                && (drv_data->rx < drv_data->rx_end)) {
 530                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 531                 drv_data->rx += 2;
 532         }
 533
 534         return drv_data->rx == drv_data->rx_end;
 535 }
 536
 537 static int u32_writer(struct driver_data *drv_data)
 538 {
 539         if (pxa2xx_spi_txfifo_full(drv_data)
 540                 || (drv_data->tx == drv_data->tx_end))
 541                 return 0;
 542
 543         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 544         drv_data->tx += 4;
 545
 546         return 1;
 547 }
 548
 549 static int u32_reader(struct driver_data *drv_data)
 550 {
 551         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 552                && (drv_data->rx < drv_data->rx_end)) {
 553                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 554                 drv_data->rx += 4;
 555         }
 556
 557         return drv_data->rx == drv_data->rx_end;
 558 }
 559
 560 static void reset_sccr1(struct driver_data *drv_data)
 561 {
 562         struct chip_data *chip =
 563                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 564         u32 sccr1_reg;
 565
 566         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 567         switch (drv_data->ssp_type) {
 568         case QUARK_X1000_SSP:
 569                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 570                 break;
 571         case CE4100_SSP:
 572                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 573                 break;
 574         default:
 575                 sccr1_reg &= ~SSCR1_RFT;
 576                 break;
 577         }
 578         sccr1_reg |= chip->threshold;
 579         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 580 }
 581
 582 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 583 {
 584         /* Stop and reset SSP */
 585         write_SSSR_CS(drv_data, drv_data->clear_sr);
 586         reset_sccr1(drv_data);
 587         if (!pxa25x_ssp_comp(drv_data))
 588                 pxa2xx_spi_write(drv_data, SSTO, 0);
 589         pxa2xx_spi_flush(drv_data);
 590         pxa2xx_spi_write(drv_data, SSCR0,
 591                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 592
 593         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 594
 595         drv_data->controller->cur_msg->status = -EIO;
 596         spi_finalize_current_transfer(drv_data->controller);
 597 }
 598
 599 static void int_transfer_complete(struct driver_data *drv_data)
 600 {
 601         /* Clear and disable interrupts */
 602         write_SSSR_CS(drv_data, drv_data->clear_sr);
 603         reset_sccr1(drv_data);
 604         if (!pxa25x_ssp_comp(drv_data))
 605                 pxa2xx_spi_write(drv_data, SSTO, 0);
 606
 607         spi_finalize_current_transfer(drv_data->controller);
 608 }
 609
 610 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 611 {
 612         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 613                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 614
 615         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 616
 617         if (irq_status & SSSR_ROR) {
 618                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 619                 return IRQ_HANDLED;
 620         }
 621
 622         if (irq_status & SSSR_TUR) {
 623                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 624                 return IRQ_HANDLED;
 625         }
 626
 627         if (irq_status & SSSR_TINT) {
 628                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 629                 if (drv_data->read(drv_data)) {
 630                         int_transfer_complete(drv_data);
 631                         return IRQ_HANDLED;
 632                 }
 633         }
 634
 635         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 636         do {
 637                 if (drv_data->read(drv_data)) {
 638                         int_transfer_complete(drv_data);
 639                         return IRQ_HANDLED;
 640                 }
 641         } while (drv_data->write(drv_data));
 642
 643         if (drv_data->read(drv_data)) {
 644                 int_transfer_complete(drv_data);
 645                 return IRQ_HANDLED;
 646         }
 647
 648         if (drv_data->tx == drv_data->tx_end) {
 649                 u32 bytes_left;
 650                 u32 sccr1_reg;
 651
 652                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 653                 sccr1_reg &= ~SSCR1_TIE;
 654
 655                 /*
 656                  * PXA25x_SSP has no timeout, set up rx threshould for the
 657                  * remaining RX bytes.
 658                  */
 659                 if (pxa25x_ssp_comp(drv_data)) {
 660                         u32 rx_thre;
 661
 662                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 663
 664                         bytes_left = drv_data->rx_end - drv_data->rx;
 665                         switch (drv_data->n_bytes) {
 666                         case 4:
 667                                 bytes_left >>= 2;
 668                                 break;
 669                         case 2:
 670                                 bytes_left >>= 1;
 671                                 break;
 672                         }
 673
 674                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 675                         if (rx_thre > bytes_left)
 676                                 rx_thre = bytes_left;
 677
 678                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 679                 }
 680                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 681         }
 682
 683         /* We did something */
 684         return IRQ_HANDLED;
 685 }
 686
 687 static void handle_bad_msg(struct driver_data *drv_data)
 688 {
 689         pxa2xx_spi_write(drv_data, SSCR0,
 690                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 691         pxa2xx_spi_write(drv_data, SSCR1,
 692                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 693         if (!pxa25x_ssp_comp(drv_data))
 694                 pxa2xx_spi_write(drv_data, SSTO, 0);
 695         write_SSSR_CS(drv_data, drv_data->clear_sr);
 696
 697         dev_err(&drv_data->pdev->dev,
 698                 "bad message state in interrupt handler\n");
 699 }
 700
 701 static irqreturn_t ssp_int(int irq, void *dev_id)
 702 {
 703         struct driver_data *drv_data = dev_id;
 704         u32 sccr1_reg;
 705         u32 mask = drv_data->mask_sr;
 706         u32 status;
 707
 708         /*
 709          * The IRQ might be shared with other peripherals so we must first
 710          * check that are we RPM suspended or not. If we are we assume that
 711          * the IRQ was not for us (we shouldn't be RPM suspended when the
 712          * interrupt is enabled).
 713          */
 714         if (pm_runtime_suspended(&drv_data->pdev->dev))
 715                 return IRQ_NONE;
 716
 717         /*
 718          * If the device is not yet in RPM suspended state and we get an
 719          * interrupt that is meant for another device, check if status bits
 720          * are all set to one. That means that the device is already
 721          * powered off.
 722          */
 723         status = pxa2xx_spi_read(drv_data, SSSR);
 724         if (status == ~0)
 725                 return IRQ_NONE;
 726
 727         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 728
 729         /* Ignore possible writes if we don't need to write */
 730         if (!(sccr1_reg & SSCR1_TIE))
 731                 mask &= ~SSSR_TFS;
 732
 733         /* Ignore RX timeout interrupt if it is disabled */
 734         if (!(sccr1_reg & SSCR1_TINTE))
 735                 mask &= ~SSSR_TINT;
 736
 737         if (!(status & mask))
 738                 return IRQ_NONE;
 739
 740         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 741         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 742
 743         if (!drv_data->controller->cur_msg) {
 744                 handle_bad_msg(drv_data);
 745                 /* Never fail */
 746                 return IRQ_HANDLED;
 747         }
 748
 749         return drv_data->transfer_handler(drv_data);
 750 }
 751
 752 /*
 753  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 754  * input frequency by fractions of 2^24. It also has a divider by 5.
 755  *
 756  * There are formulas to get baud rate value for given input frequency and
 757  * divider parameters, such as DDS_CLK_RATE and SCR:
 758  *
 759  * Fsys = 200MHz
 760  *
 761  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 762  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 763  *
 764  * DDS_CLK_RATE either 2^n or 2^n / 5.
 765  * SCR is in range 0 .. 255
 766  *
 767  * Divisor = 5^i * 2^j * 2 * k
 768  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 769  *       j = [0, 23]     j = 0 iff i = 1
 770  *       k = [1, 256]
 771  * Special case: j = 0, i = 1: Divisor = 2 / 5
 772  *
 773  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 774  * are:
 775  *      Case 1:         2^n, n = [0, 23]
 776  *      Case 2:         2^24 * 2 / 5 (0x666666)
 777  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 778  *
 779  * In all cases the lowest possible value is better.
 780  *
 781  * The function calculates parameters for all cases and chooses the one closest
 782  * to the asked baud rate.
 783  */
 784 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 785 {
 786         unsigned long xtal = 200000000;
 787         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 788                                                    see (2) */
 789                                                 /* case 3 */
 790         unsigned long fref1 = fref / 2;         /* case 1 */
 791         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 792         unsigned long scale;
 793         unsigned long q, q1, q2;
 794         long r, r1, r2;
 795         u32 mul;
 796
 797         /* Case 1 */
 798
 799         /* Set initial value for DDS_CLK_RATE */
 800         mul = (1 << 24) >> 1;
 801
 802         /* Calculate initial quot */
 803         q1 = DIV_ROUND_UP(fref1, rate);
 804
 805         /* Scale q1 if it's too big */
 806         if (q1 > 256) {
 807                 /* Scale q1 to range [1, 512] */
 808                 scale = fls_long(q1 - 1);
 809                 if (scale > 9) {
 810                         q1 >>= scale - 9;
 811                         mul >>= scale - 9;
 812                 }
 813
 814                 /* Round the result if we have a remainder */
 815                 q1 += q1 & 1;
 816         }
 817
 818         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 819         scale = __ffs(q1);
 820         q1 >>= scale;
 821         mul >>= scale;
 822
 823         /* Get the remainder */
 824         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 825
 826         /* Case 2 */
 827
 828         q2 = DIV_ROUND_UP(fref2, rate);
 829         r2 = abs(fref2 / q2 - rate);
 830
 831         /*
 832          * Choose the best between two: less remainder we have the better. We
 833          * can't go case 2 if q2 is greater than 256 since SCR register can
 834          * hold only values 0 .. 255.
 835          */
 836         if (r2 >= r1 || q2 > 256) {
 837                 /* case 1 is better */
 838                 r = r1;
 839                 q = q1;
 840         } else {
 841                 /* case 2 is better */
 842                 r = r2;
 843                 q = q2;
 844                 mul = (1 << 24) * 2 / 5;
 845         }
 846
 847         /* Check case 3 only if the divisor is big enough */
 848         if (fref / rate >= 80) {
 849                 u64 fssp;
 850                 u32 m;
 851
 852                 /* Calculate initial quot */
 853                 q1 = DIV_ROUND_UP(fref, rate);
 854                 m = (1 << 24) / q1;
 855
 856                 /* Get the remainder */
 857                 fssp = (u64)fref * m;
 858                 do_div(fssp, 1 << 24);
 859                 r1 = abs(fssp - rate);
 860
 861                 /* Choose this one if it suits better */
 862                 if (r1 < r) {
 863                         /* case 3 is better */
 864                         q = 1;
 865                         mul = m;
 866                 }
 867         }
 868
 869         *dds = mul;
 870         return q - 1;
 871 }
 872
 873 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 874 {
 875         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 876         const struct ssp_device *ssp = drv_data->ssp;
 877
 878         rate = min_t(int, ssp_clk, rate);
 879
 880         /*
 881          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 882          * that the SSP transmission rate can be greater than the device rate
 883          */
 884         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 885                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 886         else
 887                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 888 }
 889
 890 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 891                                            int rate)
 892 {
 893         struct chip_data *chip =
 894                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 895         unsigned int clk_div;
 896
 897         switch (drv_data->ssp_type) {
 898         case QUARK_X1000_SSP:
 899                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 900                 break;
 901         default:
 902                 clk_div = ssp_get_clk_div(drv_data, rate);
 903                 break;
 904         }
 905         return clk_div << 8;
 906 }
 907
 908 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 909                                struct spi_device *spi,
 910                                struct spi_transfer *xfer)
 911 {
 912         struct chip_data *chip = spi_get_ctldata(spi);
 913
 914         return chip->enable_dma &&
 915                xfer->len <= MAX_DMA_LEN &&
 916                xfer->len >= chip->dma_burst_size;
 917 }
 918
 919 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 920                                    struct spi_device *spi,
 921                                    struct spi_transfer *transfer)
 922 {
 923         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 924         struct spi_message *message = controller->cur_msg;
 925         struct chip_data *chip = spi_get_ctldata(spi);
 926         u32 dma_thresh = chip->dma_threshold;
 927         u32 dma_burst = chip->dma_burst_size;
 928         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 929         u32 clk_div;
 930         u8 bits;
 931         u32 speed;
 932         u32 cr0;
 933         u32 cr1;
 934         int err;
 935         int dma_mapped;
 936
 937         /* Check if we can DMA this transfer */
 938         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 939
 940                 /* reject already-mapped transfers; PIO won't always work */
 941                 if (message->is_dma_mapped
 942                                 || transfer->rx_dma || transfer->tx_dma) {
 943                         dev_err(&spi->dev,
 944                                 "Mapped transfer length of %u is greater than %d\n",
 945                                 transfer->len, MAX_DMA_LEN);
 946                         return -EINVAL;
 947                 }
 948
 949                 /* warn ... we force this to PIO mode */
 950                 dev_warn_ratelimited(&spi->dev,
 951                                      "DMA disabled for transfer length %ld greater than %d\n",
 952                                      (long)transfer->len, MAX_DMA_LEN);
 953         }
 954
 955         /* Setup the transfer state based on the type of transfer */
 956         if (pxa2xx_spi_flush(drv_data) == 0) {
 957                 dev_err(&spi->dev, "Flush failed\n");
 958                 return -EIO;
 959         }
 960         drv_data->n_bytes = chip->n_bytes;
 961         drv_data->tx = (void *)transfer->tx_buf;
 962         drv_data->tx_end = drv_data->tx + transfer->len;
 963         drv_data->rx = transfer->rx_buf;
 964         drv_data->rx_end = drv_data->rx + transfer->len;
 965         drv_data->write = drv_data->tx ? chip->write : null_writer;
 966         drv_data->read = drv_data->rx ? chip->read : null_reader;
 967
 968         /* Change speed and bit per word on a per transfer */
 969         bits = transfer->bits_per_word;
 970         speed = transfer->speed_hz;
 971
 972         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 973
 974         if (bits <= 8) {
 975                 drv_data->n_bytes = 1;
 976                 drv_data->read = drv_data->read != null_reader ?
 977                                         u8_reader : null_reader;
 978                 drv_data->write = drv_data->write != null_writer ?
 979                                         u8_writer : null_writer;
 980         } else if (bits <= 16) {
 981                 drv_data->n_bytes = 2;
 982                 drv_data->read = drv_data->read != null_reader ?
 983                                         u16_reader : null_reader;
 984                 drv_data->write = drv_data->write != null_writer ?
 985                                         u16_writer : null_writer;
 986         } else if (bits <= 32) {
 987                 drv_data->n_bytes = 4;
 988                 drv_data->read = drv_data->read != null_reader ?
 989                                         u32_reader : null_reader;
 990                 drv_data->write = drv_data->write != null_writer ?
 991                                         u32_writer : null_writer;
 992         }
 993         /*
 994          * if bits/word is changed in dma mode, then must check the
 995          * thresholds and burst also
 996          */
 997         if (chip->enable_dma) {
 998                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
 999                                                 spi,
1000                                                 bits, &dma_burst,
1001                                                 &dma_thresh))
1002                         dev_warn_ratelimited(&spi->dev,
1003                                              "DMA burst size reduced to match bits_per_word\n");
1004         }
1005
1006         dma_mapped = controller->can_dma &&
1007                      controller->can_dma(controller, spi, transfer) &&
1008                      controller->cur_msg_mapped;
1009         if (dma_mapped) {
1010
1011                 /* Ensure we have the correct interrupt handler */
1012                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1013
1014                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1015                 if (err)
1016                         return err;
1017
1018                 /* Clear status and start DMA engine */
1019                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1020                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1021
1022                 pxa2xx_spi_dma_start(drv_data);
1023         } else {
1024                 /* Ensure we have the correct interrupt handler */
1025                 drv_data->transfer_handler = interrupt_transfer;
1026
1027                 /* Clear status  */
1028                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1029                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1030         }
1031
1032         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1033         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1034         if (!pxa25x_ssp_comp(drv_data))
1035                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1036                         controller->max_speed_hz
1037                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1038                         dma_mapped ? "DMA" : "PIO");
1039         else
1040                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1041                         controller->max_speed_hz / 2
1042                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1043                         dma_mapped ? "DMA" : "PIO");
1044
1045         if (is_lpss_ssp(drv_data)) {
1046                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1047                     != chip->lpss_rx_threshold)
1048                         pxa2xx_spi_write(drv_data, SSIRF,
1049                                          chip->lpss_rx_threshold);
1050                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1051                     != chip->lpss_tx_threshold)
1052                         pxa2xx_spi_write(drv_data, SSITF,
1053                                          chip->lpss_tx_threshold);
1054         }
1055
1056         if (is_quark_x1000_ssp(drv_data) &&
1057             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1058                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1059
1060         /* see if we need to reload the config registers */
1061         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1062             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1063             != (cr1 & change_mask)) {
1064                 /* stop the SSP, and update the other bits */
1065                 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1066                 if (!pxa25x_ssp_comp(drv_data))
1067                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1068                 /* first set CR1 without interrupt and service enables */
1069                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1070                 /* restart the SSP */
1071                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1072
1073         } else {
1074                 if (!pxa25x_ssp_comp(drv_data))
1075                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1076         }
1077
1078         if (drv_data->ssp_type == MMP2_SSP) {
1079                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1080                                         & SSSR_TFL_MASK) >> 8;
1081
1082                 if (tx_level) {
1083                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1084                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1085                                                                 tx_level);
1086                         if (tx_level > transfer->len)
1087                                 tx_level = transfer->len;
1088                         drv_data->tx += tx_level;
1089                 }
1090         }
1091
1092         if (spi_controller_is_slave(controller)) {
1093                 while (drv_data->write(drv_data))
1094                         ;
1095                 if (drv_data->gpiod_ready) {
1096                         gpiod_set_value(drv_data->gpiod_ready, 1);
1097                         udelay(1);
1098                         gpiod_set_value(drv_data->gpiod_ready, 0);
1099                 }
1100         }
1101
1102         /*
1103          * Release the data by enabling service requests and interrupts,
1104          * without changing any mode bits
1105          */
1106         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1107
1108         return 1;
1109 }
1110
1111 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1112 {
1113         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1114
1115         /* Stop and reset SSP */
1116         write_SSSR_CS(drv_data, drv_data->clear_sr);
1117         reset_sccr1(drv_data);
1118         if (!pxa25x_ssp_comp(drv_data))
1119                 pxa2xx_spi_write(drv_data, SSTO, 0);
1120         pxa2xx_spi_flush(drv_data);
1121         pxa2xx_spi_write(drv_data, SSCR0,
1122                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1123
1124         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1125
1126         drv_data->controller->cur_msg->status = -EINTR;
1127         spi_finalize_current_transfer(drv_data->controller);
1128
1129         return 0;
1130 }
1131
1132 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1133                                  struct spi_message *msg)
1134 {
1135         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1136
1137         /* Disable the SSP */
1138         pxa2xx_spi_write(drv_data, SSCR0,
1139                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1140         /* Clear and disable interrupts and service requests */
1141         write_SSSR_CS(drv_data, drv_data->clear_sr);
1142         pxa2xx_spi_write(drv_data, SSCR1,
1143                          pxa2xx_spi_read(drv_data, SSCR1)
1144                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1145         if (!pxa25x_ssp_comp(drv_data))
1146                 pxa2xx_spi_write(drv_data, SSTO, 0);
1147
1148         /*
1149          * Stop the DMA if running. Note DMA callback handler may have unset
1150          * the dma_running already, which is fine as stopping is not needed
1151          * then but we shouldn't rely this flag for anything else than
1152          * stopping. For instance to differentiate between PIO and DMA
1153          * transfers.
1154          */
1155         if (atomic_read(&drv_data->dma_running))
1156                 pxa2xx_spi_dma_stop(drv_data);
1157 }
1158
1159 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1160 {
1161         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1162
1163         /* Disable the SSP now */
1164         pxa2xx_spi_write(drv_data, SSCR0,
1165                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1166
1167         return 0;
1168 }
1169
1170 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1171                     struct pxa2xx_spi_chip *chip_info)
1172 {
1173         struct driver_data *drv_data =
1174                 spi_controller_get_devdata(spi->controller);
1175         struct gpio_desc *gpiod;
1176         int err = 0;
1177
1178         if (chip == NULL)
1179                 return 0;
1180
1181         if (drv_data->cs_gpiods) {
1182                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1183                 if (gpiod) {
1184                         chip->gpiod_cs = gpiod;
1185                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1186                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1187                 }
1188
1189                 return 0;
1190         }
1191
1192         if (chip_info == NULL)
1193                 return 0;
1194
1195         /* NOTE: setup() can be called multiple times, possibly with
1196          * different chip_info, release previously requested GPIO
1197          */
1198         if (chip->gpiod_cs) {
1199                 gpiod_put(chip->gpiod_cs);
1200                 chip->gpiod_cs = NULL;
1201         }
1202
1203         /* If (*cs_control) is provided, ignore GPIO chip select */
1204         if (chip_info->cs_control) {
1205                 chip->cs_control = chip_info->cs_control;
1206                 return 0;
1207         }
1208
1209         if (gpio_is_valid(chip_info->gpio_cs)) {
1210                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1211                 if (err) {
1212                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1213                                 chip_info->gpio_cs);
1214                         return err;
1215                 }
1216
1217                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1218                 chip->gpiod_cs = gpiod;
1219                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1220
1221                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1222         }
1223
1224         return err;
1225 }
1226
1227 static int setup(struct spi_device *spi)
1228 {
1229         struct pxa2xx_spi_chip *chip_info;
1230         struct chip_data *chip;
1231         const struct lpss_config *config;
1232         struct driver_data *drv_data =
1233                 spi_controller_get_devdata(spi->controller);
1234         uint tx_thres, tx_hi_thres, rx_thres;
1235
1236         switch (drv_data->ssp_type) {
1237         case QUARK_X1000_SSP:
1238                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1239                 tx_hi_thres = 0;
1240                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1241                 break;
1242         case CE4100_SSP:
1243                 tx_thres = TX_THRESH_CE4100_DFLT;
1244                 tx_hi_thres = 0;
1245                 rx_thres = RX_THRESH_CE4100_DFLT;
1246                 break;
1247         case LPSS_LPT_SSP:
1248         case LPSS_BYT_SSP:
1249         case LPSS_BSW_SSP:
1250         case LPSS_SPT_SSP:
1251         case LPSS_BXT_SSP:
1252         case LPSS_CNL_SSP:
1253                 config = lpss_get_config(drv_data);
1254                 tx_thres = config->tx_threshold_lo;
1255                 tx_hi_thres = config->tx_threshold_hi;
1256                 rx_thres = config->rx_threshold;
1257                 break;
1258         default:
1259                 tx_hi_thres = 0;
1260                 if (spi_controller_is_slave(drv_data->controller)) {
1261                         tx_thres = 1;
1262                         rx_thres = 2;
1263                 } else {
1264                         tx_thres = TX_THRESH_DFLT;
1265                         rx_thres = RX_THRESH_DFLT;
1266                 }
1267                 break;
1268         }
1269
1270         /* Only alloc on first setup */
1271         chip = spi_get_ctldata(spi);
1272         if (!chip) {
1273                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1274                 if (!chip)
1275                         return -ENOMEM;
1276
1277                 if (drv_data->ssp_type == CE4100_SSP) {
1278                         if (spi->chip_select > 4) {
1279                                 dev_err(&spi->dev,
1280                                         "failed setup: cs number must not be > 4.\n");
1281                                 kfree(chip);
1282                                 return -EINVAL;
1283                         }
1284
1285                         chip->frm = spi->chip_select;
1286                 }
1287                 chip->enable_dma = drv_data->controller_info->enable_dma;
1288                 chip->timeout = TIMOUT_DFLT;
1289         }
1290
1291         /* protocol drivers may change the chip settings, so...
1292          * if chip_info exists, use it */
1293         chip_info = spi->controller_data;
1294
1295         /* chip_info isn't always needed */
1296         chip->cr1 = 0;
1297         if (chip_info) {
1298                 if (chip_info->timeout)
1299                         chip->timeout = chip_info->timeout;
1300                 if (chip_info->tx_threshold)
1301                         tx_thres = chip_info->tx_threshold;
1302                 if (chip_info->tx_hi_threshold)
1303                         tx_hi_thres = chip_info->tx_hi_threshold;
1304                 if (chip_info->rx_threshold)
1305                         rx_thres = chip_info->rx_threshold;
1306                 chip->dma_threshold = 0;
1307                 if (chip_info->enable_loopback)
1308                         chip->cr1 = SSCR1_LBM;
1309         }
1310         if (spi_controller_is_slave(drv_data->controller)) {
1311                 chip->cr1 |= SSCR1_SCFR;
1312                 chip->cr1 |= SSCR1_SCLKDIR;
1313                 chip->cr1 |= SSCR1_SFRMDIR;
1314                 chip->cr1 |= SSCR1_SPH;
1315         }
1316
1317         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1318         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1319                                 | SSITF_TxHiThresh(tx_hi_thres);
1320
1321         /* set dma burst and threshold outside of chip_info path so that if
1322          * chip_info goes away after setting chip->enable_dma, the
1323          * burst and threshold can still respond to changes in bits_per_word */
1324         if (chip->enable_dma) {
1325                 /* set up legal burst and threshold for dma */
1326                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1327                                                 spi->bits_per_word,
1328                                                 &chip->dma_burst_size,
1329                                                 &chip->dma_threshold)) {
1330                         dev_warn(&spi->dev,
1331                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1332                 }
1333                 dev_dbg(&spi->dev,
1334                         "in setup: DMA burst size set to %u\n",
1335                         chip->dma_burst_size);
1336         }
1337
1338         switch (drv_data->ssp_type) {
1339         case QUARK_X1000_SSP:
1340                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1341                                    & QUARK_X1000_SSCR1_RFT)
1342                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1343                                    & QUARK_X1000_SSCR1_TFT);
1344                 break;
1345         case CE4100_SSP:
1346                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1347                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1348                 break;
1349         default:
1350                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1351                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1352                 break;
1353         }
1354
1355         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1356         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1357                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1358
1359         if (spi->mode & SPI_LOOP)
1360                 chip->cr1 |= SSCR1_LBM;
1361
1362         if (spi->bits_per_word <= 8) {
1363                 chip->n_bytes = 1;
1364                 chip->read = u8_reader;
1365                 chip->write = u8_writer;
1366         } else if (spi->bits_per_word <= 16) {
1367                 chip->n_bytes = 2;
1368                 chip->read = u16_reader;
1369                 chip->write = u16_writer;
1370         } else if (spi->bits_per_word <= 32) {
1371                 chip->n_bytes = 4;
1372                 chip->read = u32_reader;
1373                 chip->write = u32_writer;
1374         }
1375
1376         spi_set_ctldata(spi, chip);
1377
1378         if (drv_data->ssp_type == CE4100_SSP)
1379                 return 0;
1380
1381         return setup_cs(spi, chip, chip_info);
1382 }
1383
1384 static void cleanup(struct spi_device *spi)
1385 {
1386         struct chip_data *chip = spi_get_ctldata(spi);
1387         struct driver_data *drv_data =
1388                 spi_controller_get_devdata(spi->controller);
1389
1390         if (!chip)
1391                 return;
1392
1393         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1394             chip->gpiod_cs)
1395                 gpiod_put(chip->gpiod_cs);
1396
1397         kfree(chip);
1398 }
1399
1400 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1401         { "INT33C0", LPSS_LPT_SSP },
1402         { "INT33C1", LPSS_LPT_SSP },
1403         { "INT3430", LPSS_LPT_SSP },
1404         { "INT3431", LPSS_LPT_SSP },
1405         { "80860F0E", LPSS_BYT_SSP },
1406         { "8086228E", LPSS_BSW_SSP },
1407         { },
1408 };
1409 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1410
1411 /*
1412  * PCI IDs of compound devices that integrate both host controller and private
1413  * integrated DMA engine. Please note these are not used in module
1414  * autoloading and probing in this module but matching the LPSS SSP type.
1415  */
1416 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1417         /* SPT-LP */
1418         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1419         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1420         /* SPT-H */
1421         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1422         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1423         /* KBL-H */
1424         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1425         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1426         /* BXT A-Step */
1427         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1428         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1429         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1430         /* BXT B-Step */
1431         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1432         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1433         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1434         /* GLK */
1435         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1436         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1437         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1438         /* ICL-LP */
1439         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1440         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1441         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1442         /* EHL */
1443         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1444         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1445         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1446         /* APL */
1447         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1448         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1449         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1450         /* CNL-LP */
1451         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1452         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1453         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1454         /* CNL-H */
1455         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1456         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1457         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1458         /* CML-LP */
1459         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1460         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1461         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1462         /* CML-H */
1463         { PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1464         { PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1465         { PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1466         /* TGL-LP */
1467         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1468         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1469         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1470         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1471         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1472         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1473         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1474         { },
1475 };
1476
1477 static const struct of_device_id pxa2xx_spi_of_match[] = {
1478         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1479         {},
1480 };
1481 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1482
1483 #ifdef CONFIG_ACPI
1484
1485 static int pxa2xx_spi_get_port_id(struct device *dev)
1486 {
1487         struct acpi_device *adev;
1488         unsigned int devid;
1489         int port_id = -1;
1490
1491         adev = ACPI_COMPANION(dev);
1492         if (adev && adev->pnp.unique_id &&
1493             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1494                 port_id = devid;
1495         return port_id;
1496 }
1497
1498 #else /* !CONFIG_ACPI */
1499
1500 static int pxa2xx_spi_get_port_id(struct device *dev)
1501 {
1502         return -1;
1503 }
1504
1505 #endif /* CONFIG_ACPI */
1506
1507
1508 #ifdef CONFIG_PCI
1509
1510 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1511 {
1512         return param == chan->device->dev;
1513 }
1514
1515 #endif /* CONFIG_PCI */
1516
1517 static struct pxa2xx_spi_controller *
1518 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1519 {
1520         struct pxa2xx_spi_controller *pdata;
1521         struct ssp_device *ssp;
1522         struct resource *res;
1523         struct device *parent = pdev->dev.parent;
1524         struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1525         const struct pci_device_id *pcidev_id = NULL;
1526         enum pxa_ssp_type type;
1527         const void *match;
1528
1529         if (pcidev)
1530                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1531
1532         match = device_get_match_data(&pdev->dev);
1533         if (match)
1534                 type = (enum pxa_ssp_type)match;
1535         else if (pcidev_id)
1536                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1537         else
1538                 return NULL;
1539
1540         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1541         if (!pdata)
1542                 return NULL;
1543
1544         ssp = &pdata->ssp;
1545
1546         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1547         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1548         if (IS_ERR(ssp->mmio_base))
1549                 return NULL;
1550
1551         ssp->phys_base = res->start;
1552
1553 #ifdef CONFIG_PCI
1554         if (pcidev_id) {
1555                 pdata->tx_param = parent;
1556                 pdata->rx_param = parent;
1557                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1558         }
1559 #endif
1560
1561         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1562         if (IS_ERR(ssp->clk))
1563                 return NULL;
1564
1565         ssp->irq = platform_get_irq(pdev, 0);
1566         if (ssp->irq < 0)
1567                 return NULL;
1568
1569         ssp->type = type;
1570         ssp->dev = &pdev->dev;
1571         ssp->port_id = pxa2xx_spi_get_port_id(&pdev->dev);
1572
1573         pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1574         pdata->num_chipselect = 1;
1575         pdata->enable_dma = true;
1576         pdata->dma_burst_size = 1;
1577
1578         return pdata;
1579 }
1580
1581 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1582                                       unsigned int cs)
1583 {
1584         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1585
1586         if (has_acpi_companion(&drv_data->pdev->dev)) {
1587                 switch (drv_data->ssp_type) {
1588                 /*
1589                  * For Atoms the ACPI DeviceSelection used by the Windows
1590                  * driver starts from 1 instead of 0 so translate it here
1591                  * to match what Linux expects.
1592                  */
1593                 case LPSS_BYT_SSP:
1594                 case LPSS_BSW_SSP:
1595                         return cs - 1;
1596
1597                 default:
1598                         break;
1599                 }
1600         }
1601
1602         return cs;
1603 }
1604
1605 static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi)
1606 {
1607         return MAX_DMA_LEN;
1608 }
1609
1610 static int pxa2xx_spi_probe(struct platform_device *pdev)
1611 {
1612         struct device *dev = &pdev->dev;
1613         struct pxa2xx_spi_controller *platform_info;
1614         struct spi_controller *controller;
1615         struct driver_data *drv_data;
1616         struct ssp_device *ssp;
1617         const struct lpss_config *config;
1618         int status, count;
1619         u32 tmp;
1620
1621         platform_info = dev_get_platdata(dev);
1622         if (!platform_info) {
1623                 platform_info = pxa2xx_spi_init_pdata(pdev);
1624                 if (!platform_info) {
1625                         dev_err(&pdev->dev, "missing platform data\n");
1626                         return -ENODEV;
1627                 }
1628         }
1629
1630         ssp = pxa_ssp_request(pdev->id, pdev->name);
1631         if (!ssp)
1632                 ssp = &platform_info->ssp;
1633
1634         if (!ssp->mmio_base) {
1635                 dev_err(&pdev->dev, "failed to get ssp\n");
1636                 return -ENODEV;
1637         }
1638
1639         if (platform_info->is_slave)
1640                 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1641         else
1642                 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1643
1644         if (!controller) {
1645                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1646                 pxa_ssp_free(ssp);
1647                 return -ENOMEM;
1648         }
1649         drv_data = spi_controller_get_devdata(controller);
1650         drv_data->controller = controller;
1651         drv_data->controller_info = platform_info;
1652         drv_data->pdev = pdev;
1653         drv_data->ssp = ssp;
1654
1655         controller->dev.of_node = pdev->dev.of_node;
1656         /* the spi->mode bits understood by this driver: */
1657         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1658
1659         controller->bus_num = ssp->port_id;
1660         controller->dma_alignment = DMA_ALIGNMENT;
1661         controller->cleanup = cleanup;
1662         controller->setup = setup;
1663         controller->set_cs = pxa2xx_spi_set_cs;
1664         controller->transfer_one = pxa2xx_spi_transfer_one;
1665         controller->slave_abort = pxa2xx_spi_slave_abort;
1666         controller->handle_err = pxa2xx_spi_handle_err;
1667         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1668         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1669         controller->auto_runtime_pm = true;
1670         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1671
1672         drv_data->ssp_type = ssp->type;
1673
1674         drv_data->ioaddr = ssp->mmio_base;
1675         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1676         if (pxa25x_ssp_comp(drv_data)) {
1677                 switch (drv_data->ssp_type) {
1678                 case QUARK_X1000_SSP:
1679                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1680                         break;
1681                 default:
1682                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1683                         break;
1684                 }
1685
1686                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1687                 drv_data->dma_cr1 = 0;
1688                 drv_data->clear_sr = SSSR_ROR;
1689                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1690         } else {
1691                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1692                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1693                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1694                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1695                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1696                                                 | SSSR_ROR | SSSR_TUR;
1697         }
1698
1699         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1700                         drv_data);
1701         if (status < 0) {
1702                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1703                 goto out_error_controller_alloc;
1704         }
1705
1706         /* Setup DMA if requested */
1707         if (platform_info->enable_dma) {
1708                 status = pxa2xx_spi_dma_setup(drv_data);
1709                 if (status) {
1710                         dev_warn(dev, "no DMA channels available, using PIO\n");
1711                         platform_info->enable_dma = false;
1712                 } else {
1713                         controller->can_dma = pxa2xx_spi_can_dma;
1714                         controller->max_dma_len = MAX_DMA_LEN;
1715                         controller->max_transfer_size =
1716                                 pxa2xx_spi_max_dma_transfer_size;
1717                 }
1718         }
1719
1720         /* Enable SOC clock */
1721         status = clk_prepare_enable(ssp->clk);
1722         if (status)
1723                 goto out_error_dma_irq_alloc;
1724
1725         controller->max_speed_hz = clk_get_rate(ssp->clk);
1726         /*
1727          * Set minimum speed for all other platforms than Intel Quark which is
1728          * able do under 1 Hz transfers.
1729          */
1730         if (!pxa25x_ssp_comp(drv_data))
1731                 controller->min_speed_hz =
1732                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1733         else if (!is_quark_x1000_ssp(drv_data))
1734                 controller->min_speed_hz =
1735                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1736
1737         /* Load default SSP configuration */
1738         pxa2xx_spi_write(drv_data, SSCR0, 0);
1739         switch (drv_data->ssp_type) {
1740         case QUARK_X1000_SSP:
1741                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1742                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1743                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1744
1745                 /* using the Motorola SPI protocol and use 8 bit frame */
1746                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1747                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1748                 break;
1749         case CE4100_SSP:
1750                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1751                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1752                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1753                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1754                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1755                 break;
1756         default:
1757
1758                 if (spi_controller_is_slave(controller)) {
1759                         tmp = SSCR1_SCFR |
1760                               SSCR1_SCLKDIR |
1761                               SSCR1_SFRMDIR |
1762                               SSCR1_RxTresh(2) |
1763                               SSCR1_TxTresh(1) |
1764                               SSCR1_SPH;
1765                 } else {
1766                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1767                               SSCR1_TxTresh(TX_THRESH_DFLT);
1768                 }
1769                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1770                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1771                 if (!spi_controller_is_slave(controller))
1772                         tmp |= SSCR0_SCR(2);
1773                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1774                 break;
1775         }
1776
1777         if (!pxa25x_ssp_comp(drv_data))
1778                 pxa2xx_spi_write(drv_data, SSTO, 0);
1779
1780         if (!is_quark_x1000_ssp(drv_data))
1781                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1782
1783         if (is_lpss_ssp(drv_data)) {
1784                 lpss_ssp_setup(drv_data);
1785                 config = lpss_get_config(drv_data);
1786                 if (config->reg_capabilities >= 0) {
1787                         tmp = __lpss_ssp_read_priv(drv_data,
1788                                                    config->reg_capabilities);
1789                         tmp &= LPSS_CAPS_CS_EN_MASK;
1790                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1791                         platform_info->num_chipselect = ffz(tmp);
1792                 } else if (config->cs_num) {
1793                         platform_info->num_chipselect = config->cs_num;
1794                 }
1795         }
1796         controller->num_chipselect = platform_info->num_chipselect;
1797
1798         count = gpiod_count(&pdev->dev, "cs");
1799         if (count > 0) {
1800                 int i;
1801
1802                 controller->num_chipselect = max_t(int, count,
1803                         controller->num_chipselect);
1804
1805                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1806                         controller->num_chipselect, sizeof(struct gpio_desc *),
1807                         GFP_KERNEL);
1808                 if (!drv_data->cs_gpiods) {
1809                         status = -ENOMEM;
1810                         goto out_error_clock_enabled;
1811                 }
1812
1813                 for (i = 0; i < controller->num_chipselect; i++) {
1814                         struct gpio_desc *gpiod;
1815
1816                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1817                         if (IS_ERR(gpiod)) {
1818                                 /* Means use native chip select */
1819                                 if (PTR_ERR(gpiod) == -ENOENT)
1820                                         continue;
1821
1822                                 status = PTR_ERR(gpiod);
1823                                 goto out_error_clock_enabled;
1824                         } else {
1825                                 drv_data->cs_gpiods[i] = gpiod;
1826                         }
1827                 }
1828         }
1829
1830         if (platform_info->is_slave) {
1831                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1832                                                 "ready", GPIOD_OUT_LOW);
1833                 if (IS_ERR(drv_data->gpiod_ready)) {
1834                         status = PTR_ERR(drv_data->gpiod_ready);
1835                         goto out_error_clock_enabled;
1836                 }
1837         }
1838
1839         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1840         pm_runtime_use_autosuspend(&pdev->dev);
1841         pm_runtime_set_active(&pdev->dev);
1842         pm_runtime_enable(&pdev->dev);
1843
1844         /* Register with the SPI framework */
1845         platform_set_drvdata(pdev, drv_data);
1846         status = devm_spi_register_controller(&pdev->dev, controller);
1847         if (status != 0) {
1848                 dev_err(&pdev->dev, "problem registering spi controller\n");
1849                 goto out_error_pm_runtime_enabled;
1850         }
1851
1852         return status;
1853
1854 out_error_pm_runtime_enabled:
1855         pm_runtime_put_noidle(&pdev->dev);
1856         pm_runtime_disable(&pdev->dev);
1857
1858 out_error_clock_enabled:
1859         clk_disable_unprepare(ssp->clk);
1860
1861 out_error_dma_irq_alloc:
1862         pxa2xx_spi_dma_release(drv_data);
1863         free_irq(ssp->irq, drv_data);
1864
1865 out_error_controller_alloc:
1866         spi_controller_put(controller);
1867         pxa_ssp_free(ssp);
1868         return status;
1869 }
1870
1871 static int pxa2xx_spi_remove(struct platform_device *pdev)
1872 {
1873         struct driver_data *drv_data = platform_get_drvdata(pdev);
1874         struct ssp_device *ssp;
1875
1876         if (!drv_data)
1877                 return 0;
1878         ssp = drv_data->ssp;
1879
1880         pm_runtime_get_sync(&pdev->dev);
1881
1882         /* Disable the SSP at the peripheral and SOC level */
1883         pxa2xx_spi_write(drv_data, SSCR0, 0);
1884         clk_disable_unprepare(ssp->clk);
1885
1886         /* Release DMA */
1887         if (drv_data->controller_info->enable_dma)
1888                 pxa2xx_spi_dma_release(drv_data);
1889
1890         pm_runtime_put_noidle(&pdev->dev);
1891         pm_runtime_disable(&pdev->dev);
1892
1893         /* Release IRQ */
1894         free_irq(ssp->irq, drv_data);
1895
1896         /* Release SSP */
1897         pxa_ssp_free(ssp);
1898
1899         return 0;
1900 }
1901
1902 #ifdef CONFIG_PM_SLEEP
1903 static int pxa2xx_spi_suspend(struct device *dev)
1904 {
1905         struct driver_data *drv_data = dev_get_drvdata(dev);
1906         struct ssp_device *ssp = drv_data->ssp;
1907         int status;
1908
1909         status = spi_controller_suspend(drv_data->controller);
1910         if (status != 0)
1911                 return status;
1912         pxa2xx_spi_write(drv_data, SSCR0, 0);
1913
1914         if (!pm_runtime_suspended(dev))
1915                 clk_disable_unprepare(ssp->clk);
1916
1917         return 0;
1918 }
1919
1920 static int pxa2xx_spi_resume(struct device *dev)
1921 {
1922         struct driver_data *drv_data = dev_get_drvdata(dev);
1923         struct ssp_device *ssp = drv_data->ssp;
1924         int status;
1925
1926         /* Enable the SSP clock */
1927         if (!pm_runtime_suspended(dev)) {
1928                 status = clk_prepare_enable(ssp->clk);
1929                 if (status)
1930                         return status;
1931         }
1932
1933         /* Start the queue running */
1934         return spi_controller_resume(drv_data->controller);
1935 }
1936 #endif
1937
1938 #ifdef CONFIG_PM
1939 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1940 {
1941         struct driver_data *drv_data = dev_get_drvdata(dev);
1942
1943         clk_disable_unprepare(drv_data->ssp->clk);
1944         return 0;
1945 }
1946
1947 static int pxa2xx_spi_runtime_resume(struct device *dev)
1948 {
1949         struct driver_data *drv_data = dev_get_drvdata(dev);
1950         int status;
1951
1952         status = clk_prepare_enable(drv_data->ssp->clk);
1953         return status;
1954 }
1955 #endif
1956
1957 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1958         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1959         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1960                            pxa2xx_spi_runtime_resume, NULL)
1961 };
1962
1963 static struct platform_driver driver = {
1964         .driver = {
1965                 .name   = "pxa2xx-spi",
1966                 .pm     = &pxa2xx_spi_pm_ops,
1967                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1968                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1969         },
1970         .probe = pxa2xx_spi_probe,
1971         .remove = pxa2xx_spi_remove,
1972 };
1973
1974 static int __init pxa2xx_spi_init(void)
1975 {
1976         return platform_driver_register(&driver);
1977 }
1978 subsys_initcall(pxa2xx_spi_init);
1979
1980 static void __exit pxa2xx_spi_exit(void)
1981 {
1982         platform_driver_unregister(&driver);
1983 }
1984 module_exit(pxa2xx_spi_exit);
1985
1986 MODULE_SOFTDEP("pre: dw_dmac");