drivers/spi/spi-pxa2xx.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4  * Copyright (C) 2013, Intel Corporation
   5  */
   6
   7 #include <linux/bitops.h>
   8 #include <linux/init.h>
   9 #include <linux/module.h>
  10 #include <linux/device.h>
  11 #include <linux/ioport.h>
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/spi/pxa2xx_spi.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/delay.h>
  21 #include <linux/gpio.h>
  22 #include <linux/gpio/consumer.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/acpi.h>
  27 #include <linux/of_device.h>
  28
  29 #include "spi-pxa2xx.h"
  30
  31 MODULE_AUTHOR("Stephen Street");
  32 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  33 MODULE_LICENSE("GPL");
  34 MODULE_ALIAS("platform:pxa2xx-spi");
  35
  36 #define TIMOUT_DFLT             1000
  37
  38 /*
  39  * for testing SSCR1 changes that require SSP restart, basically
  40  * everything except the service and interrupt enables, the pxa270 developer
  41  * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  42  * list, but the PXA255 dev man says all bits without really meaning the
  43  * service and interrupt enables
  44  */
  45 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  46                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  47                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  48                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  49                                 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  50                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  51
  52 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF   \
  53                                 | QUARK_X1000_SSCR1_EFWR        \
  54                                 | QUARK_X1000_SSCR1_RFT         \
  55                                 | QUARK_X1000_SSCR1_TFT         \
  56                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  57
  58 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  59                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  60                                 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  61                                 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  62                                 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
  63                                 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  64
  65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE   BIT(24)
  66 #define LPSS_CS_CONTROL_SW_MODE                 BIT(0)
  67 #define LPSS_CS_CONTROL_CS_HIGH                 BIT(1)
  68 #define LPSS_CAPS_CS_EN_SHIFT                   9
  69 #define LPSS_CAPS_CS_EN_MASK                    (0xf << LPSS_CAPS_CS_EN_SHIFT)
  70
  71 struct lpss_config {
  72         /* LPSS offset from drv_data->ioaddr */
  73         unsigned offset;
  74         /* Register offsets from drv_data->lpss_base or -1 */
  75         int reg_general;
  76         int reg_ssp;
  77         int reg_cs_ctrl;
  78         int reg_capabilities;
  79         /* FIFO thresholds */
  80         u32 rx_threshold;
  81         u32 tx_threshold_lo;
  82         u32 tx_threshold_hi;
  83         /* Chip select control */
  84         unsigned cs_sel_shift;
  85         unsigned cs_sel_mask;
  86         unsigned cs_num;
  87 };
  88
  89 /* Keep these sorted with enum pxa_ssp_type */
  90 static const struct lpss_config lpss_platforms[] = {
  91         {       /* LPSS_LPT_SSP */
  92                 .offset = 0x800,
  93                 .reg_general = 0x08,
  94                 .reg_ssp = 0x0c,
  95                 .reg_cs_ctrl = 0x18,
  96                 .reg_capabilities = -1,
  97                 .rx_threshold = 64,
  98                 .tx_threshold_lo = 160,
  99                 .tx_threshold_hi = 224,
 100         },
 101         {       /* LPSS_BYT_SSP */
 102                 .offset = 0x400,
 103                 .reg_general = 0x08,
 104                 .reg_ssp = 0x0c,
 105                 .reg_cs_ctrl = 0x18,
 106                 .reg_capabilities = -1,
 107                 .rx_threshold = 64,
 108                 .tx_threshold_lo = 160,
 109                 .tx_threshold_hi = 224,
 110         },
 111         {       /* LPSS_BSW_SSP */
 112                 .offset = 0x400,
 113                 .reg_general = 0x08,
 114                 .reg_ssp = 0x0c,
 115                 .reg_cs_ctrl = 0x18,
 116                 .reg_capabilities = -1,
 117                 .rx_threshold = 64,
 118                 .tx_threshold_lo = 160,
 119                 .tx_threshold_hi = 224,
 120                 .cs_sel_shift = 2,
 121                 .cs_sel_mask = 1 << 2,
 122                 .cs_num = 2,
 123         },
 124         {       /* LPSS_SPT_SSP */
 125                 .offset = 0x200,
 126                 .reg_general = -1,
 127                 .reg_ssp = 0x20,
 128                 .reg_cs_ctrl = 0x24,
 129                 .reg_capabilities = -1,
 130                 .rx_threshold = 1,
 131                 .tx_threshold_lo = 32,
 132                 .tx_threshold_hi = 56,
 133         },
 134         {       /* LPSS_BXT_SSP */
 135                 .offset = 0x200,
 136                 .reg_general = -1,
 137                 .reg_ssp = 0x20,
 138                 .reg_cs_ctrl = 0x24,
 139                 .reg_capabilities = 0xfc,
 140                 .rx_threshold = 1,
 141                 .tx_threshold_lo = 16,
 142                 .tx_threshold_hi = 48,
 143                 .cs_sel_shift = 8,
 144                 .cs_sel_mask = 3 << 8,
 145         },
 146         {       /* LPSS_CNL_SSP */
 147                 .offset = 0x200,
 148                 .reg_general = -1,
 149                 .reg_ssp = 0x20,
 150                 .reg_cs_ctrl = 0x24,
 151                 .reg_capabilities = 0xfc,
 152                 .rx_threshold = 1,
 153                 .tx_threshold_lo = 32,
 154                 .tx_threshold_hi = 56,
 155                 .cs_sel_shift = 8,
 156                 .cs_sel_mask = 3 << 8,
 157         },
 158 };
 159
 160 static inline const struct lpss_config
 161 *lpss_get_config(const struct driver_data *drv_data)
 162 {
 163         return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
 164 }
 165
 166 static bool is_lpss_ssp(const struct driver_data *drv_data)
 167 {
 168         switch (drv_data->ssp_type) {
 169         case LPSS_LPT_SSP:
 170         case LPSS_BYT_SSP:
 171         case LPSS_BSW_SSP:
 172         case LPSS_SPT_SSP:
 173         case LPSS_BXT_SSP:
 174         case LPSS_CNL_SSP:
 175                 return true;
 176         default:
 177                 return false;
 178         }
 179 }
 180
 181 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 182 {
 183         return drv_data->ssp_type == QUARK_X1000_SSP;
 184 }
 185
 186 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
 187 {
 188         switch (drv_data->ssp_type) {
 189         case QUARK_X1000_SSP:
 190                 return QUARK_X1000_SSCR1_CHANGE_MASK;
 191         case CE4100_SSP:
 192                 return CE4100_SSCR1_CHANGE_MASK;
 193         default:
 194                 return SSCR1_CHANGE_MASK;
 195         }
 196 }
 197
 198 static u32
 199 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
 200 {
 201         switch (drv_data->ssp_type) {
 202         case QUARK_X1000_SSP:
 203                 return RX_THRESH_QUARK_X1000_DFLT;
 204         case CE4100_SSP:
 205                 return RX_THRESH_CE4100_DFLT;
 206         default:
 207                 return RX_THRESH_DFLT;
 208         }
 209 }
 210
 211 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
 212 {
 213         u32 mask;
 214
 215         switch (drv_data->ssp_type) {
 216         case QUARK_X1000_SSP:
 217                 mask = QUARK_X1000_SSSR_TFL_MASK;
 218                 break;
 219         case CE4100_SSP:
 220                 mask = CE4100_SSSR_TFL_MASK;
 221                 break;
 222         default:
 223                 mask = SSSR_TFL_MASK;
 224                 break;
 225         }
 226
 227         return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
 228 }
 229
 230 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
 231                                      u32 *sccr1_reg)
 232 {
 233         u32 mask;
 234
 235         switch (drv_data->ssp_type) {
 236         case QUARK_X1000_SSP:
 237                 mask = QUARK_X1000_SSCR1_RFT;
 238                 break;
 239         case CE4100_SSP:
 240                 mask = CE4100_SSCR1_RFT;
 241                 break;
 242         default:
 243                 mask = SSCR1_RFT;
 244                 break;
 245         }
 246         *sccr1_reg &= ~mask;
 247 }
 248
 249 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
 250                                    u32 *sccr1_reg, u32 threshold)
 251 {
 252         switch (drv_data->ssp_type) {
 253         case QUARK_X1000_SSP:
 254                 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
 255                 break;
 256         case CE4100_SSP:
 257                 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
 258                 break;
 259         default:
 260                 *sccr1_reg |= SSCR1_RxTresh(threshold);
 261                 break;
 262         }
 263 }
 264
 265 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
 266                                   u32 clk_div, u8 bits)
 267 {
 268         switch (drv_data->ssp_type) {
 269         case QUARK_X1000_SSP:
 270                 return clk_div
 271                         | QUARK_X1000_SSCR0_Motorola
 272                         | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
 273                         | SSCR0_SSE;
 274         default:
 275                 return clk_div
 276                         | SSCR0_Motorola
 277                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 278                         | SSCR0_SSE
 279                         | (bits > 16 ? SSCR0_EDSS : 0);
 280         }
 281 }
 282
 283 /*
 284  * Read and write LPSS SSP private registers. Caller must first check that
 285  * is_lpss_ssp() returns true before these can be called.
 286  */
 287 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
 288 {
 289         WARN_ON(!drv_data->lpss_base);
 290         return readl(drv_data->lpss_base + offset);
 291 }
 292
 293 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
 294                                   unsigned offset, u32 value)
 295 {
 296         WARN_ON(!drv_data->lpss_base);
 297         writel(value, drv_data->lpss_base + offset);
 298 }
 299
 300 /*
 301  * lpss_ssp_setup - perform LPSS SSP specific setup
 302  * @drv_data: pointer to the driver private data
 303  *
 304  * Perform LPSS SSP specific setup. This function must be called first if
 305  * one is going to use LPSS SSP private registers.
 306  */
 307 static void lpss_ssp_setup(struct driver_data *drv_data)
 308 {
 309         const struct lpss_config *config;
 310         u32 value;
 311
 312         config = lpss_get_config(drv_data);
 313         drv_data->lpss_base = drv_data->ioaddr + config->offset;
 314
 315         /* Enable software chip select control */
 316         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 317         value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
 318         value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
 319         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 320
 321         /* Enable multiblock DMA transfers */
 322         if (drv_data->controller_info->enable_dma) {
 323                 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
 324
 325                 if (config->reg_general >= 0) {
 326                         value = __lpss_ssp_read_priv(drv_data,
 327                                                      config->reg_general);
 328                         value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
 329                         __lpss_ssp_write_priv(drv_data,
 330                                               config->reg_general, value);
 331                 }
 332         }
 333 }
 334
 335 static void lpss_ssp_select_cs(struct spi_device *spi,
 336                                const struct lpss_config *config)
 337 {
 338         struct driver_data *drv_data =
 339                 spi_controller_get_devdata(spi->controller);
 340         u32 value, cs;
 341
 342         if (!config->cs_sel_mask)
 343                 return;
 344
 345         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 346
 347         cs = spi->chip_select;
 348         cs <<= config->cs_sel_shift;
 349         if (cs != (value & config->cs_sel_mask)) {
 350                 /*
 351                  * When switching another chip select output active the
 352                  * output must be selected first and wait 2 ssp_clk cycles
 353                  * before changing state to active. Otherwise a short
 354                  * glitch will occur on the previous chip select since
 355                  * output select is latched but state control is not.
 356                  */
 357                 value &= ~config->cs_sel_mask;
 358                 value |= cs;
 359                 __lpss_ssp_write_priv(drv_data,
 360                                       config->reg_cs_ctrl, value);
 361                 ndelay(1000000000 /
 362                        (drv_data->controller->max_speed_hz / 2));
 363         }
 364 }
 365
 366 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 367 {
 368         struct driver_data *drv_data =
 369                 spi_controller_get_devdata(spi->controller);
 370         const struct lpss_config *config;
 371         u32 value;
 372
 373         config = lpss_get_config(drv_data);
 374
 375         if (enable)
 376                 lpss_ssp_select_cs(spi, config);
 377
 378         value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
 379         if (enable)
 380                 value &= ~LPSS_CS_CONTROL_CS_HIGH;
 381         else
 382                 value |= LPSS_CS_CONTROL_CS_HIGH;
 383         __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
 384 }
 385
 386 static void cs_assert(struct spi_device *spi)
 387 {
 388         struct chip_data *chip = spi_get_ctldata(spi);
 389         struct driver_data *drv_data =
 390                 spi_controller_get_devdata(spi->controller);
 391
 392         if (drv_data->ssp_type == CE4100_SSP) {
 393                 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
 394                 return;
 395         }
 396
 397         if (chip->cs_control) {
 398                 chip->cs_control(PXA2XX_CS_ASSERT);
 399                 return;
 400         }
 401
 402         if (chip->gpiod_cs) {
 403                 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
 404                 return;
 405         }
 406
 407         if (is_lpss_ssp(drv_data))
 408                 lpss_ssp_cs_control(spi, true);
 409 }
 410
 411 static void cs_deassert(struct spi_device *spi)
 412 {
 413         struct chip_data *chip = spi_get_ctldata(spi);
 414         struct driver_data *drv_data =
 415                 spi_controller_get_devdata(spi->controller);
 416         unsigned long timeout;
 417
 418         if (drv_data->ssp_type == CE4100_SSP)
 419                 return;
 420
 421         /* Wait until SSP becomes idle before deasserting the CS */
 422         timeout = jiffies + msecs_to_jiffies(10);
 423         while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
 424                !time_after(jiffies, timeout))
 425                 cpu_relax();
 426
 427         if (chip->cs_control) {
 428                 chip->cs_control(PXA2XX_CS_DEASSERT);
 429                 return;
 430         }
 431
 432         if (chip->gpiod_cs) {
 433                 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
 434                 return;
 435         }
 436
 437         if (is_lpss_ssp(drv_data))
 438                 lpss_ssp_cs_control(spi, false);
 439 }
 440
 441 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level)
 442 {
 443         if (level)
 444                 cs_deassert(spi);
 445         else
 446                 cs_assert(spi);
 447 }
 448
 449 int pxa2xx_spi_flush(struct driver_data *drv_data)
 450 {
 451         unsigned long limit = loops_per_jiffy << 1;
 452
 453         do {
 454                 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 455                         pxa2xx_spi_read(drv_data, SSDR);
 456         } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
 457         write_SSSR_CS(drv_data, SSSR_ROR);
 458
 459         return limit;
 460 }
 461
 462 static int null_writer(struct driver_data *drv_data)
 463 {
 464         u8 n_bytes = drv_data->n_bytes;
 465
 466         if (pxa2xx_spi_txfifo_full(drv_data)
 467                 || (drv_data->tx == drv_data->tx_end))
 468                 return 0;
 469
 470         pxa2xx_spi_write(drv_data, SSDR, 0);
 471         drv_data->tx += n_bytes;
 472
 473         return 1;
 474 }
 475
 476 static int null_reader(struct driver_data *drv_data)
 477 {
 478         u8 n_bytes = drv_data->n_bytes;
 479
 480         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 481                && (drv_data->rx < drv_data->rx_end)) {
 482                 pxa2xx_spi_read(drv_data, SSDR);
 483                 drv_data->rx += n_bytes;
 484         }
 485
 486         return drv_data->rx == drv_data->rx_end;
 487 }
 488
 489 static int u8_writer(struct driver_data *drv_data)
 490 {
 491         if (pxa2xx_spi_txfifo_full(drv_data)
 492                 || (drv_data->tx == drv_data->tx_end))
 493                 return 0;
 494
 495         pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
 496         ++drv_data->tx;
 497
 498         return 1;
 499 }
 500
 501 static int u8_reader(struct driver_data *drv_data)
 502 {
 503         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 504                && (drv_data->rx < drv_data->rx_end)) {
 505                 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 506                 ++drv_data->rx;
 507         }
 508
 509         return drv_data->rx == drv_data->rx_end;
 510 }
 511
 512 static int u16_writer(struct driver_data *drv_data)
 513 {
 514         if (pxa2xx_spi_txfifo_full(drv_data)
 515                 || (drv_data->tx == drv_data->tx_end))
 516                 return 0;
 517
 518         pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
 519         drv_data->tx += 2;
 520
 521         return 1;
 522 }
 523
 524 static int u16_reader(struct driver_data *drv_data)
 525 {
 526         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 527                && (drv_data->rx < drv_data->rx_end)) {
 528                 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 529                 drv_data->rx += 2;
 530         }
 531
 532         return drv_data->rx == drv_data->rx_end;
 533 }
 534
 535 static int u32_writer(struct driver_data *drv_data)
 536 {
 537         if (pxa2xx_spi_txfifo_full(drv_data)
 538                 || (drv_data->tx == drv_data->tx_end))
 539                 return 0;
 540
 541         pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
 542         drv_data->tx += 4;
 543
 544         return 1;
 545 }
 546
 547 static int u32_reader(struct driver_data *drv_data)
 548 {
 549         while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
 550                && (drv_data->rx < drv_data->rx_end)) {
 551                 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
 552                 drv_data->rx += 4;
 553         }
 554
 555         return drv_data->rx == drv_data->rx_end;
 556 }
 557
 558 static void reset_sccr1(struct driver_data *drv_data)
 559 {
 560         struct chip_data *chip =
 561                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 562         u32 sccr1_reg;
 563
 564         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
 565         switch (drv_data->ssp_type) {
 566         case QUARK_X1000_SSP:
 567                 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
 568                 break;
 569         case CE4100_SSP:
 570                 sccr1_reg &= ~CE4100_SSCR1_RFT;
 571                 break;
 572         default:
 573                 sccr1_reg &= ~SSCR1_RFT;
 574                 break;
 575         }
 576         sccr1_reg |= chip->threshold;
 577         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 578 }
 579
 580 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 581 {
 582         /* Stop and reset SSP */
 583         write_SSSR_CS(drv_data, drv_data->clear_sr);
 584         reset_sccr1(drv_data);
 585         if (!pxa25x_ssp_comp(drv_data))
 586                 pxa2xx_spi_write(drv_data, SSTO, 0);
 587         pxa2xx_spi_flush(drv_data);
 588         pxa2xx_spi_write(drv_data, SSCR0,
 589                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 590
 591         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 592
 593         drv_data->controller->cur_msg->status = -EIO;
 594         spi_finalize_current_transfer(drv_data->controller);
 595 }
 596
 597 static void int_transfer_complete(struct driver_data *drv_data)
 598 {
 599         /* Clear and disable interrupts */
 600         write_SSSR_CS(drv_data, drv_data->clear_sr);
 601         reset_sccr1(drv_data);
 602         if (!pxa25x_ssp_comp(drv_data))
 603                 pxa2xx_spi_write(drv_data, SSTO, 0);
 604
 605         spi_finalize_current_transfer(drv_data->controller);
 606 }
 607
 608 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 609 {
 610         u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
 611                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 612
 613         u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
 614
 615         if (irq_status & SSSR_ROR) {
 616                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 617                 return IRQ_HANDLED;
 618         }
 619
 620         if (irq_status & SSSR_TUR) {
 621                 int_error_stop(drv_data, "interrupt_transfer: fifo underrun");
 622                 return IRQ_HANDLED;
 623         }
 624
 625         if (irq_status & SSSR_TINT) {
 626                 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
 627                 if (drv_data->read(drv_data)) {
 628                         int_transfer_complete(drv_data);
 629                         return IRQ_HANDLED;
 630                 }
 631         }
 632
 633         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 634         do {
 635                 if (drv_data->read(drv_data)) {
 636                         int_transfer_complete(drv_data);
 637                         return IRQ_HANDLED;
 638                 }
 639         } while (drv_data->write(drv_data));
 640
 641         if (drv_data->read(drv_data)) {
 642                 int_transfer_complete(drv_data);
 643                 return IRQ_HANDLED;
 644         }
 645
 646         if (drv_data->tx == drv_data->tx_end) {
 647                 u32 bytes_left;
 648                 u32 sccr1_reg;
 649
 650                 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 651                 sccr1_reg &= ~SSCR1_TIE;
 652
 653                 /*
 654                  * PXA25x_SSP has no timeout, set up rx threshould for the
 655                  * remaining RX bytes.
 656                  */
 657                 if (pxa25x_ssp_comp(drv_data)) {
 658                         u32 rx_thre;
 659
 660                         pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
 661
 662                         bytes_left = drv_data->rx_end - drv_data->rx;
 663                         switch (drv_data->n_bytes) {
 664                         case 4:
 665                                 bytes_left >>= 2;
 666                                 break;
 667                         case 2:
 668                                 bytes_left >>= 1;
 669                                 break;
 670                         }
 671
 672                         rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
 673                         if (rx_thre > bytes_left)
 674                                 rx_thre = bytes_left;
 675
 676                         pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
 677                 }
 678                 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 679         }
 680
 681         /* We did something */
 682         return IRQ_HANDLED;
 683 }
 684
 685 static void handle_bad_msg(struct driver_data *drv_data)
 686 {
 687         pxa2xx_spi_write(drv_data, SSCR0,
 688                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
 689         pxa2xx_spi_write(drv_data, SSCR1,
 690                          pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
 691         if (!pxa25x_ssp_comp(drv_data))
 692                 pxa2xx_spi_write(drv_data, SSTO, 0);
 693         write_SSSR_CS(drv_data, drv_data->clear_sr);
 694
 695         dev_err(&drv_data->pdev->dev,
 696                 "bad message state in interrupt handler\n");
 697 }
 698
 699 static irqreturn_t ssp_int(int irq, void *dev_id)
 700 {
 701         struct driver_data *drv_data = dev_id;
 702         u32 sccr1_reg;
 703         u32 mask = drv_data->mask_sr;
 704         u32 status;
 705
 706         /*
 707          * The IRQ might be shared with other peripherals so we must first
 708          * check that are we RPM suspended or not. If we are we assume that
 709          * the IRQ was not for us (we shouldn't be RPM suspended when the
 710          * interrupt is enabled).
 711          */
 712         if (pm_runtime_suspended(&drv_data->pdev->dev))
 713                 return IRQ_NONE;
 714
 715         /*
 716          * If the device is not yet in RPM suspended state and we get an
 717          * interrupt that is meant for another device, check if status bits
 718          * are all set to one. That means that the device is already
 719          * powered off.
 720          */
 721         status = pxa2xx_spi_read(drv_data, SSSR);
 722         if (status == ~0)
 723                 return IRQ_NONE;
 724
 725         sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 726
 727         /* Ignore possible writes if we don't need to write */
 728         if (!(sccr1_reg & SSCR1_TIE))
 729                 mask &= ~SSSR_TFS;
 730
 731         /* Ignore RX timeout interrupt if it is disabled */
 732         if (!(sccr1_reg & SSCR1_TINTE))
 733                 mask &= ~SSSR_TINT;
 734
 735         if (!(status & mask))
 736                 return IRQ_NONE;
 737
 738         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
 739         pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
 740
 741         if (!drv_data->controller->cur_msg) {
 742                 handle_bad_msg(drv_data);
 743                 /* Never fail */
 744                 return IRQ_HANDLED;
 745         }
 746
 747         return drv_data->transfer_handler(drv_data);
 748 }
 749
 750 /*
 751  * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
 752  * input frequency by fractions of 2^24. It also has a divider by 5.
 753  *
 754  * There are formulas to get baud rate value for given input frequency and
 755  * divider parameters, such as DDS_CLK_RATE and SCR:
 756  *
 757  * Fsys = 200MHz
 758  *
 759  * Fssp = Fsys * DDS_CLK_RATE / 2^24                    (1)
 760  * Baud rate = Fsclk = Fssp / (2 * (SCR + 1))           (2)
 761  *
 762  * DDS_CLK_RATE either 2^n or 2^n / 5.
 763  * SCR is in range 0 .. 255
 764  *
 765  * Divisor = 5^i * 2^j * 2 * k
 766  *       i = [0, 1]      i = 1 iff j = 0 or j > 3
 767  *       j = [0, 23]     j = 0 iff i = 1
 768  *       k = [1, 256]
 769  * Special case: j = 0, i = 1: Divisor = 2 / 5
 770  *
 771  * Accordingly to the specification the recommended values for DDS_CLK_RATE
 772  * are:
 773  *      Case 1:         2^n, n = [0, 23]
 774  *      Case 2:         2^24 * 2 / 5 (0x666666)
 775  *      Case 3:         less than or equal to 2^24 / 5 / 16 (0x33333)
 776  *
 777  * In all cases the lowest possible value is better.
 778  *
 779  * The function calculates parameters for all cases and chooses the one closest
 780  * to the asked baud rate.
 781  */
 782 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
 783 {
 784         unsigned long xtal = 200000000;
 785         unsigned long fref = xtal / 2;          /* mandatory division by 2,
 786                                                    see (2) */
 787                                                 /* case 3 */
 788         unsigned long fref1 = fref / 2;         /* case 1 */
 789         unsigned long fref2 = fref * 2 / 5;     /* case 2 */
 790         unsigned long scale;
 791         unsigned long q, q1, q2;
 792         long r, r1, r2;
 793         u32 mul;
 794
 795         /* Case 1 */
 796
 797         /* Set initial value for DDS_CLK_RATE */
 798         mul = (1 << 24) >> 1;
 799
 800         /* Calculate initial quot */
 801         q1 = DIV_ROUND_UP(fref1, rate);
 802
 803         /* Scale q1 if it's too big */
 804         if (q1 > 256) {
 805                 /* Scale q1 to range [1, 512] */
 806                 scale = fls_long(q1 - 1);
 807                 if (scale > 9) {
 808                         q1 >>= scale - 9;
 809                         mul >>= scale - 9;
 810                 }
 811
 812                 /* Round the result if we have a remainder */
 813                 q1 += q1 & 1;
 814         }
 815
 816         /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
 817         scale = __ffs(q1);
 818         q1 >>= scale;
 819         mul >>= scale;
 820
 821         /* Get the remainder */
 822         r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
 823
 824         /* Case 2 */
 825
 826         q2 = DIV_ROUND_UP(fref2, rate);
 827         r2 = abs(fref2 / q2 - rate);
 828
 829         /*
 830          * Choose the best between two: less remainder we have the better. We
 831          * can't go case 2 if q2 is greater than 256 since SCR register can
 832          * hold only values 0 .. 255.
 833          */
 834         if (r2 >= r1 || q2 > 256) {
 835                 /* case 1 is better */
 836                 r = r1;
 837                 q = q1;
 838         } else {
 839                 /* case 2 is better */
 840                 r = r2;
 841                 q = q2;
 842                 mul = (1 << 24) * 2 / 5;
 843         }
 844
 845         /* Check case 3 only if the divisor is big enough */
 846         if (fref / rate >= 80) {
 847                 u64 fssp;
 848                 u32 m;
 849
 850                 /* Calculate initial quot */
 851                 q1 = DIV_ROUND_UP(fref, rate);
 852                 m = (1 << 24) / q1;
 853
 854                 /* Get the remainder */
 855                 fssp = (u64)fref * m;
 856                 do_div(fssp, 1 << 24);
 857                 r1 = abs(fssp - rate);
 858
 859                 /* Choose this one if it suits better */
 860                 if (r1 < r) {
 861                         /* case 3 is better */
 862                         q = 1;
 863                         mul = m;
 864                 }
 865         }
 866
 867         *dds = mul;
 868         return q - 1;
 869 }
 870
 871 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 872 {
 873         unsigned long ssp_clk = drv_data->controller->max_speed_hz;
 874         const struct ssp_device *ssp = drv_data->ssp;
 875
 876         rate = min_t(int, ssp_clk, rate);
 877
 878         /*
 879          * Calculate the divisor for the SCR (Serial Clock Rate), avoiding
 880          * that the SSP transmission rate can be greater than the device rate
 881          */
 882         if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 883                 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff;
 884         else
 885                 return (DIV_ROUND_UP(ssp_clk, rate) - 1)  & 0xfff;
 886 }
 887
 888 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
 889                                            int rate)
 890 {
 891         struct chip_data *chip =
 892                 spi_get_ctldata(drv_data->controller->cur_msg->spi);
 893         unsigned int clk_div;
 894
 895         switch (drv_data->ssp_type) {
 896         case QUARK_X1000_SSP:
 897                 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
 898                 break;
 899         default:
 900                 clk_div = ssp_get_clk_div(drv_data, rate);
 901                 break;
 902         }
 903         return clk_div << 8;
 904 }
 905
 906 static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
 907                                struct spi_device *spi,
 908                                struct spi_transfer *xfer)
 909 {
 910         struct chip_data *chip = spi_get_ctldata(spi);
 911
 912         return chip->enable_dma &&
 913                xfer->len <= MAX_DMA_LEN &&
 914                xfer->len >= chip->dma_burst_size;
 915 }
 916
 917 static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
 918                                    struct spi_device *spi,
 919                                    struct spi_transfer *transfer)
 920 {
 921         struct driver_data *drv_data = spi_controller_get_devdata(controller);
 922         struct spi_message *message = controller->cur_msg;
 923         struct chip_data *chip = spi_get_ctldata(spi);
 924         u32 dma_thresh = chip->dma_threshold;
 925         u32 dma_burst = chip->dma_burst_size;
 926         u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
 927         u32 clk_div;
 928         u8 bits;
 929         u32 speed;
 930         u32 cr0;
 931         u32 cr1;
 932         int err;
 933         int dma_mapped;
 934
 935         /* Check if we can DMA this transfer */
 936         if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
 937
 938                 /* reject already-mapped transfers; PIO won't always work */
 939                 if (message->is_dma_mapped
 940                                 || transfer->rx_dma || transfer->tx_dma) {
 941                         dev_err(&spi->dev,
 942                                 "Mapped transfer length of %u is greater than %d\n",
 943                                 transfer->len, MAX_DMA_LEN);
 944                         return -EINVAL;
 945                 }
 946
 947                 /* warn ... we force this to PIO mode */
 948                 dev_warn_ratelimited(&spi->dev,
 949                                      "DMA disabled for transfer length %ld greater than %d\n",
 950                                      (long)transfer->len, MAX_DMA_LEN);
 951         }
 952
 953         /* Setup the transfer state based on the type of transfer */
 954         if (pxa2xx_spi_flush(drv_data) == 0) {
 955                 dev_err(&spi->dev, "Flush failed\n");
 956                 return -EIO;
 957         }
 958         drv_data->n_bytes = chip->n_bytes;
 959         drv_data->tx = (void *)transfer->tx_buf;
 960         drv_data->tx_end = drv_data->tx + transfer->len;
 961         drv_data->rx = transfer->rx_buf;
 962         drv_data->rx_end = drv_data->rx + transfer->len;
 963         drv_data->write = drv_data->tx ? chip->write : null_writer;
 964         drv_data->read = drv_data->rx ? chip->read : null_reader;
 965
 966         /* Change speed and bit per word on a per transfer */
 967         bits = transfer->bits_per_word;
 968         speed = transfer->speed_hz;
 969
 970         clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
 971
 972         if (bits <= 8) {
 973                 drv_data->n_bytes = 1;
 974                 drv_data->read = drv_data->read != null_reader ?
 975                                         u8_reader : null_reader;
 976                 drv_data->write = drv_data->write != null_writer ?
 977                                         u8_writer : null_writer;
 978         } else if (bits <= 16) {
 979                 drv_data->n_bytes = 2;
 980                 drv_data->read = drv_data->read != null_reader ?
 981                                         u16_reader : null_reader;
 982                 drv_data->write = drv_data->write != null_writer ?
 983                                         u16_writer : null_writer;
 984         } else if (bits <= 32) {
 985                 drv_data->n_bytes = 4;
 986                 drv_data->read = drv_data->read != null_reader ?
 987                                         u32_reader : null_reader;
 988                 drv_data->write = drv_data->write != null_writer ?
 989                                         u32_writer : null_writer;
 990         }
 991         /*
 992          * if bits/word is changed in dma mode, then must check the
 993          * thresholds and burst also
 994          */
 995         if (chip->enable_dma) {
 996                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
 997                                                 spi,
 998                                                 bits, &dma_burst,
 999                                                 &dma_thresh))
1000                         dev_warn_ratelimited(&spi->dev,
1001                                              "DMA burst size reduced to match bits_per_word\n");
1002         }
1003
1004         dma_mapped = controller->can_dma &&
1005                      controller->can_dma(controller, spi, transfer) &&
1006                      controller->cur_msg_mapped;
1007         if (dma_mapped) {
1008
1009                 /* Ensure we have the correct interrupt handler */
1010                 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1011
1012                 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1013                 if (err)
1014                         return err;
1015
1016                 /* Clear status and start DMA engine */
1017                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1018                 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1019
1020                 pxa2xx_spi_dma_start(drv_data);
1021         } else {
1022                 /* Ensure we have the correct interrupt handler */
1023                 drv_data->transfer_handler = interrupt_transfer;
1024
1025                 /* Clear status  */
1026                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1027                 write_SSSR_CS(drv_data, drv_data->clear_sr);
1028         }
1029
1030         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1031         cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1032         if (!pxa25x_ssp_comp(drv_data))
1033                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1034                         controller->max_speed_hz
1035                                 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1036                         dma_mapped ? "DMA" : "PIO");
1037         else
1038                 dev_dbg(&spi->dev, "%u Hz actual, %s\n",
1039                         controller->max_speed_hz / 2
1040                                 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1041                         dma_mapped ? "DMA" : "PIO");
1042
1043         if (is_lpss_ssp(drv_data)) {
1044                 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1045                     != chip->lpss_rx_threshold)
1046                         pxa2xx_spi_write(drv_data, SSIRF,
1047                                          chip->lpss_rx_threshold);
1048                 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1049                     != chip->lpss_tx_threshold)
1050                         pxa2xx_spi_write(drv_data, SSITF,
1051                                          chip->lpss_tx_threshold);
1052         }
1053
1054         if (is_quark_x1000_ssp(drv_data) &&
1055             (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1056                 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1057
1058         /* see if we need to reload the config registers */
1059         if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1060             || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1061             != (cr1 & change_mask)) {
1062                 /* stop the SSP, and update the other bits */
1063                 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1064                 if (!pxa25x_ssp_comp(drv_data))
1065                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1066                 /* first set CR1 without interrupt and service enables */
1067                 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1068                 /* restart the SSP */
1069                 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1070
1071         } else {
1072                 if (!pxa25x_ssp_comp(drv_data))
1073                         pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1074         }
1075
1076         if (drv_data->ssp_type == MMP2_SSP) {
1077                 u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR)
1078                                         & SSSR_TFL_MASK) >> 8;
1079
1080                 if (tx_level) {
1081                         /* On MMP2, flipping SSE doesn't to empty TXFIFO. */
1082                         dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n",
1083                                                                 tx_level);
1084                         if (tx_level > transfer->len)
1085                                 tx_level = transfer->len;
1086                         drv_data->tx += tx_level;
1087                 }
1088         }
1089
1090         if (spi_controller_is_slave(controller)) {
1091                 while (drv_data->write(drv_data))
1092                         ;
1093                 if (drv_data->gpiod_ready) {
1094                         gpiod_set_value(drv_data->gpiod_ready, 1);
1095                         udelay(1);
1096                         gpiod_set_value(drv_data->gpiod_ready, 0);
1097                 }
1098         }
1099
1100         /*
1101          * Release the data by enabling service requests and interrupts,
1102          * without changing any mode bits
1103          */
1104         pxa2xx_spi_write(drv_data, SSCR1, cr1);
1105
1106         return 1;
1107 }
1108
1109 static int pxa2xx_spi_slave_abort(struct spi_controller *controller)
1110 {
1111         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1112
1113         /* Stop and reset SSP */
1114         write_SSSR_CS(drv_data, drv_data->clear_sr);
1115         reset_sccr1(drv_data);
1116         if (!pxa25x_ssp_comp(drv_data))
1117                 pxa2xx_spi_write(drv_data, SSTO, 0);
1118         pxa2xx_spi_flush(drv_data);
1119         pxa2xx_spi_write(drv_data, SSCR0,
1120                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1121
1122         dev_dbg(&drv_data->pdev->dev, "transfer aborted\n");
1123
1124         drv_data->controller->cur_msg->status = -EINTR;
1125         spi_finalize_current_transfer(drv_data->controller);
1126
1127         return 0;
1128 }
1129
1130 static void pxa2xx_spi_handle_err(struct spi_controller *controller,
1131                                  struct spi_message *msg)
1132 {
1133         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1134
1135         /* Disable the SSP */
1136         pxa2xx_spi_write(drv_data, SSCR0,
1137                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1138         /* Clear and disable interrupts and service requests */
1139         write_SSSR_CS(drv_data, drv_data->clear_sr);
1140         pxa2xx_spi_write(drv_data, SSCR1,
1141                          pxa2xx_spi_read(drv_data, SSCR1)
1142                          & ~(drv_data->int_cr1 | drv_data->dma_cr1));
1143         if (!pxa25x_ssp_comp(drv_data))
1144                 pxa2xx_spi_write(drv_data, SSTO, 0);
1145
1146         /*
1147          * Stop the DMA if running. Note DMA callback handler may have unset
1148          * the dma_running already, which is fine as stopping is not needed
1149          * then but we shouldn't rely this flag for anything else than
1150          * stopping. For instance to differentiate between PIO and DMA
1151          * transfers.
1152          */
1153         if (atomic_read(&drv_data->dma_running))
1154                 pxa2xx_spi_dma_stop(drv_data);
1155 }
1156
1157 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
1158 {
1159         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1160
1161         /* Disable the SSP now */
1162         pxa2xx_spi_write(drv_data, SSCR0,
1163                          pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1164
1165         return 0;
1166 }
1167
1168 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1169                     struct pxa2xx_spi_chip *chip_info)
1170 {
1171         struct driver_data *drv_data =
1172                 spi_controller_get_devdata(spi->controller);
1173         struct gpio_desc *gpiod;
1174         int err = 0;
1175
1176         if (chip == NULL)
1177                 return 0;
1178
1179         if (drv_data->cs_gpiods) {
1180                 gpiod = drv_data->cs_gpiods[spi->chip_select];
1181                 if (gpiod) {
1182                         chip->gpiod_cs = gpiod;
1183                         chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1184                         gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1185                 }
1186
1187                 return 0;
1188         }
1189
1190         if (chip_info == NULL)
1191                 return 0;
1192
1193         /* NOTE: setup() can be called multiple times, possibly with
1194          * different chip_info, release previously requested GPIO
1195          */
1196         if (chip->gpiod_cs) {
1197                 gpiod_put(chip->gpiod_cs);
1198                 chip->gpiod_cs = NULL;
1199         }
1200
1201         /* If (*cs_control) is provided, ignore GPIO chip select */
1202         if (chip_info->cs_control) {
1203                 chip->cs_control = chip_info->cs_control;
1204                 return 0;
1205         }
1206
1207         if (gpio_is_valid(chip_info->gpio_cs)) {
1208                 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1209                 if (err) {
1210                         dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1211                                 chip_info->gpio_cs);
1212                         return err;
1213                 }
1214
1215                 gpiod = gpio_to_desc(chip_info->gpio_cs);
1216                 chip->gpiod_cs = gpiod;
1217                 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1218
1219                 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1220         }
1221
1222         return err;
1223 }
1224
1225 static int setup(struct spi_device *spi)
1226 {
1227         struct pxa2xx_spi_chip *chip_info;
1228         struct chip_data *chip;
1229         const struct lpss_config *config;
1230         struct driver_data *drv_data =
1231                 spi_controller_get_devdata(spi->controller);
1232         uint tx_thres, tx_hi_thres, rx_thres;
1233
1234         switch (drv_data->ssp_type) {
1235         case QUARK_X1000_SSP:
1236                 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1237                 tx_hi_thres = 0;
1238                 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1239                 break;
1240         case CE4100_SSP:
1241                 tx_thres = TX_THRESH_CE4100_DFLT;
1242                 tx_hi_thres = 0;
1243                 rx_thres = RX_THRESH_CE4100_DFLT;
1244                 break;
1245         case LPSS_LPT_SSP:
1246         case LPSS_BYT_SSP:
1247         case LPSS_BSW_SSP:
1248         case LPSS_SPT_SSP:
1249         case LPSS_BXT_SSP:
1250         case LPSS_CNL_SSP:
1251                 config = lpss_get_config(drv_data);
1252                 tx_thres = config->tx_threshold_lo;
1253                 tx_hi_thres = config->tx_threshold_hi;
1254                 rx_thres = config->rx_threshold;
1255                 break;
1256         default:
1257                 tx_hi_thres = 0;
1258                 if (spi_controller_is_slave(drv_data->controller)) {
1259                         tx_thres = 1;
1260                         rx_thres = 2;
1261                 } else {
1262                         tx_thres = TX_THRESH_DFLT;
1263                         rx_thres = RX_THRESH_DFLT;
1264                 }
1265                 break;
1266         }
1267
1268         /* Only alloc on first setup */
1269         chip = spi_get_ctldata(spi);
1270         if (!chip) {
1271                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1272                 if (!chip)
1273                         return -ENOMEM;
1274
1275                 if (drv_data->ssp_type == CE4100_SSP) {
1276                         if (spi->chip_select > 4) {
1277                                 dev_err(&spi->dev,
1278                                         "failed setup: cs number must not be > 4.\n");
1279                                 kfree(chip);
1280                                 return -EINVAL;
1281                         }
1282
1283                         chip->frm = spi->chip_select;
1284                 }
1285                 chip->enable_dma = drv_data->controller_info->enable_dma;
1286                 chip->timeout = TIMOUT_DFLT;
1287         }
1288
1289         /* protocol drivers may change the chip settings, so...
1290          * if chip_info exists, use it */
1291         chip_info = spi->controller_data;
1292
1293         /* chip_info isn't always needed */
1294         chip->cr1 = 0;
1295         if (chip_info) {
1296                 if (chip_info->timeout)
1297                         chip->timeout = chip_info->timeout;
1298                 if (chip_info->tx_threshold)
1299                         tx_thres = chip_info->tx_threshold;
1300                 if (chip_info->tx_hi_threshold)
1301                         tx_hi_thres = chip_info->tx_hi_threshold;
1302                 if (chip_info->rx_threshold)
1303                         rx_thres = chip_info->rx_threshold;
1304                 chip->dma_threshold = 0;
1305                 if (chip_info->enable_loopback)
1306                         chip->cr1 = SSCR1_LBM;
1307         }
1308         if (spi_controller_is_slave(drv_data->controller)) {
1309                 chip->cr1 |= SSCR1_SCFR;
1310                 chip->cr1 |= SSCR1_SCLKDIR;
1311                 chip->cr1 |= SSCR1_SFRMDIR;
1312                 chip->cr1 |= SSCR1_SPH;
1313         }
1314
1315         chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1316         chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1317                                 | SSITF_TxHiThresh(tx_hi_thres);
1318
1319         /* set dma burst and threshold outside of chip_info path so that if
1320          * chip_info goes away after setting chip->enable_dma, the
1321          * burst and threshold can still respond to changes in bits_per_word */
1322         if (chip->enable_dma) {
1323                 /* set up legal burst and threshold for dma */
1324                 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1325                                                 spi->bits_per_word,
1326                                                 &chip->dma_burst_size,
1327                                                 &chip->dma_threshold)) {
1328                         dev_warn(&spi->dev,
1329                                  "in setup: DMA burst size reduced to match bits_per_word\n");
1330                 }
1331                 dev_dbg(&spi->dev,
1332                         "in setup: DMA burst size set to %u\n",
1333                         chip->dma_burst_size);
1334         }
1335
1336         switch (drv_data->ssp_type) {
1337         case QUARK_X1000_SSP:
1338                 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1339                                    & QUARK_X1000_SSCR1_RFT)
1340                                    | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1341                                    & QUARK_X1000_SSCR1_TFT);
1342                 break;
1343         case CE4100_SSP:
1344                 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) |
1345                         (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT);
1346                 break;
1347         default:
1348                 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1349                         (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1350                 break;
1351         }
1352
1353         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1354         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1355                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1356
1357         if (spi->mode & SPI_LOOP)
1358                 chip->cr1 |= SSCR1_LBM;
1359
1360         if (spi->bits_per_word <= 8) {
1361                 chip->n_bytes = 1;
1362                 chip->read = u8_reader;
1363                 chip->write = u8_writer;
1364         } else if (spi->bits_per_word <= 16) {
1365                 chip->n_bytes = 2;
1366                 chip->read = u16_reader;
1367                 chip->write = u16_writer;
1368         } else if (spi->bits_per_word <= 32) {
1369                 chip->n_bytes = 4;
1370                 chip->read = u32_reader;
1371                 chip->write = u32_writer;
1372         }
1373
1374         spi_set_ctldata(spi, chip);
1375
1376         if (drv_data->ssp_type == CE4100_SSP)
1377                 return 0;
1378
1379         return setup_cs(spi, chip, chip_info);
1380 }
1381
1382 static void cleanup(struct spi_device *spi)
1383 {
1384         struct chip_data *chip = spi_get_ctldata(spi);
1385         struct driver_data *drv_data =
1386                 spi_controller_get_devdata(spi->controller);
1387
1388         if (!chip)
1389                 return;
1390
1391         if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1392             chip->gpiod_cs)
1393                 gpiod_put(chip->gpiod_cs);
1394
1395         kfree(chip);
1396 }
1397
1398 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1399         { "INT33C0", LPSS_LPT_SSP },
1400         { "INT33C1", LPSS_LPT_SSP },
1401         { "INT3430", LPSS_LPT_SSP },
1402         { "INT3431", LPSS_LPT_SSP },
1403         { "80860F0E", LPSS_BYT_SSP },
1404         { "8086228E", LPSS_BSW_SSP },
1405         { },
1406 };
1407 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1408
1409 /*
1410  * PCI IDs of compound devices that integrate both host controller and private
1411  * integrated DMA engine. Please note these are not used in module
1412  * autoloading and probing in this module but matching the LPSS SSP type.
1413  */
1414 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1415         /* SPT-LP */
1416         { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1417         { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1418         /* SPT-H */
1419         { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1420         { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1421         /* KBL-H */
1422         { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1423         { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1424         /* BXT A-Step */
1425         { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1426         { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1427         { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1428         /* BXT B-Step */
1429         { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1430         { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1431         { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1432         /* GLK */
1433         { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1434         { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1435         { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1436         /* ICL-LP */
1437         { PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1438         { PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1439         { PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1440         /* EHL */
1441         { PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1442         { PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1443         { PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1444         /* APL */
1445         { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1446         { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1447         { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1448         /* CNL-LP */
1449         { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1450         { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1451         { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1452         /* CNL-H */
1453         { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1454         { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1455         { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1456         /* CML-LP */
1457         { PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1458         { PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1459         { PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1460         /* TGL-LP */
1461         { PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1462         { PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1463         { PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1464         { PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1465         { PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1466         { PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1467         { PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1468         { },
1469 };
1470
1471 static const struct of_device_id pxa2xx_spi_of_match[] = {
1472         { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1473         {},
1474 };
1475 MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1476
1477 #ifdef CONFIG_ACPI
1478
1479 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1480 {
1481         unsigned int devid;
1482         int port_id = -1;
1483
1484         if (adev && adev->pnp.unique_id &&
1485             !kstrtouint(adev->pnp.unique_id, 0, &devid))
1486                 port_id = devid;
1487         return port_id;
1488 }
1489
1490 #else /* !CONFIG_ACPI */
1491
1492 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1493 {
1494         return -1;
1495 }
1496
1497 #endif /* CONFIG_ACPI */
1498
1499
1500 #ifdef CONFIG_PCI
1501
1502 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1503 {
1504         return param == chan->device->dev;
1505 }
1506
1507 #endif /* CONFIG_PCI */
1508
1509 static struct pxa2xx_spi_controller *
1510 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1511 {
1512         struct pxa2xx_spi_controller *pdata;
1513         struct acpi_device *adev;
1514         struct ssp_device *ssp;
1515         struct resource *res;
1516         const struct acpi_device_id *adev_id = NULL;
1517         const struct pci_device_id *pcidev_id = NULL;
1518         const struct of_device_id *of_id = NULL;
1519         enum pxa_ssp_type type;
1520
1521         adev = ACPI_COMPANION(&pdev->dev);
1522
1523         if (pdev->dev.of_node)
1524                 of_id = of_match_device(pdev->dev.driver->of_match_table,
1525                                         &pdev->dev);
1526         else if (dev_is_pci(pdev->dev.parent))
1527                 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1528                                          to_pci_dev(pdev->dev.parent));
1529         else if (adev)
1530                 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1531                                             &pdev->dev);
1532         else
1533                 return NULL;
1534
1535         if (adev_id)
1536                 type = (enum pxa_ssp_type)adev_id->driver_data;
1537         else if (pcidev_id)
1538                 type = (enum pxa_ssp_type)pcidev_id->driver_data;
1539         else if (of_id)
1540                 type = (enum pxa_ssp_type)of_id->data;
1541         else
1542                 return NULL;
1543
1544         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1545         if (!pdata)
1546                 return NULL;
1547
1548         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1549         if (!res)
1550                 return NULL;
1551
1552         ssp = &pdata->ssp;
1553
1554         ssp->phys_base = res->start;
1555         ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1556         if (IS_ERR(ssp->mmio_base))
1557                 return NULL;
1558
1559 #ifdef CONFIG_PCI
1560         if (pcidev_id) {
1561                 pdata->tx_param = pdev->dev.parent;
1562                 pdata->rx_param = pdev->dev.parent;
1563                 pdata->dma_filter = pxa2xx_spi_idma_filter;
1564         }
1565 #endif
1566
1567         ssp->clk = devm_clk_get(&pdev->dev, NULL);
1568         ssp->irq = platform_get_irq(pdev, 0);
1569         ssp->type = type;
1570         ssp->pdev = pdev;
1571         ssp->port_id = pxa2xx_spi_get_port_id(adev);
1572
1573         pdata->is_slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
1574         pdata->num_chipselect = 1;
1575         pdata->enable_dma = true;
1576         pdata->dma_burst_size = 1;
1577
1578         return pdata;
1579 }
1580
1581 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller,
1582                                       unsigned int cs)
1583 {
1584         struct driver_data *drv_data = spi_controller_get_devdata(controller);
1585
1586         if (has_acpi_companion(&drv_data->pdev->dev)) {
1587                 switch (drv_data->ssp_type) {
1588                 /*
1589                  * For Atoms the ACPI DeviceSelection used by the Windows
1590                  * driver starts from 1 instead of 0 so translate it here
1591                  * to match what Linux expects.
1592                  */
1593                 case LPSS_BYT_SSP:
1594                 case LPSS_BSW_SSP:
1595                         return cs - 1;
1596
1597                 default:
1598                         break;
1599                 }
1600         }
1601
1602         return cs;
1603 }
1604
1605 static int pxa2xx_spi_probe(struct platform_device *pdev)
1606 {
1607         struct device *dev = &pdev->dev;
1608         struct pxa2xx_spi_controller *platform_info;
1609         struct spi_controller *controller;
1610         struct driver_data *drv_data;
1611         struct ssp_device *ssp;
1612         const struct lpss_config *config;
1613         int status, count;
1614         u32 tmp;
1615
1616         platform_info = dev_get_platdata(dev);
1617         if (!platform_info) {
1618                 platform_info = pxa2xx_spi_init_pdata(pdev);
1619                 if (!platform_info) {
1620                         dev_err(&pdev->dev, "missing platform data\n");
1621                         return -ENODEV;
1622                 }
1623         }
1624
1625         ssp = pxa_ssp_request(pdev->id, pdev->name);
1626         if (!ssp)
1627                 ssp = &platform_info->ssp;
1628
1629         if (!ssp->mmio_base) {
1630                 dev_err(&pdev->dev, "failed to get ssp\n");
1631                 return -ENODEV;
1632         }
1633
1634         if (platform_info->is_slave)
1635                 controller = spi_alloc_slave(dev, sizeof(struct driver_data));
1636         else
1637                 controller = spi_alloc_master(dev, sizeof(struct driver_data));
1638
1639         if (!controller) {
1640                 dev_err(&pdev->dev, "cannot alloc spi_controller\n");
1641                 pxa_ssp_free(ssp);
1642                 return -ENOMEM;
1643         }
1644         drv_data = spi_controller_get_devdata(controller);
1645         drv_data->controller = controller;
1646         drv_data->controller_info = platform_info;
1647         drv_data->pdev = pdev;
1648         drv_data->ssp = ssp;
1649
1650         controller->dev.of_node = pdev->dev.of_node;
1651         /* the spi->mode bits understood by this driver: */
1652         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1653
1654         controller->bus_num = ssp->port_id;
1655         controller->dma_alignment = DMA_ALIGNMENT;
1656         controller->cleanup = cleanup;
1657         controller->setup = setup;
1658         controller->set_cs = pxa2xx_spi_set_cs;
1659         controller->transfer_one = pxa2xx_spi_transfer_one;
1660         controller->slave_abort = pxa2xx_spi_slave_abort;
1661         controller->handle_err = pxa2xx_spi_handle_err;
1662         controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1663         controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1664         controller->auto_runtime_pm = true;
1665         controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
1666
1667         drv_data->ssp_type = ssp->type;
1668
1669         drv_data->ioaddr = ssp->mmio_base;
1670         drv_data->ssdr_physical = ssp->phys_base + SSDR;
1671         if (pxa25x_ssp_comp(drv_data)) {
1672                 switch (drv_data->ssp_type) {
1673                 case QUARK_X1000_SSP:
1674                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1675                         break;
1676                 default:
1677                         controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1678                         break;
1679                 }
1680
1681                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1682                 drv_data->dma_cr1 = 0;
1683                 drv_data->clear_sr = SSSR_ROR;
1684                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1685         } else {
1686                 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1687                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1688                 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1689                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1690                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1691                                                 | SSSR_ROR | SSSR_TUR;
1692         }
1693
1694         status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1695                         drv_data);
1696         if (status < 0) {
1697                 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1698                 goto out_error_controller_alloc;
1699         }
1700
1701         /* Setup DMA if requested */
1702         if (platform_info->enable_dma) {
1703                 status = pxa2xx_spi_dma_setup(drv_data);
1704                 if (status) {
1705                         dev_warn(dev, "no DMA channels available, using PIO\n");
1706                         platform_info->enable_dma = false;
1707                 } else {
1708                         controller->can_dma = pxa2xx_spi_can_dma;
1709                         controller->max_dma_len = MAX_DMA_LEN;
1710                 }
1711         }
1712
1713         /* Enable SOC clock */
1714         status = clk_prepare_enable(ssp->clk);
1715         if (status)
1716                 goto out_error_dma_irq_alloc;
1717
1718         controller->max_speed_hz = clk_get_rate(ssp->clk);
1719         /*
1720          * Set minimum speed for all other platforms than Intel Quark which is
1721          * able do under 1 Hz transfers.
1722          */
1723         if (!pxa25x_ssp_comp(drv_data))
1724                 controller->min_speed_hz =
1725                         DIV_ROUND_UP(controller->max_speed_hz, 4096);
1726         else if (!is_quark_x1000_ssp(drv_data))
1727                 controller->min_speed_hz =
1728                         DIV_ROUND_UP(controller->max_speed_hz, 512);
1729
1730         /* Load default SSP configuration */
1731         pxa2xx_spi_write(drv_data, SSCR0, 0);
1732         switch (drv_data->ssp_type) {
1733         case QUARK_X1000_SSP:
1734                 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) |
1735                       QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1736                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1737
1738                 /* using the Motorola SPI protocol and use 8 bit frame */
1739                 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8);
1740                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1741                 break;
1742         case CE4100_SSP:
1743                 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) |
1744                       CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT);
1745                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1746                 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1747                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1748                 break;
1749         default:
1750
1751                 if (spi_controller_is_slave(controller)) {
1752                         tmp = SSCR1_SCFR |
1753                               SSCR1_SCLKDIR |
1754                               SSCR1_SFRMDIR |
1755                               SSCR1_RxTresh(2) |
1756                               SSCR1_TxTresh(1) |
1757                               SSCR1_SPH;
1758                 } else {
1759                         tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1760                               SSCR1_TxTresh(TX_THRESH_DFLT);
1761                 }
1762                 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1763                 tmp = SSCR0_Motorola | SSCR0_DataSize(8);
1764                 if (!spi_controller_is_slave(controller))
1765                         tmp |= SSCR0_SCR(2);
1766                 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1767                 break;
1768         }
1769
1770         if (!pxa25x_ssp_comp(drv_data))
1771                 pxa2xx_spi_write(drv_data, SSTO, 0);
1772
1773         if (!is_quark_x1000_ssp(drv_data))
1774                 pxa2xx_spi_write(drv_data, SSPSP, 0);
1775
1776         if (is_lpss_ssp(drv_data)) {
1777                 lpss_ssp_setup(drv_data);
1778                 config = lpss_get_config(drv_data);
1779                 if (config->reg_capabilities >= 0) {
1780                         tmp = __lpss_ssp_read_priv(drv_data,
1781                                                    config->reg_capabilities);
1782                         tmp &= LPSS_CAPS_CS_EN_MASK;
1783                         tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1784                         platform_info->num_chipselect = ffz(tmp);
1785                 } else if (config->cs_num) {
1786                         platform_info->num_chipselect = config->cs_num;
1787                 }
1788         }
1789         controller->num_chipselect = platform_info->num_chipselect;
1790
1791         count = gpiod_count(&pdev->dev, "cs");
1792         if (count > 0) {
1793                 int i;
1794
1795                 controller->num_chipselect = max_t(int, count,
1796                         controller->num_chipselect);
1797
1798                 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev,
1799                         controller->num_chipselect, sizeof(struct gpio_desc *),
1800                         GFP_KERNEL);
1801                 if (!drv_data->cs_gpiods) {
1802                         status = -ENOMEM;
1803                         goto out_error_clock_enabled;
1804                 }
1805
1806                 for (i = 0; i < controller->num_chipselect; i++) {
1807                         struct gpio_desc *gpiod;
1808
1809                         gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1810                         if (IS_ERR(gpiod)) {
1811                                 /* Means use native chip select */
1812                                 if (PTR_ERR(gpiod) == -ENOENT)
1813                                         continue;
1814
1815                                 status = PTR_ERR(gpiod);
1816                                 goto out_error_clock_enabled;
1817                         } else {
1818                                 drv_data->cs_gpiods[i] = gpiod;
1819                         }
1820                 }
1821         }
1822
1823         if (platform_info->is_slave) {
1824                 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1825                                                 "ready", GPIOD_OUT_LOW);
1826                 if (IS_ERR(drv_data->gpiod_ready)) {
1827                         status = PTR_ERR(drv_data->gpiod_ready);
1828                         goto out_error_clock_enabled;
1829                 }
1830         }
1831
1832         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1833         pm_runtime_use_autosuspend(&pdev->dev);
1834         pm_runtime_set_active(&pdev->dev);
1835         pm_runtime_enable(&pdev->dev);
1836
1837         /* Register with the SPI framework */
1838         platform_set_drvdata(pdev, drv_data);
1839         status = devm_spi_register_controller(&pdev->dev, controller);
1840         if (status != 0) {
1841                 dev_err(&pdev->dev, "problem registering spi controller\n");
1842                 goto out_error_pm_runtime_enabled;
1843         }
1844
1845         return status;
1846
1847 out_error_pm_runtime_enabled:
1848         pm_runtime_put_noidle(&pdev->dev);
1849         pm_runtime_disable(&pdev->dev);
1850
1851 out_error_clock_enabled:
1852         clk_disable_unprepare(ssp->clk);
1853
1854 out_error_dma_irq_alloc:
1855         pxa2xx_spi_dma_release(drv_data);
1856         free_irq(ssp->irq, drv_data);
1857
1858 out_error_controller_alloc:
1859         spi_controller_put(controller);
1860         pxa_ssp_free(ssp);
1861         return status;
1862 }
1863
1864 static int pxa2xx_spi_remove(struct platform_device *pdev)
1865 {
1866         struct driver_data *drv_data = platform_get_drvdata(pdev);
1867         struct ssp_device *ssp;
1868
1869         if (!drv_data)
1870                 return 0;
1871         ssp = drv_data->ssp;
1872
1873         pm_runtime_get_sync(&pdev->dev);
1874
1875         /* Disable the SSP at the peripheral and SOC level */
1876         pxa2xx_spi_write(drv_data, SSCR0, 0);
1877         clk_disable_unprepare(ssp->clk);
1878
1879         /* Release DMA */
1880         if (drv_data->controller_info->enable_dma)
1881                 pxa2xx_spi_dma_release(drv_data);
1882
1883         pm_runtime_put_noidle(&pdev->dev);
1884         pm_runtime_disable(&pdev->dev);
1885
1886         /* Release IRQ */
1887         free_irq(ssp->irq, drv_data);
1888
1889         /* Release SSP */
1890         pxa_ssp_free(ssp);
1891
1892         return 0;
1893 }
1894
1895 #ifdef CONFIG_PM_SLEEP
1896 static int pxa2xx_spi_suspend(struct device *dev)
1897 {
1898         struct driver_data *drv_data = dev_get_drvdata(dev);
1899         struct ssp_device *ssp = drv_data->ssp;
1900         int status;
1901
1902         status = spi_controller_suspend(drv_data->controller);
1903         if (status != 0)
1904                 return status;
1905         pxa2xx_spi_write(drv_data, SSCR0, 0);
1906
1907         if (!pm_runtime_suspended(dev))
1908                 clk_disable_unprepare(ssp->clk);
1909
1910         return 0;
1911 }
1912
1913 static int pxa2xx_spi_resume(struct device *dev)
1914 {
1915         struct driver_data *drv_data = dev_get_drvdata(dev);
1916         struct ssp_device *ssp = drv_data->ssp;
1917         int status;
1918
1919         /* Enable the SSP clock */
1920         if (!pm_runtime_suspended(dev)) {
1921                 status = clk_prepare_enable(ssp->clk);
1922                 if (status)
1923                         return status;
1924         }
1925
1926         /* Start the queue running */
1927         return spi_controller_resume(drv_data->controller);
1928 }
1929 #endif
1930
1931 #ifdef CONFIG_PM
1932 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1933 {
1934         struct driver_data *drv_data = dev_get_drvdata(dev);
1935
1936         clk_disable_unprepare(drv_data->ssp->clk);
1937         return 0;
1938 }
1939
1940 static int pxa2xx_spi_runtime_resume(struct device *dev)
1941 {
1942         struct driver_data *drv_data = dev_get_drvdata(dev);
1943         int status;
1944
1945         status = clk_prepare_enable(drv_data->ssp->clk);
1946         return status;
1947 }
1948 #endif
1949
1950 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1951         SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1952         SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1953                            pxa2xx_spi_runtime_resume, NULL)
1954 };
1955
1956 static struct platform_driver driver = {
1957         .driver = {
1958                 .name   = "pxa2xx-spi",
1959                 .pm     = &pxa2xx_spi_pm_ops,
1960                 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1961                 .of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1962         },
1963         .probe = pxa2xx_spi_probe,
1964         .remove = pxa2xx_spi_remove,
1965 };
1966
1967 static int __init pxa2xx_spi_init(void)
1968 {
1969         return platform_driver_register(&driver);
1970 }
1971 subsys_initcall(pxa2xx_spi_init);
1972
1973 static void __exit pxa2xx_spi_exit(void)
1974 {
1975         platform_driver_unregister(&driver);
1976 }
1977 module_exit(pxa2xx_spi_exit);
1978
1979 MODULE_SOFTDEP("pre: dw_dmac");