drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/err.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/gcd.h>
  36
  37 #include <linux/spi/spi.h>
  38
  39 #include <linux/platform_data/spi-omap2-mcspi.h>
  40
  41 #define OMAP2_MCSPI_MAX_FREQ            48000000
  42 #define OMAP2_MCSPI_MAX_DIVIDER         4096
  43 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  44 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  45 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  46
  47 #define OMAP2_MCSPI_REVISION            0x00
  48 #define OMAP2_MCSPI_SYSSTATUS           0x14
  49 #define OMAP2_MCSPI_IRQSTATUS           0x18
  50 #define OMAP2_MCSPI_IRQENABLE           0x1c
  51 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  52 #define OMAP2_MCSPI_SYST                0x24
  53 #define OMAP2_MCSPI_MODULCTRL           0x28
  54 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  55
  56 /* per-channel banks, 0x14 bytes each, first is: */
  57 #define OMAP2_MCSPI_CHCONF0             0x2c
  58 #define OMAP2_MCSPI_CHSTAT0             0x30
  59 #define OMAP2_MCSPI_CHCTRL0             0x34
  60 #define OMAP2_MCSPI_TX0                 0x38
  61 #define OMAP2_MCSPI_RX0                 0x3c
  62
  63 /* per-register bitmasks: */
  64 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  65
  66 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  67 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  68 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  69
  70 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  71 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  72 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  73 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  74 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  75 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  76 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  77 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  78 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  79 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  80 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  81 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  82 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  83 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  84 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  85 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  86 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  87 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
  88
  89 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  90 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  91 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  92 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  93
  94 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  95 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
  96
  97 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  98
  99 /* We have 2 DMA channels per CS, one for RX and one for TX */
 100 struct omap2_mcspi_dma {
 101         struct dma_chan *dma_tx;
 102         struct dma_chan *dma_rx;
 103
 104         int dma_tx_sync_dev;
 105         int dma_rx_sync_dev;
 106
 107         struct completion dma_tx_completion;
 108         struct completion dma_rx_completion;
 109
 110         char dma_rx_ch_name[14];
 111         char dma_tx_ch_name[14];
 112 };
 113
 114 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 115  * cache operations; better heuristics consider wordsize and bitrate.
 116  */
 117 #define DMA_MIN_BYTES                   160
 118
 119
 120 /*
 121  * Used for context save and restore, structure members to be updated whenever
 122  * corresponding registers are modified.
 123  */
 124 struct omap2_mcspi_regs {
 125         u32 modulctrl;
 126         u32 wakeupenable;
 127         struct list_head cs;
 128 };
 129
 130 struct omap2_mcspi {
 131         struct spi_master       *master;
 132         /* Virtual base address of the controller */
 133         void __iomem            *base;
 134         unsigned long           phys;
 135         /* SPI1 has 4 channels, while SPI2 has 2 */
 136         struct omap2_mcspi_dma  *dma_channels;
 137         struct device           *dev;
 138         struct omap2_mcspi_regs ctx;
 139         int                     fifo_depth;
 140         unsigned int            pin_dir:1;
 141 };
 142
 143 struct omap2_mcspi_cs {
 144         void __iomem            *base;
 145         unsigned long           phys;
 146         int                     word_len;
 147         u16                     mode;
 148         struct list_head        node;
 149         /* Context save and restore shadow register */
 150         u32                     chconf0, chctrl0;
 151 };
 152
 153 static inline void mcspi_write_reg(struct spi_master *master,
 154                 int idx, u32 val)
 155 {
 156         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 157
 158         writel_relaxed(val, mcspi->base + idx);
 159 }
 160
 161 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 162 {
 163         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 164
 165         return readl_relaxed(mcspi->base + idx);
 166 }
 167
 168 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 169                 int idx, u32 val)
 170 {
 171         struct omap2_mcspi_cs   *cs = spi->controller_state;
 172
 173         writel_relaxed(val, cs->base +  idx);
 174 }
 175
 176 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 177 {
 178         struct omap2_mcspi_cs   *cs = spi->controller_state;
 179
 180         return readl_relaxed(cs->base + idx);
 181 }
 182
 183 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 184 {
 185         struct omap2_mcspi_cs *cs = spi->controller_state;
 186
 187         return cs->chconf0;
 188 }
 189
 190 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 191 {
 192         struct omap2_mcspi_cs *cs = spi->controller_state;
 193
 194         cs->chconf0 = val;
 195         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 196         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 197 }
 198
 199 static inline int mcspi_bytes_per_word(int word_len)
 200 {
 201         if (word_len <= 8)
 202                 return 1;
 203         else if (word_len <= 16)
 204                 return 2;
 205         else /* word_len <= 32 */
 206                 return 4;
 207 }
 208
 209 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 210                 int is_read, int enable)
 211 {
 212         u32 l, rw;
 213
 214         l = mcspi_cached_chconf0(spi);
 215
 216         if (is_read) /* 1 is read, 0 write */
 217                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 218         else
 219                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 220
 221         if (enable)
 222                 l |= rw;
 223         else
 224                 l &= ~rw;
 225
 226         mcspi_write_chconf0(spi, l);
 227 }
 228
 229 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 230 {
 231         struct omap2_mcspi_cs *cs = spi->controller_state;
 232         u32 l;
 233
 234         l = cs->chctrl0;
 235         if (enable)
 236                 l |= OMAP2_MCSPI_CHCTRL_EN;
 237         else
 238                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
 239         cs->chctrl0 = l;
 240         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 241         /* Flash post-writes */
 242         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 243 }
 244
 245 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 246 {
 247         u32 l;
 248
 249         l = mcspi_cached_chconf0(spi);
 250         if (cs_active)
 251                 l |= OMAP2_MCSPI_CHCONF_FORCE;
 252         else
 253                 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 254
 255         mcspi_write_chconf0(spi, l);
 256 }
 257
 258 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 259 {
 260         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 261         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 262         u32 l;
 263
 264         /*
 265          * Setup when switching from (reset default) slave mode
 266          * to single-channel master mode
 267          */
 268         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 269         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 270         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 271         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 272
 273         ctx->modulctrl = l;
 274 }
 275
 276 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 277                                 struct spi_transfer *t, int enable)
 278 {
 279         struct spi_master *master = spi->master;
 280         struct omap2_mcspi_cs *cs = spi->controller_state;
 281         struct omap2_mcspi *mcspi;
 282         unsigned int wcnt;
 283         int max_fifo_depth, fifo_depth, bytes_per_word;
 284         u32 chconf, xferlevel;
 285
 286         mcspi = spi_master_get_devdata(master);
 287
 288         chconf = mcspi_cached_chconf0(spi);
 289         if (enable) {
 290                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 291                 if (t->len % bytes_per_word != 0)
 292                         goto disable_fifo;
 293
 294                 if (t->rx_buf != NULL && t->tx_buf != NULL)
 295                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
 296                 else
 297                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
 298
 299                 fifo_depth = gcd(t->len, max_fifo_depth);
 300                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
 301                         goto disable_fifo;
 302
 303                 wcnt = t->len / bytes_per_word;
 304                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 305                         goto disable_fifo;
 306
 307                 xferlevel = wcnt << 16;
 308                 if (t->rx_buf != NULL) {
 309                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 310                         xferlevel |= (fifo_depth - 1) << 8;
 311                 }
 312                 if (t->tx_buf != NULL) {
 313                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 314                         xferlevel |= fifo_depth - 1;
 315                 }
 316
 317                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 318                 mcspi_write_chconf0(spi, chconf);
 319                 mcspi->fifo_depth = fifo_depth;
 320
 321                 return;
 322         }
 323
 324 disable_fifo:
 325         if (t->rx_buf != NULL)
 326                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 327
 328         if (t->tx_buf != NULL)
 329                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 330
 331         mcspi_write_chconf0(spi, chconf);
 332         mcspi->fifo_depth = 0;
 333 }
 334
 335 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 336 {
 337         struct spi_master       *spi_cntrl = mcspi->master;
 338         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 339         struct omap2_mcspi_cs   *cs;
 340
 341         /* McSPI: context restore */
 342         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 343         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 344
 345         list_for_each_entry(cs, &ctx->cs, node)
 346                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 347 }
 348
 349 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 350 {
 351         unsigned long timeout;
 352
 353         timeout = jiffies + msecs_to_jiffies(1000);
 354         while (!(readl_relaxed(reg) & bit)) {
 355                 if (time_after(jiffies, timeout)) {
 356                         if (!(readl_relaxed(reg) & bit))
 357                                 return -ETIMEDOUT;
 358                         else
 359                                 return 0;
 360                 }
 361                 cpu_relax();
 362         }
 363         return 0;
 364 }
 365
 366 static void omap2_mcspi_rx_callback(void *data)
 367 {
 368         struct spi_device *spi = data;
 369         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 370         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 371
 372         /* We must disable the DMA RX request */
 373         omap2_mcspi_set_dma_req(spi, 1, 0);
 374
 375         complete(&mcspi_dma->dma_rx_completion);
 376 }
 377
 378 static void omap2_mcspi_tx_callback(void *data)
 379 {
 380         struct spi_device *spi = data;
 381         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 382         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 383
 384         /* We must disable the DMA TX request */
 385         omap2_mcspi_set_dma_req(spi, 0, 0);
 386
 387         complete(&mcspi_dma->dma_tx_completion);
 388 }
 389
 390 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 391                                 struct spi_transfer *xfer,
 392                                 struct dma_slave_config cfg)
 393 {
 394         struct omap2_mcspi      *mcspi;
 395         struct omap2_mcspi_dma  *mcspi_dma;
 396         unsigned int            count;
 397
 398         mcspi = spi_master_get_devdata(spi->master);
 399         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 400         count = xfer->len;
 401
 402         if (mcspi_dma->dma_tx) {
 403                 struct dma_async_tx_descriptor *tx;
 404                 struct scatterlist sg;
 405
 406                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 407
 408                 sg_init_table(&sg, 1);
 409                 sg_dma_address(&sg) = xfer->tx_dma;
 410                 sg_dma_len(&sg) = xfer->len;
 411
 412                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 413                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 414                 if (tx) {
 415                         tx->callback = omap2_mcspi_tx_callback;
 416                         tx->callback_param = spi;
 417                         dmaengine_submit(tx);
 418                 } else {
 419                         /* FIXME: fall back to PIO? */
 420                 }
 421         }
 422         dma_async_issue_pending(mcspi_dma->dma_tx);
 423         omap2_mcspi_set_dma_req(spi, 0, 1);
 424
 425 }
 426
 427 static unsigned
 428 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 429                                 struct dma_slave_config cfg,
 430                                 unsigned es)
 431 {
 432         struct omap2_mcspi      *mcspi;
 433         struct omap2_mcspi_dma  *mcspi_dma;
 434         unsigned int            count, dma_count;
 435         u32                     l;
 436         int                     elements = 0;
 437         int                     word_len, element_count;
 438         struct omap2_mcspi_cs   *cs = spi->controller_state;
 439         mcspi = spi_master_get_devdata(spi->master);
 440         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 441         count = xfer->len;
 442         dma_count = xfer->len;
 443
 444         if (mcspi->fifo_depth == 0)
 445                 dma_count -= es;
 446
 447         word_len = cs->word_len;
 448         l = mcspi_cached_chconf0(spi);
 449
 450         if (word_len <= 8)
 451                 element_count = count;
 452         else if (word_len <= 16)
 453                 element_count = count >> 1;
 454         else /* word_len <= 32 */
 455                 element_count = count >> 2;
 456
 457         if (mcspi_dma->dma_rx) {
 458                 struct dma_async_tx_descriptor *tx;
 459                 struct scatterlist sg;
 460
 461                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 462
 463                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 464                         dma_count -= es;
 465
 466                 sg_init_table(&sg, 1);
 467                 sg_dma_address(&sg) = xfer->rx_dma;
 468                 sg_dma_len(&sg) = dma_count;
 469
 470                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 471                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 472                                 DMA_CTRL_ACK);
 473                 if (tx) {
 474                         tx->callback = omap2_mcspi_rx_callback;
 475                         tx->callback_param = spi;
 476                         dmaengine_submit(tx);
 477                 } else {
 478                                 /* FIXME: fall back to PIO? */
 479                 }
 480         }
 481
 482         dma_async_issue_pending(mcspi_dma->dma_rx);
 483         omap2_mcspi_set_dma_req(spi, 1, 1);
 484
 485         wait_for_completion(&mcspi_dma->dma_rx_completion);
 486         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 487                          DMA_FROM_DEVICE);
 488
 489         if (mcspi->fifo_depth > 0)
 490                 return count;
 491
 492         omap2_mcspi_set_enable(spi, 0);
 493
 494         elements = element_count - 1;
 495
 496         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 497                 elements--;
 498
 499                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 500                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 501                         u32 w;
 502
 503                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 504                         if (word_len <= 8)
 505                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 506                         else if (word_len <= 16)
 507                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 508                         else /* word_len <= 32 */
 509                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 510                 } else {
 511                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 512                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
 513                         count -= (bytes_per_word << 1);
 514                         omap2_mcspi_set_enable(spi, 1);
 515                         return count;
 516                 }
 517         }
 518         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 519                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 520                 u32 w;
 521
 522                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 523                 if (word_len <= 8)
 524                         ((u8 *)xfer->rx_buf)[elements] = w;
 525                 else if (word_len <= 16)
 526                         ((u16 *)xfer->rx_buf)[elements] = w;
 527                 else /* word_len <= 32 */
 528                         ((u32 *)xfer->rx_buf)[elements] = w;
 529         } else {
 530                 dev_err(&spi->dev, "DMA RX last word empty\n");
 531                 count -= mcspi_bytes_per_word(word_len);
 532         }
 533         omap2_mcspi_set_enable(spi, 1);
 534         return count;
 535 }
 536
 537 static unsigned
 538 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 539 {
 540         struct omap2_mcspi      *mcspi;
 541         struct omap2_mcspi_cs   *cs = spi->controller_state;
 542         struct omap2_mcspi_dma  *mcspi_dma;
 543         unsigned int            count;
 544         u32                     l;
 545         u8                      *rx;
 546         const u8                *tx;
 547         struct dma_slave_config cfg;
 548         enum dma_slave_buswidth width;
 549         unsigned es;
 550         u32                     burst;
 551         void __iomem            *chstat_reg;
 552         void __iomem            *irqstat_reg;
 553         int                     wait_res;
 554
 555         mcspi = spi_master_get_devdata(spi->master);
 556         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 557         l = mcspi_cached_chconf0(spi);
 558
 559
 560         if (cs->word_len <= 8) {
 561                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 562                 es = 1;
 563         } else if (cs->word_len <= 16) {
 564                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 565                 es = 2;
 566         } else {
 567                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 568                 es = 4;
 569         }
 570
 571         count = xfer->len;
 572         burst = 1;
 573
 574         if (mcspi->fifo_depth > 0) {
 575                 if (count > mcspi->fifo_depth)
 576                         burst = mcspi->fifo_depth / es;
 577                 else
 578                         burst = count / es;
 579         }
 580
 581         memset(&cfg, 0, sizeof(cfg));
 582         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 583         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 584         cfg.src_addr_width = width;
 585         cfg.dst_addr_width = width;
 586         cfg.src_maxburst = burst;
 587         cfg.dst_maxburst = burst;
 588
 589         rx = xfer->rx_buf;
 590         tx = xfer->tx_buf;
 591
 592         if (tx != NULL)
 593                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 594
 595         if (rx != NULL)
 596                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 597
 598         if (tx != NULL) {
 599                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 600                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 601                                  DMA_TO_DEVICE);
 602
 603                 if (mcspi->fifo_depth > 0) {
 604                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 605
 606                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 607                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 608                                 dev_err(&spi->dev, "EOW timed out\n");
 609
 610                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 611                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 612                 }
 613
 614                 /* for TX_ONLY mode, be sure all words have shifted out */
 615                 if (rx == NULL) {
 616                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 617                         if (mcspi->fifo_depth > 0) {
 618                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 619                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 620                                 if (wait_res < 0)
 621                                         dev_err(&spi->dev, "TXFFE timed out\n");
 622                         } else {
 623                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 624                                                 OMAP2_MCSPI_CHSTAT_TXS);
 625                                 if (wait_res < 0)
 626                                         dev_err(&spi->dev, "TXS timed out\n");
 627                         }
 628                         if (wait_res >= 0 &&
 629                                 (mcspi_wait_for_reg_bit(chstat_reg,
 630                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 631                                 dev_err(&spi->dev, "EOT timed out\n");
 632                 }
 633         }
 634         return count;
 635 }
 636
 637 static unsigned
 638 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 639 {
 640         struct omap2_mcspi      *mcspi;
 641         struct omap2_mcspi_cs   *cs = spi->controller_state;
 642         unsigned int            count, c;
 643         u32                     l;
 644         void __iomem            *base = cs->base;
 645         void __iomem            *tx_reg;
 646         void __iomem            *rx_reg;
 647         void __iomem            *chstat_reg;
 648         int                     word_len;
 649
 650         mcspi = spi_master_get_devdata(spi->master);
 651         count = xfer->len;
 652         c = count;
 653         word_len = cs->word_len;
 654
 655         l = mcspi_cached_chconf0(spi);
 656
 657         /* We store the pre-calculated register addresses on stack to speed
 658          * up the transfer loop. */
 659         tx_reg          = base + OMAP2_MCSPI_TX0;
 660         rx_reg          = base + OMAP2_MCSPI_RX0;
 661         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 662
 663         if (c < (word_len>>3))
 664                 return 0;
 665
 666         if (word_len <= 8) {
 667                 u8              *rx;
 668                 const u8        *tx;
 669
 670                 rx = xfer->rx_buf;
 671                 tx = xfer->tx_buf;
 672
 673                 do {
 674                         c -= 1;
 675                         if (tx != NULL) {
 676                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 677                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 678                                         dev_err(&spi->dev, "TXS timed out\n");
 679                                         goto out;
 680                                 }
 681                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 682                                                 word_len, *tx);
 683                                 writel_relaxed(*tx++, tx_reg);
 684                         }
 685                         if (rx != NULL) {
 686                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 687                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 688                                         dev_err(&spi->dev, "RXS timed out\n");
 689                                         goto out;
 690                                 }
 691
 692                                 if (c == 1 && tx == NULL &&
 693                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 694                                         omap2_mcspi_set_enable(spi, 0);
 695                                         *rx++ = readl_relaxed(rx_reg);
 696                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 697                                                     word_len, *(rx - 1));
 698                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 699                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 700                                                 dev_err(&spi->dev,
 701                                                         "RXS timed out\n");
 702                                                 goto out;
 703                                         }
 704                                         c = 0;
 705                                 } else if (c == 0 && tx == NULL) {
 706                                         omap2_mcspi_set_enable(spi, 0);
 707                                 }
 708
 709                                 *rx++ = readl_relaxed(rx_reg);
 710                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 711                                                 word_len, *(rx - 1));
 712                         }
 713                 } while (c);
 714         } else if (word_len <= 16) {
 715                 u16             *rx;
 716                 const u16       *tx;
 717
 718                 rx = xfer->rx_buf;
 719                 tx = xfer->tx_buf;
 720                 do {
 721                         c -= 2;
 722                         if (tx != NULL) {
 723                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 724                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 725                                         dev_err(&spi->dev, "TXS timed out\n");
 726                                         goto out;
 727                                 }
 728                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 729                                                 word_len, *tx);
 730                                 writel_relaxed(*tx++, tx_reg);
 731                         }
 732                         if (rx != NULL) {
 733                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 734                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 735                                         dev_err(&spi->dev, "RXS timed out\n");
 736                                         goto out;
 737                                 }
 738
 739                                 if (c == 2 && tx == NULL &&
 740                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 741                                         omap2_mcspi_set_enable(spi, 0);
 742                                         *rx++ = readl_relaxed(rx_reg);
 743                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 744                                                     word_len, *(rx - 1));
 745                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 746                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 747                                                 dev_err(&spi->dev,
 748                                                         "RXS timed out\n");
 749                                                 goto out;
 750                                         }
 751                                         c = 0;
 752                                 } else if (c == 0 && tx == NULL) {
 753                                         omap2_mcspi_set_enable(spi, 0);
 754                                 }
 755
 756                                 *rx++ = readl_relaxed(rx_reg);
 757                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 758                                                 word_len, *(rx - 1));
 759                         }
 760                 } while (c >= 2);
 761         } else if (word_len <= 32) {
 762                 u32             *rx;
 763                 const u32       *tx;
 764
 765                 rx = xfer->rx_buf;
 766                 tx = xfer->tx_buf;
 767                 do {
 768                         c -= 4;
 769                         if (tx != NULL) {
 770                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 771                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 772                                         dev_err(&spi->dev, "TXS timed out\n");
 773                                         goto out;
 774                                 }
 775                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 776                                                 word_len, *tx);
 777                                 writel_relaxed(*tx++, tx_reg);
 778                         }
 779                         if (rx != NULL) {
 780                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 781                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 782                                         dev_err(&spi->dev, "RXS timed out\n");
 783                                         goto out;
 784                                 }
 785
 786                                 if (c == 4 && tx == NULL &&
 787                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 788                                         omap2_mcspi_set_enable(spi, 0);
 789                                         *rx++ = readl_relaxed(rx_reg);
 790                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 791                                                     word_len, *(rx - 1));
 792                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 793                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 794                                                 dev_err(&spi->dev,
 795                                                         "RXS timed out\n");
 796                                                 goto out;
 797                                         }
 798                                         c = 0;
 799                                 } else if (c == 0 && tx == NULL) {
 800                                         omap2_mcspi_set_enable(spi, 0);
 801                                 }
 802
 803                                 *rx++ = readl_relaxed(rx_reg);
 804                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 805                                                 word_len, *(rx - 1));
 806                         }
 807                 } while (c >= 4);
 808         }
 809
 810         /* for TX_ONLY mode, be sure all words have shifted out */
 811         if (xfer->rx_buf == NULL) {
 812                 if (mcspi_wait_for_reg_bit(chstat_reg,
 813                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 814                         dev_err(&spi->dev, "TXS timed out\n");
 815                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 816                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 817                         dev_err(&spi->dev, "EOT timed out\n");
 818
 819                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 820                  * otherwise these rx datas will affect the direct following
 821                  * RX_ONLY transfer.
 822                  */
 823                 omap2_mcspi_set_enable(spi, 0);
 824         }
 825 out:
 826         omap2_mcspi_set_enable(spi, 1);
 827         return count - c;
 828 }
 829
 830 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 831 {
 832         u32 div;
 833
 834         for (div = 0; div < 15; div++)
 835                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 836                         return div;
 837
 838         return 15;
 839 }
 840
 841 /* called only when no transfer is active to this device */
 842 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 843                 struct spi_transfer *t)
 844 {
 845         struct omap2_mcspi_cs *cs = spi->controller_state;
 846         struct omap2_mcspi *mcspi;
 847         struct spi_master *spi_cntrl;
 848         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
 849         u8 word_len = spi->bits_per_word;
 850         u32 speed_hz = spi->max_speed_hz;
 851
 852         mcspi = spi_master_get_devdata(spi->master);
 853         spi_cntrl = mcspi->master;
 854
 855         if (t != NULL && t->bits_per_word)
 856                 word_len = t->bits_per_word;
 857
 858         cs->word_len = word_len;
 859
 860         if (t && t->speed_hz)
 861                 speed_hz = t->speed_hz;
 862
 863         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 864         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
 865                 clkd = omap2_mcspi_calc_divisor(speed_hz);
 866                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
 867                 clkg = 0;
 868         } else {
 869                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
 870                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
 871                 clkd = (div - 1) & 0xf;
 872                 extclk = (div - 1) >> 4;
 873                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
 874         }
 875
 876         l = mcspi_cached_chconf0(spi);
 877
 878         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 879          * REVISIT: this controller could support SPI_3WIRE mode.
 880          */
 881         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 882                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 883                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 884                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 885         } else {
 886                 l |= OMAP2_MCSPI_CHCONF_IS;
 887                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 888                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 889         }
 890
 891         /* wordlength */
 892         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 893         l |= (word_len - 1) << 7;
 894
 895         /* set chipselect polarity; manage with FORCE */
 896         if (!(spi->mode & SPI_CS_HIGH))
 897                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 898         else
 899                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 900
 901         /* set clock divisor */
 902         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 903         l |= clkd << 2;
 904
 905         /* set clock granularity */
 906         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
 907         l |= clkg;
 908         if (clkg) {
 909                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
 910                 cs->chctrl0 |= extclk << 8;
 911                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
 912         }
 913
 914         /* set SPI mode 0..3 */
 915         if (spi->mode & SPI_CPOL)
 916                 l |= OMAP2_MCSPI_CHCONF_POL;
 917         else
 918                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 919         if (spi->mode & SPI_CPHA)
 920                 l |= OMAP2_MCSPI_CHCONF_PHA;
 921         else
 922                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 923
 924         mcspi_write_chconf0(spi, l);
 925
 926         cs->mode = spi->mode;
 927
 928         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 929                         speed_hz,
 930                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 931                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 932
 933         return 0;
 934 }
 935
 936 /*
 937  * Note that we currently allow DMA only if we get a channel
 938  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 939  */
 940 static int omap2_mcspi_request_dma(struct spi_device *spi)
 941 {
 942         struct spi_master       *master = spi->master;
 943         struct omap2_mcspi      *mcspi;
 944         struct omap2_mcspi_dma  *mcspi_dma;
 945         dma_cap_mask_t mask;
 946         unsigned sig;
 947
 948         mcspi = spi_master_get_devdata(master);
 949         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 950
 951         init_completion(&mcspi_dma->dma_rx_completion);
 952         init_completion(&mcspi_dma->dma_tx_completion);
 953
 954         dma_cap_zero(mask);
 955         dma_cap_set(DMA_SLAVE, mask);
 956         sig = mcspi_dma->dma_rx_sync_dev;
 957
 958         mcspi_dma->dma_rx =
 959                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 960                                                  &sig, &master->dev,
 961                                                  mcspi_dma->dma_rx_ch_name);
 962         if (!mcspi_dma->dma_rx)
 963                 goto no_dma;
 964
 965         sig = mcspi_dma->dma_tx_sync_dev;
 966         mcspi_dma->dma_tx =
 967                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
 968                                                  &sig, &master->dev,
 969                                                  mcspi_dma->dma_tx_ch_name);
 970
 971         if (!mcspi_dma->dma_tx) {
 972                 dma_release_channel(mcspi_dma->dma_rx);
 973                 mcspi_dma->dma_rx = NULL;
 974                 goto no_dma;
 975         }
 976
 977         return 0;
 978
 979 no_dma:
 980         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 981         return -EAGAIN;
 982 }
 983
 984 static int omap2_mcspi_setup(struct spi_device *spi)
 985 {
 986         int                     ret;
 987         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 988         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 989         struct omap2_mcspi_dma  *mcspi_dma;
 990         struct omap2_mcspi_cs   *cs = spi->controller_state;
 991
 992         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 993
 994         if (!cs) {
 995                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 996                 if (!cs)
 997                         return -ENOMEM;
 998                 cs->base = mcspi->base + spi->chip_select * 0x14;
 999                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1000                 cs->mode = 0;
1001                 cs->chconf0 = 0;
1002                 cs->chctrl0 = 0;
1003                 spi->controller_state = cs;
1004                 /* Link this to context save list */
1005                 list_add_tail(&cs->node, &ctx->cs);
1006         }
1007
1008         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1009                 ret = omap2_mcspi_request_dma(spi);
1010                 if (ret < 0 && ret != -EAGAIN)
1011                         return ret;
1012         }
1013
1014         ret = pm_runtime_get_sync(mcspi->dev);
1015         if (ret < 0)
1016                 return ret;
1017
1018         ret = omap2_mcspi_setup_transfer(spi, NULL);
1019         pm_runtime_mark_last_busy(mcspi->dev);
1020         pm_runtime_put_autosuspend(mcspi->dev);
1021
1022         return ret;
1023 }
1024
1025 static void omap2_mcspi_cleanup(struct spi_device *spi)
1026 {
1027         struct omap2_mcspi      *mcspi;
1028         struct omap2_mcspi_dma  *mcspi_dma;
1029         struct omap2_mcspi_cs   *cs;
1030
1031         mcspi = spi_master_get_devdata(spi->master);
1032
1033         if (spi->controller_state) {
1034                 /* Unlink controller state from context save list */
1035                 cs = spi->controller_state;
1036                 list_del(&cs->node);
1037
1038                 kfree(cs);
1039         }
1040
1041         if (spi->chip_select < spi->master->num_chipselect) {
1042                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1043
1044                 if (mcspi_dma->dma_rx) {
1045                         dma_release_channel(mcspi_dma->dma_rx);
1046                         mcspi_dma->dma_rx = NULL;
1047                 }
1048                 if (mcspi_dma->dma_tx) {
1049                         dma_release_channel(mcspi_dma->dma_tx);
1050                         mcspi_dma->dma_tx = NULL;
1051                 }
1052         }
1053 }
1054
1055 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1056 {
1057
1058         /* We only enable one channel at a time -- the one whose message is
1059          * -- although this controller would gladly
1060          * arbitrate among multiple channels.  This corresponds to "single
1061          * channel" master mode.  As a side effect, we need to manage the
1062          * chipselect with the FORCE bit ... CS != channel enable.
1063          */
1064
1065         struct spi_device               *spi;
1066         struct spi_transfer             *t = NULL;
1067         struct spi_master               *master;
1068         struct omap2_mcspi_dma          *mcspi_dma;
1069         int                             cs_active = 0;
1070         struct omap2_mcspi_cs           *cs;
1071         struct omap2_mcspi_device_config *cd;
1072         int                             par_override = 0;
1073         int                             status = 0;
1074         u32                             chconf;
1075
1076         spi = m->spi;
1077         master = spi->master;
1078         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1079         cs = spi->controller_state;
1080         cd = spi->controller_data;
1081
1082         /*
1083          * The slave driver could have changed spi->mode in which case
1084          * it will be different from cs->mode (the current hardware setup).
1085          * If so, set par_override (even though its not a parity issue) so
1086          * omap2_mcspi_setup_transfer will be called to configure the hardware
1087          * with the correct mode on the first iteration of the loop below.
1088          */
1089         if (spi->mode != cs->mode)
1090                 par_override = 1;
1091
1092         omap2_mcspi_set_enable(spi, 0);
1093         list_for_each_entry(t, &m->transfers, transfer_list) {
1094                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1095                         status = -EINVAL;
1096                         break;
1097                 }
1098                 if (par_override ||
1099                     (t->speed_hz != spi->max_speed_hz) ||
1100                     (t->bits_per_word != spi->bits_per_word)) {
1101                         par_override = 1;
1102                         status = omap2_mcspi_setup_transfer(spi, t);
1103                         if (status < 0)
1104                                 break;
1105                         if (t->speed_hz == spi->max_speed_hz &&
1106                             t->bits_per_word == spi->bits_per_word)
1107                                 par_override = 0;
1108                 }
1109                 if (cd && cd->cs_per_word) {
1110                         chconf = mcspi->ctx.modulctrl;
1111                         chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1112                         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1113                         mcspi->ctx.modulctrl =
1114                                 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1115                 }
1116
1117
1118                 if (!cs_active) {
1119                         omap2_mcspi_force_cs(spi, 1);
1120                         cs_active = 1;
1121                 }
1122
1123                 chconf = mcspi_cached_chconf0(spi);
1124                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1125                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1126
1127                 if (t->tx_buf == NULL)
1128                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1129                 else if (t->rx_buf == NULL)
1130                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1131
1132                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1133                         /* Turbo mode is for more than one word */
1134                         if (t->len > ((cs->word_len + 7) >> 3))
1135                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1136                 }
1137
1138                 mcspi_write_chconf0(spi, chconf);
1139
1140                 if (t->len) {
1141                         unsigned        count;
1142
1143                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1144                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1145                                 omap2_mcspi_set_fifo(spi, t, 1);
1146
1147                         omap2_mcspi_set_enable(spi, 1);
1148
1149                         /* RX_ONLY mode needs dummy data in TX reg */
1150                         if (t->tx_buf == NULL)
1151                                 writel_relaxed(0, cs->base
1152                                                 + OMAP2_MCSPI_TX0);
1153
1154                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1155                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1156                                 count = omap2_mcspi_txrx_dma(spi, t);
1157                         else
1158                                 count = omap2_mcspi_txrx_pio(spi, t);
1159                         m->actual_length += count;
1160
1161                         if (count != t->len) {
1162                                 status = -EIO;
1163                                 break;
1164                         }
1165                 }
1166
1167                 if (t->delay_usecs)
1168                         udelay(t->delay_usecs);
1169
1170                 /* ignore the "leave it on after last xfer" hint */
1171                 if (t->cs_change) {
1172                         omap2_mcspi_force_cs(spi, 0);
1173                         cs_active = 0;
1174                 }
1175
1176                 omap2_mcspi_set_enable(spi, 0);
1177
1178                 if (mcspi->fifo_depth > 0)
1179                         omap2_mcspi_set_fifo(spi, t, 0);
1180         }
1181         /* Restore defaults if they were overriden */
1182         if (par_override) {
1183                 par_override = 0;
1184                 status = omap2_mcspi_setup_transfer(spi, NULL);
1185         }
1186
1187         if (cs_active)
1188                 omap2_mcspi_force_cs(spi, 0);
1189
1190         if (cd && cd->cs_per_word) {
1191                 chconf = mcspi->ctx.modulctrl;
1192                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1193                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1194                 mcspi->ctx.modulctrl =
1195                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1196         }
1197
1198         omap2_mcspi_set_enable(spi, 0);
1199
1200         if (mcspi->fifo_depth > 0 && t)
1201                 omap2_mcspi_set_fifo(spi, t, 0);
1202
1203         m->status = status;
1204 }
1205
1206 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1207                 struct spi_message *m)
1208 {
1209         struct spi_device       *spi;
1210         struct omap2_mcspi      *mcspi;
1211         struct omap2_mcspi_dma  *mcspi_dma;
1212         struct spi_transfer     *t;
1213         int status;
1214
1215         spi = m->spi;
1216         mcspi = spi_master_get_devdata(master);
1217         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1218         m->actual_length = 0;
1219         m->status = 0;
1220
1221         list_for_each_entry(t, &m->transfers, transfer_list) {
1222                 const void      *tx_buf = t->tx_buf;
1223                 void            *rx_buf = t->rx_buf;
1224                 unsigned        len = t->len;
1225
1226                 if ((len && !(rx_buf || tx_buf))) {
1227                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1228                                         t->speed_hz,
1229                                         len,
1230                                         tx_buf ? "tx" : "",
1231                                         rx_buf ? "rx" : "",
1232                                         t->bits_per_word);
1233                         status = -EINVAL;
1234                         goto out;
1235                 }
1236
1237                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1238                         continue;
1239
1240                 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1241                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1242                                         len, DMA_TO_DEVICE);
1243                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1244                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1245                                                 'T', len);
1246                                 status = -EINVAL;
1247                                 goto out;
1248                         }
1249                 }
1250                 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1251                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1252                                         DMA_FROM_DEVICE);
1253                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1254                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1255                                                 'R', len);
1256                                 if (tx_buf != NULL)
1257                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1258                                                         len, DMA_TO_DEVICE);
1259                                 status = -EINVAL;
1260                                 goto out;
1261                         }
1262                 }
1263         }
1264
1265         omap2_mcspi_work(mcspi, m);
1266         /* spi_finalize_current_message() changes the status inside the
1267          * spi_message, save the status here. */
1268         status = m->status;
1269 out:
1270         spi_finalize_current_message(master);
1271         return status;
1272 }
1273
1274 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1275 {
1276         struct spi_master       *master = mcspi->master;
1277         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1278         int                     ret = 0;
1279
1280         ret = pm_runtime_get_sync(mcspi->dev);
1281         if (ret < 0)
1282                 return ret;
1283
1284         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1285                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1286         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1287
1288         omap2_mcspi_set_master_mode(master);
1289         pm_runtime_mark_last_busy(mcspi->dev);
1290         pm_runtime_put_autosuspend(mcspi->dev);
1291         return 0;
1292 }
1293
1294 static int omap_mcspi_runtime_resume(struct device *dev)
1295 {
1296         struct omap2_mcspi      *mcspi;
1297         struct spi_master       *master;
1298
1299         master = dev_get_drvdata(dev);
1300         mcspi = spi_master_get_devdata(master);
1301         omap2_mcspi_restore_ctx(mcspi);
1302
1303         return 0;
1304 }
1305
1306 static struct omap2_mcspi_platform_config omap2_pdata = {
1307         .regs_offset = 0,
1308 };
1309
1310 static struct omap2_mcspi_platform_config omap4_pdata = {
1311         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1312 };
1313
1314 static const struct of_device_id omap_mcspi_of_match[] = {
1315         {
1316                 .compatible = "ti,omap2-mcspi",
1317                 .data = &omap2_pdata,
1318         },
1319         {
1320                 .compatible = "ti,omap4-mcspi",
1321                 .data = &omap4_pdata,
1322         },
1323         { },
1324 };
1325 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1326
1327 static int omap2_mcspi_probe(struct platform_device *pdev)
1328 {
1329         struct spi_master       *master;
1330         const struct omap2_mcspi_platform_config *pdata;
1331         struct omap2_mcspi      *mcspi;
1332         struct resource         *r;
1333         int                     status = 0, i;
1334         u32                     regs_offset = 0;
1335         static int              bus_num = 1;
1336         struct device_node      *node = pdev->dev.of_node;
1337         const struct of_device_id *match;
1338
1339         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1340         if (master == NULL) {
1341                 dev_dbg(&pdev->dev, "master allocation failed\n");
1342                 return -ENOMEM;
1343         }
1344
1345         /* the spi->mode bits understood by this driver: */
1346         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1347         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1348         master->setup = omap2_mcspi_setup;
1349         master->auto_runtime_pm = true;
1350         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1351         master->cleanup = omap2_mcspi_cleanup;
1352         master->dev.of_node = node;
1353         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1354         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1355
1356         platform_set_drvdata(pdev, master);
1357
1358         mcspi = spi_master_get_devdata(master);
1359         mcspi->master = master;
1360
1361         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1362         if (match) {
1363                 u32 num_cs = 1; /* default number of chipselect */
1364                 pdata = match->data;
1365
1366                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1367                 master->num_chipselect = num_cs;
1368                 master->bus_num = bus_num++;
1369                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1370                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1371         } else {
1372                 pdata = dev_get_platdata(&pdev->dev);
1373                 master->num_chipselect = pdata->num_cs;
1374                 if (pdev->id != -1)
1375                         master->bus_num = pdev->id;
1376                 mcspi->pin_dir = pdata->pin_dir;
1377         }
1378         regs_offset = pdata->regs_offset;
1379
1380         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1381         if (r == NULL) {
1382                 status = -ENODEV;
1383                 goto free_master;
1384         }
1385
1386         r->start += regs_offset;
1387         r->end += regs_offset;
1388         mcspi->phys = r->start;
1389
1390         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1391         if (IS_ERR(mcspi->base)) {
1392                 status = PTR_ERR(mcspi->base);
1393                 goto free_master;
1394         }
1395
1396         mcspi->dev = &pdev->dev;
1397
1398         INIT_LIST_HEAD(&mcspi->ctx.cs);
1399
1400         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1401                                            sizeof(struct omap2_mcspi_dma),
1402                                            GFP_KERNEL);
1403         if (mcspi->dma_channels == NULL) {
1404                 status = -ENOMEM;
1405                 goto free_master;
1406         }
1407
1408         for (i = 0; i < master->num_chipselect; i++) {
1409                 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1410                 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1411                 struct resource *dma_res;
1412
1413                 sprintf(dma_rx_ch_name, "rx%d", i);
1414                 if (!pdev->dev.of_node) {
1415                         dma_res =
1416                                 platform_get_resource_byname(pdev,
1417                                                              IORESOURCE_DMA,
1418                                                              dma_rx_ch_name);
1419                         if (!dma_res) {
1420                                 dev_dbg(&pdev->dev,
1421                                         "cannot get DMA RX channel\n");
1422                                 status = -ENODEV;
1423                                 break;
1424                         }
1425
1426                         mcspi->dma_channels[i].dma_rx_sync_dev =
1427                                 dma_res->start;
1428                 }
1429                 sprintf(dma_tx_ch_name, "tx%d", i);
1430                 if (!pdev->dev.of_node) {
1431                         dma_res =
1432                                 platform_get_resource_byname(pdev,
1433                                                              IORESOURCE_DMA,
1434                                                              dma_tx_ch_name);
1435                         if (!dma_res) {
1436                                 dev_dbg(&pdev->dev,
1437                                         "cannot get DMA TX channel\n");
1438                                 status = -ENODEV;
1439                                 break;
1440                         }
1441
1442                         mcspi->dma_channels[i].dma_tx_sync_dev =
1443                                 dma_res->start;
1444                 }
1445         }
1446
1447         if (status < 0)
1448                 goto free_master;
1449
1450         pm_runtime_use_autosuspend(&pdev->dev);
1451         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1452         pm_runtime_enable(&pdev->dev);
1453
1454         status = omap2_mcspi_master_setup(mcspi);
1455         if (status < 0)
1456                 goto disable_pm;
1457
1458         status = devm_spi_register_master(&pdev->dev, master);
1459         if (status < 0)
1460                 goto disable_pm;
1461
1462         return status;
1463
1464 disable_pm:
1465         pm_runtime_disable(&pdev->dev);
1466 free_master:
1467         spi_master_put(master);
1468         return status;
1469 }
1470
1471 static int omap2_mcspi_remove(struct platform_device *pdev)
1472 {
1473         struct spi_master *master = platform_get_drvdata(pdev);
1474         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1475
1476         pm_runtime_put_sync(mcspi->dev);
1477         pm_runtime_disable(&pdev->dev);
1478
1479         return 0;
1480 }
1481
1482 /* work with hotplug and coldplug */
1483 MODULE_ALIAS("platform:omap2_mcspi");
1484
1485 #ifdef  CONFIG_SUSPEND
1486 /*
1487  * When SPI wake up from off-mode, CS is in activate state. If it was in
1488  * unactive state when driver was suspend, then force it to unactive state at
1489  * wake up.
1490  */
1491 static int omap2_mcspi_resume(struct device *dev)
1492 {
1493         struct spi_master       *master = dev_get_drvdata(dev);
1494         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1495         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1496         struct omap2_mcspi_cs   *cs;
1497
1498         pm_runtime_get_sync(mcspi->dev);
1499         list_for_each_entry(cs, &ctx->cs, node) {
1500                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1501                         /*
1502                          * We need to toggle CS state for OMAP take this
1503                          * change in account.
1504                          */
1505                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1506                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1507                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1508                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1509                 }
1510         }
1511         pm_runtime_mark_last_busy(mcspi->dev);
1512         pm_runtime_put_autosuspend(mcspi->dev);
1513         return 0;
1514 }
1515 #else
1516 #define omap2_mcspi_resume      NULL
1517 #endif
1518
1519 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1520         .resume = omap2_mcspi_resume,
1521         .runtime_resume = omap_mcspi_runtime_resume,
1522 };
1523
1524 static struct platform_driver omap2_mcspi_driver = {
1525         .driver = {
1526                 .name =         "omap2_mcspi",
1527                 .pm =           &omap2_mcspi_pm_ops,
1528                 .of_match_table = omap_mcspi_of_match,
1529         },
1530         .probe =        omap2_mcspi_probe,
1531         .remove =       omap2_mcspi_remove,
1532 };
1533
1534 module_platform_driver(omap2_mcspi_driver);
1535 MODULE_LICENSE("GPL");