spi: omap: Allocate bus number from spi framework
[sfrench/cifs-2.6.git] / drivers / spi / spi-omap2-mcspi.c
1 /*
2  * OMAP2 McSPI controller driver
3  *
4  * Copyright (C) 2005, 2006 Nokia Corporation
5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/slab.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/gcd.h>
36
37 #include <linux/spi/spi.h>
38 #include <linux/gpio.h>
39
40 #include <linux/platform_data/spi-omap2-mcspi.h>
41
42 #define OMAP2_MCSPI_MAX_FREQ            48000000
43 #define OMAP2_MCSPI_MAX_DIVIDER         4096
44 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
45 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
46 #define SPI_AUTOSUSPEND_TIMEOUT         2000
47
48 #define OMAP2_MCSPI_REVISION            0x00
49 #define OMAP2_MCSPI_SYSSTATUS           0x14
50 #define OMAP2_MCSPI_IRQSTATUS           0x18
51 #define OMAP2_MCSPI_IRQENABLE           0x1c
52 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
53 #define OMAP2_MCSPI_SYST                0x24
54 #define OMAP2_MCSPI_MODULCTRL           0x28
55 #define OMAP2_MCSPI_XFERLEVEL           0x7c
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0             0x2c
59 #define OMAP2_MCSPI_CHSTAT0             0x30
60 #define OMAP2_MCSPI_CHCTRL0             0x34
61 #define OMAP2_MCSPI_TX0                 0x38
62 #define OMAP2_MCSPI_RX0                 0x3c
63
64 /* per-register bitmasks: */
65 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
86 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
87 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
88 #define OMAP2_MCSPI_CHCONF_CLKG         BIT(29)
89
90 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
91 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
92 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
93 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
94
95 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
97
98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
99
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma {
102         struct dma_chan *dma_tx;
103         struct dma_chan *dma_rx;
104
105         struct completion dma_tx_completion;
106         struct completion dma_rx_completion;
107
108         char dma_rx_ch_name[14];
109         char dma_tx_ch_name[14];
110 };
111
112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113  * cache operations; better heuristics consider wordsize and bitrate.
114  */
115 #define DMA_MIN_BYTES                   160
116
117
118 /*
119  * Used for context save and restore, structure members to be updated whenever
120  * corresponding registers are modified.
121  */
122 struct omap2_mcspi_regs {
123         u32 modulctrl;
124         u32 wakeupenable;
125         struct list_head cs;
126 };
127
128 struct omap2_mcspi {
129         struct spi_master       *master;
130         /* Virtual base address of the controller */
131         void __iomem            *base;
132         unsigned long           phys;
133         /* SPI1 has 4 channels, while SPI2 has 2 */
134         struct omap2_mcspi_dma  *dma_channels;
135         struct device           *dev;
136         struct omap2_mcspi_regs ctx;
137         int                     fifo_depth;
138         unsigned int            pin_dir:1;
139 };
140
141 struct omap2_mcspi_cs {
142         void __iomem            *base;
143         unsigned long           phys;
144         int                     word_len;
145         u16                     mode;
146         struct list_head        node;
147         /* Context save and restore shadow register */
148         u32                     chconf0, chctrl0;
149 };
150
151 static inline void mcspi_write_reg(struct spi_master *master,
152                 int idx, u32 val)
153 {
154         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156         writel_relaxed(val, mcspi->base + idx);
157 }
158
159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
160 {
161         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
162
163         return readl_relaxed(mcspi->base + idx);
164 }
165
166 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
167                 int idx, u32 val)
168 {
169         struct omap2_mcspi_cs   *cs = spi->controller_state;
170
171         writel_relaxed(val, cs->base +  idx);
172 }
173
174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
175 {
176         struct omap2_mcspi_cs   *cs = spi->controller_state;
177
178         return readl_relaxed(cs->base + idx);
179 }
180
181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
182 {
183         struct omap2_mcspi_cs *cs = spi->controller_state;
184
185         return cs->chconf0;
186 }
187
188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
189 {
190         struct omap2_mcspi_cs *cs = spi->controller_state;
191
192         cs->chconf0 = val;
193         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
194         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
195 }
196
197 static inline int mcspi_bytes_per_word(int word_len)
198 {
199         if (word_len <= 8)
200                 return 1;
201         else if (word_len <= 16)
202                 return 2;
203         else /* word_len <= 32 */
204                 return 4;
205 }
206
207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
208                 int is_read, int enable)
209 {
210         u32 l, rw;
211
212         l = mcspi_cached_chconf0(spi);
213
214         if (is_read) /* 1 is read, 0 write */
215                 rw = OMAP2_MCSPI_CHCONF_DMAR;
216         else
217                 rw = OMAP2_MCSPI_CHCONF_DMAW;
218
219         if (enable)
220                 l |= rw;
221         else
222                 l &= ~rw;
223
224         mcspi_write_chconf0(spi, l);
225 }
226
227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
228 {
229         struct omap2_mcspi_cs *cs = spi->controller_state;
230         u32 l;
231
232         l = cs->chctrl0;
233         if (enable)
234                 l |= OMAP2_MCSPI_CHCTRL_EN;
235         else
236                 l &= ~OMAP2_MCSPI_CHCTRL_EN;
237         cs->chctrl0 = l;
238         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
239         /* Flash post-writes */
240         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
241 }
242
243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
244 {
245         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
246         u32 l;
247
248         /* The controller handles the inverted chip selects
249          * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250          * the inversion from the core spi_set_cs function.
251          */
252         if (spi->mode & SPI_CS_HIGH)
253                 enable = !enable;
254
255         if (spi->controller_state) {
256                 int err = pm_runtime_get_sync(mcspi->dev);
257                 if (err < 0) {
258                         dev_err(mcspi->dev, "failed to get sync: %d\n", err);
259                         return;
260                 }
261
262                 l = mcspi_cached_chconf0(spi);
263
264                 if (enable)
265                         l &= ~OMAP2_MCSPI_CHCONF_FORCE;
266                 else
267                         l |= OMAP2_MCSPI_CHCONF_FORCE;
268
269                 mcspi_write_chconf0(spi, l);
270
271                 pm_runtime_mark_last_busy(mcspi->dev);
272                 pm_runtime_put_autosuspend(mcspi->dev);
273         }
274 }
275
276 static void omap2_mcspi_set_master_mode(struct spi_master *master)
277 {
278         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
279         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
280         u32 l;
281
282         /*
283          * Setup when switching from (reset default) slave mode
284          * to single-channel master mode
285          */
286         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
287         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
288         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
289         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
290
291         ctx->modulctrl = l;
292 }
293
294 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
295                                 struct spi_transfer *t, int enable)
296 {
297         struct spi_master *master = spi->master;
298         struct omap2_mcspi_cs *cs = spi->controller_state;
299         struct omap2_mcspi *mcspi;
300         unsigned int wcnt;
301         int max_fifo_depth, fifo_depth, bytes_per_word;
302         u32 chconf, xferlevel;
303
304         mcspi = spi_master_get_devdata(master);
305
306         chconf = mcspi_cached_chconf0(spi);
307         if (enable) {
308                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
309                 if (t->len % bytes_per_word != 0)
310                         goto disable_fifo;
311
312                 if (t->rx_buf != NULL && t->tx_buf != NULL)
313                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
314                 else
315                         max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
316
317                 fifo_depth = gcd(t->len, max_fifo_depth);
318                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
319                         goto disable_fifo;
320
321                 wcnt = t->len / bytes_per_word;
322                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
323                         goto disable_fifo;
324
325                 xferlevel = wcnt << 16;
326                 if (t->rx_buf != NULL) {
327                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
328                         xferlevel |= (fifo_depth - 1) << 8;
329                 }
330                 if (t->tx_buf != NULL) {
331                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
332                         xferlevel |= fifo_depth - 1;
333                 }
334
335                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
336                 mcspi_write_chconf0(spi, chconf);
337                 mcspi->fifo_depth = fifo_depth;
338
339                 return;
340         }
341
342 disable_fifo:
343         if (t->rx_buf != NULL)
344                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
345
346         if (t->tx_buf != NULL)
347                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
348
349         mcspi_write_chconf0(spi, chconf);
350         mcspi->fifo_depth = 0;
351 }
352
353 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
354 {
355         struct spi_master       *spi_cntrl = mcspi->master;
356         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
357         struct omap2_mcspi_cs   *cs;
358
359         /* McSPI: context restore */
360         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
361         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
362
363         list_for_each_entry(cs, &ctx->cs, node)
364                 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
365 }
366
367 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
368 {
369         unsigned long timeout;
370
371         timeout = jiffies + msecs_to_jiffies(1000);
372         while (!(readl_relaxed(reg) & bit)) {
373                 if (time_after(jiffies, timeout)) {
374                         if (!(readl_relaxed(reg) & bit))
375                                 return -ETIMEDOUT;
376                         else
377                                 return 0;
378                 }
379                 cpu_relax();
380         }
381         return 0;
382 }
383
384 static void omap2_mcspi_rx_callback(void *data)
385 {
386         struct spi_device *spi = data;
387         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
388         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
389
390         /* We must disable the DMA RX request */
391         omap2_mcspi_set_dma_req(spi, 1, 0);
392
393         complete(&mcspi_dma->dma_rx_completion);
394 }
395
396 static void omap2_mcspi_tx_callback(void *data)
397 {
398         struct spi_device *spi = data;
399         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
400         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
401
402         /* We must disable the DMA TX request */
403         omap2_mcspi_set_dma_req(spi, 0, 0);
404
405         complete(&mcspi_dma->dma_tx_completion);
406 }
407
408 static void omap2_mcspi_tx_dma(struct spi_device *spi,
409                                 struct spi_transfer *xfer,
410                                 struct dma_slave_config cfg)
411 {
412         struct omap2_mcspi      *mcspi;
413         struct omap2_mcspi_dma  *mcspi_dma;
414         unsigned int            count;
415
416         mcspi = spi_master_get_devdata(spi->master);
417         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
418         count = xfer->len;
419
420         if (mcspi_dma->dma_tx) {
421                 struct dma_async_tx_descriptor *tx;
422
423                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
424
425                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
426                                              xfer->tx_sg.nents,
427                                              DMA_MEM_TO_DEV,
428                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
429                 if (tx) {
430                         tx->callback = omap2_mcspi_tx_callback;
431                         tx->callback_param = spi;
432                         dmaengine_submit(tx);
433                 } else {
434                         /* FIXME: fall back to PIO? */
435                 }
436         }
437         dma_async_issue_pending(mcspi_dma->dma_tx);
438         omap2_mcspi_set_dma_req(spi, 0, 1);
439
440 }
441
442 static unsigned
443 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
444                                 struct dma_slave_config cfg,
445                                 unsigned es)
446 {
447         struct omap2_mcspi      *mcspi;
448         struct omap2_mcspi_dma  *mcspi_dma;
449         unsigned int            count, transfer_reduction = 0;
450         struct scatterlist      *sg_out[2];
451         int                     nb_sizes = 0, out_mapped_nents[2], ret, x;
452         size_t                  sizes[2];
453         u32                     l;
454         int                     elements = 0;
455         int                     word_len, element_count;
456         struct omap2_mcspi_cs   *cs = spi->controller_state;
457         void __iomem            *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
458
459         mcspi = spi_master_get_devdata(spi->master);
460         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
461         count = xfer->len;
462
463         /*
464          *  In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
465          *  it mentions reducing DMA transfer length by one element in master
466          *  normal mode.
467          */
468         if (mcspi->fifo_depth == 0)
469                 transfer_reduction = es;
470
471         word_len = cs->word_len;
472         l = mcspi_cached_chconf0(spi);
473
474         if (word_len <= 8)
475                 element_count = count;
476         else if (word_len <= 16)
477                 element_count = count >> 1;
478         else /* word_len <= 32 */
479                 element_count = count >> 2;
480
481         if (mcspi_dma->dma_rx) {
482                 struct dma_async_tx_descriptor *tx;
483
484                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
485
486                 /*
487                  *  Reduce DMA transfer length by one more if McSPI is
488                  *  configured in turbo mode.
489                  */
490                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
491                         transfer_reduction += es;
492
493                 if (transfer_reduction) {
494                         /* Split sgl into two. The second sgl won't be used. */
495                         sizes[0] = count - transfer_reduction;
496                         sizes[1] = transfer_reduction;
497                         nb_sizes = 2;
498                 } else {
499                         /*
500                          * Don't bother splitting the sgl. This essentially
501                          * clones the original sgl.
502                          */
503                         sizes[0] = count;
504                         nb_sizes = 1;
505                 }
506
507                 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
508                                0, nb_sizes,
509                                sizes,
510                                sg_out, out_mapped_nents,
511                                GFP_KERNEL);
512
513                 if (ret < 0) {
514                         dev_err(&spi->dev, "sg_split failed\n");
515                         return 0;
516                 }
517
518                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
519                                              sg_out[0],
520                                              out_mapped_nents[0],
521                                              DMA_DEV_TO_MEM,
522                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
523                 if (tx) {
524                         tx->callback = omap2_mcspi_rx_callback;
525                         tx->callback_param = spi;
526                         dmaengine_submit(tx);
527                 } else {
528                                 /* FIXME: fall back to PIO? */
529                 }
530         }
531
532         dma_async_issue_pending(mcspi_dma->dma_rx);
533         omap2_mcspi_set_dma_req(spi, 1, 1);
534
535         wait_for_completion(&mcspi_dma->dma_rx_completion);
536
537         for (x = 0; x < nb_sizes; x++)
538                 kfree(sg_out[x]);
539
540         if (mcspi->fifo_depth > 0)
541                 return count;
542
543         /*
544          *  Due to the DMA transfer length reduction the missing bytes must
545          *  be read manually to receive all of the expected data.
546          */
547         omap2_mcspi_set_enable(spi, 0);
548
549         elements = element_count - 1;
550
551         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
552                 elements--;
553
554                 if (!mcspi_wait_for_reg_bit(chstat_reg,
555                                             OMAP2_MCSPI_CHSTAT_RXS)) {
556                         u32 w;
557
558                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
559                         if (word_len <= 8)
560                                 ((u8 *)xfer->rx_buf)[elements++] = w;
561                         else if (word_len <= 16)
562                                 ((u16 *)xfer->rx_buf)[elements++] = w;
563                         else /* word_len <= 32 */
564                                 ((u32 *)xfer->rx_buf)[elements++] = w;
565                 } else {
566                         int bytes_per_word = mcspi_bytes_per_word(word_len);
567                         dev_err(&spi->dev, "DMA RX penultimate word empty\n");
568                         count -= (bytes_per_word << 1);
569                         omap2_mcspi_set_enable(spi, 1);
570                         return count;
571                 }
572         }
573         if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
574                 u32 w;
575
576                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
577                 if (word_len <= 8)
578                         ((u8 *)xfer->rx_buf)[elements] = w;
579                 else if (word_len <= 16)
580                         ((u16 *)xfer->rx_buf)[elements] = w;
581                 else /* word_len <= 32 */
582                         ((u32 *)xfer->rx_buf)[elements] = w;
583         } else {
584                 dev_err(&spi->dev, "DMA RX last word empty\n");
585                 count -= mcspi_bytes_per_word(word_len);
586         }
587         omap2_mcspi_set_enable(spi, 1);
588         return count;
589 }
590
591 static unsigned
592 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
593 {
594         struct omap2_mcspi      *mcspi;
595         struct omap2_mcspi_cs   *cs = spi->controller_state;
596         struct omap2_mcspi_dma  *mcspi_dma;
597         unsigned int            count;
598         u32                     l;
599         u8                      *rx;
600         const u8                *tx;
601         struct dma_slave_config cfg;
602         enum dma_slave_buswidth width;
603         unsigned es;
604         u32                     burst;
605         void __iomem            *chstat_reg;
606         void __iomem            *irqstat_reg;
607         int                     wait_res;
608
609         mcspi = spi_master_get_devdata(spi->master);
610         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
611         l = mcspi_cached_chconf0(spi);
612
613
614         if (cs->word_len <= 8) {
615                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
616                 es = 1;
617         } else if (cs->word_len <= 16) {
618                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
619                 es = 2;
620         } else {
621                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
622                 es = 4;
623         }
624
625         count = xfer->len;
626         burst = 1;
627
628         if (mcspi->fifo_depth > 0) {
629                 if (count > mcspi->fifo_depth)
630                         burst = mcspi->fifo_depth / es;
631                 else
632                         burst = count / es;
633         }
634
635         memset(&cfg, 0, sizeof(cfg));
636         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
637         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
638         cfg.src_addr_width = width;
639         cfg.dst_addr_width = width;
640         cfg.src_maxburst = burst;
641         cfg.dst_maxburst = burst;
642
643         rx = xfer->rx_buf;
644         tx = xfer->tx_buf;
645
646         if (tx != NULL)
647                 omap2_mcspi_tx_dma(spi, xfer, cfg);
648
649         if (rx != NULL)
650                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
651
652         if (tx != NULL) {
653                 wait_for_completion(&mcspi_dma->dma_tx_completion);
654
655                 if (mcspi->fifo_depth > 0) {
656                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
657
658                         if (mcspi_wait_for_reg_bit(irqstat_reg,
659                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
660                                 dev_err(&spi->dev, "EOW timed out\n");
661
662                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
663                                         OMAP2_MCSPI_IRQSTATUS_EOW);
664                 }
665
666                 /* for TX_ONLY mode, be sure all words have shifted out */
667                 if (rx == NULL) {
668                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
669                         if (mcspi->fifo_depth > 0) {
670                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
671                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
672                                 if (wait_res < 0)
673                                         dev_err(&spi->dev, "TXFFE timed out\n");
674                         } else {
675                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
676                                                 OMAP2_MCSPI_CHSTAT_TXS);
677                                 if (wait_res < 0)
678                                         dev_err(&spi->dev, "TXS timed out\n");
679                         }
680                         if (wait_res >= 0 &&
681                                 (mcspi_wait_for_reg_bit(chstat_reg,
682                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
683                                 dev_err(&spi->dev, "EOT timed out\n");
684                 }
685         }
686         return count;
687 }
688
689 static unsigned
690 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
691 {
692         struct omap2_mcspi      *mcspi;
693         struct omap2_mcspi_cs   *cs = spi->controller_state;
694         unsigned int            count, c;
695         u32                     l;
696         void __iomem            *base = cs->base;
697         void __iomem            *tx_reg;
698         void __iomem            *rx_reg;
699         void __iomem            *chstat_reg;
700         int                     word_len;
701
702         mcspi = spi_master_get_devdata(spi->master);
703         count = xfer->len;
704         c = count;
705         word_len = cs->word_len;
706
707         l = mcspi_cached_chconf0(spi);
708
709         /* We store the pre-calculated register addresses on stack to speed
710          * up the transfer loop. */
711         tx_reg          = base + OMAP2_MCSPI_TX0;
712         rx_reg          = base + OMAP2_MCSPI_RX0;
713         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
714
715         if (c < (word_len>>3))
716                 return 0;
717
718         if (word_len <= 8) {
719                 u8              *rx;
720                 const u8        *tx;
721
722                 rx = xfer->rx_buf;
723                 tx = xfer->tx_buf;
724
725                 do {
726                         c -= 1;
727                         if (tx != NULL) {
728                                 if (mcspi_wait_for_reg_bit(chstat_reg,
729                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
730                                         dev_err(&spi->dev, "TXS timed out\n");
731                                         goto out;
732                                 }
733                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
734                                                 word_len, *tx);
735                                 writel_relaxed(*tx++, tx_reg);
736                         }
737                         if (rx != NULL) {
738                                 if (mcspi_wait_for_reg_bit(chstat_reg,
739                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
740                                         dev_err(&spi->dev, "RXS timed out\n");
741                                         goto out;
742                                 }
743
744                                 if (c == 1 && tx == NULL &&
745                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
746                                         omap2_mcspi_set_enable(spi, 0);
747                                         *rx++ = readl_relaxed(rx_reg);
748                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
749                                                     word_len, *(rx - 1));
750                                         if (mcspi_wait_for_reg_bit(chstat_reg,
751                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
752                                                 dev_err(&spi->dev,
753                                                         "RXS timed out\n");
754                                                 goto out;
755                                         }
756                                         c = 0;
757                                 } else if (c == 0 && tx == NULL) {
758                                         omap2_mcspi_set_enable(spi, 0);
759                                 }
760
761                                 *rx++ = readl_relaxed(rx_reg);
762                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
763                                                 word_len, *(rx - 1));
764                         }
765                 } while (c);
766         } else if (word_len <= 16) {
767                 u16             *rx;
768                 const u16       *tx;
769
770                 rx = xfer->rx_buf;
771                 tx = xfer->tx_buf;
772                 do {
773                         c -= 2;
774                         if (tx != NULL) {
775                                 if (mcspi_wait_for_reg_bit(chstat_reg,
776                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
777                                         dev_err(&spi->dev, "TXS timed out\n");
778                                         goto out;
779                                 }
780                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
781                                                 word_len, *tx);
782                                 writel_relaxed(*tx++, tx_reg);
783                         }
784                         if (rx != NULL) {
785                                 if (mcspi_wait_for_reg_bit(chstat_reg,
786                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
787                                         dev_err(&spi->dev, "RXS timed out\n");
788                                         goto out;
789                                 }
790
791                                 if (c == 2 && tx == NULL &&
792                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
793                                         omap2_mcspi_set_enable(spi, 0);
794                                         *rx++ = readl_relaxed(rx_reg);
795                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
796                                                     word_len, *(rx - 1));
797                                         if (mcspi_wait_for_reg_bit(chstat_reg,
798                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
799                                                 dev_err(&spi->dev,
800                                                         "RXS timed out\n");
801                                                 goto out;
802                                         }
803                                         c = 0;
804                                 } else if (c == 0 && tx == NULL) {
805                                         omap2_mcspi_set_enable(spi, 0);
806                                 }
807
808                                 *rx++ = readl_relaxed(rx_reg);
809                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
810                                                 word_len, *(rx - 1));
811                         }
812                 } while (c >= 2);
813         } else if (word_len <= 32) {
814                 u32             *rx;
815                 const u32       *tx;
816
817                 rx = xfer->rx_buf;
818                 tx = xfer->tx_buf;
819                 do {
820                         c -= 4;
821                         if (tx != NULL) {
822                                 if (mcspi_wait_for_reg_bit(chstat_reg,
823                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
824                                         dev_err(&spi->dev, "TXS timed out\n");
825                                         goto out;
826                                 }
827                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
828                                                 word_len, *tx);
829                                 writel_relaxed(*tx++, tx_reg);
830                         }
831                         if (rx != NULL) {
832                                 if (mcspi_wait_for_reg_bit(chstat_reg,
833                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
834                                         dev_err(&spi->dev, "RXS timed out\n");
835                                         goto out;
836                                 }
837
838                                 if (c == 4 && tx == NULL &&
839                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
840                                         omap2_mcspi_set_enable(spi, 0);
841                                         *rx++ = readl_relaxed(rx_reg);
842                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
843                                                     word_len, *(rx - 1));
844                                         if (mcspi_wait_for_reg_bit(chstat_reg,
845                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
846                                                 dev_err(&spi->dev,
847                                                         "RXS timed out\n");
848                                                 goto out;
849                                         }
850                                         c = 0;
851                                 } else if (c == 0 && tx == NULL) {
852                                         omap2_mcspi_set_enable(spi, 0);
853                                 }
854
855                                 *rx++ = readl_relaxed(rx_reg);
856                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
857                                                 word_len, *(rx - 1));
858                         }
859                 } while (c >= 4);
860         }
861
862         /* for TX_ONLY mode, be sure all words have shifted out */
863         if (xfer->rx_buf == NULL) {
864                 if (mcspi_wait_for_reg_bit(chstat_reg,
865                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
866                         dev_err(&spi->dev, "TXS timed out\n");
867                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
868                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
869                         dev_err(&spi->dev, "EOT timed out\n");
870
871                 /* disable chan to purge rx datas received in TX_ONLY transfer,
872                  * otherwise these rx datas will affect the direct following
873                  * RX_ONLY transfer.
874                  */
875                 omap2_mcspi_set_enable(spi, 0);
876         }
877 out:
878         omap2_mcspi_set_enable(spi, 1);
879         return count - c;
880 }
881
882 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
883 {
884         u32 div;
885
886         for (div = 0; div < 15; div++)
887                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
888                         return div;
889
890         return 15;
891 }
892
893 /* called only when no transfer is active to this device */
894 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
895                 struct spi_transfer *t)
896 {
897         struct omap2_mcspi_cs *cs = spi->controller_state;
898         struct omap2_mcspi *mcspi;
899         struct spi_master *spi_cntrl;
900         u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
901         u8 word_len = spi->bits_per_word;
902         u32 speed_hz = spi->max_speed_hz;
903
904         mcspi = spi_master_get_devdata(spi->master);
905         spi_cntrl = mcspi->master;
906
907         if (t != NULL && t->bits_per_word)
908                 word_len = t->bits_per_word;
909
910         cs->word_len = word_len;
911
912         if (t && t->speed_hz)
913                 speed_hz = t->speed_hz;
914
915         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
916         if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
917                 clkd = omap2_mcspi_calc_divisor(speed_hz);
918                 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
919                 clkg = 0;
920         } else {
921                 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
922                 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
923                 clkd = (div - 1) & 0xf;
924                 extclk = (div - 1) >> 4;
925                 clkg = OMAP2_MCSPI_CHCONF_CLKG;
926         }
927
928         l = mcspi_cached_chconf0(spi);
929
930         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
931          * REVISIT: this controller could support SPI_3WIRE mode.
932          */
933         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
934                 l &= ~OMAP2_MCSPI_CHCONF_IS;
935                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
936                 l |= OMAP2_MCSPI_CHCONF_DPE0;
937         } else {
938                 l |= OMAP2_MCSPI_CHCONF_IS;
939                 l |= OMAP2_MCSPI_CHCONF_DPE1;
940                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
941         }
942
943         /* wordlength */
944         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
945         l |= (word_len - 1) << 7;
946
947         /* set chipselect polarity; manage with FORCE */
948         if (!(spi->mode & SPI_CS_HIGH))
949                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
950         else
951                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
952
953         /* set clock divisor */
954         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
955         l |= clkd << 2;
956
957         /* set clock granularity */
958         l &= ~OMAP2_MCSPI_CHCONF_CLKG;
959         l |= clkg;
960         if (clkg) {
961                 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
962                 cs->chctrl0 |= extclk << 8;
963                 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
964         }
965
966         /* set SPI mode 0..3 */
967         if (spi->mode & SPI_CPOL)
968                 l |= OMAP2_MCSPI_CHCONF_POL;
969         else
970                 l &= ~OMAP2_MCSPI_CHCONF_POL;
971         if (spi->mode & SPI_CPHA)
972                 l |= OMAP2_MCSPI_CHCONF_PHA;
973         else
974                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
975
976         mcspi_write_chconf0(spi, l);
977
978         cs->mode = spi->mode;
979
980         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
981                         speed_hz,
982                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
983                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
984
985         return 0;
986 }
987
988 /*
989  * Note that we currently allow DMA only if we get a channel
990  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
991  */
992 static int omap2_mcspi_request_dma(struct spi_device *spi)
993 {
994         struct spi_master       *master = spi->master;
995         struct omap2_mcspi      *mcspi;
996         struct omap2_mcspi_dma  *mcspi_dma;
997         int ret = 0;
998
999         mcspi = spi_master_get_devdata(master);
1000         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1001
1002         init_completion(&mcspi_dma->dma_rx_completion);
1003         init_completion(&mcspi_dma->dma_tx_completion);
1004
1005         mcspi_dma->dma_rx = dma_request_chan(&master->dev,
1006                                              mcspi_dma->dma_rx_ch_name);
1007         if (IS_ERR(mcspi_dma->dma_rx)) {
1008                 ret = PTR_ERR(mcspi_dma->dma_rx);
1009                 mcspi_dma->dma_rx = NULL;
1010                 goto no_dma;
1011         }
1012
1013         mcspi_dma->dma_tx = dma_request_chan(&master->dev,
1014                                              mcspi_dma->dma_tx_ch_name);
1015         if (IS_ERR(mcspi_dma->dma_tx)) {
1016                 ret = PTR_ERR(mcspi_dma->dma_tx);
1017                 mcspi_dma->dma_tx = NULL;
1018                 dma_release_channel(mcspi_dma->dma_rx);
1019                 mcspi_dma->dma_rx = NULL;
1020         }
1021
1022 no_dma:
1023         return ret;
1024 }
1025
1026 static int omap2_mcspi_setup(struct spi_device *spi)
1027 {
1028         int                     ret;
1029         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
1030         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1031         struct omap2_mcspi_dma  *mcspi_dma;
1032         struct omap2_mcspi_cs   *cs = spi->controller_state;
1033
1034         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1035
1036         if (!cs) {
1037                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1038                 if (!cs)
1039                         return -ENOMEM;
1040                 cs->base = mcspi->base + spi->chip_select * 0x14;
1041                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1042                 cs->mode = 0;
1043                 cs->chconf0 = 0;
1044                 cs->chctrl0 = 0;
1045                 spi->controller_state = cs;
1046                 /* Link this to context save list */
1047                 list_add_tail(&cs->node, &ctx->cs);
1048
1049                 if (gpio_is_valid(spi->cs_gpio)) {
1050                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1051                         if (ret) {
1052                                 dev_err(&spi->dev, "failed to request gpio\n");
1053                                 return ret;
1054                         }
1055                         gpio_direction_output(spi->cs_gpio,
1056                                          !(spi->mode & SPI_CS_HIGH));
1057                 }
1058         }
1059
1060         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1061                 ret = omap2_mcspi_request_dma(spi);
1062                 if (ret)
1063                         dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1064                                  ret);
1065         }
1066
1067         ret = pm_runtime_get_sync(mcspi->dev);
1068         if (ret < 0)
1069                 return ret;
1070
1071         ret = omap2_mcspi_setup_transfer(spi, NULL);
1072         pm_runtime_mark_last_busy(mcspi->dev);
1073         pm_runtime_put_autosuspend(mcspi->dev);
1074
1075         return ret;
1076 }
1077
1078 static void omap2_mcspi_cleanup(struct spi_device *spi)
1079 {
1080         struct omap2_mcspi      *mcspi;
1081         struct omap2_mcspi_dma  *mcspi_dma;
1082         struct omap2_mcspi_cs   *cs;
1083
1084         mcspi = spi_master_get_devdata(spi->master);
1085
1086         if (spi->controller_state) {
1087                 /* Unlink controller state from context save list */
1088                 cs = spi->controller_state;
1089                 list_del(&cs->node);
1090
1091                 kfree(cs);
1092         }
1093
1094         if (spi->chip_select < spi->master->num_chipselect) {
1095                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1096
1097                 if (mcspi_dma->dma_rx) {
1098                         dma_release_channel(mcspi_dma->dma_rx);
1099                         mcspi_dma->dma_rx = NULL;
1100                 }
1101                 if (mcspi_dma->dma_tx) {
1102                         dma_release_channel(mcspi_dma->dma_tx);
1103                         mcspi_dma->dma_tx = NULL;
1104                 }
1105         }
1106
1107         if (gpio_is_valid(spi->cs_gpio))
1108                 gpio_free(spi->cs_gpio);
1109 }
1110
1111 static int omap2_mcspi_transfer_one(struct spi_master *master,
1112                                     struct spi_device *spi,
1113                                     struct spi_transfer *t)
1114 {
1115
1116         /* We only enable one channel at a time -- the one whose message is
1117          * -- although this controller would gladly
1118          * arbitrate among multiple channels.  This corresponds to "single
1119          * channel" master mode.  As a side effect, we need to manage the
1120          * chipselect with the FORCE bit ... CS != channel enable.
1121          */
1122
1123         struct omap2_mcspi              *mcspi;
1124         struct omap2_mcspi_dma          *mcspi_dma;
1125         struct omap2_mcspi_cs           *cs;
1126         struct omap2_mcspi_device_config *cd;
1127         int                             par_override = 0;
1128         int                             status = 0;
1129         u32                             chconf;
1130
1131         mcspi = spi_master_get_devdata(master);
1132         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1133         cs = spi->controller_state;
1134         cd = spi->controller_data;
1135
1136         /*
1137          * The slave driver could have changed spi->mode in which case
1138          * it will be different from cs->mode (the current hardware setup).
1139          * If so, set par_override (even though its not a parity issue) so
1140          * omap2_mcspi_setup_transfer will be called to configure the hardware
1141          * with the correct mode on the first iteration of the loop below.
1142          */
1143         if (spi->mode != cs->mode)
1144                 par_override = 1;
1145
1146         omap2_mcspi_set_enable(spi, 0);
1147
1148         if (gpio_is_valid(spi->cs_gpio))
1149                 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1150
1151         if (par_override ||
1152             (t->speed_hz != spi->max_speed_hz) ||
1153             (t->bits_per_word != spi->bits_per_word)) {
1154                 par_override = 1;
1155                 status = omap2_mcspi_setup_transfer(spi, t);
1156                 if (status < 0)
1157                         goto out;
1158                 if (t->speed_hz == spi->max_speed_hz &&
1159                     t->bits_per_word == spi->bits_per_word)
1160                         par_override = 0;
1161         }
1162         if (cd && cd->cs_per_word) {
1163                 chconf = mcspi->ctx.modulctrl;
1164                 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1165                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1166                 mcspi->ctx.modulctrl =
1167                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1168         }
1169
1170         chconf = mcspi_cached_chconf0(spi);
1171         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1172         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1173
1174         if (t->tx_buf == NULL)
1175                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1176         else if (t->rx_buf == NULL)
1177                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1178
1179         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1180                 /* Turbo mode is for more than one word */
1181                 if (t->len > ((cs->word_len + 7) >> 3))
1182                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1183         }
1184
1185         mcspi_write_chconf0(spi, chconf);
1186
1187         if (t->len) {
1188                 unsigned        count;
1189
1190                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1191                     master->cur_msg_mapped &&
1192                     master->can_dma(master, spi, t))
1193                         omap2_mcspi_set_fifo(spi, t, 1);
1194
1195                 omap2_mcspi_set_enable(spi, 1);
1196
1197                 /* RX_ONLY mode needs dummy data in TX reg */
1198                 if (t->tx_buf == NULL)
1199                         writel_relaxed(0, cs->base
1200                                         + OMAP2_MCSPI_TX0);
1201
1202                 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1203                     master->cur_msg_mapped &&
1204                     master->can_dma(master, spi, t))
1205                         count = omap2_mcspi_txrx_dma(spi, t);
1206                 else
1207                         count = omap2_mcspi_txrx_pio(spi, t);
1208
1209                 if (count != t->len) {
1210                         status = -EIO;
1211                         goto out;
1212                 }
1213         }
1214
1215         omap2_mcspi_set_enable(spi, 0);
1216
1217         if (mcspi->fifo_depth > 0)
1218                 omap2_mcspi_set_fifo(spi, t, 0);
1219
1220 out:
1221         /* Restore defaults if they were overriden */
1222         if (par_override) {
1223                 par_override = 0;
1224                 status = omap2_mcspi_setup_transfer(spi, NULL);
1225         }
1226
1227         if (cd && cd->cs_per_word) {
1228                 chconf = mcspi->ctx.modulctrl;
1229                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1230                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1231                 mcspi->ctx.modulctrl =
1232                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1233         }
1234
1235         omap2_mcspi_set_enable(spi, 0);
1236
1237         if (gpio_is_valid(spi->cs_gpio))
1238                 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1239
1240         if (mcspi->fifo_depth > 0 && t)
1241                 omap2_mcspi_set_fifo(spi, t, 0);
1242
1243         return status;
1244 }
1245
1246 static int omap2_mcspi_prepare_message(struct spi_master *master,
1247                                        struct spi_message *msg)
1248 {
1249         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1250         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1251         struct omap2_mcspi_cs   *cs;
1252
1253         /* Only a single channel can have the FORCE bit enabled
1254          * in its chconf0 register.
1255          * Scan all channels and disable them except the current one.
1256          * A FORCE can remain from a last transfer having cs_change enabled
1257          */
1258         list_for_each_entry(cs, &ctx->cs, node) {
1259                 if (msg->spi->controller_state == cs)
1260                         continue;
1261
1262                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1263                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1264                         writel_relaxed(cs->chconf0,
1265                                         cs->base + OMAP2_MCSPI_CHCONF0);
1266                         readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1267                 }
1268         }
1269
1270         return 0;
1271 }
1272
1273 static bool omap2_mcspi_can_dma(struct spi_master *master,
1274                                 struct spi_device *spi,
1275                                 struct spi_transfer *xfer)
1276 {
1277         return (xfer->len >= DMA_MIN_BYTES);
1278 }
1279
1280 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1281 {
1282         struct spi_master       *master = mcspi->master;
1283         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1284         int                     ret = 0;
1285
1286         ret = pm_runtime_get_sync(mcspi->dev);
1287         if (ret < 0)
1288                 return ret;
1289
1290         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1291                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1292         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1293
1294         omap2_mcspi_set_master_mode(master);
1295         pm_runtime_mark_last_busy(mcspi->dev);
1296         pm_runtime_put_autosuspend(mcspi->dev);
1297         return 0;
1298 }
1299
1300 static int omap_mcspi_runtime_resume(struct device *dev)
1301 {
1302         struct omap2_mcspi      *mcspi;
1303         struct spi_master       *master;
1304
1305         master = dev_get_drvdata(dev);
1306         mcspi = spi_master_get_devdata(master);
1307         omap2_mcspi_restore_ctx(mcspi);
1308
1309         return 0;
1310 }
1311
1312 static struct omap2_mcspi_platform_config omap2_pdata = {
1313         .regs_offset = 0,
1314 };
1315
1316 static struct omap2_mcspi_platform_config omap4_pdata = {
1317         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1318 };
1319
1320 static const struct of_device_id omap_mcspi_of_match[] = {
1321         {
1322                 .compatible = "ti,omap2-mcspi",
1323                 .data = &omap2_pdata,
1324         },
1325         {
1326                 .compatible = "ti,omap4-mcspi",
1327                 .data = &omap4_pdata,
1328         },
1329         { },
1330 };
1331 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1332
1333 static int omap2_mcspi_probe(struct platform_device *pdev)
1334 {
1335         struct spi_master       *master;
1336         const struct omap2_mcspi_platform_config *pdata;
1337         struct omap2_mcspi      *mcspi;
1338         struct resource         *r;
1339         int                     status = 0, i;
1340         u32                     regs_offset = 0;
1341         struct device_node      *node = pdev->dev.of_node;
1342         const struct of_device_id *match;
1343
1344         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1345         if (master == NULL) {
1346                 dev_dbg(&pdev->dev, "master allocation failed\n");
1347                 return -ENOMEM;
1348         }
1349
1350         /* the spi->mode bits understood by this driver: */
1351         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1352         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1353         master->setup = omap2_mcspi_setup;
1354         master->auto_runtime_pm = true;
1355         master->prepare_message = omap2_mcspi_prepare_message;
1356         master->can_dma = omap2_mcspi_can_dma;
1357         master->transfer_one = omap2_mcspi_transfer_one;
1358         master->set_cs = omap2_mcspi_set_cs;
1359         master->cleanup = omap2_mcspi_cleanup;
1360         master->dev.of_node = node;
1361         master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1362         master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1363
1364         platform_set_drvdata(pdev, master);
1365
1366         mcspi = spi_master_get_devdata(master);
1367         mcspi->master = master;
1368
1369         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1370         if (match) {
1371                 u32 num_cs = 1; /* default number of chipselect */
1372                 pdata = match->data;
1373
1374                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1375                 master->num_chipselect = num_cs;
1376                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1377                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1378         } else {
1379                 pdata = dev_get_platdata(&pdev->dev);
1380                 master->num_chipselect = pdata->num_cs;
1381                 mcspi->pin_dir = pdata->pin_dir;
1382         }
1383         regs_offset = pdata->regs_offset;
1384
1385         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1387         if (IS_ERR(mcspi->base)) {
1388                 status = PTR_ERR(mcspi->base);
1389                 goto free_master;
1390         }
1391         mcspi->phys = r->start + regs_offset;
1392         mcspi->base += regs_offset;
1393
1394         mcspi->dev = &pdev->dev;
1395
1396         INIT_LIST_HEAD(&mcspi->ctx.cs);
1397
1398         mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1399                                            sizeof(struct omap2_mcspi_dma),
1400                                            GFP_KERNEL);
1401         if (mcspi->dma_channels == NULL) {
1402                 status = -ENOMEM;
1403                 goto free_master;
1404         }
1405
1406         for (i = 0; i < master->num_chipselect; i++) {
1407                 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1408                 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1409         }
1410
1411         pm_runtime_use_autosuspend(&pdev->dev);
1412         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1413         pm_runtime_enable(&pdev->dev);
1414
1415         status = omap2_mcspi_master_setup(mcspi);
1416         if (status < 0)
1417                 goto disable_pm;
1418
1419         status = devm_spi_register_master(&pdev->dev, master);
1420         if (status < 0)
1421                 goto disable_pm;
1422
1423         return status;
1424
1425 disable_pm:
1426         pm_runtime_dont_use_autosuspend(&pdev->dev);
1427         pm_runtime_put_sync(&pdev->dev);
1428         pm_runtime_disable(&pdev->dev);
1429 free_master:
1430         spi_master_put(master);
1431         return status;
1432 }
1433
1434 static int omap2_mcspi_remove(struct platform_device *pdev)
1435 {
1436         struct spi_master *master = platform_get_drvdata(pdev);
1437         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1438
1439         pm_runtime_dont_use_autosuspend(mcspi->dev);
1440         pm_runtime_put_sync(mcspi->dev);
1441         pm_runtime_disable(&pdev->dev);
1442
1443         return 0;
1444 }
1445
1446 /* work with hotplug and coldplug */
1447 MODULE_ALIAS("platform:omap2_mcspi");
1448
1449 #ifdef  CONFIG_SUSPEND
1450 /*
1451  * When SPI wake up from off-mode, CS is in activate state. If it was in
1452  * unactive state when driver was suspend, then force it to unactive state at
1453  * wake up.
1454  */
1455 static int omap2_mcspi_resume(struct device *dev)
1456 {
1457         struct spi_master       *master = dev_get_drvdata(dev);
1458         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1459         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1460         struct omap2_mcspi_cs   *cs;
1461
1462         pm_runtime_get_sync(mcspi->dev);
1463         list_for_each_entry(cs, &ctx->cs, node) {
1464                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1465                         /*
1466                          * We need to toggle CS state for OMAP take this
1467                          * change in account.
1468                          */
1469                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1470                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1471                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1472                         writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1473                 }
1474         }
1475         pm_runtime_mark_last_busy(mcspi->dev);
1476         pm_runtime_put_autosuspend(mcspi->dev);
1477
1478         return pinctrl_pm_select_default_state(dev);
1479 }
1480
1481 static int omap2_mcspi_suspend(struct device *dev)
1482 {
1483         return pinctrl_pm_select_sleep_state(dev);
1484 }
1485
1486 #else
1487 #define omap2_mcspi_suspend     NULL
1488 #define omap2_mcspi_resume      NULL
1489 #endif
1490
1491 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1492         .resume = omap2_mcspi_resume,
1493         .suspend = omap2_mcspi_suspend,
1494         .runtime_resume = omap_mcspi_runtime_resume,
1495 };
1496
1497 static struct platform_driver omap2_mcspi_driver = {
1498         .driver = {
1499                 .name =         "omap2_mcspi",
1500                 .pm =           &omap2_mcspi_pm_ops,
1501                 .of_match_table = omap_mcspi_of_match,
1502         },
1503         .probe =        omap2_mcspi_probe,
1504         .remove =       omap2_mcspi_remove,
1505 };
1506
1507 module_platform_driver(omap2_mcspi_driver);
1508 MODULE_LICENSE("GPL");