76d6b94a7597ff9b0686f3ac81c989f1fac711d2
[sfrench/cifs-2.6.git] / drivers / spi / spi-dw.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Designware SPI core controller driver (refer pxa2xx_spi.c)
4  *
5  * Copyright (c) 2009, Intel Corporation.
6  */
7
8 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/highmem.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spi/spi.h>
15
16 #include "spi-dw.h"
17
18 #ifdef CONFIG_DEBUG_FS
19 #include <linux/debugfs.h>
20 #endif
21
22 /* Slave spi_dev related */
23 struct chip_data {
24         u8 tmode;               /* TR/TO/RO/EEPROM */
25         u8 type;                /* SPI/SSP/MicroWire */
26
27         u8 poll_mode;           /* 1 means use poll mode */
28
29         u16 clk_div;            /* baud rate divider */
30         u32 speed_hz;           /* baud rate */
31         void (*cs_control)(u32 command);
32 };
33
34 #ifdef CONFIG_DEBUG_FS
35 #define SPI_REGS_BUFSIZE        1024
36 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
37                 size_t count, loff_t *ppos)
38 {
39         struct dw_spi *dws = file->private_data;
40         char *buf;
41         u32 len = 0;
42         ssize_t ret;
43
44         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
45         if (!buf)
46                 return 0;
47
48         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
49                         "%s registers:\n", dev_name(&dws->master->dev));
50         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
51                         "=================================\n");
52         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
53                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
54         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
55                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
56         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
57                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
58         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
59                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
60         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
61                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
62         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
63                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
64         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
65                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
66         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
67                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
68         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
69                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
70         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
71                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
72         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
73                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
74         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
75                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
76         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
77                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
78         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
79                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
80         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
81                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
82         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
83                         "=================================\n");
84
85         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
86         kfree(buf);
87         return ret;
88 }
89
90 static const struct file_operations dw_spi_regs_ops = {
91         .owner          = THIS_MODULE,
92         .open           = simple_open,
93         .read           = dw_spi_show_regs,
94         .llseek         = default_llseek,
95 };
96
97 static int dw_spi_debugfs_init(struct dw_spi *dws)
98 {
99         char name[32];
100
101         snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
102         dws->debugfs = debugfs_create_dir(name, NULL);
103         if (!dws->debugfs)
104                 return -ENOMEM;
105
106         debugfs_create_file("registers", S_IFREG | S_IRUGO,
107                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
108         return 0;
109 }
110
111 static void dw_spi_debugfs_remove(struct dw_spi *dws)
112 {
113         debugfs_remove_recursive(dws->debugfs);
114 }
115
116 #else
117 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
118 {
119         return 0;
120 }
121
122 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
123 {
124 }
125 #endif /* CONFIG_DEBUG_FS */
126
127 void dw_spi_set_cs(struct spi_device *spi, bool enable)
128 {
129         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
130         struct chip_data *chip = spi_get_ctldata(spi);
131
132         /* Chip select logic is inverted from spi_set_cs() */
133         if (chip && chip->cs_control)
134                 chip->cs_control(!enable);
135
136         if (!enable)
137                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
138         else if (dws->cs_override)
139                 dw_writel(dws, DW_SPI_SER, 0);
140 }
141 EXPORT_SYMBOL_GPL(dw_spi_set_cs);
142
143 /* Return the max entries we can fill into tx fifo */
144 static inline u32 tx_max(struct dw_spi *dws)
145 {
146         u32 tx_left, tx_room, rxtx_gap;
147
148         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
149         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
150
151         /*
152          * Another concern is about the tx/rx mismatch, we
153          * though to use (dws->fifo_len - rxflr - txflr) as
154          * one maximum value for tx, but it doesn't cover the
155          * data which is out of tx/rx fifo and inside the
156          * shift registers. So a control from sw point of
157          * view is taken.
158          */
159         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
160                         / dws->n_bytes;
161
162         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
163 }
164
165 /* Return the max entries we should read out of rx fifo */
166 static inline u32 rx_max(struct dw_spi *dws)
167 {
168         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
169
170         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
171 }
172
173 static void dw_writer(struct dw_spi *dws)
174 {
175         u32 max = tx_max(dws);
176         u16 txw = 0;
177
178         while (max--) {
179                 /* Set the tx word if the transfer's original "tx" is not null */
180                 if (dws->tx_end - dws->len) {
181                         if (dws->n_bytes == 1)
182                                 txw = *(u8 *)(dws->tx);
183                         else
184                                 txw = *(u16 *)(dws->tx);
185                 }
186                 dw_write_io_reg(dws, DW_SPI_DR, txw);
187                 dws->tx += dws->n_bytes;
188         }
189 }
190
191 static void dw_reader(struct dw_spi *dws)
192 {
193         u32 max = rx_max(dws);
194         u16 rxw;
195
196         while (max--) {
197                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
198                 /* Care rx only if the transfer's original "rx" is not null */
199                 if (dws->rx_end - dws->len) {
200                         if (dws->n_bytes == 1)
201                                 *(u8 *)(dws->rx) = rxw;
202                         else
203                                 *(u16 *)(dws->rx) = rxw;
204                 }
205                 dws->rx += dws->n_bytes;
206         }
207 }
208
209 static void int_error_stop(struct dw_spi *dws, const char *msg)
210 {
211         spi_reset_chip(dws);
212
213         dev_err(&dws->master->dev, "%s\n", msg);
214         dws->master->cur_msg->status = -EIO;
215         spi_finalize_current_transfer(dws->master);
216 }
217
218 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
219 {
220         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
221
222         /* Error handling */
223         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
224                 dw_readl(dws, DW_SPI_ICR);
225                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
226                 return IRQ_HANDLED;
227         }
228
229         dw_reader(dws);
230         if (dws->rx_end == dws->rx) {
231                 spi_mask_intr(dws, SPI_INT_TXEI);
232                 spi_finalize_current_transfer(dws->master);
233                 return IRQ_HANDLED;
234         }
235         if (irq_status & SPI_INT_TXEI) {
236                 spi_mask_intr(dws, SPI_INT_TXEI);
237                 dw_writer(dws);
238                 /* Enable TX irq always, it will be disabled when RX finished */
239                 spi_umask_intr(dws, SPI_INT_TXEI);
240         }
241
242         return IRQ_HANDLED;
243 }
244
245 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
246 {
247         struct spi_controller *master = dev_id;
248         struct dw_spi *dws = spi_controller_get_devdata(master);
249         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
250
251         if (!irq_status)
252                 return IRQ_NONE;
253
254         if (!master->cur_msg) {
255                 spi_mask_intr(dws, SPI_INT_TXEI);
256                 return IRQ_HANDLED;
257         }
258
259         return dws->transfer_handler(dws);
260 }
261
262 /* Must be called inside pump_transfers() */
263 static int poll_transfer(struct dw_spi *dws)
264 {
265         do {
266                 dw_writer(dws);
267                 dw_reader(dws);
268                 cpu_relax();
269         } while (dws->rx_end > dws->rx);
270
271         return 0;
272 }
273
274 static int dw_spi_transfer_one(struct spi_controller *master,
275                 struct spi_device *spi, struct spi_transfer *transfer)
276 {
277         struct dw_spi *dws = spi_controller_get_devdata(master);
278         struct chip_data *chip = spi_get_ctldata(spi);
279         u8 imask = 0;
280         u16 txlevel = 0;
281         u32 cr0;
282         int ret;
283
284         dws->dma_mapped = 0;
285
286         dws->tx = (void *)transfer->tx_buf;
287         dws->tx_end = dws->tx + transfer->len;
288         dws->rx = transfer->rx_buf;
289         dws->rx_end = dws->rx + transfer->len;
290         dws->len = transfer->len;
291
292         spi_enable_chip(dws, 0);
293
294         /* Handle per transfer options for bpw and speed */
295         if (transfer->speed_hz != dws->current_freq) {
296                 if (transfer->speed_hz != chip->speed_hz) {
297                         /* clk_div doesn't support odd number */
298                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
299                         chip->speed_hz = transfer->speed_hz;
300                 }
301                 dws->current_freq = transfer->speed_hz;
302                 spi_set_clk(dws, chip->clk_div);
303         }
304
305         dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
306         dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
307
308         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
309         cr0 = (transfer->bits_per_word - 1)
310                 | (chip->type << SPI_FRF_OFFSET)
311                 | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |
312                         (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |
313                         (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
314                 | (chip->tmode << SPI_TMOD_OFFSET);
315
316         /*
317          * Adjust transfer mode if necessary. Requires platform dependent
318          * chipselect mechanism.
319          */
320         if (chip->cs_control) {
321                 if (dws->rx && dws->tx)
322                         chip->tmode = SPI_TMOD_TR;
323                 else if (dws->rx)
324                         chip->tmode = SPI_TMOD_RO;
325                 else
326                         chip->tmode = SPI_TMOD_TO;
327
328                 cr0 &= ~SPI_TMOD_MASK;
329                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
330         }
331
332         dw_writel(dws, DW_SPI_CTRL0, cr0);
333
334         /* Check if current transfer is a DMA transaction */
335         if (master->can_dma && master->can_dma(master, spi, transfer))
336                 dws->dma_mapped = master->cur_msg_mapped;
337
338         /* For poll mode just disable all interrupts */
339         spi_mask_intr(dws, 0xff);
340
341         /*
342          * Interrupt mode
343          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
344          */
345         if (dws->dma_mapped) {
346                 ret = dws->dma_ops->dma_setup(dws, transfer);
347                 if (ret < 0) {
348                         spi_enable_chip(dws, 1);
349                         return ret;
350                 }
351         } else if (!chip->poll_mode) {
352                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
353                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
354
355                 /* Set the interrupt mask */
356                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
357                          SPI_INT_RXUI | SPI_INT_RXOI;
358                 spi_umask_intr(dws, imask);
359
360                 dws->transfer_handler = interrupt_transfer;
361         }
362
363         spi_enable_chip(dws, 1);
364
365         if (dws->dma_mapped) {
366                 ret = dws->dma_ops->dma_transfer(dws, transfer);
367                 if (ret < 0)
368                         return ret;
369         }
370
371         if (chip->poll_mode)
372                 return poll_transfer(dws);
373
374         return 1;
375 }
376
377 static void dw_spi_handle_err(struct spi_controller *master,
378                 struct spi_message *msg)
379 {
380         struct dw_spi *dws = spi_controller_get_devdata(master);
381
382         if (dws->dma_mapped)
383                 dws->dma_ops->dma_stop(dws);
384
385         spi_reset_chip(dws);
386 }
387
388 /* This may be called twice for each spi dev */
389 static int dw_spi_setup(struct spi_device *spi)
390 {
391         struct dw_spi_chip *chip_info = NULL;
392         struct chip_data *chip;
393
394         /* Only alloc on first setup */
395         chip = spi_get_ctldata(spi);
396         if (!chip) {
397                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
398                 if (!chip)
399                         return -ENOMEM;
400                 spi_set_ctldata(spi, chip);
401         }
402
403         /*
404          * Protocol drivers may change the chip settings, so...
405          * if chip_info exists, use it
406          */
407         chip_info = spi->controller_data;
408
409         /* chip_info doesn't always exist */
410         if (chip_info) {
411                 if (chip_info->cs_control)
412                         chip->cs_control = chip_info->cs_control;
413
414                 chip->poll_mode = chip_info->poll_mode;
415                 chip->type = chip_info->type;
416         }
417
418         chip->tmode = SPI_TMOD_TR;
419
420         return 0;
421 }
422
423 static void dw_spi_cleanup(struct spi_device *spi)
424 {
425         struct chip_data *chip = spi_get_ctldata(spi);
426
427         kfree(chip);
428         spi_set_ctldata(spi, NULL);
429 }
430
431 /* Restart the controller, disable all interrupts, clean rx fifo */
432 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
433 {
434         spi_reset_chip(dws);
435
436         /*
437          * Try to detect the FIFO depth if not set by interface driver,
438          * the depth could be from 2 to 256 from HW spec
439          */
440         if (!dws->fifo_len) {
441                 u32 fifo;
442
443                 for (fifo = 1; fifo < 256; fifo++) {
444                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
445                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
446                                 break;
447                 }
448                 dw_writel(dws, DW_SPI_TXFLTR, 0);
449
450                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
451                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
452         }
453
454         /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
455         if (dws->cs_override)
456                 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
457 }
458
459 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
460 {
461         struct spi_controller *master;
462         int ret;
463
464         BUG_ON(dws == NULL);
465
466         master = spi_alloc_master(dev, 0);
467         if (!master)
468                 return -ENOMEM;
469
470         dws->master = master;
471         dws->type = SSI_MOTO_SPI;
472         dws->dma_inited = 0;
473         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
474
475         spi_controller_set_devdata(master, dws);
476
477         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
478                           master);
479         if (ret < 0) {
480                 dev_err(dev, "can not get IRQ\n");
481                 goto err_free_master;
482         }
483
484         master->use_gpio_descriptors = true;
485         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
486         master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(4, 16);
487         master->bus_num = dws->bus_num;
488         master->num_chipselect = dws->num_cs;
489         master->setup = dw_spi_setup;
490         master->cleanup = dw_spi_cleanup;
491         master->set_cs = dw_spi_set_cs;
492         master->transfer_one = dw_spi_transfer_one;
493         master->handle_err = dw_spi_handle_err;
494         master->max_speed_hz = dws->max_freq;
495         master->dev.of_node = dev->of_node;
496         master->dev.fwnode = dev->fwnode;
497         master->flags = SPI_MASTER_GPIO_SS;
498         master->auto_runtime_pm = true;
499
500         if (dws->set_cs)
501                 master->set_cs = dws->set_cs;
502
503         /* Basic HW init */
504         spi_hw_init(dev, dws);
505
506         if (dws->dma_ops && dws->dma_ops->dma_init) {
507                 ret = dws->dma_ops->dma_init(dws);
508                 if (ret) {
509                         dev_warn(dev, "DMA init failed\n");
510                         dws->dma_inited = 0;
511                 } else {
512                         master->can_dma = dws->dma_ops->can_dma;
513                 }
514         }
515
516         ret = devm_spi_register_controller(dev, master);
517         if (ret) {
518                 dev_err(&master->dev, "problem registering spi master\n");
519                 goto err_dma_exit;
520         }
521
522         dw_spi_debugfs_init(dws);
523         return 0;
524
525 err_dma_exit:
526         if (dws->dma_ops && dws->dma_ops->dma_exit)
527                 dws->dma_ops->dma_exit(dws);
528         spi_enable_chip(dws, 0);
529         free_irq(dws->irq, master);
530 err_free_master:
531         spi_controller_put(master);
532         return ret;
533 }
534 EXPORT_SYMBOL_GPL(dw_spi_add_host);
535
536 void dw_spi_remove_host(struct dw_spi *dws)
537 {
538         dw_spi_debugfs_remove(dws);
539
540         if (dws->dma_ops && dws->dma_ops->dma_exit)
541                 dws->dma_ops->dma_exit(dws);
542
543         spi_shutdown_chip(dws);
544
545         free_irq(dws->irq, dws->master);
546 }
547 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
548
549 int dw_spi_suspend_host(struct dw_spi *dws)
550 {
551         int ret;
552
553         ret = spi_controller_suspend(dws->master);
554         if (ret)
555                 return ret;
556
557         spi_shutdown_chip(dws);
558         return 0;
559 }
560 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
561
562 int dw_spi_resume_host(struct dw_spi *dws)
563 {
564         spi_hw_init(&dws->master->dev, dws);
565         return spi_controller_resume(dws->master);
566 }
567 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
568
569 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
570 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
571 MODULE_LICENSE("GPL v2");