2 * Driver for Broadcom BCM2835 SPI Controllers
4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren
6 * Copyright (C) 2015 Martin Sperl
8 * This driver is inspired by:
9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/clk.h>
24 #include <linux/completion.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/err.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
34 #include <linux/of_address.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/of_irq.h>
38 #include <linux/spi/spi.h>
40 /* SPI register offsets */
41 #define BCM2835_SPI_CS 0x00
42 #define BCM2835_SPI_FIFO 0x04
43 #define BCM2835_SPI_CLK 0x08
44 #define BCM2835_SPI_DLEN 0x0c
45 #define BCM2835_SPI_LTOH 0x10
46 #define BCM2835_SPI_DC 0x14
49 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
50 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
51 #define BCM2835_SPI_CS_CSPOL2 0x00800000
52 #define BCM2835_SPI_CS_CSPOL1 0x00400000
53 #define BCM2835_SPI_CS_CSPOL0 0x00200000
54 #define BCM2835_SPI_CS_RXF 0x00100000
55 #define BCM2835_SPI_CS_RXR 0x00080000
56 #define BCM2835_SPI_CS_TXD 0x00040000
57 #define BCM2835_SPI_CS_RXD 0x00020000
58 #define BCM2835_SPI_CS_DONE 0x00010000
59 #define BCM2835_SPI_CS_LEN 0x00002000
60 #define BCM2835_SPI_CS_REN 0x00001000
61 #define BCM2835_SPI_CS_ADCS 0x00000800
62 #define BCM2835_SPI_CS_INTR 0x00000400
63 #define BCM2835_SPI_CS_INTD 0x00000200
64 #define BCM2835_SPI_CS_DMAEN 0x00000100
65 #define BCM2835_SPI_CS_TA 0x00000080
66 #define BCM2835_SPI_CS_CSPOL 0x00000040
67 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
68 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
69 #define BCM2835_SPI_CS_CPOL 0x00000008
70 #define BCM2835_SPI_CS_CPHA 0x00000004
71 #define BCM2835_SPI_CS_CS_10 0x00000002
72 #define BCM2835_SPI_CS_CS_01 0x00000001
74 #define BCM2835_SPI_FIFO_SIZE 64
75 #define BCM2835_SPI_FIFO_SIZE_3_4 48
76 #define BCM2835_SPI_POLLING_LIMIT_US 30
77 #define BCM2835_SPI_POLLING_JIFFIES 2
78 #define BCM2835_SPI_DMA_MIN_LENGTH 96
79 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
80 | SPI_NO_CS | SPI_3WIRE)
82 #define DRV_NAME "spi-bcm2835"
85 * struct bcm2835_spi - BCM2835 SPI controller
86 * @regs: base address of register map
87 * @clk: core clock, divided to calculate serial clock
88 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
89 * @tfr: SPI transfer currently processed
90 * @tx_buf: pointer whence next transmitted byte is read
91 * @rx_buf: pointer where next received byte is written
92 * @tx_len: remaining bytes to transmit
93 * @rx_len: remaining bytes to receive
94 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
95 * length is not a multiple of 4 (to overcome hardware limitation)
96 * @rx_prologue: bytes received without DMA if first RX sglist entry's
97 * length is not a multiple of 4 (to overcome hardware limitation)
98 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
99 * @dma_pending: whether a DMA transfer is in progress
105 struct spi_transfer *tfr;
112 unsigned int tx_spillover;
113 unsigned int dma_pending;
116 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
118 return readl(bs->regs + reg);
121 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
123 writel(val, bs->regs + reg);
126 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
130 while ((bs->rx_len) &&
131 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
132 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
134 *bs->rx_buf++ = byte;
139 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
143 while ((bs->tx_len) &&
144 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
145 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
146 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
152 * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
153 * @bs: BCM2835 SPI controller
154 * @count: bytes to read from RX FIFO
156 * The caller must ensure that @bs->rx_len is greater than or equal to @count,
157 * that the RX FIFO contains at least @count bytes and that the DMA Enable flag
158 * in the CS register is set (such that a read from the FIFO register receives
159 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
161 static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
169 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
171 memcpy(bs->rx_buf, &val, len);
178 * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
179 * @bs: BCM2835 SPI controller
180 * @count: bytes to write to TX FIFO
182 * The caller must ensure that @bs->tx_len is greater than or equal to @count,
183 * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
184 * in the CS register is set (such that a write to the FIFO register transmits
185 * 32-bit instead of just 8-bit).
187 static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
197 memcpy(&val, bs->tx_buf, len);
202 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
208 * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
209 * @bs: BCM2835 SPI controller
211 * The caller must ensure that the RX FIFO can accommodate as many bytes
212 * as have been written to the TX FIFO: Transmission is halted once the
213 * RX FIFO is full, causing this function to spin forever.
215 static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
217 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
222 * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
223 * @bs: BCM2835 SPI controller
224 * @count: bytes available for reading in RX FIFO
226 static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
230 count = min(count, bs->rx_len);
234 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
242 * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
243 * @bs: BCM2835 SPI controller
244 * @count: bytes available for writing in TX FIFO
246 static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
250 count = min(count, bs->tx_len);
254 val = bs->tx_buf ? *bs->tx_buf++ : 0;
255 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
260 static void bcm2835_spi_reset_hw(struct spi_master *master)
262 struct bcm2835_spi *bs = spi_master_get_devdata(master);
263 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
265 /* Disable SPI interrupts and transfer */
266 cs &= ~(BCM2835_SPI_CS_INTR |
267 BCM2835_SPI_CS_INTD |
268 BCM2835_SPI_CS_DMAEN |
270 /* and reset RX/TX FIFOS */
271 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
273 /* and reset the SPI_HW */
274 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
275 /* as well as DLEN */
276 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
279 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
281 struct spi_master *master = dev_id;
282 struct bcm2835_spi *bs = spi_master_get_devdata(master);
283 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
286 * An interrupt is signaled either if DONE is set (TX FIFO empty)
287 * or if RXR is set (RX FIFO >= ¾ full).
289 if (cs & BCM2835_SPI_CS_RXF)
290 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
291 else if (cs & BCM2835_SPI_CS_RXR)
292 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
294 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
295 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
297 /* Read as many bytes as possible from FIFO */
299 /* Write as many bytes as possible to FIFO */
303 /* Transfer complete - reset SPI HW */
304 bcm2835_spi_reset_hw(master);
305 /* wake up the framework */
306 complete(&master->xfer_completion);
312 static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
313 struct spi_device *spi,
314 struct spi_transfer *tfr,
315 u32 cs, bool fifo_empty)
317 struct bcm2835_spi *bs = spi_master_get_devdata(master);
320 * Enable HW block, but with interrupts still disabled.
321 * Otherwise the empty TX FIFO would immediately trigger an interrupt.
323 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
325 /* fill TX FIFO as much as possible */
327 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
330 /* enable interrupts */
331 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
332 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
334 /* signal that we need to wait for completion */
339 * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
340 * @master: SPI master
342 * @bs: BCM2835 SPI controller
345 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
346 * Only the final write access is permitted to transmit less than 4 bytes, the
347 * SPI controller deduces its intended size from the DLEN register.
349 * If a TX or RX sglist contains multiple entries, one per page, and the first
350 * entry starts in the middle of a page, that first entry's length may not be
351 * a multiple of 4. Subsequent entries are fine because they span an entire
352 * page, hence do have a length that's a multiple of 4.
354 * This cannot happen with kmalloc'ed buffers (which is what most clients use)
355 * because they are contiguous in physical memory and therefore not split on
356 * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
359 * The DMA engine is incapable of combining sglist entries into a continuous
360 * stream of 4 byte chunks, it treats every entry separately: A TX entry is
361 * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
362 * entry is rounded up by throwing away received bytes.
364 * Overcome this limitation by transferring the first few bytes without DMA:
365 * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
366 * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
367 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
368 * the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
370 * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
371 * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
372 * Caution, the additional 4 bytes spill over to the second TX sglist entry
373 * if the length of the first is *exactly* 1.
375 * At most 6 bytes are written and at most 3 bytes read. Do we know the
376 * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
378 * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
379 * by the DMA engine. Toggling the DMA Enable flag in the CS register switches
380 * the width but also garbles the FIFO's contents. The prologue must therefore
381 * be transmitted in 32-bit width to ensure that the following DMA transfer can
382 * pick up the residue in the RX FIFO in ungarbled form.
384 static void bcm2835_spi_transfer_prologue(struct spi_master *master,
385 struct spi_transfer *tfr,
386 struct bcm2835_spi *bs,
394 bs->tx_spillover = false;
396 if (!sg_is_last(&tfr->tx_sg.sgl[0]))
397 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
399 if (!sg_is_last(&tfr->rx_sg.sgl[0])) {
400 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
402 if (bs->rx_prologue > bs->tx_prologue) {
403 if (sg_is_last(&tfr->tx_sg.sgl[0])) {
404 bs->tx_prologue = bs->rx_prologue;
406 bs->tx_prologue += 4;
408 !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
413 /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
414 if (!bs->tx_prologue)
417 /* Write and read RX prologue. Adjust first entry in RX sglist. */
418 if (bs->rx_prologue) {
419 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
420 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
421 | BCM2835_SPI_CS_DMAEN);
422 bcm2835_wr_fifo_count(bs, bs->rx_prologue);
423 bcm2835_wait_tx_fifo_empty(bs);
424 bcm2835_rd_fifo_count(bs, bs->rx_prologue);
425 bcm2835_spi_reset_hw(master);
427 dma_sync_single_for_device(master->dma_rx->device->dev,
428 sg_dma_address(&tfr->rx_sg.sgl[0]),
429 bs->rx_prologue, DMA_FROM_DEVICE);
431 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
432 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
436 * Write remaining TX prologue. Adjust first entry in TX sglist.
437 * Also adjust second entry if prologue spills over to it.
439 tx_remaining = bs->tx_prologue - bs->rx_prologue;
441 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
442 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
443 | BCM2835_SPI_CS_DMAEN);
444 bcm2835_wr_fifo_count(bs, tx_remaining);
445 bcm2835_wait_tx_fifo_empty(bs);
446 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX);
449 if (likely(!bs->tx_spillover)) {
450 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
451 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
453 sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
454 sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
455 sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
460 * bcm2835_spi_undo_prologue() - reconstruct original sglist state
461 * @bs: BCM2835 SPI controller
463 * Undo changes which were made to an SPI transfer's sglist when transmitting
464 * the prologue. This is necessary to ensure the same memory ranges are
465 * unmapped that were originally mapped.
467 static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
469 struct spi_transfer *tfr = bs->tfr;
471 if (!bs->tx_prologue)
474 if (bs->rx_prologue) {
475 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
476 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
479 if (likely(!bs->tx_spillover)) {
480 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
481 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
483 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
484 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
485 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
489 static void bcm2835_spi_dma_done(void *data)
491 struct spi_master *master = data;
492 struct bcm2835_spi *bs = spi_master_get_devdata(master);
494 /* reset fifo and HW */
495 bcm2835_spi_reset_hw(master);
497 /* and terminate tx-dma as we do not have an irq for it
498 * because when the rx dma will terminate and this callback
499 * is called the tx-dma must have finished - can't get to this
500 * situation otherwise...
502 if (cmpxchg(&bs->dma_pending, true, false)) {
503 dmaengine_terminate_async(master->dma_tx);
504 bcm2835_spi_undo_prologue(bs);
507 /* and mark as completed */;
508 complete(&master->xfer_completion);
511 static int bcm2835_spi_prepare_sg(struct spi_master *master,
512 struct spi_transfer *tfr,
515 struct dma_chan *chan;
516 struct scatterlist *sgl;
518 enum dma_transfer_direction dir;
521 struct dma_async_tx_descriptor *desc;
525 dir = DMA_MEM_TO_DEV;
526 chan = master->dma_tx;
527 nents = tfr->tx_sg.nents;
528 sgl = tfr->tx_sg.sgl;
529 flags = 0 /* no tx interrupt */;
532 dir = DMA_DEV_TO_MEM;
533 chan = master->dma_rx;
534 nents = tfr->rx_sg.nents;
535 sgl = tfr->rx_sg.sgl;
536 flags = DMA_PREP_INTERRUPT;
538 /* prepare the channel */
539 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
543 /* set callback for rx */
545 desc->callback = bcm2835_spi_dma_done;
546 desc->callback_param = master;
549 /* submit it to DMA-engine */
550 cookie = dmaengine_submit(desc);
552 return dma_submit_error(cookie);
555 static int bcm2835_spi_transfer_one_dma(struct spi_master *master,
556 struct spi_device *spi,
557 struct spi_transfer *tfr,
560 struct bcm2835_spi *bs = spi_master_get_devdata(master);
564 * Transfer first few bytes without DMA if length of first TX or RX
565 * sglist entry is not a multiple of 4 bytes (hardware limitation).
567 bcm2835_spi_transfer_prologue(master, tfr, bs, cs);
570 ret = bcm2835_spi_prepare_sg(master, tfr, true);
575 dma_async_issue_pending(master->dma_tx);
577 /* mark as dma pending */
580 /* set the DMA length */
581 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
584 bcm2835_wr(bs, BCM2835_SPI_CS,
585 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
587 /* setup rx-DMA late - to run transfers while
588 * mapping of the rx buffers still takes place
589 * this saves 10us or more.
591 ret = bcm2835_spi_prepare_sg(master, tfr, false);
593 /* need to reset on errors */
594 dmaengine_terminate_sync(master->dma_tx);
595 bs->dma_pending = false;
599 /* start rx dma late */
600 dma_async_issue_pending(master->dma_rx);
602 /* wait for wakeup in framework */
606 bcm2835_spi_reset_hw(master);
607 bcm2835_spi_undo_prologue(bs);
611 static bool bcm2835_spi_can_dma(struct spi_master *master,
612 struct spi_device *spi,
613 struct spi_transfer *tfr)
615 /* we start DMA efforts only on bigger transfers */
616 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
623 static void bcm2835_dma_release(struct spi_master *master)
625 if (master->dma_tx) {
626 dmaengine_terminate_sync(master->dma_tx);
627 dma_release_channel(master->dma_tx);
628 master->dma_tx = NULL;
630 if (master->dma_rx) {
631 dmaengine_terminate_sync(master->dma_rx);
632 dma_release_channel(master->dma_rx);
633 master->dma_rx = NULL;
637 static void bcm2835_dma_init(struct spi_master *master, struct device *dev)
639 struct dma_slave_config slave_config;
641 dma_addr_t dma_reg_base;
644 /* base address in dma-space */
645 addr = of_get_address(master->dev.of_node, 0, NULL, NULL);
647 dev_err(dev, "could not get DMA-register address - not using dma mode\n");
650 dma_reg_base = be32_to_cpup(addr);
653 master->dma_tx = dma_request_slave_channel(dev, "tx");
654 if (!master->dma_tx) {
655 dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
658 master->dma_rx = dma_request_slave_channel(dev, "rx");
659 if (!master->dma_rx) {
660 dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
665 slave_config.direction = DMA_MEM_TO_DEV;
666 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
667 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
669 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
673 slave_config.direction = DMA_DEV_TO_MEM;
674 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
675 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
677 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
681 /* all went well, so set can_dma */
682 master->can_dma = bcm2835_spi_can_dma;
683 /* need to do TX AND RX DMA, so we need dummy buffers */
684 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
689 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
692 bcm2835_dma_release(master);
697 static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
698 struct spi_device *spi,
699 struct spi_transfer *tfr,
701 unsigned long long xfer_time_us)
703 struct bcm2835_spi *bs = spi_master_get_devdata(master);
704 unsigned long timeout;
706 /* enable HW block without interrupts */
707 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
709 /* fill in the fifo before timeout calculations
710 * if we are interrupted here, then the data is
711 * getting transferred by the HW while we are interrupted
713 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
715 /* set the timeout */
716 timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES;
718 /* loop until finished the transfer */
720 /* fill in tx fifo with remaining data */
723 /* read from fifo as much as possible */
726 /* if there is still data pending to read
727 * then check the timeout
729 if (bs->rx_len && time_after(jiffies, timeout)) {
730 dev_dbg_ratelimited(&spi->dev,
731 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
733 bs->tx_len, bs->rx_len);
734 /* fall back to interrupt mode */
735 return bcm2835_spi_transfer_one_irq(master, spi,
740 /* Transfer complete - reset SPI HW */
741 bcm2835_spi_reset_hw(master);
742 /* and return without waiting for completion */
746 static int bcm2835_spi_transfer_one(struct spi_master *master,
747 struct spi_device *spi,
748 struct spi_transfer *tfr)
750 struct bcm2835_spi *bs = spi_master_get_devdata(master);
751 unsigned long spi_hz, clk_hz, cdiv;
752 unsigned long spi_used_hz;
753 unsigned long long xfer_time_us;
754 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
757 spi_hz = tfr->speed_hz;
758 clk_hz = clk_get_rate(bs->clk);
760 if (spi_hz >= clk_hz / 2) {
761 cdiv = 2; /* clk_hz/2 is the fastest we can go */
763 /* CDIV must be a multiple of two */
764 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
768 cdiv = 0; /* 0 is the slowest we can go */
770 cdiv = 0; /* 0 is the slowest we can go */
772 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
773 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
775 /* handle all the 3-wire mode */
776 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
777 cs |= BCM2835_SPI_CS_REN;
779 cs &= ~BCM2835_SPI_CS_REN;
782 * The driver always uses software-controlled GPIO Chip Select.
783 * Set the hardware-controlled native Chip Select to an invalid
784 * value to prevent it from interfering.
786 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
788 /* set transmit buffers and length */
789 bs->tx_buf = tfr->tx_buf;
790 bs->rx_buf = tfr->rx_buf;
791 bs->tx_len = tfr->len;
792 bs->rx_len = tfr->len;
794 /* calculate the estimated time in us the transfer runs */
795 xfer_time_us = (unsigned long long)tfr->len
796 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
798 do_div(xfer_time_us, spi_used_hz);
800 /* for short requests run polling*/
801 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
802 return bcm2835_spi_transfer_one_poll(master, spi, tfr,
805 /* run in dma mode if conditions are right */
806 if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr))
807 return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs);
809 /* run in interrupt-mode */
810 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs, true);
813 static int bcm2835_spi_prepare_message(struct spi_master *master,
814 struct spi_message *msg)
816 struct spi_device *spi = msg->spi;
817 struct bcm2835_spi *bs = spi_master_get_devdata(master);
818 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
822 * DMA transfers are limited to 16 bit (0 to 65535 bytes) by the SPI HW
823 * due to DLEN. Split up transfers (32-bit FIFO aligned) if the limit is
826 ret = spi_split_transfers_maxsize(master, msg, 65532,
827 GFP_KERNEL | GFP_DMA);
831 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA);
833 if (spi->mode & SPI_CPOL)
834 cs |= BCM2835_SPI_CS_CPOL;
835 if (spi->mode & SPI_CPHA)
836 cs |= BCM2835_SPI_CS_CPHA;
838 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
843 static void bcm2835_spi_handle_err(struct spi_master *master,
844 struct spi_message *msg)
846 struct bcm2835_spi *bs = spi_master_get_devdata(master);
848 /* if an error occurred and we have an active dma, then terminate */
849 if (cmpxchg(&bs->dma_pending, true, false)) {
850 dmaengine_terminate_sync(master->dma_tx);
851 dmaengine_terminate_sync(master->dma_rx);
852 bcm2835_spi_undo_prologue(bs);
855 bcm2835_spi_reset_hw(master);
858 static int chip_match_name(struct gpio_chip *chip, void *data)
860 return !strcmp(chip->label, data);
863 static int bcm2835_spi_setup(struct spi_device *spi)
866 struct gpio_chip *chip;
868 * sanity checking the native-chipselects
870 if (spi->mode & SPI_NO_CS)
872 if (gpio_is_valid(spi->cs_gpio))
874 if (spi->chip_select > 1) {
875 /* error in the case of native CS requested with CS > 1
876 * officially there is a CS2, but it is not documented
877 * which GPIO is connected with that...
880 "setup: only two native chip-selects are supported\n");
883 /* now translate native cs to GPIO */
885 /* get the gpio chip for the base */
886 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
890 /* and calculate the real CS */
891 spi->cs_gpio = chip->base + 8 - spi->chip_select;
893 /* and set up the "mode" and level */
894 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
895 spi->chip_select, spi->cs_gpio);
897 /* set up GPIO as output and pull to the correct level */
898 err = gpio_direction_output(spi->cs_gpio,
899 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
902 "could not set CS%i gpio %i as output: %i",
903 spi->chip_select, spi->cs_gpio, err);
910 static int bcm2835_spi_probe(struct platform_device *pdev)
912 struct spi_master *master;
913 struct bcm2835_spi *bs;
914 struct resource *res;
917 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
919 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
923 platform_set_drvdata(pdev, master);
925 master->mode_bits = BCM2835_SPI_MODE_BITS;
926 master->bits_per_word_mask = SPI_BPW_MASK(8);
927 master->num_chipselect = 3;
928 master->setup = bcm2835_spi_setup;
929 master->transfer_one = bcm2835_spi_transfer_one;
930 master->handle_err = bcm2835_spi_handle_err;
931 master->prepare_message = bcm2835_spi_prepare_message;
932 master->dev.of_node = pdev->dev.of_node;
934 bs = spi_master_get_devdata(master);
936 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
937 bs->regs = devm_ioremap_resource(&pdev->dev, res);
938 if (IS_ERR(bs->regs)) {
939 err = PTR_ERR(bs->regs);
943 bs->clk = devm_clk_get(&pdev->dev, NULL);
944 if (IS_ERR(bs->clk)) {
945 err = PTR_ERR(bs->clk);
946 dev_err(&pdev->dev, "could not get clk: %d\n", err);
950 bs->irq = platform_get_irq(pdev, 0);
952 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
953 err = bs->irq ? bs->irq : -ENODEV;
957 clk_prepare_enable(bs->clk);
959 bcm2835_dma_init(master, &pdev->dev);
961 /* initialise the hardware with the default polarities */
962 bcm2835_wr(bs, BCM2835_SPI_CS,
963 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
965 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
966 dev_name(&pdev->dev), master);
968 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
969 goto out_clk_disable;
972 err = devm_spi_register_master(&pdev->dev, master);
974 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
975 goto out_clk_disable;
981 clk_disable_unprepare(bs->clk);
983 spi_master_put(master);
987 static int bcm2835_spi_remove(struct platform_device *pdev)
989 struct spi_master *master = platform_get_drvdata(pdev);
990 struct bcm2835_spi *bs = spi_master_get_devdata(master);
992 /* Clear FIFOs, and disable the HW block */
993 bcm2835_wr(bs, BCM2835_SPI_CS,
994 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
996 clk_disable_unprepare(bs->clk);
998 bcm2835_dma_release(master);
1003 static const struct of_device_id bcm2835_spi_match[] = {
1004 { .compatible = "brcm,bcm2835-spi", },
1007 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
1009 static struct platform_driver bcm2835_spi_driver = {
1012 .of_match_table = bcm2835_spi_match,
1014 .probe = bcm2835_spi_probe,
1015 .remove = bcm2835_spi_remove,
1017 module_platform_driver(bcm2835_spi_driver);
1019 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
1020 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1021 MODULE_LICENSE("GPL");