Linux 4.12
[sfrench/cifs-2.6.git] / drivers / spi / spi-atmel.c
1 /*
2  * Driver for Atmel AT32 and AT91 SPI Controllers
3  *
4  * Copyright (C) 2006 Atmel Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/dma-atmel.h>
23 #include <linux/of.h>
24
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pm_runtime.h>
30
31 /* SPI register offsets */
32 #define SPI_CR                                  0x0000
33 #define SPI_MR                                  0x0004
34 #define SPI_RDR                                 0x0008
35 #define SPI_TDR                                 0x000c
36 #define SPI_SR                                  0x0010
37 #define SPI_IER                                 0x0014
38 #define SPI_IDR                                 0x0018
39 #define SPI_IMR                                 0x001c
40 #define SPI_CSR0                                0x0030
41 #define SPI_CSR1                                0x0034
42 #define SPI_CSR2                                0x0038
43 #define SPI_CSR3                                0x003c
44 #define SPI_FMR                                 0x0040
45 #define SPI_FLR                                 0x0044
46 #define SPI_VERSION                             0x00fc
47 #define SPI_RPR                                 0x0100
48 #define SPI_RCR                                 0x0104
49 #define SPI_TPR                                 0x0108
50 #define SPI_TCR                                 0x010c
51 #define SPI_RNPR                                0x0110
52 #define SPI_RNCR                                0x0114
53 #define SPI_TNPR                                0x0118
54 #define SPI_TNCR                                0x011c
55 #define SPI_PTCR                                0x0120
56 #define SPI_PTSR                                0x0124
57
58 /* Bitfields in CR */
59 #define SPI_SPIEN_OFFSET                        0
60 #define SPI_SPIEN_SIZE                          1
61 #define SPI_SPIDIS_OFFSET                       1
62 #define SPI_SPIDIS_SIZE                         1
63 #define SPI_SWRST_OFFSET                        7
64 #define SPI_SWRST_SIZE                          1
65 #define SPI_LASTXFER_OFFSET                     24
66 #define SPI_LASTXFER_SIZE                       1
67 #define SPI_TXFCLR_OFFSET                       16
68 #define SPI_TXFCLR_SIZE                         1
69 #define SPI_RXFCLR_OFFSET                       17
70 #define SPI_RXFCLR_SIZE                         1
71 #define SPI_FIFOEN_OFFSET                       30
72 #define SPI_FIFOEN_SIZE                         1
73 #define SPI_FIFODIS_OFFSET                      31
74 #define SPI_FIFODIS_SIZE                        1
75
76 /* Bitfields in MR */
77 #define SPI_MSTR_OFFSET                         0
78 #define SPI_MSTR_SIZE                           1
79 #define SPI_PS_OFFSET                           1
80 #define SPI_PS_SIZE                             1
81 #define SPI_PCSDEC_OFFSET                       2
82 #define SPI_PCSDEC_SIZE                         1
83 #define SPI_FDIV_OFFSET                         3
84 #define SPI_FDIV_SIZE                           1
85 #define SPI_MODFDIS_OFFSET                      4
86 #define SPI_MODFDIS_SIZE                        1
87 #define SPI_WDRBT_OFFSET                        5
88 #define SPI_WDRBT_SIZE                          1
89 #define SPI_LLB_OFFSET                          7
90 #define SPI_LLB_SIZE                            1
91 #define SPI_PCS_OFFSET                          16
92 #define SPI_PCS_SIZE                            4
93 #define SPI_DLYBCS_OFFSET                       24
94 #define SPI_DLYBCS_SIZE                         8
95
96 /* Bitfields in RDR */
97 #define SPI_RD_OFFSET                           0
98 #define SPI_RD_SIZE                             16
99
100 /* Bitfields in TDR */
101 #define SPI_TD_OFFSET                           0
102 #define SPI_TD_SIZE                             16
103
104 /* Bitfields in SR */
105 #define SPI_RDRF_OFFSET                         0
106 #define SPI_RDRF_SIZE                           1
107 #define SPI_TDRE_OFFSET                         1
108 #define SPI_TDRE_SIZE                           1
109 #define SPI_MODF_OFFSET                         2
110 #define SPI_MODF_SIZE                           1
111 #define SPI_OVRES_OFFSET                        3
112 #define SPI_OVRES_SIZE                          1
113 #define SPI_ENDRX_OFFSET                        4
114 #define SPI_ENDRX_SIZE                          1
115 #define SPI_ENDTX_OFFSET                        5
116 #define SPI_ENDTX_SIZE                          1
117 #define SPI_RXBUFF_OFFSET                       6
118 #define SPI_RXBUFF_SIZE                         1
119 #define SPI_TXBUFE_OFFSET                       7
120 #define SPI_TXBUFE_SIZE                         1
121 #define SPI_NSSR_OFFSET                         8
122 #define SPI_NSSR_SIZE                           1
123 #define SPI_TXEMPTY_OFFSET                      9
124 #define SPI_TXEMPTY_SIZE                        1
125 #define SPI_SPIENS_OFFSET                       16
126 #define SPI_SPIENS_SIZE                         1
127 #define SPI_TXFEF_OFFSET                        24
128 #define SPI_TXFEF_SIZE                          1
129 #define SPI_TXFFF_OFFSET                        25
130 #define SPI_TXFFF_SIZE                          1
131 #define SPI_TXFTHF_OFFSET                       26
132 #define SPI_TXFTHF_SIZE                         1
133 #define SPI_RXFEF_OFFSET                        27
134 #define SPI_RXFEF_SIZE                          1
135 #define SPI_RXFFF_OFFSET                        28
136 #define SPI_RXFFF_SIZE                          1
137 #define SPI_RXFTHF_OFFSET                       29
138 #define SPI_RXFTHF_SIZE                         1
139 #define SPI_TXFPTEF_OFFSET                      30
140 #define SPI_TXFPTEF_SIZE                        1
141 #define SPI_RXFPTEF_OFFSET                      31
142 #define SPI_RXFPTEF_SIZE                        1
143
144 /* Bitfields in CSR0 */
145 #define SPI_CPOL_OFFSET                         0
146 #define SPI_CPOL_SIZE                           1
147 #define SPI_NCPHA_OFFSET                        1
148 #define SPI_NCPHA_SIZE                          1
149 #define SPI_CSAAT_OFFSET                        3
150 #define SPI_CSAAT_SIZE                          1
151 #define SPI_BITS_OFFSET                         4
152 #define SPI_BITS_SIZE                           4
153 #define SPI_SCBR_OFFSET                         8
154 #define SPI_SCBR_SIZE                           8
155 #define SPI_DLYBS_OFFSET                        16
156 #define SPI_DLYBS_SIZE                          8
157 #define SPI_DLYBCT_OFFSET                       24
158 #define SPI_DLYBCT_SIZE                         8
159
160 /* Bitfields in RCR */
161 #define SPI_RXCTR_OFFSET                        0
162 #define SPI_RXCTR_SIZE                          16
163
164 /* Bitfields in TCR */
165 #define SPI_TXCTR_OFFSET                        0
166 #define SPI_TXCTR_SIZE                          16
167
168 /* Bitfields in RNCR */
169 #define SPI_RXNCR_OFFSET                        0
170 #define SPI_RXNCR_SIZE                          16
171
172 /* Bitfields in TNCR */
173 #define SPI_TXNCR_OFFSET                        0
174 #define SPI_TXNCR_SIZE                          16
175
176 /* Bitfields in PTCR */
177 #define SPI_RXTEN_OFFSET                        0
178 #define SPI_RXTEN_SIZE                          1
179 #define SPI_RXTDIS_OFFSET                       1
180 #define SPI_RXTDIS_SIZE                         1
181 #define SPI_TXTEN_OFFSET                        8
182 #define SPI_TXTEN_SIZE                          1
183 #define SPI_TXTDIS_OFFSET                       9
184 #define SPI_TXTDIS_SIZE                         1
185
186 /* Bitfields in FMR */
187 #define SPI_TXRDYM_OFFSET                       0
188 #define SPI_TXRDYM_SIZE                         2
189 #define SPI_RXRDYM_OFFSET                       4
190 #define SPI_RXRDYM_SIZE                         2
191 #define SPI_TXFTHRES_OFFSET                     16
192 #define SPI_TXFTHRES_SIZE                       6
193 #define SPI_RXFTHRES_OFFSET                     24
194 #define SPI_RXFTHRES_SIZE                       6
195
196 /* Bitfields in FLR */
197 #define SPI_TXFL_OFFSET                         0
198 #define SPI_TXFL_SIZE                           6
199 #define SPI_RXFL_OFFSET                         16
200 #define SPI_RXFL_SIZE                           6
201
202 /* Constants for BITS */
203 #define SPI_BITS_8_BPT                          0
204 #define SPI_BITS_9_BPT                          1
205 #define SPI_BITS_10_BPT                         2
206 #define SPI_BITS_11_BPT                         3
207 #define SPI_BITS_12_BPT                         4
208 #define SPI_BITS_13_BPT                         5
209 #define SPI_BITS_14_BPT                         6
210 #define SPI_BITS_15_BPT                         7
211 #define SPI_BITS_16_BPT                         8
212 #define SPI_ONE_DATA                            0
213 #define SPI_TWO_DATA                            1
214 #define SPI_FOUR_DATA                           2
215
216 /* Bit manipulation macros */
217 #define SPI_BIT(name) \
218         (1 << SPI_##name##_OFFSET)
219 #define SPI_BF(name, value) \
220         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
221 #define SPI_BFEXT(name, value) \
222         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
223 #define SPI_BFINS(name, value, old) \
224         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225           | SPI_BF(name, value))
226
227 /* Register access macros */
228 #ifdef CONFIG_AVR32
229 #define spi_readl(port, reg) \
230         __raw_readl((port)->regs + SPI_##reg)
231 #define spi_writel(port, reg, value) \
232         __raw_writel((value), (port)->regs + SPI_##reg)
233
234 #define spi_readw(port, reg) \
235         __raw_readw((port)->regs + SPI_##reg)
236 #define spi_writew(port, reg, value) \
237         __raw_writew((value), (port)->regs + SPI_##reg)
238
239 #define spi_readb(port, reg) \
240         __raw_readb((port)->regs + SPI_##reg)
241 #define spi_writeb(port, reg, value) \
242         __raw_writeb((value), (port)->regs + SPI_##reg)
243 #else
244 #define spi_readl(port, reg) \
245         readl_relaxed((port)->regs + SPI_##reg)
246 #define spi_writel(port, reg, value) \
247         writel_relaxed((value), (port)->regs + SPI_##reg)
248
249 #define spi_readw(port, reg) \
250         readw_relaxed((port)->regs + SPI_##reg)
251 #define spi_writew(port, reg, value) \
252         writew_relaxed((value), (port)->regs + SPI_##reg)
253
254 #define spi_readb(port, reg) \
255         readb_relaxed((port)->regs + SPI_##reg)
256 #define spi_writeb(port, reg, value) \
257         writeb_relaxed((value), (port)->regs + SPI_##reg)
258 #endif
259 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
260  * cache operations; better heuristics consider wordsize and bitrate.
261  */
262 #define DMA_MIN_BYTES   16
263
264 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
265
266 #define AUTOSUSPEND_TIMEOUT     2000
267
268 struct atmel_spi_caps {
269         bool    is_spi2;
270         bool    has_wdrbt;
271         bool    has_dma_support;
272 };
273
274 /*
275  * The core SPI transfer engine just talks to a register bank to set up
276  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
277  * framework provides the base clock, subdivided for each spi_device.
278  */
279 struct atmel_spi {
280         spinlock_t              lock;
281         unsigned long           flags;
282
283         phys_addr_t             phybase;
284         void __iomem            *regs;
285         int                     irq;
286         struct clk              *clk;
287         struct platform_device  *pdev;
288         unsigned long           spi_clk;
289
290         struct spi_transfer     *current_transfer;
291         int                     current_remaining_bytes;
292         int                     done_status;
293
294         struct completion       xfer_completion;
295
296         struct atmel_spi_caps   caps;
297
298         bool                    use_dma;
299         bool                    use_pdc;
300         bool                    use_cs_gpios;
301
302         bool                    keep_cs;
303         bool                    cs_active;
304
305         u32                     fifo_size;
306 };
307
308 /* Controller-specific per-slave state */
309 struct atmel_spi_device {
310         unsigned int            npcs_pin;
311         u32                     csr;
312 };
313
314 #define SPI_MAX_DMA_XFER        65535 /* true for both PDC and DMA */
315 #define INVALID_DMA_ADDRESS     0xffffffff
316
317 /*
318  * Version 2 of the SPI controller has
319  *  - CR.LASTXFER
320  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
321  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
322  *  - SPI_CSRx.CSAAT
323  *  - SPI_CSRx.SBCR allows faster clocking
324  */
325 static bool atmel_spi_is_v2(struct atmel_spi *as)
326 {
327         return as->caps.is_spi2;
328 }
329
330 /*
331  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
332  * they assume that spi slave device state will not change on deselect, so
333  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
334  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
335  * controllers have CSAAT and friends.
336  *
337  * Since the CSAAT functionality is a bit weird on newer controllers as
338  * well, we use GPIO to control nCSx pins on all controllers, updating
339  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
340  * support active-high chipselects despite the controller's belief that
341  * only active-low devices/systems exists.
342  *
343  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
344  * right when driven with GPIO.  ("Mode Fault does not allow more than one
345  * Master on Chip Select 0.")  No workaround exists for that ... so for
346  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
347  * and (c) will trigger that first erratum in some cases.
348  */
349
350 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
351 {
352         struct atmel_spi_device *asd = spi->controller_state;
353         unsigned active = spi->mode & SPI_CS_HIGH;
354         u32 mr;
355
356         if (atmel_spi_is_v2(as)) {
357                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
358                 /* For the low SPI version, there is a issue that PDC transfer
359                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
360                  */
361                 spi_writel(as, CSR0, asd->csr);
362                 if (as->caps.has_wdrbt) {
363                         spi_writel(as, MR,
364                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
365                                         | SPI_BIT(WDRBT)
366                                         | SPI_BIT(MODFDIS)
367                                         | SPI_BIT(MSTR));
368                 } else {
369                         spi_writel(as, MR,
370                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
371                                         | SPI_BIT(MODFDIS)
372                                         | SPI_BIT(MSTR));
373                 }
374
375                 mr = spi_readl(as, MR);
376                 if (as->use_cs_gpios)
377                         gpio_set_value(asd->npcs_pin, active);
378         } else {
379                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
380                 int i;
381                 u32 csr;
382
383                 /* Make sure clock polarity is correct */
384                 for (i = 0; i < spi->master->num_chipselect; i++) {
385                         csr = spi_readl(as, CSR0 + 4 * i);
386                         if ((csr ^ cpol) & SPI_BIT(CPOL))
387                                 spi_writel(as, CSR0 + 4 * i,
388                                                 csr ^ SPI_BIT(CPOL));
389                 }
390
391                 mr = spi_readl(as, MR);
392                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
393                 if (as->use_cs_gpios && spi->chip_select != 0)
394                         gpio_set_value(asd->npcs_pin, active);
395                 spi_writel(as, MR, mr);
396         }
397
398         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
399                         asd->npcs_pin, active ? " (high)" : "",
400                         mr);
401 }
402
403 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
404 {
405         struct atmel_spi_device *asd = spi->controller_state;
406         unsigned active = spi->mode & SPI_CS_HIGH;
407         u32 mr;
408
409         /* only deactivate *this* device; sometimes transfers to
410          * another device may be active when this routine is called.
411          */
412         mr = spi_readl(as, MR);
413         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
414                 mr = SPI_BFINS(PCS, 0xf, mr);
415                 spi_writel(as, MR, mr);
416         }
417
418         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
419                         asd->npcs_pin, active ? " (low)" : "",
420                         mr);
421
422         if (!as->use_cs_gpios)
423                 spi_writel(as, CR, SPI_BIT(LASTXFER));
424         else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
425                 gpio_set_value(asd->npcs_pin, !active);
426 }
427
428 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
429 {
430         spin_lock_irqsave(&as->lock, as->flags);
431 }
432
433 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
434 {
435         spin_unlock_irqrestore(&as->lock, as->flags);
436 }
437
438 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
439                                 struct spi_transfer *xfer)
440 {
441         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
442 }
443
444 static bool atmel_spi_can_dma(struct spi_master *master,
445                               struct spi_device *spi,
446                               struct spi_transfer *xfer)
447 {
448         struct atmel_spi *as = spi_master_get_devdata(master);
449
450         return atmel_spi_use_dma(as, xfer);
451 }
452
453 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
454                                 struct dma_slave_config *slave_config,
455                                 u8 bits_per_word)
456 {
457         struct spi_master *master = platform_get_drvdata(as->pdev);
458         int err = 0;
459
460         if (bits_per_word > 8) {
461                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
462                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
463         } else {
464                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
465                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
466         }
467
468         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
469         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
470         slave_config->src_maxburst = 1;
471         slave_config->dst_maxburst = 1;
472         slave_config->device_fc = false;
473
474         /*
475          * This driver uses fixed peripheral select mode (PS bit set to '0' in
476          * the Mode Register).
477          * So according to the datasheet, when FIFOs are available (and
478          * enabled), the Transmit FIFO operates in Multiple Data Mode.
479          * In this mode, up to 2 data, not 4, can be written into the Transmit
480          * Data Register in a single access.
481          * However, the first data has to be written into the lowest 16 bits and
482          * the second data into the highest 16 bits of the Transmit
483          * Data Register. For 8bit data (the most frequent case), it would
484          * require to rework tx_buf so each data would actualy fit 16 bits.
485          * So we'd rather write only one data at the time. Hence the transmit
486          * path works the same whether FIFOs are available (and enabled) or not.
487          */
488         slave_config->direction = DMA_MEM_TO_DEV;
489         if (dmaengine_slave_config(master->dma_tx, slave_config)) {
490                 dev_err(&as->pdev->dev,
491                         "failed to configure tx dma channel\n");
492                 err = -EINVAL;
493         }
494
495         /*
496          * This driver configures the spi controller for master mode (MSTR bit
497          * set to '1' in the Mode Register).
498          * So according to the datasheet, when FIFOs are available (and
499          * enabled), the Receive FIFO operates in Single Data Mode.
500          * So the receive path works the same whether FIFOs are available (and
501          * enabled) or not.
502          */
503         slave_config->direction = DMA_DEV_TO_MEM;
504         if (dmaengine_slave_config(master->dma_rx, slave_config)) {
505                 dev_err(&as->pdev->dev,
506                         "failed to configure rx dma channel\n");
507                 err = -EINVAL;
508         }
509
510         return err;
511 }
512
513 static int atmel_spi_configure_dma(struct spi_master *master,
514                                    struct atmel_spi *as)
515 {
516         struct dma_slave_config slave_config;
517         struct device *dev = &as->pdev->dev;
518         int err;
519
520         dma_cap_mask_t mask;
521         dma_cap_zero(mask);
522         dma_cap_set(DMA_SLAVE, mask);
523
524         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
525         if (IS_ERR(master->dma_tx)) {
526                 err = PTR_ERR(master->dma_tx);
527                 if (err == -EPROBE_DEFER) {
528                         dev_warn(dev, "no DMA channel available at the moment\n");
529                         goto error_clear;
530                 }
531                 dev_err(dev,
532                         "DMA TX channel not available, SPI unable to use DMA\n");
533                 err = -EBUSY;
534                 goto error_clear;
535         }
536
537         /*
538          * No reason to check EPROBE_DEFER here since we have already requested
539          * tx channel. If it fails here, it's for another reason.
540          */
541         master->dma_rx = dma_request_slave_channel(dev, "rx");
542
543         if (!master->dma_rx) {
544                 dev_err(dev,
545                         "DMA RX channel not available, SPI unable to use DMA\n");
546                 err = -EBUSY;
547                 goto error;
548         }
549
550         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
551         if (err)
552                 goto error;
553
554         dev_info(&as->pdev->dev,
555                         "Using %s (tx) and %s (rx) for DMA transfers\n",
556                         dma_chan_name(master->dma_tx),
557                         dma_chan_name(master->dma_rx));
558
559         return 0;
560 error:
561         if (master->dma_rx)
562                 dma_release_channel(master->dma_rx);
563         if (!IS_ERR(master->dma_tx))
564                 dma_release_channel(master->dma_tx);
565 error_clear:
566         master->dma_tx = master->dma_rx = NULL;
567         return err;
568 }
569
570 static void atmel_spi_stop_dma(struct spi_master *master)
571 {
572         if (master->dma_rx)
573                 dmaengine_terminate_all(master->dma_rx);
574         if (master->dma_tx)
575                 dmaengine_terminate_all(master->dma_tx);
576 }
577
578 static void atmel_spi_release_dma(struct spi_master *master)
579 {
580         if (master->dma_rx) {
581                 dma_release_channel(master->dma_rx);
582                 master->dma_rx = NULL;
583         }
584         if (master->dma_tx) {
585                 dma_release_channel(master->dma_tx);
586                 master->dma_tx = NULL;
587         }
588 }
589
590 /* This function is called by the DMA driver from tasklet context */
591 static void dma_callback(void *data)
592 {
593         struct spi_master       *master = data;
594         struct atmel_spi        *as = spi_master_get_devdata(master);
595
596         complete(&as->xfer_completion);
597 }
598
599 /*
600  * Next transfer using PIO without FIFO.
601  */
602 static void atmel_spi_next_xfer_single(struct spi_master *master,
603                                        struct spi_transfer *xfer)
604 {
605         struct atmel_spi        *as = spi_master_get_devdata(master);
606         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
607
608         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
609
610         /* Make sure data is not remaining in RDR */
611         spi_readl(as, RDR);
612         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
613                 spi_readl(as, RDR);
614                 cpu_relax();
615         }
616
617         if (xfer->bits_per_word > 8)
618                 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
619         else
620                 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
621
622         dev_dbg(master->dev.parent,
623                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
624                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
625                 xfer->bits_per_word);
626
627         /* Enable relevant interrupts */
628         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
629 }
630
631 /*
632  * Next transfer using PIO with FIFO.
633  */
634 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
635                                      struct spi_transfer *xfer)
636 {
637         struct atmel_spi *as = spi_master_get_devdata(master);
638         u32 current_remaining_data, num_data;
639         u32 offset = xfer->len - as->current_remaining_bytes;
640         const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
641         const u8  *bytes = (const u8  *)((u8 *)xfer->tx_buf + offset);
642         u16 td0, td1;
643         u32 fifomr;
644
645         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
646
647         /* Compute the number of data to transfer in the current iteration */
648         current_remaining_data = ((xfer->bits_per_word > 8) ?
649                                   ((u32)as->current_remaining_bytes >> 1) :
650                                   (u32)as->current_remaining_bytes);
651         num_data = min(current_remaining_data, as->fifo_size);
652
653         /* Flush RX and TX FIFOs */
654         spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
655         while (spi_readl(as, FLR))
656                 cpu_relax();
657
658         /* Set RX FIFO Threshold to the number of data to transfer */
659         fifomr = spi_readl(as, FMR);
660         spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
661
662         /* Clear FIFO flags in the Status Register, especially RXFTHF */
663         (void)spi_readl(as, SR);
664
665         /* Fill TX FIFO */
666         while (num_data >= 2) {
667                 if (xfer->bits_per_word > 8) {
668                         td0 = *words++;
669                         td1 = *words++;
670                 } else {
671                         td0 = *bytes++;
672                         td1 = *bytes++;
673                 }
674
675                 spi_writel(as, TDR, (td1 << 16) | td0);
676                 num_data -= 2;
677         }
678
679         if (num_data) {
680                 if (xfer->bits_per_word > 8)
681                         td0 = *words++;
682                 else
683                         td0 = *bytes++;
684
685                 spi_writew(as, TDR, td0);
686                 num_data--;
687         }
688
689         dev_dbg(master->dev.parent,
690                 "  start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
691                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
692                 xfer->bits_per_word);
693
694         /*
695          * Enable RX FIFO Threshold Flag interrupt to be notified about
696          * transfer completion.
697          */
698         spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
699 }
700
701 /*
702  * Next transfer using PIO.
703  */
704 static void atmel_spi_next_xfer_pio(struct spi_master *master,
705                                     struct spi_transfer *xfer)
706 {
707         struct atmel_spi *as = spi_master_get_devdata(master);
708
709         if (as->fifo_size)
710                 atmel_spi_next_xfer_fifo(master, xfer);
711         else
712                 atmel_spi_next_xfer_single(master, xfer);
713 }
714
715 /*
716  * Submit next transfer for DMA.
717  */
718 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
719                                 struct spi_transfer *xfer,
720                                 u32 *plen)
721 {
722         struct atmel_spi        *as = spi_master_get_devdata(master);
723         struct dma_chan         *rxchan = master->dma_rx;
724         struct dma_chan         *txchan = master->dma_tx;
725         struct dma_async_tx_descriptor *rxdesc;
726         struct dma_async_tx_descriptor *txdesc;
727         struct dma_slave_config slave_config;
728         dma_cookie_t            cookie;
729
730         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
731
732         /* Check that the channels are available */
733         if (!rxchan || !txchan)
734                 return -ENODEV;
735
736         /* release lock for DMA operations */
737         atmel_spi_unlock(as);
738
739         *plen = xfer->len;
740
741         if (atmel_spi_dma_slave_config(as, &slave_config,
742                                        xfer->bits_per_word))
743                 goto err_exit;
744
745         /* Send both scatterlists */
746         rxdesc = dmaengine_prep_slave_sg(rxchan,
747                                          xfer->rx_sg.sgl, xfer->rx_sg.nents,
748                                          DMA_FROM_DEVICE,
749                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
750         if (!rxdesc)
751                 goto err_dma;
752
753         txdesc = dmaengine_prep_slave_sg(txchan,
754                                          xfer->tx_sg.sgl, xfer->tx_sg.nents,
755                                          DMA_TO_DEVICE,
756                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
757         if (!txdesc)
758                 goto err_dma;
759
760         dev_dbg(master->dev.parent,
761                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
762                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
763                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
764
765         /* Enable relevant interrupts */
766         spi_writel(as, IER, SPI_BIT(OVRES));
767
768         /* Put the callback on the RX transfer only, that should finish last */
769         rxdesc->callback = dma_callback;
770         rxdesc->callback_param = master;
771
772         /* Submit and fire RX and TX with TX last so we're ready to read! */
773         cookie = rxdesc->tx_submit(rxdesc);
774         if (dma_submit_error(cookie))
775                 goto err_dma;
776         cookie = txdesc->tx_submit(txdesc);
777         if (dma_submit_error(cookie))
778                 goto err_dma;
779         rxchan->device->device_issue_pending(rxchan);
780         txchan->device->device_issue_pending(txchan);
781
782         /* take back lock */
783         atmel_spi_lock(as);
784         return 0;
785
786 err_dma:
787         spi_writel(as, IDR, SPI_BIT(OVRES));
788         atmel_spi_stop_dma(master);
789 err_exit:
790         atmel_spi_lock(as);
791         return -ENOMEM;
792 }
793
794 static void atmel_spi_next_xfer_data(struct spi_master *master,
795                                 struct spi_transfer *xfer,
796                                 dma_addr_t *tx_dma,
797                                 dma_addr_t *rx_dma,
798                                 u32 *plen)
799 {
800         *rx_dma = xfer->rx_dma + xfer->len - *plen;
801         *tx_dma = xfer->tx_dma + xfer->len - *plen;
802         if (*plen > master->max_dma_len)
803                 *plen = master->max_dma_len;
804 }
805
806 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
807                                     struct spi_device *spi,
808                                     struct spi_transfer *xfer)
809 {
810         u32                     scbr, csr;
811         unsigned long           bus_hz;
812
813         /* v1 chips start out at half the peripheral bus speed. */
814         bus_hz = as->spi_clk;
815         if (!atmel_spi_is_v2(as))
816                 bus_hz /= 2;
817
818         /*
819          * Calculate the lowest divider that satisfies the
820          * constraint, assuming div32/fdiv/mbz == 0.
821          */
822         scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
823
824         /*
825          * If the resulting divider doesn't fit into the
826          * register bitfield, we can't satisfy the constraint.
827          */
828         if (scbr >= (1 << SPI_SCBR_SIZE)) {
829                 dev_err(&spi->dev,
830                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
831                         xfer->speed_hz, scbr, bus_hz/255);
832                 return -EINVAL;
833         }
834         if (scbr == 0) {
835                 dev_err(&spi->dev,
836                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
837                         xfer->speed_hz, scbr, bus_hz);
838                 return -EINVAL;
839         }
840         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
841         csr = SPI_BFINS(SCBR, scbr, csr);
842         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
843
844         return 0;
845 }
846
847 /*
848  * Submit next transfer for PDC.
849  * lock is held, spi irq is blocked
850  */
851 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
852                                         struct spi_message *msg,
853                                         struct spi_transfer *xfer)
854 {
855         struct atmel_spi        *as = spi_master_get_devdata(master);
856         u32                     len;
857         dma_addr_t              tx_dma, rx_dma;
858
859         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
860
861         len = as->current_remaining_bytes;
862         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
863         as->current_remaining_bytes -= len;
864
865         spi_writel(as, RPR, rx_dma);
866         spi_writel(as, TPR, tx_dma);
867
868         if (msg->spi->bits_per_word > 8)
869                 len >>= 1;
870         spi_writel(as, RCR, len);
871         spi_writel(as, TCR, len);
872
873         dev_dbg(&msg->spi->dev,
874                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
875                 xfer, xfer->len, xfer->tx_buf,
876                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
877                 (unsigned long long)xfer->rx_dma);
878
879         if (as->current_remaining_bytes) {
880                 len = as->current_remaining_bytes;
881                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
882                 as->current_remaining_bytes -= len;
883
884                 spi_writel(as, RNPR, rx_dma);
885                 spi_writel(as, TNPR, tx_dma);
886
887                 if (msg->spi->bits_per_word > 8)
888                         len >>= 1;
889                 spi_writel(as, RNCR, len);
890                 spi_writel(as, TNCR, len);
891
892                 dev_dbg(&msg->spi->dev,
893                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
894                         xfer, xfer->len, xfer->tx_buf,
895                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
896                         (unsigned long long)xfer->rx_dma);
897         }
898
899         /* REVISIT: We're waiting for RXBUFF before we start the next
900          * transfer because we need to handle some difficult timing
901          * issues otherwise. If we wait for TXBUFE in one transfer and
902          * then starts waiting for RXBUFF in the next, it's difficult
903          * to tell the difference between the RXBUFF interrupt we're
904          * actually waiting for and the RXBUFF interrupt of the
905          * previous transfer.
906          *
907          * It should be doable, though. Just not now...
908          */
909         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
910         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
911 }
912
913 /*
914  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
915  *  - The buffer is either valid for CPU access, else NULL
916  *  - If the buffer is valid, so is its DMA address
917  *
918  * This driver manages the dma address unless message->is_dma_mapped.
919  */
920 static int
921 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
922 {
923         struct device   *dev = &as->pdev->dev;
924
925         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
926         if (xfer->tx_buf) {
927                 /* tx_buf is a const void* where we need a void * for the dma
928                  * mapping */
929                 void *nonconst_tx = (void *)xfer->tx_buf;
930
931                 xfer->tx_dma = dma_map_single(dev,
932                                 nonconst_tx, xfer->len,
933                                 DMA_TO_DEVICE);
934                 if (dma_mapping_error(dev, xfer->tx_dma))
935                         return -ENOMEM;
936         }
937         if (xfer->rx_buf) {
938                 xfer->rx_dma = dma_map_single(dev,
939                                 xfer->rx_buf, xfer->len,
940                                 DMA_FROM_DEVICE);
941                 if (dma_mapping_error(dev, xfer->rx_dma)) {
942                         if (xfer->tx_buf)
943                                 dma_unmap_single(dev,
944                                                 xfer->tx_dma, xfer->len,
945                                                 DMA_TO_DEVICE);
946                         return -ENOMEM;
947                 }
948         }
949         return 0;
950 }
951
952 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
953                                      struct spi_transfer *xfer)
954 {
955         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
956                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
957                                  xfer->len, DMA_TO_DEVICE);
958         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
959                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
960                                  xfer->len, DMA_FROM_DEVICE);
961 }
962
963 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
964 {
965         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
966 }
967
968 static void
969 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
970 {
971         u8              *rxp;
972         u16             *rxp16;
973         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
974
975         if (xfer->bits_per_word > 8) {
976                 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
977                 *rxp16 = spi_readl(as, RDR);
978         } else {
979                 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
980                 *rxp = spi_readl(as, RDR);
981         }
982         if (xfer->bits_per_word > 8) {
983                 if (as->current_remaining_bytes > 2)
984                         as->current_remaining_bytes -= 2;
985                 else
986                         as->current_remaining_bytes = 0;
987         } else {
988                 as->current_remaining_bytes--;
989         }
990 }
991
992 static void
993 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
994 {
995         u32 fifolr = spi_readl(as, FLR);
996         u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
997         u32 offset = xfer->len - as->current_remaining_bytes;
998         u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
999         u8  *bytes = (u8  *)((u8 *)xfer->rx_buf + offset);
1000         u16 rd; /* RD field is the lowest 16 bits of RDR */
1001
1002         /* Update the number of remaining bytes to transfer */
1003         num_bytes = ((xfer->bits_per_word > 8) ?
1004                      (num_data << 1) :
1005                      num_data);
1006
1007         if (as->current_remaining_bytes > num_bytes)
1008                 as->current_remaining_bytes -= num_bytes;
1009         else
1010                 as->current_remaining_bytes = 0;
1011
1012         /* Handle odd number of bytes when data are more than 8bit width */
1013         if (xfer->bits_per_word > 8)
1014                 as->current_remaining_bytes &= ~0x1;
1015
1016         /* Read data */
1017         while (num_data) {
1018                 rd = spi_readl(as, RDR);
1019                 if (xfer->bits_per_word > 8)
1020                         *words++ = rd;
1021                 else
1022                         *bytes++ = rd;
1023                 num_data--;
1024         }
1025 }
1026
1027 /* Called from IRQ
1028  *
1029  * Must update "current_remaining_bytes" to keep track of data
1030  * to transfer.
1031  */
1032 static void
1033 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1034 {
1035         if (as->fifo_size)
1036                 atmel_spi_pump_fifo_data(as, xfer);
1037         else
1038                 atmel_spi_pump_single_data(as, xfer);
1039 }
1040
1041 /* Interrupt
1042  *
1043  * No need for locking in this Interrupt handler: done_status is the
1044  * only information modified.
1045  */
1046 static irqreturn_t
1047 atmel_spi_pio_interrupt(int irq, void *dev_id)
1048 {
1049         struct spi_master       *master = dev_id;
1050         struct atmel_spi        *as = spi_master_get_devdata(master);
1051         u32                     status, pending, imr;
1052         struct spi_transfer     *xfer;
1053         int                     ret = IRQ_NONE;
1054
1055         imr = spi_readl(as, IMR);
1056         status = spi_readl(as, SR);
1057         pending = status & imr;
1058
1059         if (pending & SPI_BIT(OVRES)) {
1060                 ret = IRQ_HANDLED;
1061                 spi_writel(as, IDR, SPI_BIT(OVRES));
1062                 dev_warn(master->dev.parent, "overrun\n");
1063
1064                 /*
1065                  * When we get an overrun, we disregard the current
1066                  * transfer. Data will not be copied back from any
1067                  * bounce buffer and msg->actual_len will not be
1068                  * updated with the last xfer.
1069                  *
1070                  * We will also not process any remaning transfers in
1071                  * the message.
1072                  */
1073                 as->done_status = -EIO;
1074                 smp_wmb();
1075
1076                 /* Clear any overrun happening while cleaning up */
1077                 spi_readl(as, SR);
1078
1079                 complete(&as->xfer_completion);
1080
1081         } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1082                 atmel_spi_lock(as);
1083
1084                 if (as->current_remaining_bytes) {
1085                         ret = IRQ_HANDLED;
1086                         xfer = as->current_transfer;
1087                         atmel_spi_pump_pio_data(as, xfer);
1088                         if (!as->current_remaining_bytes)
1089                                 spi_writel(as, IDR, pending);
1090
1091                         complete(&as->xfer_completion);
1092                 }
1093
1094                 atmel_spi_unlock(as);
1095         } else {
1096                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1097                 ret = IRQ_HANDLED;
1098                 spi_writel(as, IDR, pending);
1099         }
1100
1101         return ret;
1102 }
1103
1104 static irqreturn_t
1105 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1106 {
1107         struct spi_master       *master = dev_id;
1108         struct atmel_spi        *as = spi_master_get_devdata(master);
1109         u32                     status, pending, imr;
1110         int                     ret = IRQ_NONE;
1111
1112         imr = spi_readl(as, IMR);
1113         status = spi_readl(as, SR);
1114         pending = status & imr;
1115
1116         if (pending & SPI_BIT(OVRES)) {
1117
1118                 ret = IRQ_HANDLED;
1119
1120                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1121                                      | SPI_BIT(OVRES)));
1122
1123                 /* Clear any overrun happening while cleaning up */
1124                 spi_readl(as, SR);
1125
1126                 as->done_status = -EIO;
1127
1128                 complete(&as->xfer_completion);
1129
1130         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1131                 ret = IRQ_HANDLED;
1132
1133                 spi_writel(as, IDR, pending);
1134
1135                 complete(&as->xfer_completion);
1136         }
1137
1138         return ret;
1139 }
1140
1141 static int atmel_spi_setup(struct spi_device *spi)
1142 {
1143         struct atmel_spi        *as;
1144         struct atmel_spi_device *asd;
1145         u32                     csr;
1146         unsigned int            bits = spi->bits_per_word;
1147         unsigned int            npcs_pin;
1148
1149         as = spi_master_get_devdata(spi->master);
1150
1151         /* see notes above re chipselect */
1152         if (!atmel_spi_is_v2(as)
1153                         && spi->chip_select == 0
1154                         && (spi->mode & SPI_CS_HIGH)) {
1155                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1156                 return -EINVAL;
1157         }
1158
1159         csr = SPI_BF(BITS, bits - 8);
1160         if (spi->mode & SPI_CPOL)
1161                 csr |= SPI_BIT(CPOL);
1162         if (!(spi->mode & SPI_CPHA))
1163                 csr |= SPI_BIT(NCPHA);
1164         if (!as->use_cs_gpios)
1165                 csr |= SPI_BIT(CSAAT);
1166
1167         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1168          *
1169          * DLYBCT would add delays between words, slowing down transfers.
1170          * It could potentially be useful to cope with DMA bottlenecks, but
1171          * in those cases it's probably best to just use a lower bitrate.
1172          */
1173         csr |= SPI_BF(DLYBS, 0);
1174         csr |= SPI_BF(DLYBCT, 0);
1175
1176         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1177         npcs_pin = (unsigned long)spi->controller_data;
1178
1179         if (!as->use_cs_gpios)
1180                 npcs_pin = spi->chip_select;
1181         else if (gpio_is_valid(spi->cs_gpio))
1182                 npcs_pin = spi->cs_gpio;
1183
1184         asd = spi->controller_state;
1185         if (!asd) {
1186                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1187                 if (!asd)
1188                         return -ENOMEM;
1189
1190                 if (as->use_cs_gpios)
1191                         gpio_direction_output(npcs_pin,
1192                                               !(spi->mode & SPI_CS_HIGH));
1193
1194                 asd->npcs_pin = npcs_pin;
1195                 spi->controller_state = asd;
1196         }
1197
1198         asd->csr = csr;
1199
1200         dev_dbg(&spi->dev,
1201                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1202                 bits, spi->mode, spi->chip_select, csr);
1203
1204         if (!atmel_spi_is_v2(as))
1205                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1206
1207         return 0;
1208 }
1209
1210 static int atmel_spi_one_transfer(struct spi_master *master,
1211                                         struct spi_message *msg,
1212                                         struct spi_transfer *xfer)
1213 {
1214         struct atmel_spi        *as;
1215         struct spi_device       *spi = msg->spi;
1216         u8                      bits;
1217         u32                     len;
1218         struct atmel_spi_device *asd;
1219         int                     timeout;
1220         int                     ret;
1221         unsigned long           dma_timeout;
1222
1223         as = spi_master_get_devdata(master);
1224
1225         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1226                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1227                 return -EINVAL;
1228         }
1229
1230         asd = spi->controller_state;
1231         bits = (asd->csr >> 4) & 0xf;
1232         if (bits != xfer->bits_per_word - 8) {
1233                 dev_dbg(&spi->dev,
1234                         "you can't yet change bits_per_word in transfers\n");
1235                 return -ENOPROTOOPT;
1236         }
1237
1238         /*
1239          * DMA map early, for performance (empties dcache ASAP) and
1240          * better fault reporting.
1241          */
1242         if ((!msg->is_dma_mapped)
1243                 && as->use_pdc) {
1244                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1245                         return -ENOMEM;
1246         }
1247
1248         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1249
1250         as->done_status = 0;
1251         as->current_transfer = xfer;
1252         as->current_remaining_bytes = xfer->len;
1253         while (as->current_remaining_bytes) {
1254                 reinit_completion(&as->xfer_completion);
1255
1256                 if (as->use_pdc) {
1257                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1258                 } else if (atmel_spi_use_dma(as, xfer)) {
1259                         len = as->current_remaining_bytes;
1260                         ret = atmel_spi_next_xfer_dma_submit(master,
1261                                                                 xfer, &len);
1262                         if (ret) {
1263                                 dev_err(&spi->dev,
1264                                         "unable to use DMA, fallback to PIO\n");
1265                                 atmel_spi_next_xfer_pio(master, xfer);
1266                         } else {
1267                                 as->current_remaining_bytes -= len;
1268                                 if (as->current_remaining_bytes < 0)
1269                                         as->current_remaining_bytes = 0;
1270                         }
1271                 } else {
1272                         atmel_spi_next_xfer_pio(master, xfer);
1273                 }
1274
1275                 /* interrupts are disabled, so free the lock for schedule */
1276                 atmel_spi_unlock(as);
1277                 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1278                                                           SPI_DMA_TIMEOUT);
1279                 atmel_spi_lock(as);
1280                 if (WARN_ON(dma_timeout == 0)) {
1281                         dev_err(&spi->dev, "spi transfer timeout\n");
1282                         as->done_status = -EIO;
1283                 }
1284
1285                 if (as->done_status)
1286                         break;
1287         }
1288
1289         if (as->done_status) {
1290                 if (as->use_pdc) {
1291                         dev_warn(master->dev.parent,
1292                                 "overrun (%u/%u remaining)\n",
1293                                 spi_readl(as, TCR), spi_readl(as, RCR));
1294
1295                         /*
1296                          * Clean up DMA registers and make sure the data
1297                          * registers are empty.
1298                          */
1299                         spi_writel(as, RNCR, 0);
1300                         spi_writel(as, TNCR, 0);
1301                         spi_writel(as, RCR, 0);
1302                         spi_writel(as, TCR, 0);
1303                         for (timeout = 1000; timeout; timeout--)
1304                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1305                                         break;
1306                         if (!timeout)
1307                                 dev_warn(master->dev.parent,
1308                                          "timeout waiting for TXEMPTY");
1309                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1310                                 spi_readl(as, RDR);
1311
1312                         /* Clear any overrun happening while cleaning up */
1313                         spi_readl(as, SR);
1314
1315                 } else if (atmel_spi_use_dma(as, xfer)) {
1316                         atmel_spi_stop_dma(master);
1317                 }
1318
1319                 if (!msg->is_dma_mapped
1320                         && as->use_pdc)
1321                         atmel_spi_dma_unmap_xfer(master, xfer);
1322
1323                 return 0;
1324
1325         } else {
1326                 /* only update length if no error */
1327                 msg->actual_length += xfer->len;
1328         }
1329
1330         if (!msg->is_dma_mapped
1331                 && as->use_pdc)
1332                 atmel_spi_dma_unmap_xfer(master, xfer);
1333
1334         if (xfer->delay_usecs)
1335                 udelay(xfer->delay_usecs);
1336
1337         if (xfer->cs_change) {
1338                 if (list_is_last(&xfer->transfer_list,
1339                                  &msg->transfers)) {
1340                         as->keep_cs = true;
1341                 } else {
1342                         as->cs_active = !as->cs_active;
1343                         if (as->cs_active)
1344                                 cs_activate(as, msg->spi);
1345                         else
1346                                 cs_deactivate(as, msg->spi);
1347                 }
1348         }
1349
1350         return 0;
1351 }
1352
1353 static int atmel_spi_transfer_one_message(struct spi_master *master,
1354                                                 struct spi_message *msg)
1355 {
1356         struct atmel_spi *as;
1357         struct spi_transfer *xfer;
1358         struct spi_device *spi = msg->spi;
1359         int ret = 0;
1360
1361         as = spi_master_get_devdata(master);
1362
1363         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1364                                         msg, dev_name(&spi->dev));
1365
1366         atmel_spi_lock(as);
1367         cs_activate(as, spi);
1368
1369         as->cs_active = true;
1370         as->keep_cs = false;
1371
1372         msg->status = 0;
1373         msg->actual_length = 0;
1374
1375         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1376                 ret = atmel_spi_one_transfer(master, msg, xfer);
1377                 if (ret)
1378                         goto msg_done;
1379         }
1380
1381         if (as->use_pdc)
1382                 atmel_spi_disable_pdc_transfer(as);
1383
1384         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1385                 dev_dbg(&spi->dev,
1386                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1387                         xfer, xfer->len,
1388                         xfer->tx_buf, &xfer->tx_dma,
1389                         xfer->rx_buf, &xfer->rx_dma);
1390         }
1391
1392 msg_done:
1393         if (!as->keep_cs)
1394                 cs_deactivate(as, msg->spi);
1395
1396         atmel_spi_unlock(as);
1397
1398         msg->status = as->done_status;
1399         spi_finalize_current_message(spi->master);
1400
1401         return ret;
1402 }
1403
1404 static void atmel_spi_cleanup(struct spi_device *spi)
1405 {
1406         struct atmel_spi_device *asd = spi->controller_state;
1407
1408         if (!asd)
1409                 return;
1410
1411         spi->controller_state = NULL;
1412         kfree(asd);
1413 }
1414
1415 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1416 {
1417         return spi_readl(as, VERSION) & 0x00000fff;
1418 }
1419
1420 static void atmel_get_caps(struct atmel_spi *as)
1421 {
1422         unsigned int version;
1423
1424         version = atmel_get_version(as);
1425         dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1426
1427         as->caps.is_spi2 = version > 0x121;
1428         as->caps.has_wdrbt = version >= 0x210;
1429         as->caps.has_dma_support = version >= 0x212;
1430 }
1431
1432 /*-------------------------------------------------------------------------*/
1433 static int atmel_spi_gpio_cs(struct platform_device *pdev)
1434 {
1435         struct spi_master       *master = platform_get_drvdata(pdev);
1436         struct atmel_spi        *as = spi_master_get_devdata(master);
1437         struct device_node      *np = master->dev.of_node;
1438         int                     i;
1439         int                     ret = 0;
1440         int                     nb = 0;
1441
1442         if (!as->use_cs_gpios)
1443                 return 0;
1444
1445         if (!np)
1446                 return 0;
1447
1448         nb = of_gpio_named_count(np, "cs-gpios");
1449         for (i = 0; i < nb; i++) {
1450                 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1451                                                 "cs-gpios", i);
1452
1453                 if (cs_gpio == -EPROBE_DEFER)
1454                         return cs_gpio;
1455
1456                 if (gpio_is_valid(cs_gpio)) {
1457                         ret = devm_gpio_request(&pdev->dev, cs_gpio,
1458                                                 dev_name(&pdev->dev));
1459                         if (ret)
1460                                 return ret;
1461                 }
1462         }
1463
1464         return 0;
1465 }
1466
1467 static void atmel_spi_init(struct atmel_spi *as)
1468 {
1469         spi_writel(as, CR, SPI_BIT(SWRST));
1470         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1471         if (as->caps.has_wdrbt) {
1472                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1473                                 | SPI_BIT(MSTR));
1474         } else {
1475                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1476         }
1477
1478         if (as->use_pdc)
1479                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1480         spi_writel(as, CR, SPI_BIT(SPIEN));
1481
1482         if (as->fifo_size)
1483                 spi_writel(as, CR, SPI_BIT(FIFOEN));
1484 }
1485
1486 static int atmel_spi_probe(struct platform_device *pdev)
1487 {
1488         struct resource         *regs;
1489         int                     irq;
1490         struct clk              *clk;
1491         int                     ret;
1492         struct spi_master       *master;
1493         struct atmel_spi        *as;
1494
1495         /* Select default pin state */
1496         pinctrl_pm_select_default_state(&pdev->dev);
1497
1498         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1499         if (!regs)
1500                 return -ENXIO;
1501
1502         irq = platform_get_irq(pdev, 0);
1503         if (irq < 0)
1504                 return irq;
1505
1506         clk = devm_clk_get(&pdev->dev, "spi_clk");
1507         if (IS_ERR(clk))
1508                 return PTR_ERR(clk);
1509
1510         /* setup spi core then atmel-specific driver state */
1511         ret = -ENOMEM;
1512         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1513         if (!master)
1514                 goto out_free;
1515
1516         /* the spi->mode bits understood by this driver: */
1517         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1518         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1519         master->dev.of_node = pdev->dev.of_node;
1520         master->bus_num = pdev->id;
1521         master->num_chipselect = master->dev.of_node ? 0 : 4;
1522         master->setup = atmel_spi_setup;
1523         master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1524         master->transfer_one_message = atmel_spi_transfer_one_message;
1525         master->cleanup = atmel_spi_cleanup;
1526         master->auto_runtime_pm = true;
1527         master->max_dma_len = SPI_MAX_DMA_XFER;
1528         master->can_dma = atmel_spi_can_dma;
1529         platform_set_drvdata(pdev, master);
1530
1531         as = spi_master_get_devdata(master);
1532
1533         spin_lock_init(&as->lock);
1534
1535         as->pdev = pdev;
1536         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1537         if (IS_ERR(as->regs)) {
1538                 ret = PTR_ERR(as->regs);
1539                 goto out_unmap_regs;
1540         }
1541         as->phybase = regs->start;
1542         as->irq = irq;
1543         as->clk = clk;
1544
1545         init_completion(&as->xfer_completion);
1546
1547         atmel_get_caps(as);
1548
1549         as->use_cs_gpios = true;
1550         if (atmel_spi_is_v2(as) &&
1551             pdev->dev.of_node &&
1552             !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1553                 as->use_cs_gpios = false;
1554                 master->num_chipselect = 4;
1555         }
1556
1557         ret = atmel_spi_gpio_cs(pdev);
1558         if (ret)
1559                 goto out_unmap_regs;
1560
1561         as->use_dma = false;
1562         as->use_pdc = false;
1563         if (as->caps.has_dma_support) {
1564                 ret = atmel_spi_configure_dma(master, as);
1565                 if (ret == 0) {
1566                         as->use_dma = true;
1567                 } else if (ret == -EPROBE_DEFER) {
1568                         return ret;
1569                 }
1570         } else {
1571                 as->use_pdc = true;
1572         }
1573
1574         if (as->caps.has_dma_support && !as->use_dma)
1575                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1576
1577         if (as->use_pdc) {
1578                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1579                                         0, dev_name(&pdev->dev), master);
1580         } else {
1581                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1582                                         0, dev_name(&pdev->dev), master);
1583         }
1584         if (ret)
1585                 goto out_unmap_regs;
1586
1587         /* Initialize the hardware */
1588         ret = clk_prepare_enable(clk);
1589         if (ret)
1590                 goto out_free_irq;
1591
1592         as->spi_clk = clk_get_rate(clk);
1593
1594         as->fifo_size = 0;
1595         if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1596                                   &as->fifo_size)) {
1597                 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1598         }
1599
1600         atmel_spi_init(as);
1601
1602         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1603         pm_runtime_use_autosuspend(&pdev->dev);
1604         pm_runtime_set_active(&pdev->dev);
1605         pm_runtime_enable(&pdev->dev);
1606
1607         ret = devm_spi_register_master(&pdev->dev, master);
1608         if (ret)
1609                 goto out_free_dma;
1610
1611         /* go! */
1612         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1613                         (unsigned long)regs->start, irq);
1614
1615         return 0;
1616
1617 out_free_dma:
1618         pm_runtime_disable(&pdev->dev);
1619         pm_runtime_set_suspended(&pdev->dev);
1620
1621         if (as->use_dma)
1622                 atmel_spi_release_dma(master);
1623
1624         spi_writel(as, CR, SPI_BIT(SWRST));
1625         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1626         clk_disable_unprepare(clk);
1627 out_free_irq:
1628 out_unmap_regs:
1629 out_free:
1630         spi_master_put(master);
1631         return ret;
1632 }
1633
1634 static int atmel_spi_remove(struct platform_device *pdev)
1635 {
1636         struct spi_master       *master = platform_get_drvdata(pdev);
1637         struct atmel_spi        *as = spi_master_get_devdata(master);
1638
1639         pm_runtime_get_sync(&pdev->dev);
1640
1641         /* reset the hardware and block queue progress */
1642         spin_lock_irq(&as->lock);
1643         if (as->use_dma) {
1644                 atmel_spi_stop_dma(master);
1645                 atmel_spi_release_dma(master);
1646         }
1647
1648         spi_writel(as, CR, SPI_BIT(SWRST));
1649         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1650         spi_readl(as, SR);
1651         spin_unlock_irq(&as->lock);
1652
1653         clk_disable_unprepare(as->clk);
1654
1655         pm_runtime_put_noidle(&pdev->dev);
1656         pm_runtime_disable(&pdev->dev);
1657
1658         return 0;
1659 }
1660
1661 #ifdef CONFIG_PM
1662 static int atmel_spi_runtime_suspend(struct device *dev)
1663 {
1664         struct spi_master *master = dev_get_drvdata(dev);
1665         struct atmel_spi *as = spi_master_get_devdata(master);
1666
1667         clk_disable_unprepare(as->clk);
1668         pinctrl_pm_select_sleep_state(dev);
1669
1670         return 0;
1671 }
1672
1673 static int atmel_spi_runtime_resume(struct device *dev)
1674 {
1675         struct spi_master *master = dev_get_drvdata(dev);
1676         struct atmel_spi *as = spi_master_get_devdata(master);
1677
1678         pinctrl_pm_select_default_state(dev);
1679
1680         return clk_prepare_enable(as->clk);
1681 }
1682
1683 #ifdef CONFIG_PM_SLEEP
1684 static int atmel_spi_suspend(struct device *dev)
1685 {
1686         struct spi_master *master = dev_get_drvdata(dev);
1687         int ret;
1688
1689         /* Stop the queue running */
1690         ret = spi_master_suspend(master);
1691         if (ret) {
1692                 dev_warn(dev, "cannot suspend master\n");
1693                 return ret;
1694         }
1695
1696         if (!pm_runtime_suspended(dev))
1697                 atmel_spi_runtime_suspend(dev);
1698
1699         return 0;
1700 }
1701
1702 static int atmel_spi_resume(struct device *dev)
1703 {
1704         struct spi_master *master = dev_get_drvdata(dev);
1705         struct atmel_spi *as = spi_master_get_devdata(master);
1706         int ret;
1707
1708         ret = clk_prepare_enable(as->clk);
1709         if (ret)
1710                 return ret;
1711
1712         atmel_spi_init(as);
1713
1714         clk_disable_unprepare(as->clk);
1715
1716         if (!pm_runtime_suspended(dev)) {
1717                 ret = atmel_spi_runtime_resume(dev);
1718                 if (ret)
1719                         return ret;
1720         }
1721
1722         /* Start the queue running */
1723         ret = spi_master_resume(master);
1724         if (ret)
1725                 dev_err(dev, "problem starting queue (%d)\n", ret);
1726
1727         return ret;
1728 }
1729 #endif
1730
1731 static const struct dev_pm_ops atmel_spi_pm_ops = {
1732         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1733         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1734                            atmel_spi_runtime_resume, NULL)
1735 };
1736 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1737 #else
1738 #define ATMEL_SPI_PM_OPS        NULL
1739 #endif
1740
1741 #if defined(CONFIG_OF)
1742 static const struct of_device_id atmel_spi_dt_ids[] = {
1743         { .compatible = "atmel,at91rm9200-spi" },
1744         { /* sentinel */ }
1745 };
1746
1747 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1748 #endif
1749
1750 static struct platform_driver atmel_spi_driver = {
1751         .driver         = {
1752                 .name   = "atmel_spi",
1753                 .pm     = ATMEL_SPI_PM_OPS,
1754                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1755         },
1756         .probe          = atmel_spi_probe,
1757         .remove         = atmel_spi_remove,
1758 };
1759 module_platform_driver(atmel_spi_driver);
1760
1761 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1762 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1763 MODULE_LICENSE("GPL");
1764 MODULE_ALIAS("platform:atmel_spi");