Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
[sfrench/cifs-2.6.git] / drivers / spi / omap2_mcspi.c
1 /*
2  * OMAP2 McSPI controller driver
3  *
4  * Copyright (C) 2005, 2006 Nokia Corporation
5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
6  *              Juha Yrjölä <juha.yrjola@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  *
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35 #include <linux/slab.h>
36
37 #include <linux/spi/spi.h>
38
39 #include <plat/dma.h>
40 #include <plat/clock.h>
41 #include <plat/mcspi.h>
42
43 #define OMAP2_MCSPI_MAX_FREQ            48000000
44
45 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
46 #define OMAP2_MCSPI_MAX_CTRL            4
47
48 #define OMAP2_MCSPI_REVISION            0x00
49 #define OMAP2_MCSPI_SYSCONFIG           0x10
50 #define OMAP2_MCSPI_SYSSTATUS           0x14
51 #define OMAP2_MCSPI_IRQSTATUS           0x18
52 #define OMAP2_MCSPI_IRQENABLE           0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
54 #define OMAP2_MCSPI_SYST                0x24
55 #define OMAP2_MCSPI_MODULCTRL           0x28
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0             0x2c
59 #define OMAP2_MCSPI_CHSTAT0             0x30
60 #define OMAP2_MCSPI_CHCTRL0             0x34
61 #define OMAP2_MCSPI_TX0                 0x38
62 #define OMAP2_MCSPI_RX0                 0x3c
63
64 /* per-register bitmasks: */
65
66 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  BIT(0)
69 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
70
71 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
72
73 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
74 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
75 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
76
77 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
78 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
79 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
80 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
81 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
82 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
83 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
84 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
85 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
86 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
87 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
88 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
89 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
90 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
91 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
92
93 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
96
97 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
98
99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
100
101 /* We have 2 DMA channels per CS, one for RX and one for TX */
102 struct omap2_mcspi_dma {
103         int dma_tx_channel;
104         int dma_rx_channel;
105
106         int dma_tx_sync_dev;
107         int dma_rx_sync_dev;
108
109         struct completion dma_tx_completion;
110         struct completion dma_rx_completion;
111 };
112
113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114  * cache operations; better heuristics consider wordsize and bitrate.
115  */
116 #define DMA_MIN_BYTES                   160
117
118
119 struct omap2_mcspi {
120         struct work_struct      work;
121         /* lock protects queue and registers */
122         spinlock_t              lock;
123         struct list_head        msg_queue;
124         struct spi_master       *master;
125         struct clk              *ick;
126         struct clk              *fck;
127         /* Virtual base address of the controller */
128         void __iomem            *base;
129         unsigned long           phys;
130         /* SPI1 has 4 channels, while SPI2 has 2 */
131         struct omap2_mcspi_dma  *dma_channels;
132 };
133
134 struct omap2_mcspi_cs {
135         void __iomem            *base;
136         unsigned long           phys;
137         int                     word_len;
138         struct list_head        node;
139         /* Context save and restore shadow register */
140         u32                     chconf0;
141 };
142
143 /* used for context save and restore, structure members to be updated whenever
144  * corresponding registers are modified.
145  */
146 struct omap2_mcspi_regs {
147         u32 sysconfig;
148         u32 modulctrl;
149         u32 wakeupenable;
150         struct list_head cs;
151 };
152
153 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
154
155 static struct workqueue_struct *omap2_mcspi_wq;
156
157 #define MOD_REG_BIT(val, mask, set) do { \
158         if (set) \
159                 val |= mask; \
160         else \
161                 val &= ~mask; \
162 } while (0)
163
164 static inline void mcspi_write_reg(struct spi_master *master,
165                 int idx, u32 val)
166 {
167         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
168
169         __raw_writel(val, mcspi->base + idx);
170 }
171
172 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
173 {
174         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
175
176         return __raw_readl(mcspi->base + idx);
177 }
178
179 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
180                 int idx, u32 val)
181 {
182         struct omap2_mcspi_cs   *cs = spi->controller_state;
183
184         __raw_writel(val, cs->base +  idx);
185 }
186
187 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
188 {
189         struct omap2_mcspi_cs   *cs = spi->controller_state;
190
191         return __raw_readl(cs->base + idx);
192 }
193
194 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
195 {
196         struct omap2_mcspi_cs *cs = spi->controller_state;
197
198         return cs->chconf0;
199 }
200
201 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
202 {
203         struct omap2_mcspi_cs *cs = spi->controller_state;
204
205         cs->chconf0 = val;
206         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
207         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
208 }
209
210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
211                 int is_read, int enable)
212 {
213         u32 l, rw;
214
215         l = mcspi_cached_chconf0(spi);
216
217         if (is_read) /* 1 is read, 0 write */
218                 rw = OMAP2_MCSPI_CHCONF_DMAR;
219         else
220                 rw = OMAP2_MCSPI_CHCONF_DMAW;
221
222         MOD_REG_BIT(l, rw, enable);
223         mcspi_write_chconf0(spi, l);
224 }
225
226 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
227 {
228         u32 l;
229
230         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
231         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
232         /* Flash post-writes */
233         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
234 }
235
236 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
237 {
238         u32 l;
239
240         l = mcspi_cached_chconf0(spi);
241         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
242         mcspi_write_chconf0(spi, l);
243 }
244
245 static void omap2_mcspi_set_master_mode(struct spi_master *master)
246 {
247         u32 l;
248
249         /* setup when switching from (reset default) slave mode
250          * to single-channel master mode
251          */
252         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
253         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
254         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
255         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
256         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
257
258         omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
259 }
260
261 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
262 {
263         struct spi_master *spi_cntrl;
264         struct omap2_mcspi_cs *cs;
265         spi_cntrl = mcspi->master;
266
267         /* McSPI: context restore */
268         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
269                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
270
271         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
272                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
273
274         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
275                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
276
277         list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
278                         node)
279                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
280 }
281 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
282 {
283         clk_disable(mcspi->ick);
284         clk_disable(mcspi->fck);
285 }
286
287 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
288 {
289         if (clk_enable(mcspi->ick))
290                 return -ENODEV;
291         if (clk_enable(mcspi->fck))
292                 return -ENODEV;
293
294         omap2_mcspi_restore_ctx(mcspi);
295
296         return 0;
297 }
298
299 static unsigned
300 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
301 {
302         struct omap2_mcspi      *mcspi;
303         struct omap2_mcspi_cs   *cs = spi->controller_state;
304         struct omap2_mcspi_dma  *mcspi_dma;
305         unsigned int            count, c;
306         unsigned long           base, tx_reg, rx_reg;
307         int                     word_len, data_type, element_count;
308         int                     elements;
309         u32                     l;
310         u8                      * rx;
311         const u8                * tx;
312
313         mcspi = spi_master_get_devdata(spi->master);
314         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
315         l = mcspi_cached_chconf0(spi);
316
317         count = xfer->len;
318         c = count;
319         word_len = cs->word_len;
320
321         base = cs->phys;
322         tx_reg = base + OMAP2_MCSPI_TX0;
323         rx_reg = base + OMAP2_MCSPI_RX0;
324         rx = xfer->rx_buf;
325         tx = xfer->tx_buf;
326
327         if (word_len <= 8) {
328                 data_type = OMAP_DMA_DATA_TYPE_S8;
329                 element_count = count;
330         } else if (word_len <= 16) {
331                 data_type = OMAP_DMA_DATA_TYPE_S16;
332                 element_count = count >> 1;
333         } else /* word_len <= 32 */ {
334                 data_type = OMAP_DMA_DATA_TYPE_S32;
335                 element_count = count >> 2;
336         }
337
338         if (tx != NULL) {
339                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
340                                 data_type, element_count, 1,
341                                 OMAP_DMA_SYNC_ELEMENT,
342                                 mcspi_dma->dma_tx_sync_dev, 0);
343
344                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
345                                 OMAP_DMA_AMODE_CONSTANT,
346                                 tx_reg, 0, 0);
347
348                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
349                                 OMAP_DMA_AMODE_POST_INC,
350                                 xfer->tx_dma, 0, 0);
351         }
352
353         if (rx != NULL) {
354                 elements = element_count - 1;
355                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
356                         elements--;
357
358                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
359                                 data_type, elements, 1,
360                                 OMAP_DMA_SYNC_ELEMENT,
361                                 mcspi_dma->dma_rx_sync_dev, 1);
362
363                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
364                                 OMAP_DMA_AMODE_CONSTANT,
365                                 rx_reg, 0, 0);
366
367                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
368                                 OMAP_DMA_AMODE_POST_INC,
369                                 xfer->rx_dma, 0, 0);
370         }
371
372         if (tx != NULL) {
373                 omap_start_dma(mcspi_dma->dma_tx_channel);
374                 omap2_mcspi_set_dma_req(spi, 0, 1);
375         }
376
377         if (rx != NULL) {
378                 omap_start_dma(mcspi_dma->dma_rx_channel);
379                 omap2_mcspi_set_dma_req(spi, 1, 1);
380         }
381
382         if (tx != NULL) {
383                 wait_for_completion(&mcspi_dma->dma_tx_completion);
384                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
385         }
386
387         if (rx != NULL) {
388                 wait_for_completion(&mcspi_dma->dma_rx_completion);
389                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
390                 omap2_mcspi_set_enable(spi, 0);
391
392                 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
393
394                         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
395                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
396                                 u32 w;
397
398                                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
399                                 if (word_len <= 8)
400                                         ((u8 *)xfer->rx_buf)[elements++] = w;
401                                 else if (word_len <= 16)
402                                         ((u16 *)xfer->rx_buf)[elements++] = w;
403                                 else /* word_len <= 32 */
404                                         ((u32 *)xfer->rx_buf)[elements++] = w;
405                         } else {
406                                 dev_err(&spi->dev,
407                                         "DMA RX penultimate word empty");
408                                 count -= (word_len <= 8)  ? 2 :
409                                         (word_len <= 16) ? 4 :
410                                         /* word_len <= 32 */ 8;
411                                 omap2_mcspi_set_enable(spi, 1);
412                                 return count;
413                         }
414                 }
415
416                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
417                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
418                         u32 w;
419
420                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
421                         if (word_len <= 8)
422                                 ((u8 *)xfer->rx_buf)[elements] = w;
423                         else if (word_len <= 16)
424                                 ((u16 *)xfer->rx_buf)[elements] = w;
425                         else /* word_len <= 32 */
426                                 ((u32 *)xfer->rx_buf)[elements] = w;
427                 } else {
428                         dev_err(&spi->dev, "DMA RX last word empty");
429                         count -= (word_len <= 8)  ? 1 :
430                                  (word_len <= 16) ? 2 :
431                                /* word_len <= 32 */ 4;
432                 }
433                 omap2_mcspi_set_enable(spi, 1);
434         }
435         return count;
436 }
437
438 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
439 {
440         unsigned long timeout;
441
442         timeout = jiffies + msecs_to_jiffies(1000);
443         while (!(__raw_readl(reg) & bit)) {
444                 if (time_after(jiffies, timeout))
445                         return -1;
446                 cpu_relax();
447         }
448         return 0;
449 }
450
451 static unsigned
452 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
453 {
454         struct omap2_mcspi      *mcspi;
455         struct omap2_mcspi_cs   *cs = spi->controller_state;
456         unsigned int            count, c;
457         u32                     l;
458         void __iomem            *base = cs->base;
459         void __iomem            *tx_reg;
460         void __iomem            *rx_reg;
461         void __iomem            *chstat_reg;
462         int                     word_len;
463
464         mcspi = spi_master_get_devdata(spi->master);
465         count = xfer->len;
466         c = count;
467         word_len = cs->word_len;
468
469         l = mcspi_cached_chconf0(spi);
470
471         /* We store the pre-calculated register addresses on stack to speed
472          * up the transfer loop. */
473         tx_reg          = base + OMAP2_MCSPI_TX0;
474         rx_reg          = base + OMAP2_MCSPI_RX0;
475         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
476
477         if (word_len <= 8) {
478                 u8              *rx;
479                 const u8        *tx;
480
481                 rx = xfer->rx_buf;
482                 tx = xfer->tx_buf;
483
484                 do {
485                         c -= 1;
486                         if (tx != NULL) {
487                                 if (mcspi_wait_for_reg_bit(chstat_reg,
488                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
489                                         dev_err(&spi->dev, "TXS timed out\n");
490                                         goto out;
491                                 }
492 #ifdef VERBOSE
493                                 dev_dbg(&spi->dev, "write-%d %02x\n",
494                                                 word_len, *tx);
495 #endif
496                                 __raw_writel(*tx++, tx_reg);
497                         }
498                         if (rx != NULL) {
499                                 if (mcspi_wait_for_reg_bit(chstat_reg,
500                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
501                                         dev_err(&spi->dev, "RXS timed out\n");
502                                         goto out;
503                                 }
504
505                                 if (c == 1 && tx == NULL &&
506                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
507                                         omap2_mcspi_set_enable(spi, 0);
508                                         *rx++ = __raw_readl(rx_reg);
509 #ifdef VERBOSE
510                                         dev_dbg(&spi->dev, "read-%d %02x\n",
511                                                     word_len, *(rx - 1));
512 #endif
513                                         if (mcspi_wait_for_reg_bit(chstat_reg,
514                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
515                                                 dev_err(&spi->dev,
516                                                         "RXS timed out\n");
517                                                 goto out;
518                                         }
519                                         c = 0;
520                                 } else if (c == 0 && tx == NULL) {
521                                         omap2_mcspi_set_enable(spi, 0);
522                                 }
523
524                                 *rx++ = __raw_readl(rx_reg);
525 #ifdef VERBOSE
526                                 dev_dbg(&spi->dev, "read-%d %02x\n",
527                                                 word_len, *(rx - 1));
528 #endif
529                         }
530                 } while (c);
531         } else if (word_len <= 16) {
532                 u16             *rx;
533                 const u16       *tx;
534
535                 rx = xfer->rx_buf;
536                 tx = xfer->tx_buf;
537                 do {
538                         c -= 2;
539                         if (tx != NULL) {
540                                 if (mcspi_wait_for_reg_bit(chstat_reg,
541                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
542                                         dev_err(&spi->dev, "TXS timed out\n");
543                                         goto out;
544                                 }
545 #ifdef VERBOSE
546                                 dev_dbg(&spi->dev, "write-%d %04x\n",
547                                                 word_len, *tx);
548 #endif
549                                 __raw_writel(*tx++, tx_reg);
550                         }
551                         if (rx != NULL) {
552                                 if (mcspi_wait_for_reg_bit(chstat_reg,
553                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
554                                         dev_err(&spi->dev, "RXS timed out\n");
555                                         goto out;
556                                 }
557
558                                 if (c == 2 && tx == NULL &&
559                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
560                                         omap2_mcspi_set_enable(spi, 0);
561                                         *rx++ = __raw_readl(rx_reg);
562 #ifdef VERBOSE
563                                         dev_dbg(&spi->dev, "read-%d %04x\n",
564                                                     word_len, *(rx - 1));
565 #endif
566                                         if (mcspi_wait_for_reg_bit(chstat_reg,
567                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
568                                                 dev_err(&spi->dev,
569                                                         "RXS timed out\n");
570                                                 goto out;
571                                         }
572                                         c = 0;
573                                 } else if (c == 0 && tx == NULL) {
574                                         omap2_mcspi_set_enable(spi, 0);
575                                 }
576
577                                 *rx++ = __raw_readl(rx_reg);
578 #ifdef VERBOSE
579                                 dev_dbg(&spi->dev, "read-%d %04x\n",
580                                                 word_len, *(rx - 1));
581 #endif
582                         }
583                 } while (c);
584         } else if (word_len <= 32) {
585                 u32             *rx;
586                 const u32       *tx;
587
588                 rx = xfer->rx_buf;
589                 tx = xfer->tx_buf;
590                 do {
591                         c -= 4;
592                         if (tx != NULL) {
593                                 if (mcspi_wait_for_reg_bit(chstat_reg,
594                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
595                                         dev_err(&spi->dev, "TXS timed out\n");
596                                         goto out;
597                                 }
598 #ifdef VERBOSE
599                                 dev_dbg(&spi->dev, "write-%d %08x\n",
600                                                 word_len, *tx);
601 #endif
602                                 __raw_writel(*tx++, tx_reg);
603                         }
604                         if (rx != NULL) {
605                                 if (mcspi_wait_for_reg_bit(chstat_reg,
606                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
607                                         dev_err(&spi->dev, "RXS timed out\n");
608                                         goto out;
609                                 }
610
611                                 if (c == 4 && tx == NULL &&
612                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
613                                         omap2_mcspi_set_enable(spi, 0);
614                                         *rx++ = __raw_readl(rx_reg);
615 #ifdef VERBOSE
616                                         dev_dbg(&spi->dev, "read-%d %08x\n",
617                                                     word_len, *(rx - 1));
618 #endif
619                                         if (mcspi_wait_for_reg_bit(chstat_reg,
620                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
621                                                 dev_err(&spi->dev,
622                                                         "RXS timed out\n");
623                                                 goto out;
624                                         }
625                                         c = 0;
626                                 } else if (c == 0 && tx == NULL) {
627                                         omap2_mcspi_set_enable(spi, 0);
628                                 }
629
630                                 *rx++ = __raw_readl(rx_reg);
631 #ifdef VERBOSE
632                                 dev_dbg(&spi->dev, "read-%d %08x\n",
633                                                 word_len, *(rx - 1));
634 #endif
635                         }
636                 } while (c);
637         }
638
639         /* for TX_ONLY mode, be sure all words have shifted out */
640         if (xfer->rx_buf == NULL) {
641                 if (mcspi_wait_for_reg_bit(chstat_reg,
642                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
643                         dev_err(&spi->dev, "TXS timed out\n");
644                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
645                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
646                         dev_err(&spi->dev, "EOT timed out\n");
647         }
648 out:
649         omap2_mcspi_set_enable(spi, 1);
650         return count - c;
651 }
652
653 /* called only when no transfer is active to this device */
654 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
655                 struct spi_transfer *t)
656 {
657         struct omap2_mcspi_cs *cs = spi->controller_state;
658         struct omap2_mcspi *mcspi;
659         struct spi_master *spi_cntrl;
660         u32 l = 0, div = 0;
661         u8 word_len = spi->bits_per_word;
662         u32 speed_hz = spi->max_speed_hz;
663
664         mcspi = spi_master_get_devdata(spi->master);
665         spi_cntrl = mcspi->master;
666
667         if (t != NULL && t->bits_per_word)
668                 word_len = t->bits_per_word;
669
670         cs->word_len = word_len;
671
672         if (t && t->speed_hz)
673                 speed_hz = t->speed_hz;
674
675         if (speed_hz) {
676                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
677                                         > speed_hz)
678                         div++;
679         } else
680                 div = 15;
681
682         l = mcspi_cached_chconf0(spi);
683
684         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
685          * REVISIT: this controller could support SPI_3WIRE mode.
686          */
687         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
688         l |= OMAP2_MCSPI_CHCONF_DPE0;
689
690         /* wordlength */
691         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
692         l |= (word_len - 1) << 7;
693
694         /* set chipselect polarity; manage with FORCE */
695         if (!(spi->mode & SPI_CS_HIGH))
696                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
697         else
698                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
699
700         /* set clock divisor */
701         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
702         l |= div << 2;
703
704         /* set SPI mode 0..3 */
705         if (spi->mode & SPI_CPOL)
706                 l |= OMAP2_MCSPI_CHCONF_POL;
707         else
708                 l &= ~OMAP2_MCSPI_CHCONF_POL;
709         if (spi->mode & SPI_CPHA)
710                 l |= OMAP2_MCSPI_CHCONF_PHA;
711         else
712                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
713
714         mcspi_write_chconf0(spi, l);
715
716         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
717                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
718                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
719                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
720
721         return 0;
722 }
723
724 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
725 {
726         struct spi_device       *spi = data;
727         struct omap2_mcspi      *mcspi;
728         struct omap2_mcspi_dma  *mcspi_dma;
729
730         mcspi = spi_master_get_devdata(spi->master);
731         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
732
733         complete(&mcspi_dma->dma_rx_completion);
734
735         /* We must disable the DMA RX request */
736         omap2_mcspi_set_dma_req(spi, 1, 0);
737 }
738
739 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
740 {
741         struct spi_device       *spi = data;
742         struct omap2_mcspi      *mcspi;
743         struct omap2_mcspi_dma  *mcspi_dma;
744
745         mcspi = spi_master_get_devdata(spi->master);
746         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
747
748         complete(&mcspi_dma->dma_tx_completion);
749
750         /* We must disable the DMA TX request */
751         omap2_mcspi_set_dma_req(spi, 0, 0);
752 }
753
754 static int omap2_mcspi_request_dma(struct spi_device *spi)
755 {
756         struct spi_master       *master = spi->master;
757         struct omap2_mcspi      *mcspi;
758         struct omap2_mcspi_dma  *mcspi_dma;
759
760         mcspi = spi_master_get_devdata(master);
761         mcspi_dma = mcspi->dma_channels + spi->chip_select;
762
763         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
764                         omap2_mcspi_dma_rx_callback, spi,
765                         &mcspi_dma->dma_rx_channel)) {
766                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
767                 return -EAGAIN;
768         }
769
770         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
771                         omap2_mcspi_dma_tx_callback, spi,
772                         &mcspi_dma->dma_tx_channel)) {
773                 omap_free_dma(mcspi_dma->dma_rx_channel);
774                 mcspi_dma->dma_rx_channel = -1;
775                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
776                 return -EAGAIN;
777         }
778
779         init_completion(&mcspi_dma->dma_rx_completion);
780         init_completion(&mcspi_dma->dma_tx_completion);
781
782         return 0;
783 }
784
785 static int omap2_mcspi_setup(struct spi_device *spi)
786 {
787         int                     ret;
788         struct omap2_mcspi      *mcspi;
789         struct omap2_mcspi_dma  *mcspi_dma;
790         struct omap2_mcspi_cs   *cs = spi->controller_state;
791
792         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
793                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
794                         spi->bits_per_word);
795                 return -EINVAL;
796         }
797
798         mcspi = spi_master_get_devdata(spi->master);
799         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
800
801         if (!cs) {
802                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
803                 if (!cs)
804                         return -ENOMEM;
805                 cs->base = mcspi->base + spi->chip_select * 0x14;
806                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
807                 cs->chconf0 = 0;
808                 spi->controller_state = cs;
809                 /* Link this to context save list */
810                 list_add_tail(&cs->node,
811                         &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
812         }
813
814         if (mcspi_dma->dma_rx_channel == -1
815                         || mcspi_dma->dma_tx_channel == -1) {
816                 ret = omap2_mcspi_request_dma(spi);
817                 if (ret < 0)
818                         return ret;
819         }
820
821         if (omap2_mcspi_enable_clocks(mcspi))
822                 return -ENODEV;
823
824         ret = omap2_mcspi_setup_transfer(spi, NULL);
825         omap2_mcspi_disable_clocks(mcspi);
826
827         return ret;
828 }
829
830 static void omap2_mcspi_cleanup(struct spi_device *spi)
831 {
832         struct omap2_mcspi      *mcspi;
833         struct omap2_mcspi_dma  *mcspi_dma;
834         struct omap2_mcspi_cs   *cs;
835
836         mcspi = spi_master_get_devdata(spi->master);
837
838         if (spi->controller_state) {
839                 /* Unlink controller state from context save list */
840                 cs = spi->controller_state;
841                 list_del(&cs->node);
842
843                 kfree(spi->controller_state);
844         }
845
846         if (spi->chip_select < spi->master->num_chipselect) {
847                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
848
849                 if (mcspi_dma->dma_rx_channel != -1) {
850                         omap_free_dma(mcspi_dma->dma_rx_channel);
851                         mcspi_dma->dma_rx_channel = -1;
852                 }
853                 if (mcspi_dma->dma_tx_channel != -1) {
854                         omap_free_dma(mcspi_dma->dma_tx_channel);
855                         mcspi_dma->dma_tx_channel = -1;
856                 }
857         }
858 }
859
860 static void omap2_mcspi_work(struct work_struct *work)
861 {
862         struct omap2_mcspi      *mcspi;
863
864         mcspi = container_of(work, struct omap2_mcspi, work);
865         spin_lock_irq(&mcspi->lock);
866
867         if (omap2_mcspi_enable_clocks(mcspi))
868                 goto out;
869
870         /* We only enable one channel at a time -- the one whose message is
871          * at the head of the queue -- although this controller would gladly
872          * arbitrate among multiple channels.  This corresponds to "single
873          * channel" master mode.  As a side effect, we need to manage the
874          * chipselect with the FORCE bit ... CS != channel enable.
875          */
876         while (!list_empty(&mcspi->msg_queue)) {
877                 struct spi_message              *m;
878                 struct spi_device               *spi;
879                 struct spi_transfer             *t = NULL;
880                 int                             cs_active = 0;
881                 struct omap2_mcspi_cs           *cs;
882                 struct omap2_mcspi_device_config *cd;
883                 int                             par_override = 0;
884                 int                             status = 0;
885                 u32                             chconf;
886
887                 m = container_of(mcspi->msg_queue.next, struct spi_message,
888                                  queue);
889
890                 list_del_init(&m->queue);
891                 spin_unlock_irq(&mcspi->lock);
892
893                 spi = m->spi;
894                 cs = spi->controller_state;
895                 cd = spi->controller_data;
896
897                 omap2_mcspi_set_enable(spi, 1);
898                 list_for_each_entry(t, &m->transfers, transfer_list) {
899                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
900                                 status = -EINVAL;
901                                 break;
902                         }
903                         if (par_override || t->speed_hz || t->bits_per_word) {
904                                 par_override = 1;
905                                 status = omap2_mcspi_setup_transfer(spi, t);
906                                 if (status < 0)
907                                         break;
908                                 if (!t->speed_hz && !t->bits_per_word)
909                                         par_override = 0;
910                         }
911
912                         if (!cs_active) {
913                                 omap2_mcspi_force_cs(spi, 1);
914                                 cs_active = 1;
915                         }
916
917                         chconf = mcspi_cached_chconf0(spi);
918                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
919                         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
920
921                         if (t->tx_buf == NULL)
922                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
923                         else if (t->rx_buf == NULL)
924                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
925
926                         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
927                                 /* Turbo mode is for more than one word */
928                                 if (t->len > ((cs->word_len + 7) >> 3))
929                                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
930                         }
931
932                         mcspi_write_chconf0(spi, chconf);
933
934                         if (t->len) {
935                                 unsigned        count;
936
937                                 /* RX_ONLY mode needs dummy data in TX reg */
938                                 if (t->tx_buf == NULL)
939                                         __raw_writel(0, cs->base
940                                                         + OMAP2_MCSPI_TX0);
941
942                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
943                                         count = omap2_mcspi_txrx_dma(spi, t);
944                                 else
945                                         count = omap2_mcspi_txrx_pio(spi, t);
946                                 m->actual_length += count;
947
948                                 if (count != t->len) {
949                                         status = -EIO;
950                                         break;
951                                 }
952                         }
953
954                         if (t->delay_usecs)
955                                 udelay(t->delay_usecs);
956
957                         /* ignore the "leave it on after last xfer" hint */
958                         if (t->cs_change) {
959                                 omap2_mcspi_force_cs(spi, 0);
960                                 cs_active = 0;
961                         }
962                 }
963
964                 /* Restore defaults if they were overriden */
965                 if (par_override) {
966                         par_override = 0;
967                         status = omap2_mcspi_setup_transfer(spi, NULL);
968                 }
969
970                 if (cs_active)
971                         omap2_mcspi_force_cs(spi, 0);
972
973                 omap2_mcspi_set_enable(spi, 0);
974
975                 m->status = status;
976                 m->complete(m->context);
977
978                 spin_lock_irq(&mcspi->lock);
979         }
980
981         omap2_mcspi_disable_clocks(mcspi);
982
983 out:
984         spin_unlock_irq(&mcspi->lock);
985 }
986
987 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
988 {
989         struct omap2_mcspi      *mcspi;
990         unsigned long           flags;
991         struct spi_transfer     *t;
992
993         m->actual_length = 0;
994         m->status = 0;
995
996         /* reject invalid messages and transfers */
997         if (list_empty(&m->transfers) || !m->complete)
998                 return -EINVAL;
999         list_for_each_entry(t, &m->transfers, transfer_list) {
1000                 const void      *tx_buf = t->tx_buf;
1001                 void            *rx_buf = t->rx_buf;
1002                 unsigned        len = t->len;
1003
1004                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1005                                 || (len && !(rx_buf || tx_buf))
1006                                 || (t->bits_per_word &&
1007                                         (  t->bits_per_word < 4
1008                                         || t->bits_per_word > 32))) {
1009                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1010                                         t->speed_hz,
1011                                         len,
1012                                         tx_buf ? "tx" : "",
1013                                         rx_buf ? "rx" : "",
1014                                         t->bits_per_word);
1015                         return -EINVAL;
1016                 }
1017                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
1018                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
1019                                         t->speed_hz,
1020                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
1021                         return -EINVAL;
1022                 }
1023
1024                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1025                         continue;
1026
1027                 /* Do DMA mapping "early" for better error reporting and
1028                  * dcache use.  Note that if dma_unmap_single() ever starts
1029                  * to do real work on ARM, we'd need to clean up mappings
1030                  * for previous transfers on *ALL* exits of this loop...
1031                  */
1032                 if (tx_buf != NULL) {
1033                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
1034                                         len, DMA_TO_DEVICE);
1035                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
1036                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1037                                                 'T', len);
1038                                 return -EINVAL;
1039                         }
1040                 }
1041                 if (rx_buf != NULL) {
1042                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
1043                                         DMA_FROM_DEVICE);
1044                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
1045                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1046                                                 'R', len);
1047                                 if (tx_buf != NULL)
1048                                         dma_unmap_single(NULL, t->tx_dma,
1049                                                         len, DMA_TO_DEVICE);
1050                                 return -EINVAL;
1051                         }
1052                 }
1053         }
1054
1055         mcspi = spi_master_get_devdata(spi->master);
1056
1057         spin_lock_irqsave(&mcspi->lock, flags);
1058         list_add_tail(&m->queue, &mcspi->msg_queue);
1059         queue_work(omap2_mcspi_wq, &mcspi->work);
1060         spin_unlock_irqrestore(&mcspi->lock, flags);
1061
1062         return 0;
1063 }
1064
1065 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
1066 {
1067         struct spi_master       *master = mcspi->master;
1068         u32                     tmp;
1069
1070         if (omap2_mcspi_enable_clocks(mcspi))
1071                 return -1;
1072
1073         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
1074                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
1075         do {
1076                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
1077         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
1078
1079         tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
1080                 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
1081                 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
1082         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
1083         omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
1084
1085         tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1086         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1087         omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
1088
1089         omap2_mcspi_set_master_mode(master);
1090         omap2_mcspi_disable_clocks(mcspi);
1091         return 0;
1092 }
1093
1094 static u8 __initdata spi1_rxdma_id [] = {
1095         OMAP24XX_DMA_SPI1_RX0,
1096         OMAP24XX_DMA_SPI1_RX1,
1097         OMAP24XX_DMA_SPI1_RX2,
1098         OMAP24XX_DMA_SPI1_RX3,
1099 };
1100
1101 static u8 __initdata spi1_txdma_id [] = {
1102         OMAP24XX_DMA_SPI1_TX0,
1103         OMAP24XX_DMA_SPI1_TX1,
1104         OMAP24XX_DMA_SPI1_TX2,
1105         OMAP24XX_DMA_SPI1_TX3,
1106 };
1107
1108 static u8 __initdata spi2_rxdma_id[] = {
1109         OMAP24XX_DMA_SPI2_RX0,
1110         OMAP24XX_DMA_SPI2_RX1,
1111 };
1112
1113 static u8 __initdata spi2_txdma_id[] = {
1114         OMAP24XX_DMA_SPI2_TX0,
1115         OMAP24XX_DMA_SPI2_TX1,
1116 };
1117
1118 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1119         || defined(CONFIG_ARCH_OMAP4)
1120 static u8 __initdata spi3_rxdma_id[] = {
1121         OMAP24XX_DMA_SPI3_RX0,
1122         OMAP24XX_DMA_SPI3_RX1,
1123 };
1124
1125 static u8 __initdata spi3_txdma_id[] = {
1126         OMAP24XX_DMA_SPI3_TX0,
1127         OMAP24XX_DMA_SPI3_TX1,
1128 };
1129 #endif
1130
1131 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1132 static u8 __initdata spi4_rxdma_id[] = {
1133         OMAP34XX_DMA_SPI4_RX0,
1134 };
1135
1136 static u8 __initdata spi4_txdma_id[] = {
1137         OMAP34XX_DMA_SPI4_TX0,
1138 };
1139 #endif
1140
1141 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1142 {
1143         struct spi_master       *master;
1144         struct omap2_mcspi      *mcspi;
1145         struct resource         *r;
1146         int                     status = 0, i;
1147         const u8                *rxdma_id, *txdma_id;
1148         unsigned                num_chipselect;
1149
1150         switch (pdev->id) {
1151         case 1:
1152                 rxdma_id = spi1_rxdma_id;
1153                 txdma_id = spi1_txdma_id;
1154                 num_chipselect = 4;
1155                 break;
1156         case 2:
1157                 rxdma_id = spi2_rxdma_id;
1158                 txdma_id = spi2_txdma_id;
1159                 num_chipselect = 2;
1160                 break;
1161 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1162         || defined(CONFIG_ARCH_OMAP4)
1163         case 3:
1164                 rxdma_id = spi3_rxdma_id;
1165                 txdma_id = spi3_txdma_id;
1166                 num_chipselect = 2;
1167                 break;
1168 #endif
1169 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1170         case 4:
1171                 rxdma_id = spi4_rxdma_id;
1172                 txdma_id = spi4_txdma_id;
1173                 num_chipselect = 1;
1174                 break;
1175 #endif
1176         default:
1177                 return -EINVAL;
1178         }
1179
1180         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1181         if (master == NULL) {
1182                 dev_dbg(&pdev->dev, "master allocation failed\n");
1183                 return -ENOMEM;
1184         }
1185
1186         /* the spi->mode bits understood by this driver: */
1187         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1188
1189         if (pdev->id != -1)
1190                 master->bus_num = pdev->id;
1191
1192         master->setup = omap2_mcspi_setup;
1193         master->transfer = omap2_mcspi_transfer;
1194         master->cleanup = omap2_mcspi_cleanup;
1195         master->num_chipselect = num_chipselect;
1196
1197         dev_set_drvdata(&pdev->dev, master);
1198
1199         mcspi = spi_master_get_devdata(master);
1200         mcspi->master = master;
1201
1202         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203         if (r == NULL) {
1204                 status = -ENODEV;
1205                 goto err1;
1206         }
1207         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1208                         dev_name(&pdev->dev))) {
1209                 status = -EBUSY;
1210                 goto err1;
1211         }
1212
1213         mcspi->phys = r->start;
1214         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1215         if (!mcspi->base) {
1216                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1217                 status = -ENOMEM;
1218                 goto err1aa;
1219         }
1220
1221         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1222
1223         spin_lock_init(&mcspi->lock);
1224         INIT_LIST_HEAD(&mcspi->msg_queue);
1225         INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1226
1227         mcspi->ick = clk_get(&pdev->dev, "ick");
1228         if (IS_ERR(mcspi->ick)) {
1229                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1230                 status = PTR_ERR(mcspi->ick);
1231                 goto err1a;
1232         }
1233         mcspi->fck = clk_get(&pdev->dev, "fck");
1234         if (IS_ERR(mcspi->fck)) {
1235                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1236                 status = PTR_ERR(mcspi->fck);
1237                 goto err2;
1238         }
1239
1240         mcspi->dma_channels = kcalloc(master->num_chipselect,
1241                         sizeof(struct omap2_mcspi_dma),
1242                         GFP_KERNEL);
1243
1244         if (mcspi->dma_channels == NULL)
1245                 goto err3;
1246
1247         for (i = 0; i < num_chipselect; i++) {
1248                 mcspi->dma_channels[i].dma_rx_channel = -1;
1249                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1250                 mcspi->dma_channels[i].dma_tx_channel = -1;
1251                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1252         }
1253
1254         if (omap2_mcspi_reset(mcspi) < 0)
1255                 goto err4;
1256
1257         status = spi_register_master(master);
1258         if (status < 0)
1259                 goto err4;
1260
1261         return status;
1262
1263 err4:
1264         kfree(mcspi->dma_channels);
1265 err3:
1266         clk_put(mcspi->fck);
1267 err2:
1268         clk_put(mcspi->ick);
1269 err1a:
1270         iounmap(mcspi->base);
1271 err1aa:
1272         release_mem_region(r->start, (r->end - r->start) + 1);
1273 err1:
1274         spi_master_put(master);
1275         return status;
1276 }
1277
1278 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1279 {
1280         struct spi_master       *master;
1281         struct omap2_mcspi      *mcspi;
1282         struct omap2_mcspi_dma  *dma_channels;
1283         struct resource         *r;
1284         void __iomem *base;
1285
1286         master = dev_get_drvdata(&pdev->dev);
1287         mcspi = spi_master_get_devdata(master);
1288         dma_channels = mcspi->dma_channels;
1289
1290         clk_put(mcspi->fck);
1291         clk_put(mcspi->ick);
1292
1293         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294         release_mem_region(r->start, (r->end - r->start) + 1);
1295
1296         base = mcspi->base;
1297         spi_unregister_master(master);
1298         iounmap(base);
1299         kfree(dma_channels);
1300
1301         return 0;
1302 }
1303
1304 /* work with hotplug and coldplug */
1305 MODULE_ALIAS("platform:omap2_mcspi");
1306
1307 static struct platform_driver omap2_mcspi_driver = {
1308         .driver = {
1309                 .name =         "omap2_mcspi",
1310                 .owner =        THIS_MODULE,
1311         },
1312         .remove =       __exit_p(omap2_mcspi_remove),
1313 };
1314
1315
1316 static int __init omap2_mcspi_init(void)
1317 {
1318         omap2_mcspi_wq = create_singlethread_workqueue(
1319                                 omap2_mcspi_driver.driver.name);
1320         if (omap2_mcspi_wq == NULL)
1321                 return -1;
1322         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1323 }
1324 subsys_initcall(omap2_mcspi_init);
1325
1326 static void __exit omap2_mcspi_exit(void)
1327 {
1328         platform_driver_unregister(&omap2_mcspi_driver);
1329
1330         destroy_workqueue(omap2_mcspi_wq);
1331 }
1332 module_exit(omap2_mcspi_exit);
1333
1334 MODULE_LICENSE("GPL");