1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
5 * Authors: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
7 * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
10 * General Purpose functions for the global management of the
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/string.h>
18 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/crc32.h>
25 #include <linux/mod_devicetable.h>
26 #include <linux/of_platform.h>
29 #include <asm/pgtable.h>
30 #include <soc/fsl/qe/immap_qe.h>
31 #include <soc/fsl/qe/qe.h>
33 #include <asm/rheap.h>
35 static void qe_snums_init(void);
36 static int qe_sdma_init(void);
38 static DEFINE_SPINLOCK(qe_lock);
39 DEFINE_SPINLOCK(cmxgcr_lock);
40 EXPORT_SYMBOL(cmxgcr_lock);
51 enum qe_snum_state state;
54 /* We allocate this here because it is used almost exclusively for
55 * the communication processor devices.
57 struct qe_immap __iomem *qe_immr;
58 EXPORT_SYMBOL(qe_immr);
60 static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
61 static unsigned int qe_num_of_snum;
63 static phys_addr_t qebase = -1;
65 static phys_addr_t get_qe_base(void)
67 struct device_node *qe;
74 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
76 qe = of_find_node_by_type(NULL, "qe");
81 ret = of_address_to_resource(qe, 0, &res);
92 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
96 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
97 QE_CR_PROTOCOL_UNSPECIFIED, 0);
99 /* Reclaim the MURAM memory for our use. */
103 panic("sdma init failed!");
106 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
109 u8 mcn_shift = 0, dev_shift = 0;
112 spin_lock_irqsave(&qe_lock, flags);
113 if (cmd == QE_RESET) {
114 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
116 if (cmd == QE_ASSIGN_PAGE) {
117 /* Here device is the SNUM, not sub-block */
118 dev_shift = QE_CR_SNUM_SHIFT;
119 } else if (cmd == QE_ASSIGN_RISC) {
120 /* Here device is the SNUM, and mcnProtocol is
121 * e_QeCmdRiscAssignment value */
122 dev_shift = QE_CR_SNUM_SHIFT;
123 mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
125 if (device == QE_CR_SUBBLOCK_USB)
126 mcn_shift = QE_CR_MCN_USB_SHIFT;
128 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
131 out_be32(&qe_immr->cp.cecdr, cmd_input);
132 out_be32(&qe_immr->cp.cecr,
133 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
134 mcn_protocol << mcn_shift));
137 /* wait for the QE_CR_FLG to clear */
138 ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
140 /* On timeout (e.g. failure), the expression will be false (ret == 0),
141 otherwise it will be true (ret == 1). */
142 spin_unlock_irqrestore(&qe_lock, flags);
146 EXPORT_SYMBOL(qe_issue_cmd);
148 /* Set a baud rate generator. This needs lots of work. There are
149 * 16 BRGs, which can be connected to the QE channels or output
150 * as clocks. The BRGs are in two different block of internal
151 * memory mapped space.
152 * The BRG clock is the QE clock divided by 2.
153 * It was set up long ago during the initial boot phase and is
155 * Baud rate clocks are zero-based in the driver code (as that maps
156 * to port numbers). Documentation uses 1-based numbering.
158 static unsigned int brg_clk = 0;
160 #define CLK_GRAN (1000)
161 #define CLK_GRAN_LIMIT (5)
163 unsigned int qe_get_brg_clk(void)
165 struct device_node *qe;
173 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
175 qe = of_find_node_by_type(NULL, "qe");
180 prop = of_get_property(qe, "brg-frequency", &size);
181 if (prop && size == sizeof(*prop))
186 /* round this if near to a multiple of CLK_GRAN */
187 mod = brg_clk % CLK_GRAN;
189 if (mod < CLK_GRAN_LIMIT)
191 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
192 brg_clk += CLK_GRAN - mod;
197 EXPORT_SYMBOL(qe_get_brg_clk);
199 #define PVR_VER_836x 0x8083
200 #define PVR_VER_832x 0x8084
202 /* Program the BRG to the given sampling rate and multiplier
204 * @brg: the BRG, QE_BRG1 - QE_BRG16
205 * @rate: the desired sampling rate
206 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
207 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
208 * then 'multiplier' should be 8.
210 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
212 u32 divisor, tempval;
215 if ((brg < QE_BRG1) || (brg > QE_BRG16))
218 divisor = qe_get_brg_clk() / (rate * multiplier);
220 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
221 div16 = QE_BRGC_DIV16;
225 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
226 that the BRG divisor must be even if you're not using divide-by-16
228 if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
229 if (!div16 && (divisor & 1) && (divisor > 3))
232 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
233 QE_BRGC_ENABLE | div16;
235 out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
239 EXPORT_SYMBOL(qe_setbrg);
241 /* Convert a string to a QE clock source enum
243 * This function takes a string, typically from a property in the device
244 * tree, and returns the corresponding "enum qe_clock" value.
246 enum qe_clock qe_clock_source(const char *source)
250 if (strcasecmp(source, "none") == 0)
253 if (strcmp(source, "tsync_pin") == 0)
256 if (strcmp(source, "rsync_pin") == 0)
259 if (strncasecmp(source, "brg", 3) == 0) {
260 i = simple_strtoul(source + 3, NULL, 10);
261 if ((i >= 1) && (i <= 16))
262 return (QE_BRG1 - 1) + i;
267 if (strncasecmp(source, "clk", 3) == 0) {
268 i = simple_strtoul(source + 3, NULL, 10);
269 if ((i >= 1) && (i <= 24))
270 return (QE_CLK1 - 1) + i;
277 EXPORT_SYMBOL(qe_clock_source);
279 /* Initialize SNUMs (thread serial numbers) according to
280 * QE Module Control chapter, SNUM table
282 static void qe_snums_init(void)
285 static const u8 snum_init_76[] = {
286 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
287 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
288 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
289 0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
290 0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
291 0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
292 0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
293 0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
294 0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
295 0xF4, 0xF5, 0xFC, 0xFD,
297 static const u8 snum_init_46[] = {
298 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
299 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
300 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
301 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
302 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
303 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
305 static const u8 *snum_init;
307 qe_num_of_snum = qe_get_num_of_snums();
309 if (qe_num_of_snum == 76)
310 snum_init = snum_init_76;
312 snum_init = snum_init_46;
314 for (i = 0; i < qe_num_of_snum; i++) {
315 snums[i].num = snum_init[i];
316 snums[i].state = QE_SNUM_STATE_FREE;
320 int qe_get_snum(void)
326 spin_lock_irqsave(&qe_lock, flags);
327 for (i = 0; i < qe_num_of_snum; i++) {
328 if (snums[i].state == QE_SNUM_STATE_FREE) {
329 snums[i].state = QE_SNUM_STATE_USED;
334 spin_unlock_irqrestore(&qe_lock, flags);
338 EXPORT_SYMBOL(qe_get_snum);
340 void qe_put_snum(u8 snum)
344 for (i = 0; i < qe_num_of_snum; i++) {
345 if (snums[i].num == snum) {
346 snums[i].state = QE_SNUM_STATE_FREE;
351 EXPORT_SYMBOL(qe_put_snum);
353 static int qe_sdma_init(void)
355 struct sdma __iomem *sdma = &qe_immr->sdma;
356 static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
361 /* allocate 2 internal temporary buffers (512 bytes size each) for
363 if (IS_ERR_VALUE(sdma_buf_offset)) {
364 sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
365 if (IS_ERR_VALUE(sdma_buf_offset))
369 out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
370 out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
371 (0x1 << QE_SDMR_CEN_SHIFT)));
376 /* The maximum number of RISCs we support */
377 #define MAX_QE_RISC 4
379 /* Firmware information stored here for qe_get_firmware_info() */
380 static struct qe_firmware_info qe_firmware_info;
383 * Set to 1 if QE firmware has been uploaded, and therefore
384 * qe_firmware_info contains valid data.
386 static int qe_firmware_uploaded;
389 * Upload a QE microcode
391 * This function is a worker function for qe_upload_firmware(). It does
392 * the actual uploading of the microcode.
394 static void qe_upload_microcode(const void *base,
395 const struct qe_microcode *ucode)
397 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
400 if (ucode->major || ucode->minor || ucode->revision)
401 printk(KERN_INFO "qe-firmware: "
402 "uploading microcode '%s' version %u.%u.%u\n",
403 ucode->id, ucode->major, ucode->minor, ucode->revision);
405 printk(KERN_INFO "qe-firmware: "
406 "uploading microcode '%s'\n", ucode->id);
408 /* Use auto-increment */
409 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
410 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
412 for (i = 0; i < be32_to_cpu(ucode->count); i++)
413 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
415 /* Set I-RAM Ready Register */
416 out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
420 * Upload a microcode to the I-RAM at a specific address.
422 * See Documentation/powerpc/qe_firmware.rst for information on QE microcode
425 * Currently, only version 1 is supported, so the 'version' field must be
428 * The SOC model and revision are not validated, they are only displayed for
429 * informational purposes.
431 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
432 * all of the microcode structures, minus the CRC.
434 * 'length' is the size that the structure says it is, including the CRC.
436 int qe_upload_firmware(const struct qe_firmware *firmware)
441 size_t calc_size = sizeof(struct qe_firmware);
443 const struct qe_header *hdr;
446 printk(KERN_ERR "qe-firmware: invalid pointer\n");
450 hdr = &firmware->header;
451 length = be32_to_cpu(hdr->length);
453 /* Check the magic */
454 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
455 (hdr->magic[2] != 'F')) {
456 printk(KERN_ERR "qe-firmware: not a microcode\n");
460 /* Check the version */
461 if (hdr->version != 1) {
462 printk(KERN_ERR "qe-firmware: unsupported version\n");
466 /* Validate some of the fields */
467 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
468 printk(KERN_ERR "qe-firmware: invalid data\n");
472 /* Validate the length and check if there's a CRC */
473 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
475 for (i = 0; i < firmware->count; i++)
477 * For situations where the second RISC uses the same microcode
478 * as the first, the 'code_offset' and 'count' fields will be
479 * zero, so it's okay to add those.
481 calc_size += sizeof(__be32) *
482 be32_to_cpu(firmware->microcode[i].count);
484 /* Validate the length */
485 if (length != calc_size + sizeof(__be32)) {
486 printk(KERN_ERR "qe-firmware: invalid length\n");
490 /* Validate the CRC */
491 crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
492 if (crc != crc32(0, firmware, calc_size)) {
493 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
498 * If the microcode calls for it, split the I-RAM.
500 if (!firmware->split)
501 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
503 if (firmware->soc.model)
505 "qe-firmware: firmware '%s' for %u V%u.%u\n",
506 firmware->id, be16_to_cpu(firmware->soc.model),
507 firmware->soc.major, firmware->soc.minor);
509 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
513 * The QE only supports one microcode per RISC, so clear out all the
514 * saved microcode information and put in the new.
516 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
517 strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
518 qe_firmware_info.extended_modes = firmware->extended_modes;
519 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
520 sizeof(firmware->vtraps));
522 /* Loop through each microcode. */
523 for (i = 0; i < firmware->count; i++) {
524 const struct qe_microcode *ucode = &firmware->microcode[i];
526 /* Upload a microcode if it's present */
527 if (ucode->code_offset)
528 qe_upload_microcode(firmware, ucode);
530 /* Program the traps for this processor */
531 for (j = 0; j < 16; j++) {
532 u32 trap = be32_to_cpu(ucode->traps[j]);
535 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
539 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
542 qe_firmware_uploaded = 1;
546 EXPORT_SYMBOL(qe_upload_firmware);
549 * Get info on the currently-loaded firmware
551 * This function also checks the device tree to see if the boot loader has
552 * uploaded a firmware already.
554 struct qe_firmware_info *qe_get_firmware_info(void)
556 static int initialized;
557 struct property *prop;
558 struct device_node *qe;
559 struct device_node *fw = NULL;
564 * If we haven't checked yet, and a driver hasn't uploaded a firmware
565 * yet, then check the device tree for information.
567 if (qe_firmware_uploaded)
568 return &qe_firmware_info;
576 * Newer device trees have an "fsl,qe" compatible property for the QE
577 * node, but we still need to support older device trees.
579 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
581 qe = of_find_node_by_type(NULL, "qe");
586 /* Find the 'firmware' child node */
587 fw = of_get_child_by_name(qe, "firmware");
590 /* Did we find the 'firmware' node? */
594 qe_firmware_uploaded = 1;
596 /* Copy the data into qe_firmware_info*/
597 sprop = of_get_property(fw, "id", NULL);
599 strlcpy(qe_firmware_info.id, sprop,
600 sizeof(qe_firmware_info.id));
602 prop = of_find_property(fw, "extended-modes", NULL);
603 if (prop && (prop->length == sizeof(u64))) {
604 const u64 *iprop = prop->value;
606 qe_firmware_info.extended_modes = *iprop;
609 prop = of_find_property(fw, "virtual-traps", NULL);
610 if (prop && (prop->length == 32)) {
611 const u32 *iprop = prop->value;
613 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
614 qe_firmware_info.vtraps[i] = iprop[i];
619 return &qe_firmware_info;
621 EXPORT_SYMBOL(qe_get_firmware_info);
623 unsigned int qe_get_num_of_risc(void)
625 struct device_node *qe;
627 unsigned int num_of_risc = 0;
630 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
632 /* Older devices trees did not have an "fsl,qe"
633 * compatible property, so we need to look for
634 * the QE node by name.
636 qe = of_find_node_by_type(NULL, "qe");
641 prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
642 if (prop && size == sizeof(*prop))
649 EXPORT_SYMBOL(qe_get_num_of_risc);
651 unsigned int qe_get_num_of_snums(void)
653 struct device_node *qe;
655 unsigned int num_of_snums;
658 num_of_snums = 28; /* The default number of snum for threads is 28 */
659 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
661 /* Older devices trees did not have an "fsl,qe"
662 * compatible property, so we need to look for
663 * the QE node by name.
665 qe = of_find_node_by_type(NULL, "qe");
670 prop = of_get_property(qe, "fsl,qe-num-snums", &size);
671 if (prop && size == sizeof(*prop)) {
672 num_of_snums = *prop;
673 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
674 /* No QE ever has fewer than 28 SNUMs */
675 pr_err("QE: number of snum is invalid\n");
685 EXPORT_SYMBOL(qe_get_num_of_snums);
687 static int __init qe_init(void)
689 struct device_node *np;
691 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
698 subsys_initcall(qe_init);
700 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
701 static int qe_resume(struct platform_device *ofdev)
703 if (!qe_alive_during_sleep())
708 static int qe_probe(struct platform_device *ofdev)
713 static const struct of_device_id qe_ids[] = {
714 { .compatible = "fsl,qe", },
718 static struct platform_driver qe_driver = {
721 .of_match_table = qe_ids,
727 builtin_platform_driver(qe_driver);
728 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */