drivers/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2010 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14 /* Notes:
  15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  17  *    are used for RX, odd chans for TX
  18  *
  19  * 2. In A0 stepping, UART will not support TX half empty flag
  20  *
  21  * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  22  *    asserted, only when the HW is reset the DDCD and DDSR will
  23  *    be triggered
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/console.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/circ_buf.h>
  32 #include <linux/delay.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial_mfd.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/pci.h>
  40 #include <linux/io.h>
  41 #include <linux/debugfs.h>
  42
  43 #define  MFD_HSU_A0_STEPPING    1
  44
  45 #define HSU_DMA_BUF_SIZE        2048
  46
  47 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  48 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  49
  50 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  51 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  52
  53 #define HSU_DMA_TIMEOUT_CHECK_FREQ      (HZ/10)
  54
  55 struct hsu_dma_buffer {
  56         u8              *buf;
  57         dma_addr_t      dma_addr;
  58         u32             dma_size;
  59         u32             ofs;
  60 };
  61
  62 struct hsu_dma_chan {
  63         u32     id;
  64         enum dma_data_direction dirt;
  65         struct uart_hsu_port    *uport;
  66         void __iomem            *reg;
  67         struct timer_list       rx_timer; /* only needed by RX channel */
  68 };
  69
  70 struct uart_hsu_port {
  71         struct uart_port        port;
  72         unsigned char           ier;
  73         unsigned char           lcr;
  74         unsigned char           mcr;
  75         unsigned int            lsr_break_flag;
  76         char                    name[12];
  77         int                     index;
  78         struct device           *dev;
  79
  80         struct hsu_dma_chan     *txc;
  81         struct hsu_dma_chan     *rxc;
  82         struct hsu_dma_buffer   txbuf;
  83         struct hsu_dma_buffer   rxbuf;
  84         int                     use_dma;        /* flag for DMA/PIO */
  85         int                     running;
  86         int                     dma_tx_on;
  87 };
  88
  89 /* Top level data structure of HSU */
  90 struct hsu_port {
  91         void __iomem    *reg;
  92         unsigned long   paddr;
  93         unsigned long   iolen;
  94         u32             irq;
  95
  96         struct uart_hsu_port    port[3];
  97         struct hsu_dma_chan     chans[10];
  98
  99         struct dentry *debugfs;
 100 };
 101
 102 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 103 {
 104         unsigned int val;
 105
 106         if (offset > UART_MSR) {
 107                 offset <<= 2;
 108                 val = readl(up->port.membase + offset);
 109         } else
 110                 val = (unsigned int)readb(up->port.membase + offset);
 111
 112         return val;
 113 }
 114
 115 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 116 {
 117         if (offset > UART_MSR) {
 118                 offset <<= 2;
 119                 writel(value, up->port.membase + offset);
 120         } else {
 121                 unsigned char val = value & 0xff;
 122                 writeb(val, up->port.membase + offset);
 123         }
 124 }
 125
 126 #ifdef CONFIG_DEBUG_FS
 127
 128 #define HSU_REGS_BUFSIZE        1024
 129
 130 static int hsu_show_regs_open(struct inode *inode, struct file *file)
 131 {
 132         file->private_data = inode->i_private;
 133         return 0;
 134 }
 135
 136 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 137                                 size_t count, loff_t *ppos)
 138 {
 139         struct uart_hsu_port *up = file->private_data;
 140         char *buf;
 141         u32 len = 0;
 142         ssize_t ret;
 143
 144         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 145         if (!buf)
 146                 return 0;
 147
 148         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 149                         "MFD HSU port[%d] regs:\n", up->index);
 150
 151         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 152                         "=================================\n");
 153         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 154                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 155         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 156                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 157         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 158                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 159         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 160                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 161         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 162                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 163         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 164                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 165         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 166                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 167         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 168                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 169         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 170                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 171         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 172                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 173
 174         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 175         kfree(buf);
 176         return ret;
 177 }
 178
 179 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 180                                 size_t count, loff_t *ppos)
 181 {
 182         struct hsu_dma_chan *chan = file->private_data;
 183         char *buf;
 184         u32 len = 0;
 185         ssize_t ret;
 186
 187         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 188         if (!buf)
 189                 return 0;
 190
 191         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 192                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 193
 194         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 195                         "=================================\n");
 196         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 197                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 198         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 199                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 200         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 201                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 202         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 203                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 204         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 205                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 206         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 207                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 208         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 209                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 210         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 211                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 212         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 213                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 214         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 215                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 216         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 217                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 218         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 219                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 220
 221         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 222         kfree(buf);
 223         return ret;
 224 }
 225
 226 static const struct file_operations port_regs_ops = {
 227         .owner          = THIS_MODULE,
 228         .open           = hsu_show_regs_open,
 229         .read           = port_show_regs,
 230 };
 231
 232 static const struct file_operations dma_regs_ops = {
 233         .owner          = THIS_MODULE,
 234         .open           = hsu_show_regs_open,
 235         .read           = dma_show_regs,
 236 };
 237
 238 static int hsu_debugfs_init(struct hsu_port *hsu)
 239 {
 240         int i;
 241         char name[32];
 242
 243         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 244         if (!hsu->debugfs)
 245                 return -ENOMEM;
 246
 247         for (i = 0; i < 3; i++) {
 248                 snprintf(name, sizeof(name), "port_%d_regs", i);
 249                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 250                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 251         }
 252
 253         for (i = 0; i < 6; i++) {
 254                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 255                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 256                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 257         }
 258
 259         return 0;
 260 }
 261
 262 static void hsu_debugfs_remove(struct hsu_port *hsu)
 263 {
 264         if (hsu->debugfs)
 265                 debugfs_remove_recursive(hsu->debugfs);
 266 }
 267
 268 #else
 269 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 270 {
 271         return 0;
 272 }
 273
 274 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 275 {
 276 }
 277 #endif /* CONFIG_DEBUG_FS */
 278
 279 static void serial_hsu_enable_ms(struct uart_port *port)
 280 {
 281         struct uart_hsu_port *up =
 282                 container_of(port, struct uart_hsu_port, port);
 283
 284         up->ier |= UART_IER_MSI;
 285         serial_out(up, UART_IER, up->ier);
 286 }
 287
 288 void hsu_dma_tx(struct uart_hsu_port *up)
 289 {
 290         struct circ_buf *xmit = &up->port.state->xmit;
 291         struct hsu_dma_buffer *dbuf = &up->txbuf;
 292         int count;
 293
 294         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 295         if (up->dma_tx_on)
 296                 return;
 297
 298         /* Update the circ buf info */
 299         xmit->tail += dbuf->ofs;
 300         xmit->tail &= UART_XMIT_SIZE - 1;
 301
 302         up->port.icount.tx += dbuf->ofs;
 303         dbuf->ofs = 0;
 304
 305         /* Disable the channel */
 306         chan_writel(up->txc, HSU_CH_CR, 0x0);
 307
 308         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 309                 dma_sync_single_for_device(up->port.dev,
 310                                            dbuf->dma_addr,
 311                                            dbuf->dma_size,
 312                                            DMA_TO_DEVICE);
 313
 314                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 315                 dbuf->ofs = count;
 316
 317                 /* Reprogram the channel */
 318                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 319                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 320
 321                 /* Reenable the channel */
 322                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 323                                                  | (0x1 << 8)
 324                                                  | (0x1 << 16)
 325                                                  | (0x1 << 24));
 326                 up->dma_tx_on = 1;
 327                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 328         }
 329
 330         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 331                 uart_write_wakeup(&up->port);
 332 }
 333
 334 /* The buffer is already cache coherent */
 335 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 336 {
 337         dbuf->ofs = 0;
 338
 339         chan_writel(rxc, HSU_CH_BSR, 32);
 340         chan_writel(rxc, HSU_CH_MOTSR, 4);
 341
 342         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 343         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 344         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 345                                          | (0x1 << 16)
 346                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 347                                          );
 348         chan_writel(rxc, HSU_CH_CR, 0x3);
 349
 350         mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
 351 }
 352
 353 /* Protected by spin_lock_irqsave(port->lock) */
 354 static void serial_hsu_start_tx(struct uart_port *port)
 355 {
 356         struct uart_hsu_port *up =
 357                 container_of(port, struct uart_hsu_port, port);
 358
 359         if (up->use_dma) {
 360                 hsu_dma_tx(up);
 361         } else if (!(up->ier & UART_IER_THRI)) {
 362                 up->ier |= UART_IER_THRI;
 363                 serial_out(up, UART_IER, up->ier);
 364         }
 365 }
 366
 367 static void serial_hsu_stop_tx(struct uart_port *port)
 368 {
 369         struct uart_hsu_port *up =
 370                 container_of(port, struct uart_hsu_port, port);
 371         struct hsu_dma_chan *txc = up->txc;
 372
 373         if (up->use_dma)
 374                 chan_writel(txc, HSU_CH_CR, 0x0);
 375         else if (up->ier & UART_IER_THRI) {
 376                 up->ier &= ~UART_IER_THRI;
 377                 serial_out(up, UART_IER, up->ier);
 378         }
 379 }
 380
 381 /* This is always called in spinlock protected mode, so
 382  * modify timeout timer is safe here */
 383 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 384 {
 385         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 386         struct hsu_dma_chan *chan = up->rxc;
 387         struct uart_port *port = &up->port;
 388         struct tty_struct *tty = port->state->port.tty;
 389         int count;
 390
 391         if (!tty)
 392                 return;
 393
 394         /*
 395          * First need to know how many is already transferred,
 396          * then check if its a timeout DMA irq, and return
 397          * the trail bytes out, push them up and reenable the
 398          * channel
 399          */
 400
 401         /* Timeout IRQ, need wait some time, see Errata 2 */
 402         if (int_sts & 0xf00)
 403                 udelay(2);
 404
 405         /* Stop the channel */
 406         chan_writel(chan, HSU_CH_CR, 0x0);
 407
 408         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 409         if (!count) {
 410                 /* Restart the channel before we leave */
 411                 chan_writel(chan, HSU_CH_CR, 0x3);
 412                 return;
 413         }
 414         del_timer(&chan->rx_timer);
 415
 416         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 417                         dbuf->dma_size, DMA_FROM_DEVICE);
 418
 419         /*
 420          * Head will only wrap around when we recycle
 421          * the DMA buffer, and when that happens, we
 422          * explicitly set tail to 0. So head will
 423          * always be greater than tail.
 424          */
 425         tty_insert_flip_string(tty, dbuf->buf, count);
 426         port->icount.rx += count;
 427
 428         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 429                         dbuf->dma_size, DMA_FROM_DEVICE);
 430
 431         /* Reprogram the channel */
 432         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 433         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 434         chan_writel(chan, HSU_CH_DCR, 0x1
 435                                          | (0x1 << 8)
 436                                          | (0x1 << 16)
 437                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 438                                          );
 439         tty_flip_buffer_push(tty);
 440
 441         chan_writel(chan, HSU_CH_CR, 0x3);
 442         chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
 443         add_timer(&chan->rx_timer);
 444
 445 }
 446
 447 static void serial_hsu_stop_rx(struct uart_port *port)
 448 {
 449         struct uart_hsu_port *up =
 450                 container_of(port, struct uart_hsu_port, port);
 451         struct hsu_dma_chan *chan = up->rxc;
 452
 453         if (up->use_dma)
 454                 chan_writel(chan, HSU_CH_CR, 0x2);
 455         else {
 456                 up->ier &= ~UART_IER_RLSI;
 457                 up->port.read_status_mask &= ~UART_LSR_DR;
 458                 serial_out(up, UART_IER, up->ier);
 459         }
 460 }
 461
 462 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 463 {
 464         struct tty_struct *tty = up->port.state->port.tty;
 465         unsigned int ch, flag;
 466         unsigned int max_count = 256;
 467
 468         if (!tty)
 469                 return;
 470
 471         do {
 472                 ch = serial_in(up, UART_RX);
 473                 flag = TTY_NORMAL;
 474                 up->port.icount.rx++;
 475
 476                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 477                                        UART_LSR_FE | UART_LSR_OE))) {
 478
 479                         dev_warn(up->dev, "We really rush into ERR/BI case"
 480                                 "status = 0x%02x", *status);
 481                         /* For statistics only */
 482                         if (*status & UART_LSR_BI) {
 483                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 484                                 up->port.icount.brk++;
 485                                 /*
 486                                  * We do the SysRQ and SAK checking
 487                                  * here because otherwise the break
 488                                  * may get masked by ignore_status_mask
 489                                  * or read_status_mask.
 490                                  */
 491                                 if (uart_handle_break(&up->port))
 492                                         goto ignore_char;
 493                         } else if (*status & UART_LSR_PE)
 494                                 up->port.icount.parity++;
 495                         else if (*status & UART_LSR_FE)
 496                                 up->port.icount.frame++;
 497                         if (*status & UART_LSR_OE)
 498                                 up->port.icount.overrun++;
 499
 500                         /* Mask off conditions which should be ignored. */
 501                         *status &= up->port.read_status_mask;
 502
 503 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 504                         if (up->port.cons &&
 505                                 up->port.cons->index == up->port.line) {
 506                                 /* Recover the break flag from console xmit */
 507                                 *status |= up->lsr_break_flag;
 508                                 up->lsr_break_flag = 0;
 509                         }
 510 #endif
 511                         if (*status & UART_LSR_BI) {
 512                                 flag = TTY_BREAK;
 513                         } else if (*status & UART_LSR_PE)
 514                                 flag = TTY_PARITY;
 515                         else if (*status & UART_LSR_FE)
 516                                 flag = TTY_FRAME;
 517                 }
 518
 519                 if (uart_handle_sysrq_char(&up->port, ch))
 520                         goto ignore_char;
 521
 522                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 523         ignore_char:
 524                 *status = serial_in(up, UART_LSR);
 525         } while ((*status & UART_LSR_DR) && max_count--);
 526         tty_flip_buffer_push(tty);
 527 }
 528
 529 static void transmit_chars(struct uart_hsu_port *up)
 530 {
 531         struct circ_buf *xmit = &up->port.state->xmit;
 532         int count;
 533
 534         if (up->port.x_char) {
 535                 serial_out(up, UART_TX, up->port.x_char);
 536                 up->port.icount.tx++;
 537                 up->port.x_char = 0;
 538                 return;
 539         }
 540         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 541                 serial_hsu_stop_tx(&up->port);
 542                 return;
 543         }
 544
 545 #ifndef MFD_HSU_A0_STEPPING
 546         count = up->port.fifosize / 2;
 547 #else
 548         /*
 549          * A0 only supports fully empty IRQ, and the first char written
 550          * into it won't clear the EMPT bit, so we may need be cautious
 551          * by useing a shorter buffer
 552          */
 553         count = up->port.fifosize - 4;
 554 #endif
 555         do {
 556                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 557                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 558
 559                 up->port.icount.tx++;
 560                 if (uart_circ_empty(xmit))
 561                         break;
 562         } while (--count > 0);
 563
 564         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 565                 uart_write_wakeup(&up->port);
 566
 567         if (uart_circ_empty(xmit))
 568                 serial_hsu_stop_tx(&up->port);
 569 }
 570
 571 static inline void check_modem_status(struct uart_hsu_port *up)
 572 {
 573         int status;
 574
 575         status = serial_in(up, UART_MSR);
 576
 577         if ((status & UART_MSR_ANY_DELTA) == 0)
 578                 return;
 579
 580         if (status & UART_MSR_TERI)
 581                 up->port.icount.rng++;
 582         if (status & UART_MSR_DDSR)
 583                 up->port.icount.dsr++;
 584         /* We may only get DDCD when HW init and reset */
 585         if (status & UART_MSR_DDCD)
 586                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 587         /* Will start/stop_tx accordingly */
 588         if (status & UART_MSR_DCTS)
 589                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 590
 591         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 592 }
 593
 594 /*
 595  * This handles the interrupt from one port.
 596  */
 597 static irqreturn_t port_irq(int irq, void *dev_id)
 598 {
 599         struct uart_hsu_port *up = dev_id;
 600         unsigned int iir, lsr;
 601         unsigned long flags;
 602
 603         if (unlikely(!up->running))
 604                 return IRQ_NONE;
 605
 606         spin_lock_irqsave(&up->port.lock, flags);
 607         if (up->use_dma) {
 608                 lsr = serial_in(up, UART_LSR);
 609                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 610                                        UART_LSR_FE | UART_LSR_OE)))
 611                         dev_warn(up->dev,
 612                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 613                                 lsr);
 614                 check_modem_status(up);
 615                 spin_unlock_irqrestore(&up->port.lock, flags);
 616                 return IRQ_HANDLED;
 617         }
 618
 619         iir = serial_in(up, UART_IIR);
 620         if (iir & UART_IIR_NO_INT) {
 621                 spin_unlock_irqrestore(&up->port.lock, flags);
 622                 return IRQ_NONE;
 623         }
 624
 625         lsr = serial_in(up, UART_LSR);
 626         if (lsr & UART_LSR_DR)
 627                 receive_chars(up, &lsr);
 628         check_modem_status(up);
 629
 630         /* lsr will be renewed during the receive_chars */
 631         if (lsr & UART_LSR_THRE)
 632                 transmit_chars(up);
 633
 634         spin_unlock_irqrestore(&up->port.lock, flags);
 635         return IRQ_HANDLED;
 636 }
 637
 638 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 639 {
 640         struct uart_hsu_port *up = chan->uport;
 641         unsigned long flags;
 642         u32 int_sts;
 643
 644         spin_lock_irqsave(&up->port.lock, flags);
 645
 646         if (!up->use_dma || !up->running)
 647                 goto exit;
 648
 649         /*
 650          * No matter what situation, need read clear the IRQ status
 651          * There is a bug, see Errata 5, HSD 2900918
 652          */
 653         int_sts = chan_readl(chan, HSU_CH_SR);
 654
 655         /* Rx channel */
 656         if (chan->dirt == DMA_FROM_DEVICE)
 657                 hsu_dma_rx(up, int_sts);
 658
 659         /* Tx channel */
 660         if (chan->dirt == DMA_TO_DEVICE) {
 661                 chan_writel(chan, HSU_CH_CR, 0x0);
 662                 up->dma_tx_on = 0;
 663                 hsu_dma_tx(up);
 664         }
 665
 666 exit:
 667         spin_unlock_irqrestore(&up->port.lock, flags);
 668         return;
 669 }
 670
 671 static irqreturn_t dma_irq(int irq, void *dev_id)
 672 {
 673         struct hsu_port *hsu = dev_id;
 674         u32 int_sts, i;
 675
 676         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 677
 678         /* Currently we only have 6 channels may be used */
 679         for (i = 0; i < 6; i++) {
 680                 if (int_sts & 0x1)
 681                         dma_chan_irq(&hsu->chans[i]);
 682                 int_sts >>= 1;
 683         }
 684
 685         return IRQ_HANDLED;
 686 }
 687
 688 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 689 {
 690         struct uart_hsu_port *up =
 691                 container_of(port, struct uart_hsu_port, port);
 692         unsigned long flags;
 693         unsigned int ret;
 694
 695         spin_lock_irqsave(&up->port.lock, flags);
 696         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 697         spin_unlock_irqrestore(&up->port.lock, flags);
 698
 699         return ret;
 700 }
 701
 702 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 703 {
 704         struct uart_hsu_port *up =
 705                 container_of(port, struct uart_hsu_port, port);
 706         unsigned char status;
 707         unsigned int ret;
 708
 709         status = serial_in(up, UART_MSR);
 710
 711         ret = 0;
 712         if (status & UART_MSR_DCD)
 713                 ret |= TIOCM_CAR;
 714         if (status & UART_MSR_RI)
 715                 ret |= TIOCM_RNG;
 716         if (status & UART_MSR_DSR)
 717                 ret |= TIOCM_DSR;
 718         if (status & UART_MSR_CTS)
 719                 ret |= TIOCM_CTS;
 720         return ret;
 721 }
 722
 723 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 724 {
 725         struct uart_hsu_port *up =
 726                 container_of(port, struct uart_hsu_port, port);
 727         unsigned char mcr = 0;
 728
 729         if (mctrl & TIOCM_RTS)
 730                 mcr |= UART_MCR_RTS;
 731         if (mctrl & TIOCM_DTR)
 732                 mcr |= UART_MCR_DTR;
 733         if (mctrl & TIOCM_OUT1)
 734                 mcr |= UART_MCR_OUT1;
 735         if (mctrl & TIOCM_OUT2)
 736                 mcr |= UART_MCR_OUT2;
 737         if (mctrl & TIOCM_LOOP)
 738                 mcr |= UART_MCR_LOOP;
 739
 740         mcr |= up->mcr;
 741
 742         serial_out(up, UART_MCR, mcr);
 743 }
 744
 745 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 746 {
 747         struct uart_hsu_port *up =
 748                 container_of(port, struct uart_hsu_port, port);
 749         unsigned long flags;
 750
 751         spin_lock_irqsave(&up->port.lock, flags);
 752         if (break_state == -1)
 753                 up->lcr |= UART_LCR_SBC;
 754         else
 755                 up->lcr &= ~UART_LCR_SBC;
 756         serial_out(up, UART_LCR, up->lcr);
 757         spin_unlock_irqrestore(&up->port.lock, flags);
 758 }
 759
 760 /*
 761  * What special to do:
 762  * 1. chose the 64B fifo mode
 763  * 2. make sure not to select half empty mode for A0 stepping
 764  * 3. start dma or pio depends on configuration
 765  * 4. we only allocate dma memory when needed
 766  */
 767 static int serial_hsu_startup(struct uart_port *port)
 768 {
 769         struct uart_hsu_port *up =
 770                 container_of(port, struct uart_hsu_port, port);
 771         unsigned long flags;
 772
 773         /*
 774          * Clear the FIFO buffers and disable them.
 775          * (they will be reenabled in set_termios())
 776          */
 777         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 778         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 779                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 780         serial_out(up, UART_FCR, 0);
 781
 782         /* Clear the interrupt registers. */
 783         (void) serial_in(up, UART_LSR);
 784         (void) serial_in(up, UART_RX);
 785         (void) serial_in(up, UART_IIR);
 786         (void) serial_in(up, UART_MSR);
 787
 788         /* Now, initialize the UART, default is 8n1 */
 789         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 790
 791         spin_lock_irqsave(&up->port.lock, flags);
 792
 793         up->port.mctrl |= TIOCM_OUT2;
 794         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 795
 796         /*
 797          * Finally, enable interrupts.  Note: Modem status interrupts
 798          * are set via set_termios(), which will be occurring imminently
 799          * anyway, so we don't enable them here.
 800          */
 801         if (!up->use_dma)
 802                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 803         else
 804                 up->ier = 0;
 805         serial_out(up, UART_IER, up->ier);
 806
 807         spin_unlock_irqrestore(&up->port.lock, flags);
 808
 809         /* DMA init */
 810         if (up->use_dma) {
 811                 struct hsu_dma_buffer *dbuf;
 812                 struct circ_buf *xmit = &port->state->xmit;
 813
 814                 up->dma_tx_on = 0;
 815
 816                 /* First allocate the RX buffer */
 817                 dbuf = &up->rxbuf;
 818                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 819                 if (!dbuf->buf) {
 820                         up->use_dma = 0;
 821                         goto exit;
 822                 }
 823                 dbuf->dma_addr = dma_map_single(port->dev,
 824                                                 dbuf->buf,
 825                                                 HSU_DMA_BUF_SIZE,
 826                                                 DMA_FROM_DEVICE);
 827                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 828
 829                 /* Start the RX channel right now */
 830                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 831
 832                 /* Next init the TX DMA */
 833                 dbuf = &up->txbuf;
 834                 dbuf->buf = xmit->buf;
 835                 dbuf->dma_addr = dma_map_single(port->dev,
 836                                                dbuf->buf,
 837                                                UART_XMIT_SIZE,
 838                                                DMA_TO_DEVICE);
 839                 dbuf->dma_size = UART_XMIT_SIZE;
 840
 841                 /* This should not be changed all around */
 842                 chan_writel(up->txc, HSU_CH_BSR, 32);
 843                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 844                 dbuf->ofs = 0;
 845         }
 846
 847 exit:
 848          /* And clear the interrupt registers again for luck. */
 849         (void) serial_in(up, UART_LSR);
 850         (void) serial_in(up, UART_RX);
 851         (void) serial_in(up, UART_IIR);
 852         (void) serial_in(up, UART_MSR);
 853
 854         up->running = 1;
 855         return 0;
 856 }
 857
 858 static void serial_hsu_shutdown(struct uart_port *port)
 859 {
 860         struct uart_hsu_port *up =
 861                 container_of(port, struct uart_hsu_port, port);
 862         unsigned long flags;
 863
 864         del_timer_sync(&up->rxc->rx_timer);
 865
 866         /* Disable interrupts from this port */
 867         up->ier = 0;
 868         serial_out(up, UART_IER, 0);
 869         up->running = 0;
 870
 871         spin_lock_irqsave(&up->port.lock, flags);
 872         up->port.mctrl &= ~TIOCM_OUT2;
 873         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 874         spin_unlock_irqrestore(&up->port.lock, flags);
 875
 876         /* Disable break condition and FIFOs */
 877         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 878         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 879                                   UART_FCR_CLEAR_RCVR |
 880                                   UART_FCR_CLEAR_XMIT);
 881         serial_out(up, UART_FCR, 0);
 882 }
 883
 884 static void
 885 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 886                        struct ktermios *old)
 887 {
 888         struct uart_hsu_port *up =
 889                         container_of(port, struct uart_hsu_port, port);
 890         struct tty_struct *tty = port->state->port.tty;
 891         unsigned char cval, fcr = 0;
 892         unsigned long flags;
 893         unsigned int baud, quot;
 894         u32 mul = 0x3600;
 895         u32 ps = 0x10;
 896
 897         switch (termios->c_cflag & CSIZE) {
 898         case CS5:
 899                 cval = UART_LCR_WLEN5;
 900                 break;
 901         case CS6:
 902                 cval = UART_LCR_WLEN6;
 903                 break;
 904         case CS7:
 905                 cval = UART_LCR_WLEN7;
 906                 break;
 907         default:
 908         case CS8:
 909                 cval = UART_LCR_WLEN8;
 910                 break;
 911         }
 912
 913         /* CMSPAR isn't supported by this driver */
 914         if (tty)
 915                 tty->termios->c_cflag &= ~CMSPAR;
 916
 917         if (termios->c_cflag & CSTOPB)
 918                 cval |= UART_LCR_STOP;
 919         if (termios->c_cflag & PARENB)
 920                 cval |= UART_LCR_PARITY;
 921         if (!(termios->c_cflag & PARODD))
 922                 cval |= UART_LCR_EPAR;
 923
 924         /*
 925          * For those basic low baud rate we can get the direct
 926          * scalar from 2746800, like 115200 = 2746800/24, for those
 927          * higher baud rate, we have to handle them case by case,
 928          * but DIV reg is never touched as its default value 0x3d09
 929          */
 930         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 931         quot = uart_get_divisor(port, baud);
 932
 933         switch (baud) {
 934         case 3500000:
 935                 mul = 0x3345;
 936                 ps = 0xC;
 937                 quot = 1;
 938                 break;
 939         case 2500000:
 940                 mul = 0x2710;
 941                 ps = 0x10;
 942                 quot = 1;
 943                 break;
 944         case 18432000:
 945                 mul = 0x2400;
 946                 ps = 0x10;
 947                 quot = 1;
 948                 break;
 949         case 1500000:
 950                 mul = 0x1D4C;
 951                 ps = 0xc;
 952                 quot = 1;
 953                 break;
 954         default:
 955                 ;
 956         }
 957
 958         if ((up->port.uartclk / quot) < (2400 * 16))
 959                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
 960         else if ((up->port.uartclk / quot) < (230400 * 16))
 961                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
 962         else
 963                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
 964
 965         fcr |= UART_FCR_HSU_64B_FIFO;
 966 #ifdef MFD_HSU_A0_STEPPING
 967         /* A0 doesn't support half empty IRQ */
 968         fcr |= UART_FCR_FULL_EMPT_TXI;
 969 #endif
 970
 971         /*
 972          * Ok, we're now changing the port state.  Do it with
 973          * interrupts disabled.
 974          */
 975         spin_lock_irqsave(&up->port.lock, flags);
 976
 977         /* Update the per-port timeout */
 978         uart_update_timeout(port, termios->c_cflag, baud);
 979
 980         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 981         if (termios->c_iflag & INPCK)
 982                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 983         if (termios->c_iflag & (BRKINT | PARMRK))
 984                 up->port.read_status_mask |= UART_LSR_BI;
 985
 986         /* Characters to ignore */
 987         up->port.ignore_status_mask = 0;
 988         if (termios->c_iflag & IGNPAR)
 989                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 990         if (termios->c_iflag & IGNBRK) {
 991                 up->port.ignore_status_mask |= UART_LSR_BI;
 992                 /*
 993                  * If we're ignoring parity and break indicators,
 994                  * ignore overruns too (for real raw support).
 995                  */
 996                 if (termios->c_iflag & IGNPAR)
 997                         up->port.ignore_status_mask |= UART_LSR_OE;
 998         }
 999
1000         /* Ignore all characters if CREAD is not set */
1001         if ((termios->c_cflag & CREAD) == 0)
1002                 up->port.ignore_status_mask |= UART_LSR_DR;
1003
1004         /*
1005          * CTS flow control flag and modem status interrupts, disable
1006          * MSI by default
1007          */
1008         up->ier &= ~UART_IER_MSI;
1009         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1010                 up->ier |= UART_IER_MSI;
1011
1012         serial_out(up, UART_IER, up->ier);
1013
1014         if (termios->c_cflag & CRTSCTS)
1015                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1016         else
1017                 up->mcr &= ~UART_MCR_AFE;
1018
1019         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1020         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1021         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1022         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1023         serial_out(up, UART_MUL, mul);                  /* set MUL */
1024         serial_out(up, UART_PS, ps);                    /* set PS */
1025         up->lcr = cval;                                 /* Save LCR */
1026         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1027         serial_out(up, UART_FCR, fcr);
1028         spin_unlock_irqrestore(&up->port.lock, flags);
1029 }
1030
1031 static void
1032 serial_hsu_pm(struct uart_port *port, unsigned int state,
1033               unsigned int oldstate)
1034 {
1035 }
1036
1037 static void serial_hsu_release_port(struct uart_port *port)
1038 {
1039 }
1040
1041 static int serial_hsu_request_port(struct uart_port *port)
1042 {
1043         return 0;
1044 }
1045
1046 static void serial_hsu_config_port(struct uart_port *port, int flags)
1047 {
1048         struct uart_hsu_port *up =
1049                 container_of(port, struct uart_hsu_port, port);
1050         up->port.type = PORT_MFD;
1051 }
1052
1053 static int
1054 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1055 {
1056         /* We don't want the core code to modify any port params */
1057         return -EINVAL;
1058 }
1059
1060 static const char *
1061 serial_hsu_type(struct uart_port *port)
1062 {
1063         struct uart_hsu_port *up =
1064                 container_of(port, struct uart_hsu_port, port);
1065         return up->name;
1066 }
1067
1068 /* Mainly for uart console use */
1069 static struct uart_hsu_port *serial_hsu_ports[3];
1070 static struct uart_driver serial_hsu_reg;
1071
1072 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1073
1074 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1075
1076 /* Wait for transmitter & holding register to empty */
1077 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1078 {
1079         unsigned int status, tmout = 1000;
1080
1081         /* Wait up to 1ms for the character to be sent. */
1082         do {
1083                 status = serial_in(up, UART_LSR);
1084
1085                 if (status & UART_LSR_BI)
1086                         up->lsr_break_flag = UART_LSR_BI;
1087
1088                 if (--tmout == 0)
1089                         break;
1090                 udelay(1);
1091         } while (!(status & BOTH_EMPTY));
1092
1093         /* Wait up to 1s for flow control if necessary */
1094         if (up->port.flags & UPF_CONS_FLOW) {
1095                 tmout = 1000000;
1096                 while (--tmout &&
1097                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1098                         udelay(1);
1099         }
1100 }
1101
1102 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1103 {
1104         struct uart_hsu_port *up =
1105                 container_of(port, struct uart_hsu_port, port);
1106
1107         wait_for_xmitr(up);
1108         serial_out(up, UART_TX, ch);
1109 }
1110
1111 /*
1112  * Print a string to the serial port trying not to disturb
1113  * any possible real use of the port...
1114  *
1115  *      The console_lock must be held when we get here.
1116  */
1117 static void
1118 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1119 {
1120         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1121         unsigned long flags;
1122         unsigned int ier;
1123         int locked = 1;
1124
1125         local_irq_save(flags);
1126         if (up->port.sysrq)
1127                 locked = 0;
1128         else if (oops_in_progress) {
1129                 locked = spin_trylock(&up->port.lock);
1130         } else
1131                 spin_lock(&up->port.lock);
1132
1133         /* First save the IER then disable the interrupts */
1134         ier = serial_in(up, UART_IER);
1135         serial_out(up, UART_IER, 0);
1136
1137         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1138
1139         /*
1140          * Finally, wait for transmitter to become empty
1141          * and restore the IER
1142          */
1143         wait_for_xmitr(up);
1144         serial_out(up, UART_IER, ier);
1145
1146         if (locked)
1147                 spin_unlock(&up->port.lock);
1148         local_irq_restore(flags);
1149 }
1150
1151 static struct console serial_hsu_console;
1152
1153 static int __init
1154 serial_hsu_console_setup(struct console *co, char *options)
1155 {
1156         struct uart_hsu_port *up;
1157         int baud = 115200;
1158         int bits = 8;
1159         int parity = 'n';
1160         int flow = 'n';
1161         int ret;
1162
1163         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1164                 co->index = 0;
1165         up = serial_hsu_ports[co->index];
1166         if (!up)
1167                 return -ENODEV;
1168
1169         if (options)
1170                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171
1172         ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1173
1174         return ret;
1175 }
1176
1177 static struct console serial_hsu_console = {
1178         .name           = "ttyMFD",
1179         .write          = serial_hsu_console_write,
1180         .device         = uart_console_device,
1181         .setup          = serial_hsu_console_setup,
1182         .flags          = CON_PRINTBUFFER,
1183         .index          = 2,
1184         .data           = &serial_hsu_reg,
1185 };
1186 #endif
1187
1188 struct uart_ops serial_hsu_pops = {
1189         .tx_empty       = serial_hsu_tx_empty,
1190         .set_mctrl      = serial_hsu_set_mctrl,
1191         .get_mctrl      = serial_hsu_get_mctrl,
1192         .stop_tx        = serial_hsu_stop_tx,
1193         .start_tx       = serial_hsu_start_tx,
1194         .stop_rx        = serial_hsu_stop_rx,
1195         .enable_ms      = serial_hsu_enable_ms,
1196         .break_ctl      = serial_hsu_break_ctl,
1197         .startup        = serial_hsu_startup,
1198         .shutdown       = serial_hsu_shutdown,
1199         .set_termios    = serial_hsu_set_termios,
1200         .pm             = serial_hsu_pm,
1201         .type           = serial_hsu_type,
1202         .release_port   = serial_hsu_release_port,
1203         .request_port   = serial_hsu_request_port,
1204         .config_port    = serial_hsu_config_port,
1205         .verify_port    = serial_hsu_verify_port,
1206 };
1207
1208 static struct uart_driver serial_hsu_reg = {
1209         .owner          = THIS_MODULE,
1210         .driver_name    = "MFD serial",
1211         .dev_name       = "ttyMFD",
1212         .major          = TTY_MAJOR,
1213         .minor          = 128,
1214         .nr             = 3,
1215 };
1216
1217 #ifdef CONFIG_PM
1218 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1219 {
1220         void *priv = pci_get_drvdata(pdev);
1221         struct uart_hsu_port *up;
1222
1223         /* Make sure this is not the internal dma controller */
1224         if (priv && (pdev->device != 0x081E)) {
1225                 up = priv;
1226                 uart_suspend_port(&serial_hsu_reg, &up->port);
1227         }
1228
1229         pci_save_state(pdev);
1230         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1231         return 0;
1232 }
1233
1234 static int serial_hsu_resume(struct pci_dev *pdev)
1235 {
1236         void *priv = pci_get_drvdata(pdev);
1237         struct uart_hsu_port *up;
1238         int ret;
1239
1240         pci_set_power_state(pdev, PCI_D0);
1241         pci_restore_state(pdev);
1242
1243         ret = pci_enable_device(pdev);
1244         if (ret)
1245                 dev_warn(&pdev->dev,
1246                         "HSU: can't re-enable device, try to continue\n");
1247
1248         if (priv && (pdev->device != 0x081E)) {
1249                 up = priv;
1250                 uart_resume_port(&serial_hsu_reg, &up->port);
1251         }
1252         return 0;
1253 }
1254 #else
1255 #define serial_hsu_suspend      NULL
1256 #define serial_hsu_resume       NULL
1257 #endif
1258
1259 /* temp global pointer before we settle down on using one or four PCI dev */
1260 static struct hsu_port *phsu;
1261
1262 static int serial_hsu_probe(struct pci_dev *pdev,
1263                                 const struct pci_device_id *ent)
1264 {
1265         struct uart_hsu_port *uport;
1266         int index, ret;
1267
1268         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1269                 pdev->vendor, pdev->device);
1270
1271         switch (pdev->device) {
1272         case 0x081B:
1273                 index = 0;
1274                 break;
1275         case 0x081C:
1276                 index = 1;
1277                 break;
1278         case 0x081D:
1279                 index = 2;
1280                 break;
1281         case 0x081E:
1282                 /* internal DMA controller */
1283                 index = 3;
1284                 break;
1285         default:
1286                 dev_err(&pdev->dev, "HSU: out of index!");
1287                 return -ENODEV;
1288         }
1289
1290         ret = pci_enable_device(pdev);
1291         if (ret)
1292                 return ret;
1293
1294         if (index == 3) {
1295                 /* DMA controller */
1296                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1297                 if (ret) {
1298                         dev_err(&pdev->dev, "can not get IRQ\n");
1299                         goto err_disable;
1300                 }
1301                 pci_set_drvdata(pdev, phsu);
1302         } else {
1303                 /* UART port 0~2 */
1304                 uport = &phsu->port[index];
1305                 uport->port.irq = pdev->irq;
1306                 uport->port.dev = &pdev->dev;
1307                 uport->dev = &pdev->dev;
1308
1309                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1310                 if (ret) {
1311                         dev_err(&pdev->dev, "can not get IRQ\n");
1312                         goto err_disable;
1313                 }
1314                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1315
1316 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1317                 if (index == 2) {
1318                         register_console(&serial_hsu_console);
1319                         uport->port.cons = &serial_hsu_console;
1320                 }
1321 #endif
1322                 pci_set_drvdata(pdev, uport);
1323         }
1324
1325         return 0;
1326
1327 err_disable:
1328         pci_disable_device(pdev);
1329         return ret;
1330 }
1331
1332 static void hsu_dma_rx_timeout(unsigned long data)
1333 {
1334         struct hsu_dma_chan *chan = (void *)data;
1335         struct uart_hsu_port *up = chan->uport;
1336         struct hsu_dma_buffer *dbuf = &up->rxbuf;
1337         int count = 0;
1338         unsigned long flags;
1339
1340         spin_lock_irqsave(&up->port.lock, flags);
1341
1342         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1343
1344         if (!count) {
1345                 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1346                 goto exit;
1347         }
1348
1349         hsu_dma_rx(up, 0);
1350 exit:
1351         spin_unlock_irqrestore(&up->port.lock, flags);
1352 }
1353
1354 static void hsu_global_init(void)
1355 {
1356         struct hsu_port *hsu;
1357         struct uart_hsu_port *uport;
1358         struct hsu_dma_chan *dchan;
1359         int i, ret;
1360
1361         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1362         if (!hsu)
1363                 return;
1364
1365         /* Get basic io resource and map it */
1366         hsu->paddr = 0xffa28000;
1367         hsu->iolen = 0x1000;
1368
1369         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1370                 pr_warning("HSU: error in request mem region\n");
1371
1372         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1373         if (!hsu->reg) {
1374                 pr_err("HSU: error in ioremap\n");
1375                 ret = -ENOMEM;
1376                 goto err_free_region;
1377         }
1378
1379         /* Initialise the 3 UART ports */
1380         uport = hsu->port;
1381         for (i = 0; i < 3; i++) {
1382                 uport->port.type = PORT_MFD;
1383                 uport->port.iotype = UPIO_MEM;
1384                 uport->port.mapbase = (resource_size_t)hsu->paddr
1385                                         + HSU_PORT_REG_OFFSET
1386                                         + i * HSU_PORT_REG_LENGTH;
1387                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1388                                         + i * HSU_PORT_REG_LENGTH;
1389
1390                 sprintf(uport->name, "hsu_port%d", i);
1391                 uport->port.fifosize = 64;
1392                 uport->port.ops = &serial_hsu_pops;
1393                 uport->port.line = i;
1394                 uport->port.flags = UPF_IOREMAP;
1395                 /* set the scalable maxim support rate to 2746800 bps */
1396                 uport->port.uartclk = 115200 * 24 * 16;
1397
1398                 uport->running = 0;
1399                 uport->txc = &hsu->chans[i * 2];
1400                 uport->rxc = &hsu->chans[i * 2 + 1];
1401
1402                 serial_hsu_ports[i] = uport;
1403                 uport->index = i;
1404                 uport++;
1405         }
1406
1407         /* Initialise 6 dma channels */
1408         dchan = hsu->chans;
1409         for (i = 0; i < 6; i++) {
1410                 dchan->id = i;
1411                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1412                 dchan->uport = &hsu->port[i/2];
1413                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1414                                 i * HSU_DMA_CHANS_REG_LENGTH;
1415
1416                 /* Work around for RX */
1417                 if (dchan->dirt == DMA_FROM_DEVICE) {
1418                         init_timer(&dchan->rx_timer);
1419                         dchan->rx_timer.function = hsu_dma_rx_timeout;
1420                         dchan->rx_timer.data = (unsigned long)dchan;
1421                 }
1422                 dchan++;
1423         }
1424
1425         phsu = hsu;
1426
1427         hsu_debugfs_init(hsu);
1428         return;
1429
1430 err_free_region:
1431         release_mem_region(hsu->paddr, hsu->iolen);
1432         kfree(hsu);
1433         return;
1434 }
1435
1436 static void serial_hsu_remove(struct pci_dev *pdev)
1437 {
1438         struct hsu_port *hsu;
1439         int i;
1440
1441         hsu = pci_get_drvdata(pdev);
1442         if (!hsu)
1443                 return;
1444
1445         for (i = 0; i < 3; i++)
1446                 uart_remove_one_port(&serial_hsu_reg, &hsu->port[i].port);
1447
1448         pci_set_drvdata(pdev, NULL);
1449         free_irq(hsu->irq, hsu);
1450         pci_disable_device(pdev);
1451 }
1452
1453 /* First 3 are UART ports, and the 4th is the DMA */
1454 static const struct pci_device_id pci_ids[] __devinitdata = {
1455         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1456         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1457         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1458         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1459         {},
1460 };
1461
1462 static struct pci_driver hsu_pci_driver = {
1463         .name =         "HSU serial",
1464         .id_table =     pci_ids,
1465         .probe =        serial_hsu_probe,
1466         .remove =       __devexit_p(serial_hsu_remove),
1467         .suspend =      serial_hsu_suspend,
1468         .resume =       serial_hsu_resume,
1469 };
1470
1471 static int __init hsu_pci_init(void)
1472 {
1473         int ret;
1474
1475         hsu_global_init();
1476
1477         ret = uart_register_driver(&serial_hsu_reg);
1478         if (ret)
1479                 return ret;
1480
1481         return pci_register_driver(&hsu_pci_driver);
1482 }
1483
1484 static void __exit hsu_pci_exit(void)
1485 {
1486         pci_unregister_driver(&hsu_pci_driver);
1487         uart_unregister_driver(&serial_hsu_reg);
1488
1489         hsu_debugfs_remove(phsu);
1490
1491         kfree(phsu);
1492 }
1493
1494 module_init(hsu_pci_init);
1495 module_exit(hsu_pci_exit);
1496
1497 MODULE_LICENSE("GPL v2");
1498 MODULE_ALIAS("platform:medfield-hsu");