drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/string.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/tty.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/8250_pci.h>
  24 #include <linux/bitops.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include "8250.h"
  30
  31 #undef SERIAL_DEBUG_PCI
  32
  33 /*
  34  * init function returns:
  35  *  > 0 - number of ports
  36  *  = 0 - use board->num_ports
  37  *  < 0 - error
  38  */
  39 struct pci_serial_quirk {
  40         u32     vendor;
  41         u32     device;
  42         u32     subvendor;
  43         u32     subdevice;
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static void moan_device(const char *str, struct pci_dev *dev)
  62 {
  63         printk(KERN_WARNING
  64                "%s: %s\n"
  65                "Please send the output of lspci -vv, this\n"
  66                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  67                "manufacturer and name of serial board or\n"
  68                "modem board to rmk+serial@arm.linux.org.uk.\n",
  69                pci_name(dev), str, dev->vendor, dev->device,
  70                dev->subsystem_vendor, dev->subsystem_device);
  71 }
  72
  73 static int
  74 setup_port(struct serial_private *priv, struct uart_port *port,
  75            int bar, int offset, int regshift)
  76 {
  77         struct pci_dev *dev = priv->dev;
  78         unsigned long base, len;
  79
  80         if (bar >= PCI_NUM_BAR_RESOURCES)
  81                 return -EINVAL;
  82
  83         base = pci_resource_start(dev, bar);
  84
  85         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  86                 len =  pci_resource_len(dev, bar);
  87
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->iotype = UPIO_MEM;
  94                 port->iobase = 0;
  95                 port->mapbase = base + offset;
  96                 port->membase = priv->remapped_bar[bar] + offset;
  97                 port->regshift = regshift;
  98         } else {
  99                 port->iotype = UPIO_PORT;
 100                 port->iobase = base + offset;
 101                 port->mapbase = 0;
 102                 port->membase = NULL;
 103                 port->regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 110  */
 111 static int addidata_apci7800_setup(struct serial_private *priv,
 112                                 const struct pciserial_board *board,
 113                                 struct uart_port *port, int idx)
 114 {
 115         unsigned int bar = 0, offset = board->first_offset;
 116         bar = FL_GET_BASE(board->flags);
 117
 118         if (idx < 2) {
 119                 offset += idx * board->uart_offset;
 120         } else if ((idx >= 2) && (idx < 4)) {
 121                 bar += 1;
 122                 offset += ((idx - 2) * board->uart_offset);
 123         } else if ((idx >= 4) && (idx < 6)) {
 124                 bar += 2;
 125                 offset += ((idx - 4) * board->uart_offset);
 126         } else if (idx >= 6) {
 127                 bar += 3;
 128                 offset += ((idx - 6) * board->uart_offset);
 129         }
 130
 131         return setup_port(priv, port, bar, offset, board->reg_shift);
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 140               struct uart_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(priv, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct serial_private *priv,
 194                 const struct pciserial_board *board,
 195                 struct uart_port *port, int idx)
 196 {
 197         unsigned int offset = board->first_offset;
 198         unsigned int bar = FL_GET_BASE(board->flags);
 199
 200         switch (priv->dev->subsystem_device) {
 201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 202                 if (idx == 3)
 203                         idx++;
 204                 break;
 205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 206                 if (idx > 0)
 207                         idx++;
 208                 if (idx > 2)
 209                         idx++;
 210                 break;
 211         }
 212         if (idx > 2)
 213                 offset = 0x18;
 214
 215         offset += idx * board->uart_offset;
 216
 217         return setup_port(priv, port, bar, offset, board->reg_shift);
 218 }
 219
 220 /*
 221  * Added for EKF Intel i960 serial boards
 222  */
 223 static int pci_inteli960ni_init(struct pci_dev *dev)
 224 {
 225         unsigned long oldval;
 226
 227         if (!(dev->subsystem_device & 0x1000))
 228                 return -ENODEV;
 229
 230         /* is firmware started? */
 231         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 232         if (oldval == 0x00001000L) { /* RESET value */
 233                 printk(KERN_DEBUG "Local i960 firmware missing");
 234                 return -ENODEV;
 235         }
 236         return 0;
 237 }
 238
 239 /*
 240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 241  * that the card interrupt be explicitly enabled or disabled.  This
 242  * seems to be mainly needed on card using the PLX which also use I/O
 243  * mapped memory.
 244  */
 245 static int pci_plx9050_init(struct pci_dev *dev)
 246 {
 247         u8 irq_config;
 248         void __iomem *p;
 249
 250         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 251                 moan_device("no memory in bar 0", dev);
 252                 return 0;
 253         }
 254
 255         irq_config = 0x41;
 256         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 257             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 258                 irq_config = 0x43;
 259
 260         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 261             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 262                 /*
 263                  * As the megawolf cards have the int pins active
 264                  * high, and have 2 UART chips, both ints must be
 265                  * enabled on the 9050. Also, the UARTS are set in
 266                  * 16450 mode by default, so we have to enable the
 267                  * 16C950 'enhanced' mode so that we can use the
 268                  * deep FIFOs
 269                  */
 270                 irq_config = 0x5b;
 271         /*
 272          * enable/disable interrupts
 273          */
 274         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 275         if (p == NULL)
 276                 return -ENOMEM;
 277         writel(irq_config, p + 0x4c);
 278
 279         /*
 280          * Read the register back to ensure that it took effect.
 281          */
 282         readl(p + 0x4c);
 283         iounmap(p);
 284
 285         return 0;
 286 }
 287
 288 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 289 {
 290         u8 __iomem *p;
 291
 292         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 293                 return;
 294
 295         /*
 296          * disable interrupts
 297          */
 298         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 299         if (p != NULL) {
 300                 writel(0, p + 0x4c);
 301
 302                 /*
 303                  * Read the register back to ensure that it took effect.
 304                  */
 305                 readl(p + 0x4c);
 306                 iounmap(p);
 307         }
 308 }
 309
 310 #define NI8420_INT_ENABLE_REG   0x38
 311 #define NI8420_INT_ENABLE_BIT   0x2000
 312
 313 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 314 {
 315         void __iomem *p;
 316         unsigned long base, len;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         base = pci_resource_start(dev, bar);
 325         len =  pci_resource_len(dev, bar);
 326         p = ioremap_nocache(base, len);
 327         if (p == NULL)
 328                 return;
 329
 330         /* Disable the CPU Interrupt */
 331         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 332                p + NI8420_INT_ENABLE_REG);
 333         iounmap(p);
 334 }
 335
 336
 337 /* MITE registers */
 338 #define MITE_IOWBSR1    0xc4
 339 #define MITE_IOWCR1     0xf4
 340 #define MITE_LCIMR1     0x08
 341 #define MITE_LCIMR2     0x10
 342
 343 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 344
 345 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 346 {
 347         void __iomem *p;
 348         unsigned long base, len;
 349         unsigned int bar = 0;
 350
 351         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 352                 moan_device("no memory in bar", dev);
 353                 return;
 354         }
 355
 356         base = pci_resource_start(dev, bar);
 357         len =  pci_resource_len(dev, bar);
 358         p = ioremap_nocache(base, len);
 359         if (p == NULL)
 360                 return;
 361
 362         /* Disable the CPU Interrupt */
 363         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 364         iounmap(p);
 365 }
 366
 367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 368 static int
 369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 370                 struct uart_port *port, int idx)
 371 {
 372         unsigned int bar, offset = board->first_offset;
 373
 374         bar = 0;
 375
 376         if (idx < 4) {
 377                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 378                 offset += idx * board->uart_offset;
 379         } else if (idx < 8) {
 380                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 381                 offset += idx * board->uart_offset + 0xC00;
 382         } else /* we have only 8 ports on PMC-OCTALPRO */
 383                 return 1;
 384
 385         return setup_port(priv, port, bar, offset, board->reg_shift);
 386 }
 387
 388 /*
 389 * This does initialization for PMC OCTALPRO cards:
 390 * maps the device memory, resets the UARTs (needed, bc
 391 * if the module is removed and inserted again, the card
 392 * is in the sleep mode) and enables global interrupt.
 393 */
 394
 395 /* global control register offset for SBS PMC-OctalPro */
 396 #define OCT_REG_CR_OFF          0x500
 397
 398 static int sbs_init(struct pci_dev *dev)
 399 {
 400         u8 __iomem *p;
 401
 402         p = pci_ioremap_bar(dev, 0);
 403
 404         if (p == NULL)
 405                 return -ENOMEM;
 406         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 407         writeb(0x10, p + OCT_REG_CR_OFF);
 408         udelay(50);
 409         writeb(0x0, p + OCT_REG_CR_OFF);
 410
 411         /* Set bit-2 (INTENABLE) of Control Register */
 412         writeb(0x4, p + OCT_REG_CR_OFF);
 413         iounmap(p);
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * Disables the global interrupt of PMC-OctalPro
 420  */
 421
 422 static void __devexit sbs_exit(struct pci_dev *dev)
 423 {
 424         u8 __iomem *p;
 425
 426         p = pci_ioremap_bar(dev, 0);
 427         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 428         if (p != NULL)
 429                 writeb(0, p + OCT_REG_CR_OFF);
 430         iounmap(p);
 431 }
 432
 433 /*
 434  * SIIG serial cards have an PCI interface chip which also controls
 435  * the UART clocking frequency. Each UART can be clocked independently
 436  * (except cards equiped with 4 UARTs) and initial clocking settings
 437  * are stored in the EEPROM chip. It can cause problems because this
 438  * version of serial driver doesn't support differently clocked UART's
 439  * on single PCI card. To prevent this, initialization functions set
 440  * high frequency clocking for all UART's on given card. It is safe (I
 441  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 442  * with other OSes (like M$ DOS).
 443  *
 444  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 445  *
 446  * There is two family of SIIG serial cards with different PCI
 447  * interface chip and different configuration methods:
 448  *     - 10x cards have control registers in IO and/or memory space;
 449  *     - 20x cards have control registers in standard PCI configuration space.
 450  *
 451  * Note: all 10x cards have PCI device ids 0x10..
 452  *       all 20x cards have PCI device ids 0x20..
 453  *
 454  * There are also Quartet Serial cards which use Oxford Semiconductor
 455  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 456  *
 457  * Note: some SIIG cards are probed by the parport_serial object.
 458  */
 459
 460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 462
 463 static int pci_siig10x_init(struct pci_dev *dev)
 464 {
 465         u16 data;
 466         void __iomem *p;
 467
 468         switch (dev->device & 0xfff8) {
 469         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 470                 data = 0xffdf;
 471                 break;
 472         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 473                 data = 0xf7ff;
 474                 break;
 475         default:                        /* 1S1P, 4S */
 476                 data = 0xfffb;
 477                 break;
 478         }
 479
 480         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 481         if (p == NULL)
 482                 return -ENOMEM;
 483
 484         writew(readw(p + 0x28) & data, p + 0x28);
 485         readw(p + 0x28);
 486         iounmap(p);
 487         return 0;
 488 }
 489
 490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 492
 493 static int pci_siig20x_init(struct pci_dev *dev)
 494 {
 495         u8 data;
 496
 497         /* Change clock frequency for the first UART. */
 498         pci_read_config_byte(dev, 0x6f, &data);
 499         pci_write_config_byte(dev, 0x6f, data & 0xef);
 500
 501         /* If this card has 2 UART, we have to do the same with second UART. */
 502         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 503             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 504                 pci_read_config_byte(dev, 0x73, &data);
 505                 pci_write_config_byte(dev, 0x73, data & 0xef);
 506         }
 507         return 0;
 508 }
 509
 510 static int pci_siig_init(struct pci_dev *dev)
 511 {
 512         unsigned int type = dev->device & 0xff00;
 513
 514         if (type == 0x1000)
 515                 return pci_siig10x_init(dev);
 516         else if (type == 0x2000)
 517                 return pci_siig20x_init(dev);
 518
 519         moan_device("Unknown SIIG card", dev);
 520         return -ENODEV;
 521 }
 522
 523 static int pci_siig_setup(struct serial_private *priv,
 524                           const struct pciserial_board *board,
 525                           struct uart_port *port, int idx)
 526 {
 527         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 528
 529         if (idx > 3) {
 530                 bar = 4;
 531                 offset = (idx - 4) * 8;
 532         }
 533
 534         return setup_port(priv, port, bar, offset, 0);
 535 }
 536
 537 /*
 538  * Timedia has an explosion of boards, and to avoid the PCI table from
 539  * growing *huge*, we use this function to collapse some 70 entries
 540  * in the PCI table into one, for sanity's and compactness's sake.
 541  */
 542 static const unsigned short timedia_single_port[] = {
 543         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 544 };
 545
 546 static const unsigned short timedia_dual_port[] = {
 547         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 548         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 549         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 550         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 551         0xD079, 0
 552 };
 553
 554 static const unsigned short timedia_quad_port[] = {
 555         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 556         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 557         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 558         0xB157, 0
 559 };
 560
 561 static const unsigned short timedia_eight_port[] = {
 562         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 563         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 564 };
 565
 566 static const struct timedia_struct {
 567         int num;
 568         const unsigned short *ids;
 569 } timedia_data[] = {
 570         { 1, timedia_single_port },
 571         { 2, timedia_dual_port },
 572         { 4, timedia_quad_port },
 573         { 8, timedia_eight_port }
 574 };
 575
 576 static int pci_timedia_init(struct pci_dev *dev)
 577 {
 578         const unsigned short *ids;
 579         int i, j;
 580
 581         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 582                 ids = timedia_data[i].ids;
 583                 for (j = 0; ids[j]; j++)
 584                         if (dev->subsystem_device == ids[j])
 585                                 return timedia_data[i].num;
 586         }
 587         return 0;
 588 }
 589
 590 /*
 591  * Timedia/SUNIX uses a mixture of BARs and offsets
 592  * Ugh, this is ugly as all hell --- TYT
 593  */
 594 static int
 595 pci_timedia_setup(struct serial_private *priv,
 596                   const struct pciserial_board *board,
 597                   struct uart_port *port, int idx)
 598 {
 599         unsigned int bar = 0, offset = board->first_offset;
 600
 601         switch (idx) {
 602         case 0:
 603                 bar = 0;
 604                 break;
 605         case 1:
 606                 offset = board->uart_offset;
 607                 bar = 0;
 608                 break;
 609         case 2:
 610                 bar = 1;
 611                 break;
 612         case 3:
 613                 offset = board->uart_offset;
 614                 /* FALLTHROUGH */
 615         case 4: /* BAR 2 */
 616         case 5: /* BAR 3 */
 617         case 6: /* BAR 4 */
 618         case 7: /* BAR 5 */
 619                 bar = idx - 2;
 620         }
 621
 622         return setup_port(priv, port, bar, offset, board->reg_shift);
 623 }
 624
 625 /*
 626  * Some Titan cards are also a little weird
 627  */
 628 static int
 629 titan_400l_800l_setup(struct serial_private *priv,
 630                       const struct pciserial_board *board,
 631                       struct uart_port *port, int idx)
 632 {
 633         unsigned int bar, offset = board->first_offset;
 634
 635         switch (idx) {
 636         case 0:
 637                 bar = 1;
 638                 break;
 639         case 1:
 640                 bar = 2;
 641                 break;
 642         default:
 643                 bar = 4;
 644                 offset = (idx - 2) * board->uart_offset;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 static int pci_xircom_init(struct pci_dev *dev)
 651 {
 652         msleep(100);
 653         return 0;
 654 }
 655
 656 static int pci_ni8420_init(struct pci_dev *dev)
 657 {
 658         void __iomem *p;
 659         unsigned long base, len;
 660         unsigned int bar = 0;
 661
 662         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 663                 moan_device("no memory in bar", dev);
 664                 return 0;
 665         }
 666
 667         base = pci_resource_start(dev, bar);
 668         len =  pci_resource_len(dev, bar);
 669         p = ioremap_nocache(base, len);
 670         if (p == NULL)
 671                 return -ENOMEM;
 672
 673         /* Enable CPU Interrupt */
 674         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 675                p + NI8420_INT_ENABLE_REG);
 676
 677         iounmap(p);
 678         return 0;
 679 }
 680
 681 #define MITE_IOWBSR1_WSIZE      0xa
 682 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 683 #define MITE_IOWBSR1_WENAB      (1 << 7)
 684 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 685 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 687
 688 static int pci_ni8430_init(struct pci_dev *dev)
 689 {
 690         void __iomem *p;
 691         unsigned long base, len;
 692         u32 device_window;
 693         unsigned int bar = 0;
 694
 695         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 696                 moan_device("no memory in bar", dev);
 697                 return 0;
 698         }
 699
 700         base = pci_resource_start(dev, bar);
 701         len =  pci_resource_len(dev, bar);
 702         p = ioremap_nocache(base, len);
 703         if (p == NULL)
 704                 return -ENOMEM;
 705
 706         /* Set device window address and size in BAR0 */
 707         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 708                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 709         writel(device_window, p + MITE_IOWBSR1);
 710
 711         /* Set window access to go to RAMSEL IO address space */
 712         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 713                p + MITE_IOWCR1);
 714
 715         /* Enable IO Bus Interrupt 0 */
 716         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 717
 718         /* Enable CPU Interrupt */
 719         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 720
 721         iounmap(p);
 722         return 0;
 723 }
 724
 725 /* UART Port Control Register */
 726 #define NI8430_PORTCON  0x0f
 727 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 728
 729 static int
 730 pci_ni8430_setup(struct serial_private *priv,
 731                  const struct pciserial_board *board,
 732                  struct uart_port *port, int idx)
 733 {
 734         void __iomem *p;
 735         unsigned long base, len;
 736         unsigned int bar, offset = board->first_offset;
 737
 738         if (idx >= board->num_ports)
 739                 return 1;
 740
 741         bar = FL_GET_BASE(board->flags);
 742         offset += idx * board->uart_offset;
 743
 744         base = pci_resource_start(priv->dev, bar);
 745         len =  pci_resource_len(priv->dev, bar);
 746         p = ioremap_nocache(base, len);
 747
 748         /* enable the transciever */
 749         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 750                p + offset + NI8430_PORTCON);
 751
 752         iounmap(p);
 753
 754         return setup_port(priv, port, bar, offset, board->reg_shift);
 755 }
 756
 757
 758 static int pci_netmos_init(struct pci_dev *dev)
 759 {
 760         /* subdevice 0x00PS means <P> parallel, <S> serial */
 761         unsigned int num_serial = dev->subsystem_device & 0xf;
 762
 763         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 764                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 765                 return 0;
 766         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 767                         dev->subsystem_device == 0x0299)
 768                 return 0;
 769
 770         if (num_serial == 0)
 771                 return -ENODEV;
 772         return num_serial;
 773 }
 774
 775 /*
 776  * These chips are available with optionally one parallel port and up to
 777  * two serial ports. Unfortunately they all have the same product id.
 778  *
 779  * Basic configuration is done over a region of 32 I/O ports. The base
 780  * ioport is called INTA or INTC, depending on docs/other drivers.
 781  *
 782  * The region of the 32 I/O ports is configured in POSIO0R...
 783  */
 784
 785 /* registers */
 786 #define ITE_887x_MISCR          0x9c
 787 #define ITE_887x_INTCBAR        0x78
 788 #define ITE_887x_UARTBAR        0x7c
 789 #define ITE_887x_PS0BAR         0x10
 790 #define ITE_887x_POSIO0         0x60
 791
 792 /* I/O space size */
 793 #define ITE_887x_IOSIZE         32
 794 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 795 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 796 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 797 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 798 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 799 #define ITE_887x_POSIO_SPEED            (3 << 29)
 800 /* enable IO_Space bit */
 801 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 802
 803 static int pci_ite887x_init(struct pci_dev *dev)
 804 {
 805         /* inta_addr are the configuration addresses of the ITE */
 806         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 807                                                         0x200, 0x280, 0 };
 808         int ret, i, type;
 809         struct resource *iobase = NULL;
 810         u32 miscr, uartbar, ioport;
 811
 812         /* search for the base-ioport */
 813         i = 0;
 814         while (inta_addr[i] && iobase == NULL) {
 815                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 816                                                                 "ite887x");
 817                 if (iobase != NULL) {
 818                         /* write POSIO0R - speed | size | ioport */
 819                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 820                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 821                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 822                         /* write INTCBAR - ioport */
 823                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 824                                                                 inta_addr[i]);
 825                         ret = inb(inta_addr[i]);
 826                         if (ret != 0xff) {
 827                                 /* ioport connected */
 828                                 break;
 829                         }
 830                         release_region(iobase->start, ITE_887x_IOSIZE);
 831                         iobase = NULL;
 832                 }
 833                 i++;
 834         }
 835
 836         if (!inta_addr[i]) {
 837                 printk(KERN_ERR "ite887x: could not find iobase\n");
 838                 return -ENODEV;
 839         }
 840
 841         /* start of undocumented type checking (see parport_pc.c) */
 842         type = inb(iobase->start + 0x18) & 0x0f;
 843
 844         switch (type) {
 845         case 0x2:       /* ITE8871 (1P) */
 846         case 0xa:       /* ITE8875 (1P) */
 847                 ret = 0;
 848                 break;
 849         case 0xe:       /* ITE8872 (2S1P) */
 850                 ret = 2;
 851                 break;
 852         case 0x6:       /* ITE8873 (1S) */
 853                 ret = 1;
 854                 break;
 855         case 0x8:       /* ITE8874 (2S) */
 856                 ret = 2;
 857                 break;
 858         default:
 859                 moan_device("Unknown ITE887x", dev);
 860                 ret = -ENODEV;
 861         }
 862
 863         /* configure all serial ports */
 864         for (i = 0; i < ret; i++) {
 865                 /* read the I/O port from the device */
 866                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 867                                                                 &ioport);
 868                 ioport &= 0x0000FF00;   /* the actual base address */
 869                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 870                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 871                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 872
 873                 /* write the ioport to the UARTBAR */
 874                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 875                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 876                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 877                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 878
 879                 /* get current config */
 880                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 881                 /* disable interrupts (UARTx_Routing[3:0]) */
 882                 miscr &= ~(0xf << (12 - 4 * i));
 883                 /* activate the UART (UARTx_En) */
 884                 miscr |= 1 << (23 - i);
 885                 /* write new config with activated UART */
 886                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 887         }
 888
 889         if (ret <= 0) {
 890                 /* the device has no UARTs if we get here */
 891                 release_region(iobase->start, ITE_887x_IOSIZE);
 892         }
 893
 894         return ret;
 895 }
 896
 897 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 898 {
 899         u32 ioport;
 900         /* the ioport is bit 0-15 in POSIO0R */
 901         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 902         ioport &= 0xffff;
 903         release_region(ioport, ITE_887x_IOSIZE);
 904 }
 905
 906 /*
 907  * Oxford Semiconductor Inc.
 908  * Check that device is part of the Tornado range of devices, then determine
 909  * the number of ports available on the device.
 910  */
 911 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
 912 {
 913         u8 __iomem *p;
 914         unsigned long deviceID;
 915         unsigned int  number_uarts = 0;
 916
 917         /* OxSemi Tornado devices are all 0xCxxx */
 918         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
 919             (dev->device & 0xF000) != 0xC000)
 920                 return 0;
 921
 922         p = pci_iomap(dev, 0, 5);
 923         if (p == NULL)
 924                 return -ENOMEM;
 925
 926         deviceID = ioread32(p);
 927         /* Tornado device */
 928         if (deviceID == 0x07000200) {
 929                 number_uarts = ioread8(p + 4);
 930                 printk(KERN_DEBUG
 931                         "%d ports detected on Oxford PCI Express device\n",
 932                                                                 number_uarts);
 933         }
 934         pci_iounmap(dev, p);
 935         return number_uarts;
 936 }
 937
 938 static int
 939 pci_default_setup(struct serial_private *priv,
 940                   const struct pciserial_board *board,
 941                   struct uart_port *port, int idx)
 942 {
 943         unsigned int bar, offset = board->first_offset, maxnr;
 944
 945         bar = FL_GET_BASE(board->flags);
 946         if (board->flags & FL_BASE_BARS)
 947                 bar += idx;
 948         else
 949                 offset += idx * board->uart_offset;
 950
 951         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 952                 (board->reg_shift + 3);
 953
 954         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 955                 return 1;
 956
 957         return setup_port(priv, port, bar, offset, board->reg_shift);
 958 }
 959
 960 static int skip_tx_en_setup(struct serial_private *priv,
 961                         const struct pciserial_board *board,
 962                         struct uart_port *port, int idx)
 963 {
 964         port->flags |= UPF_NO_TXEN_TEST;
 965         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
 966                           "[%04x:%04x] subsystem [%04x:%04x]\n",
 967                           priv->dev->vendor,
 968                           priv->dev->device,
 969                           priv->dev->subsystem_vendor,
 970                           priv->dev->subsystem_device);
 971
 972         return pci_default_setup(priv, board, port, idx);
 973 }
 974
 975 /* This should be in linux/pci_ids.h */
 976 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 977 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 978 #define PCI_DEVICE_ID_OCTPRO            0x0001
 979 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 980 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 981 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 982 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 983 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
 984 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
 985 #define PCI_DEVICE_ID_TITAN_200I        0x8028
 986 #define PCI_DEVICE_ID_TITAN_400I        0x8048
 987 #define PCI_DEVICE_ID_TITAN_800I        0x8088
 988 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
 989 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
 990 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
 991 #define PCI_DEVICE_ID_TITAN_100E        0xA010
 992 #define PCI_DEVICE_ID_TITAN_200E        0xA012
 993 #define PCI_DEVICE_ID_TITAN_400E        0xA013
 994 #define PCI_DEVICE_ID_TITAN_800E        0xA014
 995 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
 996 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
 997 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
 998
 999 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1000 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1001
1002 /*
1003  * Master list of serial port init/setup/exit quirks.
1004  * This does not describe the general nature of the port.
1005  * (ie, baud base, number and location of ports, etc)
1006  *
1007  * This list is ordered alphabetically by vendor then device.
1008  * Specific entries must come before more generic entries.
1009  */
1010 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1011         /*
1012         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1013         */
1014         {
1015                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1016                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1017                 .subvendor      = PCI_ANY_ID,
1018                 .subdevice      = PCI_ANY_ID,
1019                 .setup          = addidata_apci7800_setup,
1020         },
1021         /*
1022          * AFAVLAB cards - these may be called via parport_serial
1023          *  It is not clear whether this applies to all products.
1024          */
1025         {
1026                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1027                 .device         = PCI_ANY_ID,
1028                 .subvendor      = PCI_ANY_ID,
1029                 .subdevice      = PCI_ANY_ID,
1030                 .setup          = afavlab_setup,
1031         },
1032         /*
1033          * HP Diva
1034          */
1035         {
1036                 .vendor         = PCI_VENDOR_ID_HP,
1037                 .device         = PCI_DEVICE_ID_HP_DIVA,
1038                 .subvendor      = PCI_ANY_ID,
1039                 .subdevice      = PCI_ANY_ID,
1040                 .init           = pci_hp_diva_init,
1041                 .setup          = pci_hp_diva_setup,
1042         },
1043         /*
1044          * Intel
1045          */
1046         {
1047                 .vendor         = PCI_VENDOR_ID_INTEL,
1048                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1049                 .subvendor      = 0xe4bf,
1050                 .subdevice      = PCI_ANY_ID,
1051                 .init           = pci_inteli960ni_init,
1052                 .setup          = pci_default_setup,
1053         },
1054         {
1055                 .vendor         = PCI_VENDOR_ID_INTEL,
1056                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1057                 .subvendor      = PCI_ANY_ID,
1058                 .subdevice      = PCI_ANY_ID,
1059                 .setup          = skip_tx_en_setup,
1060         },
1061         {
1062                 .vendor         = PCI_VENDOR_ID_INTEL,
1063                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1064                 .subvendor      = PCI_ANY_ID,
1065                 .subdevice      = PCI_ANY_ID,
1066                 .setup          = skip_tx_en_setup,
1067         },
1068         {
1069                 .vendor         = PCI_VENDOR_ID_INTEL,
1070                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1071                 .subvendor      = PCI_ANY_ID,
1072                 .subdevice      = PCI_ANY_ID,
1073                 .setup          = skip_tx_en_setup,
1074         },
1075         /*
1076          * ITE
1077          */
1078         {
1079                 .vendor         = PCI_VENDOR_ID_ITE,
1080                 .device         = PCI_DEVICE_ID_ITE_8872,
1081                 .subvendor      = PCI_ANY_ID,
1082                 .subdevice      = PCI_ANY_ID,
1083                 .init           = pci_ite887x_init,
1084                 .setup          = pci_default_setup,
1085                 .exit           = __devexit_p(pci_ite887x_exit),
1086         },
1087         /*
1088          * National Instruments
1089          */
1090         {
1091                 .vendor         = PCI_VENDOR_ID_NI,
1092                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1093                 .subvendor      = PCI_ANY_ID,
1094                 .subdevice      = PCI_ANY_ID,
1095                 .init           = pci_ni8420_init,
1096                 .setup          = pci_default_setup,
1097                 .exit           = __devexit_p(pci_ni8420_exit),
1098         },
1099         {
1100                 .vendor         = PCI_VENDOR_ID_NI,
1101                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1102                 .subvendor      = PCI_ANY_ID,
1103                 .subdevice      = PCI_ANY_ID,
1104                 .init           = pci_ni8420_init,
1105                 .setup          = pci_default_setup,
1106                 .exit           = __devexit_p(pci_ni8420_exit),
1107         },
1108         {
1109                 .vendor         = PCI_VENDOR_ID_NI,
1110                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1111                 .subvendor      = PCI_ANY_ID,
1112                 .subdevice      = PCI_ANY_ID,
1113                 .init           = pci_ni8420_init,
1114                 .setup          = pci_default_setup,
1115                 .exit           = __devexit_p(pci_ni8420_exit),
1116         },
1117         {
1118                 .vendor         = PCI_VENDOR_ID_NI,
1119                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1120                 .subvendor      = PCI_ANY_ID,
1121                 .subdevice      = PCI_ANY_ID,
1122                 .init           = pci_ni8420_init,
1123                 .setup          = pci_default_setup,
1124                 .exit           = __devexit_p(pci_ni8420_exit),
1125         },
1126         {
1127                 .vendor         = PCI_VENDOR_ID_NI,
1128                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1129                 .subvendor      = PCI_ANY_ID,
1130                 .subdevice      = PCI_ANY_ID,
1131                 .init           = pci_ni8420_init,
1132                 .setup          = pci_default_setup,
1133                 .exit           = __devexit_p(pci_ni8420_exit),
1134         },
1135         {
1136                 .vendor         = PCI_VENDOR_ID_NI,
1137                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1138                 .subvendor      = PCI_ANY_ID,
1139                 .subdevice      = PCI_ANY_ID,
1140                 .init           = pci_ni8420_init,
1141                 .setup          = pci_default_setup,
1142                 .exit           = __devexit_p(pci_ni8420_exit),
1143         },
1144         {
1145                 .vendor         = PCI_VENDOR_ID_NI,
1146                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1147                 .subvendor      = PCI_ANY_ID,
1148                 .subdevice      = PCI_ANY_ID,
1149                 .init           = pci_ni8420_init,
1150                 .setup          = pci_default_setup,
1151                 .exit           = __devexit_p(pci_ni8420_exit),
1152         },
1153         {
1154                 .vendor         = PCI_VENDOR_ID_NI,
1155                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1156                 .subvendor      = PCI_ANY_ID,
1157                 .subdevice      = PCI_ANY_ID,
1158                 .init           = pci_ni8420_init,
1159                 .setup          = pci_default_setup,
1160                 .exit           = __devexit_p(pci_ni8420_exit),
1161         },
1162         {
1163                 .vendor         = PCI_VENDOR_ID_NI,
1164                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1165                 .subvendor      = PCI_ANY_ID,
1166                 .subdevice      = PCI_ANY_ID,
1167                 .init           = pci_ni8420_init,
1168                 .setup          = pci_default_setup,
1169                 .exit           = __devexit_p(pci_ni8420_exit),
1170         },
1171         {
1172                 .vendor         = PCI_VENDOR_ID_NI,
1173                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1174                 .subvendor      = PCI_ANY_ID,
1175                 .subdevice      = PCI_ANY_ID,
1176                 .init           = pci_ni8420_init,
1177                 .setup          = pci_default_setup,
1178                 .exit           = __devexit_p(pci_ni8420_exit),
1179         },
1180         {
1181                 .vendor         = PCI_VENDOR_ID_NI,
1182                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1183                 .subvendor      = PCI_ANY_ID,
1184                 .subdevice      = PCI_ANY_ID,
1185                 .init           = pci_ni8420_init,
1186                 .setup          = pci_default_setup,
1187                 .exit           = __devexit_p(pci_ni8420_exit),
1188         },
1189         {
1190                 .vendor         = PCI_VENDOR_ID_NI,
1191                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1192                 .subvendor      = PCI_ANY_ID,
1193                 .subdevice      = PCI_ANY_ID,
1194                 .init           = pci_ni8420_init,
1195                 .setup          = pci_default_setup,
1196                 .exit           = __devexit_p(pci_ni8420_exit),
1197         },
1198         {
1199                 .vendor         = PCI_VENDOR_ID_NI,
1200                 .device         = PCI_ANY_ID,
1201                 .subvendor      = PCI_ANY_ID,
1202                 .subdevice      = PCI_ANY_ID,
1203                 .init           = pci_ni8430_init,
1204                 .setup          = pci_ni8430_setup,
1205                 .exit           = __devexit_p(pci_ni8430_exit),
1206         },
1207         /*
1208          * Panacom
1209          */
1210         {
1211                 .vendor         = PCI_VENDOR_ID_PANACOM,
1212                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1213                 .subvendor      = PCI_ANY_ID,
1214                 .subdevice      = PCI_ANY_ID,
1215                 .init           = pci_plx9050_init,
1216                 .setup          = pci_default_setup,
1217                 .exit           = __devexit_p(pci_plx9050_exit),
1218         },
1219         {
1220                 .vendor         = PCI_VENDOR_ID_PANACOM,
1221                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1222                 .subvendor      = PCI_ANY_ID,
1223                 .subdevice      = PCI_ANY_ID,
1224                 .init           = pci_plx9050_init,
1225                 .setup          = pci_default_setup,
1226                 .exit           = __devexit_p(pci_plx9050_exit),
1227         },
1228         /*
1229          * PLX
1230          */
1231         {
1232                 .vendor         = PCI_VENDOR_ID_PLX,
1233                 .device         = PCI_DEVICE_ID_PLX_9030,
1234                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1235                 .subdevice      = PCI_ANY_ID,
1236                 .setup          = pci_default_setup,
1237         },
1238         {
1239                 .vendor         = PCI_VENDOR_ID_PLX,
1240                 .device         = PCI_DEVICE_ID_PLX_9050,
1241                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1242                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1243                 .init           = pci_plx9050_init,
1244                 .setup          = pci_default_setup,
1245                 .exit           = __devexit_p(pci_plx9050_exit),
1246         },
1247         {
1248                 .vendor         = PCI_VENDOR_ID_PLX,
1249                 .device         = PCI_DEVICE_ID_PLX_9050,
1250                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1251                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1252                 .init           = pci_plx9050_init,
1253                 .setup          = pci_default_setup,
1254                 .exit           = __devexit_p(pci_plx9050_exit),
1255         },
1256         {
1257                 .vendor         = PCI_VENDOR_ID_PLX,
1258                 .device         = PCI_DEVICE_ID_PLX_9050,
1259                 .subvendor      = PCI_VENDOR_ID_PLX,
1260                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1261                 .init           = pci_plx9050_init,
1262                 .setup          = pci_default_setup,
1263                 .exit           = __devexit_p(pci_plx9050_exit),
1264         },
1265         {
1266                 .vendor         = PCI_VENDOR_ID_PLX,
1267                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1268                 .subvendor      = PCI_VENDOR_ID_PLX,
1269                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1270                 .init           = pci_plx9050_init,
1271                 .setup          = pci_default_setup,
1272                 .exit           = __devexit_p(pci_plx9050_exit),
1273         },
1274         /*
1275          * SBS Technologies, Inc., PMC-OCTALPRO 232
1276          */
1277         {
1278                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1279                 .device         = PCI_DEVICE_ID_OCTPRO,
1280                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1281                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1282                 .init           = sbs_init,
1283                 .setup          = sbs_setup,
1284                 .exit           = __devexit_p(sbs_exit),
1285         },
1286         /*
1287          * SBS Technologies, Inc., PMC-OCTALPRO 422
1288          */
1289         {
1290                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1291                 .device         = PCI_DEVICE_ID_OCTPRO,
1292                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1293                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1294                 .init           = sbs_init,
1295                 .setup          = sbs_setup,
1296                 .exit           = __devexit_p(sbs_exit),
1297         },
1298         /*
1299          * SBS Technologies, Inc., P-Octal 232
1300          */
1301         {
1302                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1303                 .device         = PCI_DEVICE_ID_OCTPRO,
1304                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1305                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1306                 .init           = sbs_init,
1307                 .setup          = sbs_setup,
1308                 .exit           = __devexit_p(sbs_exit),
1309         },
1310         /*
1311          * SBS Technologies, Inc., P-Octal 422
1312          */
1313         {
1314                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1315                 .device         = PCI_DEVICE_ID_OCTPRO,
1316                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1317                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1318                 .init           = sbs_init,
1319                 .setup          = sbs_setup,
1320                 .exit           = __devexit_p(sbs_exit),
1321         },
1322         /*
1323          * SIIG cards - these may be called via parport_serial
1324          */
1325         {
1326                 .vendor         = PCI_VENDOR_ID_SIIG,
1327                 .device         = PCI_ANY_ID,
1328                 .subvendor      = PCI_ANY_ID,
1329                 .subdevice      = PCI_ANY_ID,
1330                 .init           = pci_siig_init,
1331                 .setup          = pci_siig_setup,
1332         },
1333         /*
1334          * Titan cards
1335          */
1336         {
1337                 .vendor         = PCI_VENDOR_ID_TITAN,
1338                 .device         = PCI_DEVICE_ID_TITAN_400L,
1339                 .subvendor      = PCI_ANY_ID,
1340                 .subdevice      = PCI_ANY_ID,
1341                 .setup          = titan_400l_800l_setup,
1342         },
1343         {
1344                 .vendor         = PCI_VENDOR_ID_TITAN,
1345                 .device         = PCI_DEVICE_ID_TITAN_800L,
1346                 .subvendor      = PCI_ANY_ID,
1347                 .subdevice      = PCI_ANY_ID,
1348                 .setup          = titan_400l_800l_setup,
1349         },
1350         /*
1351          * Timedia cards
1352          */
1353         {
1354                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1355                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1356                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1357                 .subdevice      = PCI_ANY_ID,
1358                 .init           = pci_timedia_init,
1359                 .setup          = pci_timedia_setup,
1360         },
1361         {
1362                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1363                 .device         = PCI_ANY_ID,
1364                 .subvendor      = PCI_ANY_ID,
1365                 .subdevice      = PCI_ANY_ID,
1366                 .setup          = pci_timedia_setup,
1367         },
1368         /*
1369          * Xircom cards
1370          */
1371         {
1372                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1373                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1374                 .subvendor      = PCI_ANY_ID,
1375                 .subdevice      = PCI_ANY_ID,
1376                 .init           = pci_xircom_init,
1377                 .setup          = pci_default_setup,
1378         },
1379         /*
1380          * Netmos cards - these may be called via parport_serial
1381          */
1382         {
1383                 .vendor         = PCI_VENDOR_ID_NETMOS,
1384                 .device         = PCI_ANY_ID,
1385                 .subvendor      = PCI_ANY_ID,
1386                 .subdevice      = PCI_ANY_ID,
1387                 .init           = pci_netmos_init,
1388                 .setup          = pci_default_setup,
1389         },
1390         /*
1391          * For Oxford Semiconductor and Mainpine
1392          */
1393         {
1394                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1395                 .device         = PCI_ANY_ID,
1396                 .subvendor      = PCI_ANY_ID,
1397                 .subdevice      = PCI_ANY_ID,
1398                 .init           = pci_oxsemi_tornado_init,
1399                 .setup          = pci_default_setup,
1400         },
1401         {
1402                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1403                 .device         = PCI_ANY_ID,
1404                 .subvendor      = PCI_ANY_ID,
1405                 .subdevice      = PCI_ANY_ID,
1406                 .init           = pci_oxsemi_tornado_init,
1407                 .setup          = pci_default_setup,
1408         },
1409         /*
1410          * Default "match everything" terminator entry
1411          */
1412         {
1413                 .vendor         = PCI_ANY_ID,
1414                 .device         = PCI_ANY_ID,
1415                 .subvendor      = PCI_ANY_ID,
1416                 .subdevice      = PCI_ANY_ID,
1417                 .setup          = pci_default_setup,
1418         }
1419 };
1420
1421 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1422 {
1423         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1424 }
1425
1426 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1427 {
1428         struct pci_serial_quirk *quirk;
1429
1430         for (quirk = pci_serial_quirks; ; quirk++)
1431                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1432                     quirk_id_matches(quirk->device, dev->device) &&
1433                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1434                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1435                         break;
1436         return quirk;
1437 }
1438
1439 static inline int get_pci_irq(struct pci_dev *dev,
1440                                 const struct pciserial_board *board)
1441 {
1442         if (board->flags & FL_NOIRQ)
1443                 return 0;
1444         else
1445                 return dev->irq;
1446 }
1447
1448 /*
1449  * This is the configuration table for all of the PCI serial boards
1450  * which we support.  It is directly indexed by the pci_board_num_t enum
1451  * value, which is encoded in the pci_device_id PCI probe table's
1452  * driver_data member.
1453  *
1454  * The makeup of these names are:
1455  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1456  *
1457  *  bn          = PCI BAR number
1458  *  bt          = Index using PCI BARs
1459  *  n           = number of serial ports
1460  *  baud        = baud rate
1461  *  offsetinhex = offset for each sequential port (in hex)
1462  *
1463  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1464  *
1465  * Please note: in theory if n = 1, _bt infix should make no difference.
1466  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1467  */
1468 enum pci_board_num_t {
1469         pbn_default = 0,
1470
1471         pbn_b0_1_115200,
1472         pbn_b0_2_115200,
1473         pbn_b0_4_115200,
1474         pbn_b0_5_115200,
1475         pbn_b0_8_115200,
1476
1477         pbn_b0_1_921600,
1478         pbn_b0_2_921600,
1479         pbn_b0_4_921600,
1480
1481         pbn_b0_2_1130000,
1482
1483         pbn_b0_4_1152000,
1484
1485         pbn_b0_2_1843200,
1486         pbn_b0_4_1843200,
1487
1488         pbn_b0_2_1843200_200,
1489         pbn_b0_4_1843200_200,
1490         pbn_b0_8_1843200_200,
1491
1492         pbn_b0_1_4000000,
1493
1494         pbn_b0_bt_1_115200,
1495         pbn_b0_bt_2_115200,
1496         pbn_b0_bt_4_115200,
1497         pbn_b0_bt_8_115200,
1498
1499         pbn_b0_bt_1_460800,
1500         pbn_b0_bt_2_460800,
1501         pbn_b0_bt_4_460800,
1502
1503         pbn_b0_bt_1_921600,
1504         pbn_b0_bt_2_921600,
1505         pbn_b0_bt_4_921600,
1506         pbn_b0_bt_8_921600,
1507
1508         pbn_b1_1_115200,
1509         pbn_b1_2_115200,
1510         pbn_b1_4_115200,
1511         pbn_b1_8_115200,
1512         pbn_b1_16_115200,
1513
1514         pbn_b1_1_921600,
1515         pbn_b1_2_921600,
1516         pbn_b1_4_921600,
1517         pbn_b1_8_921600,
1518
1519         pbn_b1_2_1250000,
1520
1521         pbn_b1_bt_1_115200,
1522         pbn_b1_bt_2_115200,
1523         pbn_b1_bt_4_115200,
1524
1525         pbn_b1_bt_2_921600,
1526
1527         pbn_b1_1_1382400,
1528         pbn_b1_2_1382400,
1529         pbn_b1_4_1382400,
1530         pbn_b1_8_1382400,
1531
1532         pbn_b2_1_115200,
1533         pbn_b2_2_115200,
1534         pbn_b2_4_115200,
1535         pbn_b2_8_115200,
1536
1537         pbn_b2_1_460800,
1538         pbn_b2_4_460800,
1539         pbn_b2_8_460800,
1540         pbn_b2_16_460800,
1541
1542         pbn_b2_1_921600,
1543         pbn_b2_4_921600,
1544         pbn_b2_8_921600,
1545
1546         pbn_b2_8_1152000,
1547
1548         pbn_b2_bt_1_115200,
1549         pbn_b2_bt_2_115200,
1550         pbn_b2_bt_4_115200,
1551
1552         pbn_b2_bt_2_921600,
1553         pbn_b2_bt_4_921600,
1554
1555         pbn_b3_2_115200,
1556         pbn_b3_4_115200,
1557         pbn_b3_8_115200,
1558
1559         pbn_b4_bt_2_921600,
1560         pbn_b4_bt_4_921600,
1561         pbn_b4_bt_8_921600,
1562
1563         /*
1564          * Board-specific versions.
1565          */
1566         pbn_panacom,
1567         pbn_panacom2,
1568         pbn_panacom4,
1569         pbn_exsys_4055,
1570         pbn_plx_romulus,
1571         pbn_oxsemi,
1572         pbn_oxsemi_1_4000000,
1573         pbn_oxsemi_2_4000000,
1574         pbn_oxsemi_4_4000000,
1575         pbn_oxsemi_8_4000000,
1576         pbn_intel_i960,
1577         pbn_sgi_ioc3,
1578         pbn_computone_4,
1579         pbn_computone_6,
1580         pbn_computone_8,
1581         pbn_sbsxrsio,
1582         pbn_exar_XR17C152,
1583         pbn_exar_XR17C154,
1584         pbn_exar_XR17C158,
1585         pbn_exar_ibm_saturn,
1586         pbn_pasemi_1682M,
1587         pbn_ni8430_2,
1588         pbn_ni8430_4,
1589         pbn_ni8430_8,
1590         pbn_ni8430_16,
1591         pbn_ADDIDATA_PCIe_1_3906250,
1592         pbn_ADDIDATA_PCIe_2_3906250,
1593         pbn_ADDIDATA_PCIe_4_3906250,
1594         pbn_ADDIDATA_PCIe_8_3906250,
1595 };
1596
1597 /*
1598  * uart_offset - the space between channels
1599  * reg_shift   - describes how the UART registers are mapped
1600  *               to PCI memory by the card.
1601  * For example IER register on SBS, Inc. PMC-OctPro is located at
1602  * offset 0x10 from the UART base, while UART_IER is defined as 1
1603  * in include/linux/serial_reg.h,
1604  * see first lines of serial_in() and serial_out() in 8250.c
1605 */
1606
1607 static struct pciserial_board pci_boards[] __devinitdata = {
1608         [pbn_default] = {
1609                 .flags          = FL_BASE0,
1610                 .num_ports      = 1,
1611                 .base_baud      = 115200,
1612                 .uart_offset    = 8,
1613         },
1614         [pbn_b0_1_115200] = {
1615                 .flags          = FL_BASE0,
1616                 .num_ports      = 1,
1617                 .base_baud      = 115200,
1618                 .uart_offset    = 8,
1619         },
1620         [pbn_b0_2_115200] = {
1621                 .flags          = FL_BASE0,
1622                 .num_ports      = 2,
1623                 .base_baud      = 115200,
1624                 .uart_offset    = 8,
1625         },
1626         [pbn_b0_4_115200] = {
1627                 .flags          = FL_BASE0,
1628                 .num_ports      = 4,
1629                 .base_baud      = 115200,
1630                 .uart_offset    = 8,
1631         },
1632         [pbn_b0_5_115200] = {
1633                 .flags          = FL_BASE0,
1634                 .num_ports      = 5,
1635                 .base_baud      = 115200,
1636                 .uart_offset    = 8,
1637         },
1638         [pbn_b0_8_115200] = {
1639                 .flags          = FL_BASE0,
1640                 .num_ports      = 8,
1641                 .base_baud      = 115200,
1642                 .uart_offset    = 8,
1643         },
1644         [pbn_b0_1_921600] = {
1645                 .flags          = FL_BASE0,
1646                 .num_ports      = 1,
1647                 .base_baud      = 921600,
1648                 .uart_offset    = 8,
1649         },
1650         [pbn_b0_2_921600] = {
1651                 .flags          = FL_BASE0,
1652                 .num_ports      = 2,
1653                 .base_baud      = 921600,
1654                 .uart_offset    = 8,
1655         },
1656         [pbn_b0_4_921600] = {
1657                 .flags          = FL_BASE0,
1658                 .num_ports      = 4,
1659                 .base_baud      = 921600,
1660                 .uart_offset    = 8,
1661         },
1662
1663         [pbn_b0_2_1130000] = {
1664                 .flags          = FL_BASE0,
1665                 .num_ports      = 2,
1666                 .base_baud      = 1130000,
1667                 .uart_offset    = 8,
1668         },
1669
1670         [pbn_b0_4_1152000] = {
1671                 .flags          = FL_BASE0,
1672                 .num_ports      = 4,
1673                 .base_baud      = 1152000,
1674                 .uart_offset    = 8,
1675         },
1676
1677         [pbn_b0_2_1843200] = {
1678                 .flags          = FL_BASE0,
1679                 .num_ports      = 2,
1680                 .base_baud      = 1843200,
1681                 .uart_offset    = 8,
1682         },
1683         [pbn_b0_4_1843200] = {
1684                 .flags          = FL_BASE0,
1685                 .num_ports      = 4,
1686                 .base_baud      = 1843200,
1687                 .uart_offset    = 8,
1688         },
1689
1690         [pbn_b0_2_1843200_200] = {
1691                 .flags          = FL_BASE0,
1692                 .num_ports      = 2,
1693                 .base_baud      = 1843200,
1694                 .uart_offset    = 0x200,
1695         },
1696         [pbn_b0_4_1843200_200] = {
1697                 .flags          = FL_BASE0,
1698                 .num_ports      = 4,
1699                 .base_baud      = 1843200,
1700                 .uart_offset    = 0x200,
1701         },
1702         [pbn_b0_8_1843200_200] = {
1703                 .flags          = FL_BASE0,
1704                 .num_ports      = 8,
1705                 .base_baud      = 1843200,
1706                 .uart_offset    = 0x200,
1707         },
1708         [pbn_b0_1_4000000] = {
1709                 .flags          = FL_BASE0,
1710                 .num_ports      = 1,
1711                 .base_baud      = 4000000,
1712                 .uart_offset    = 8,
1713         },
1714
1715         [pbn_b0_bt_1_115200] = {
1716                 .flags          = FL_BASE0|FL_BASE_BARS,
1717                 .num_ports      = 1,
1718                 .base_baud      = 115200,
1719                 .uart_offset    = 8,
1720         },
1721         [pbn_b0_bt_2_115200] = {
1722                 .flags          = FL_BASE0|FL_BASE_BARS,
1723                 .num_ports      = 2,
1724                 .base_baud      = 115200,
1725                 .uart_offset    = 8,
1726         },
1727         [pbn_b0_bt_4_115200] = {
1728                 .flags          = FL_BASE0|FL_BASE_BARS,
1729                 .num_ports      = 4,
1730                 .base_baud      = 115200,
1731                 .uart_offset    = 8,
1732         },
1733         [pbn_b0_bt_8_115200] = {
1734                 .flags          = FL_BASE0|FL_BASE_BARS,
1735                 .num_ports      = 8,
1736                 .base_baud      = 115200,
1737                 .uart_offset    = 8,
1738         },
1739
1740         [pbn_b0_bt_1_460800] = {
1741                 .flags          = FL_BASE0|FL_BASE_BARS,
1742                 .num_ports      = 1,
1743                 .base_baud      = 460800,
1744                 .uart_offset    = 8,
1745         },
1746         [pbn_b0_bt_2_460800] = {
1747                 .flags          = FL_BASE0|FL_BASE_BARS,
1748                 .num_ports      = 2,
1749                 .base_baud      = 460800,
1750                 .uart_offset    = 8,
1751         },
1752         [pbn_b0_bt_4_460800] = {
1753                 .flags          = FL_BASE0|FL_BASE_BARS,
1754                 .num_ports      = 4,
1755                 .base_baud      = 460800,
1756                 .uart_offset    = 8,
1757         },
1758
1759         [pbn_b0_bt_1_921600] = {
1760                 .flags          = FL_BASE0|FL_BASE_BARS,
1761                 .num_ports      = 1,
1762                 .base_baud      = 921600,
1763                 .uart_offset    = 8,
1764         },
1765         [pbn_b0_bt_2_921600] = {
1766                 .flags          = FL_BASE0|FL_BASE_BARS,
1767                 .num_ports      = 2,
1768                 .base_baud      = 921600,
1769                 .uart_offset    = 8,
1770         },
1771         [pbn_b0_bt_4_921600] = {
1772                 .flags          = FL_BASE0|FL_BASE_BARS,
1773                 .num_ports      = 4,
1774                 .base_baud      = 921600,
1775                 .uart_offset    = 8,
1776         },
1777         [pbn_b0_bt_8_921600] = {
1778                 .flags          = FL_BASE0|FL_BASE_BARS,
1779                 .num_ports      = 8,
1780                 .base_baud      = 921600,
1781                 .uart_offset    = 8,
1782         },
1783
1784         [pbn_b1_1_115200] = {
1785                 .flags          = FL_BASE1,
1786                 .num_ports      = 1,
1787                 .base_baud      = 115200,
1788                 .uart_offset    = 8,
1789         },
1790         [pbn_b1_2_115200] = {
1791                 .flags          = FL_BASE1,
1792                 .num_ports      = 2,
1793                 .base_baud      = 115200,
1794                 .uart_offset    = 8,
1795         },
1796         [pbn_b1_4_115200] = {
1797                 .flags          = FL_BASE1,
1798                 .num_ports      = 4,
1799                 .base_baud      = 115200,
1800                 .uart_offset    = 8,
1801         },
1802         [pbn_b1_8_115200] = {
1803                 .flags          = FL_BASE1,
1804                 .num_ports      = 8,
1805                 .base_baud      = 115200,
1806                 .uart_offset    = 8,
1807         },
1808         [pbn_b1_16_115200] = {
1809                 .flags          = FL_BASE1,
1810                 .num_ports      = 16,
1811                 .base_baud      = 115200,
1812                 .uart_offset    = 8,
1813         },
1814
1815         [pbn_b1_1_921600] = {
1816                 .flags          = FL_BASE1,
1817                 .num_ports      = 1,
1818                 .base_baud      = 921600,
1819                 .uart_offset    = 8,
1820         },
1821         [pbn_b1_2_921600] = {
1822                 .flags          = FL_BASE1,
1823                 .num_ports      = 2,
1824                 .base_baud      = 921600,
1825                 .uart_offset    = 8,
1826         },
1827         [pbn_b1_4_921600] = {
1828                 .flags          = FL_BASE1,
1829                 .num_ports      = 4,
1830                 .base_baud      = 921600,
1831                 .uart_offset    = 8,
1832         },
1833         [pbn_b1_8_921600] = {
1834                 .flags          = FL_BASE1,
1835                 .num_ports      = 8,
1836                 .base_baud      = 921600,
1837                 .uart_offset    = 8,
1838         },
1839         [pbn_b1_2_1250000] = {
1840                 .flags          = FL_BASE1,
1841                 .num_ports      = 2,
1842                 .base_baud      = 1250000,
1843                 .uart_offset    = 8,
1844         },
1845
1846         [pbn_b1_bt_1_115200] = {
1847                 .flags          = FL_BASE1|FL_BASE_BARS,
1848                 .num_ports      = 1,
1849                 .base_baud      = 115200,
1850                 .uart_offset    = 8,
1851         },
1852         [pbn_b1_bt_2_115200] = {
1853                 .flags          = FL_BASE1|FL_BASE_BARS,
1854                 .num_ports      = 2,
1855                 .base_baud      = 115200,
1856                 .uart_offset    = 8,
1857         },
1858         [pbn_b1_bt_4_115200] = {
1859                 .flags          = FL_BASE1|FL_BASE_BARS,
1860                 .num_ports      = 4,
1861                 .base_baud      = 115200,
1862                 .uart_offset    = 8,
1863         },
1864
1865         [pbn_b1_bt_2_921600] = {
1866                 .flags          = FL_BASE1|FL_BASE_BARS,
1867                 .num_ports      = 2,
1868                 .base_baud      = 921600,
1869                 .uart_offset    = 8,
1870         },
1871
1872         [pbn_b1_1_1382400] = {
1873                 .flags          = FL_BASE1,
1874                 .num_ports      = 1,
1875                 .base_baud      = 1382400,
1876                 .uart_offset    = 8,
1877         },
1878         [pbn_b1_2_1382400] = {
1879                 .flags          = FL_BASE1,
1880                 .num_ports      = 2,
1881                 .base_baud      = 1382400,
1882                 .uart_offset    = 8,
1883         },
1884         [pbn_b1_4_1382400] = {
1885                 .flags          = FL_BASE1,
1886                 .num_ports      = 4,
1887                 .base_baud      = 1382400,
1888                 .uart_offset    = 8,
1889         },
1890         [pbn_b1_8_1382400] = {
1891                 .flags          = FL_BASE1,
1892                 .num_ports      = 8,
1893                 .base_baud      = 1382400,
1894                 .uart_offset    = 8,
1895         },
1896
1897         [pbn_b2_1_115200] = {
1898                 .flags          = FL_BASE2,
1899                 .num_ports      = 1,
1900                 .base_baud      = 115200,
1901                 .uart_offset    = 8,
1902         },
1903         [pbn_b2_2_115200] = {
1904                 .flags          = FL_BASE2,
1905                 .num_ports      = 2,
1906                 .base_baud      = 115200,
1907                 .uart_offset    = 8,
1908         },
1909         [pbn_b2_4_115200] = {
1910                 .flags          = FL_BASE2,
1911                 .num_ports      = 4,
1912                 .base_baud      = 115200,
1913                 .uart_offset    = 8,
1914         },
1915         [pbn_b2_8_115200] = {
1916                 .flags          = FL_BASE2,
1917                 .num_ports      = 8,
1918                 .base_baud      = 115200,
1919                 .uart_offset    = 8,
1920         },
1921
1922         [pbn_b2_1_460800] = {
1923                 .flags          = FL_BASE2,
1924                 .num_ports      = 1,
1925                 .base_baud      = 460800,
1926                 .uart_offset    = 8,
1927         },
1928         [pbn_b2_4_460800] = {
1929                 .flags          = FL_BASE2,
1930                 .num_ports      = 4,
1931                 .base_baud      = 460800,
1932                 .uart_offset    = 8,
1933         },
1934         [pbn_b2_8_460800] = {
1935                 .flags          = FL_BASE2,
1936                 .num_ports      = 8,
1937                 .base_baud      = 460800,
1938                 .uart_offset    = 8,
1939         },
1940         [pbn_b2_16_460800] = {
1941                 .flags          = FL_BASE2,
1942                 .num_ports      = 16,
1943                 .base_baud      = 460800,
1944                 .uart_offset    = 8,
1945          },
1946
1947         [pbn_b2_1_921600] = {
1948                 .flags          = FL_BASE2,
1949                 .num_ports      = 1,
1950                 .base_baud      = 921600,
1951                 .uart_offset    = 8,
1952         },
1953         [pbn_b2_4_921600] = {
1954                 .flags          = FL_BASE2,
1955                 .num_ports      = 4,
1956                 .base_baud      = 921600,
1957                 .uart_offset    = 8,
1958         },
1959         [pbn_b2_8_921600] = {
1960                 .flags          = FL_BASE2,
1961                 .num_ports      = 8,
1962                 .base_baud      = 921600,
1963                 .uart_offset    = 8,
1964         },
1965
1966         [pbn_b2_8_1152000] = {
1967                 .flags          = FL_BASE2,
1968                 .num_ports      = 8,
1969                 .base_baud      = 1152000,
1970                 .uart_offset    = 8,
1971         },
1972
1973         [pbn_b2_bt_1_115200] = {
1974                 .flags          = FL_BASE2|FL_BASE_BARS,
1975                 .num_ports      = 1,
1976                 .base_baud      = 115200,
1977                 .uart_offset    = 8,
1978         },
1979         [pbn_b2_bt_2_115200] = {
1980                 .flags          = FL_BASE2|FL_BASE_BARS,
1981                 .num_ports      = 2,
1982                 .base_baud      = 115200,
1983                 .uart_offset    = 8,
1984         },
1985         [pbn_b2_bt_4_115200] = {
1986                 .flags          = FL_BASE2|FL_BASE_BARS,
1987                 .num_ports      = 4,
1988                 .base_baud      = 115200,
1989                 .uart_offset    = 8,
1990         },
1991
1992         [pbn_b2_bt_2_921600] = {
1993                 .flags          = FL_BASE2|FL_BASE_BARS,
1994                 .num_ports      = 2,
1995                 .base_baud      = 921600,
1996                 .uart_offset    = 8,
1997         },
1998         [pbn_b2_bt_4_921600] = {
1999                 .flags          = FL_BASE2|FL_BASE_BARS,
2000                 .num_ports      = 4,
2001                 .base_baud      = 921600,
2002                 .uart_offset    = 8,
2003         },
2004
2005         [pbn_b3_2_115200] = {
2006                 .flags          = FL_BASE3,
2007                 .num_ports      = 2,
2008                 .base_baud      = 115200,
2009                 .uart_offset    = 8,
2010         },
2011         [pbn_b3_4_115200] = {
2012                 .flags          = FL_BASE3,
2013                 .num_ports      = 4,
2014                 .base_baud      = 115200,
2015                 .uart_offset    = 8,
2016         },
2017         [pbn_b3_8_115200] = {
2018                 .flags          = FL_BASE3,
2019                 .num_ports      = 8,
2020                 .base_baud      = 115200,
2021                 .uart_offset    = 8,
2022         },
2023
2024         [pbn_b4_bt_2_921600] = {
2025                 .flags          = FL_BASE4,
2026                 .num_ports      = 2,
2027                 .base_baud      = 921600,
2028                 .uart_offset    = 8,
2029         },
2030         [pbn_b4_bt_4_921600] = {
2031                 .flags          = FL_BASE4,
2032                 .num_ports      = 4,
2033                 .base_baud      = 921600,
2034                 .uart_offset    = 8,
2035         },
2036         [pbn_b4_bt_8_921600] = {
2037                 .flags          = FL_BASE4,
2038                 .num_ports      = 8,
2039                 .base_baud      = 921600,
2040                 .uart_offset    = 8,
2041         },
2042
2043         /*
2044          * Entries following this are board-specific.
2045          */
2046
2047         /*
2048          * Panacom - IOMEM
2049          */
2050         [pbn_panacom] = {
2051                 .flags          = FL_BASE2,
2052                 .num_ports      = 2,
2053                 .base_baud      = 921600,
2054                 .uart_offset    = 0x400,
2055                 .reg_shift      = 7,
2056         },
2057         [pbn_panacom2] = {
2058                 .flags          = FL_BASE2|FL_BASE_BARS,
2059                 .num_ports      = 2,
2060                 .base_baud      = 921600,
2061                 .uart_offset    = 0x400,
2062                 .reg_shift      = 7,
2063         },
2064         [pbn_panacom4] = {
2065                 .flags          = FL_BASE2|FL_BASE_BARS,
2066                 .num_ports      = 4,
2067                 .base_baud      = 921600,
2068                 .uart_offset    = 0x400,
2069                 .reg_shift      = 7,
2070         },
2071
2072         [pbn_exsys_4055] = {
2073                 .flags          = FL_BASE2,
2074                 .num_ports      = 4,
2075                 .base_baud      = 115200,
2076                 .uart_offset    = 8,
2077         },
2078
2079         /* I think this entry is broken - the first_offset looks wrong --rmk */
2080         [pbn_plx_romulus] = {
2081                 .flags          = FL_BASE2,
2082                 .num_ports      = 4,
2083                 .base_baud      = 921600,
2084                 .uart_offset    = 8 << 2,
2085                 .reg_shift      = 2,
2086                 .first_offset   = 0x03,
2087         },
2088
2089         /*
2090          * This board uses the size of PCI Base region 0 to
2091          * signal now many ports are available
2092          */
2093         [pbn_oxsemi] = {
2094                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2095                 .num_ports      = 32,
2096                 .base_baud      = 115200,
2097                 .uart_offset    = 8,
2098         },
2099         [pbn_oxsemi_1_4000000] = {
2100                 .flags          = FL_BASE0,
2101                 .num_ports      = 1,
2102                 .base_baud      = 4000000,
2103                 .uart_offset    = 0x200,
2104                 .first_offset   = 0x1000,
2105         },
2106         [pbn_oxsemi_2_4000000] = {
2107                 .flags          = FL_BASE0,
2108                 .num_ports      = 2,
2109                 .base_baud      = 4000000,
2110                 .uart_offset    = 0x200,
2111                 .first_offset   = 0x1000,
2112         },
2113         [pbn_oxsemi_4_4000000] = {
2114                 .flags          = FL_BASE0,
2115                 .num_ports      = 4,
2116                 .base_baud      = 4000000,
2117                 .uart_offset    = 0x200,
2118                 .first_offset   = 0x1000,
2119         },
2120         [pbn_oxsemi_8_4000000] = {
2121                 .flags          = FL_BASE0,
2122                 .num_ports      = 8,
2123                 .base_baud      = 4000000,
2124                 .uart_offset    = 0x200,
2125                 .first_offset   = 0x1000,
2126         },
2127
2128
2129         /*
2130          * EKF addition for i960 Boards form EKF with serial port.
2131          * Max 256 ports.
2132          */
2133         [pbn_intel_i960] = {
2134                 .flags          = FL_BASE0,
2135                 .num_ports      = 32,
2136                 .base_baud      = 921600,
2137                 .uart_offset    = 8 << 2,
2138                 .reg_shift      = 2,
2139                 .first_offset   = 0x10000,
2140         },
2141         [pbn_sgi_ioc3] = {
2142                 .flags          = FL_BASE0|FL_NOIRQ,
2143                 .num_ports      = 1,
2144                 .base_baud      = 458333,
2145                 .uart_offset    = 8,
2146                 .reg_shift      = 0,
2147                 .first_offset   = 0x20178,
2148         },
2149
2150         /*
2151          * Computone - uses IOMEM.
2152          */
2153         [pbn_computone_4] = {
2154                 .flags          = FL_BASE0,
2155                 .num_ports      = 4,
2156                 .base_baud      = 921600,
2157                 .uart_offset    = 0x40,
2158                 .reg_shift      = 2,
2159                 .first_offset   = 0x200,
2160         },
2161         [pbn_computone_6] = {
2162                 .flags          = FL_BASE0,
2163                 .num_ports      = 6,
2164                 .base_baud      = 921600,
2165                 .uart_offset    = 0x40,
2166                 .reg_shift      = 2,
2167                 .first_offset   = 0x200,
2168         },
2169         [pbn_computone_8] = {
2170                 .flags          = FL_BASE0,
2171                 .num_ports      = 8,
2172                 .base_baud      = 921600,
2173                 .uart_offset    = 0x40,
2174                 .reg_shift      = 2,
2175                 .first_offset   = 0x200,
2176         },
2177         [pbn_sbsxrsio] = {
2178                 .flags          = FL_BASE0,
2179                 .num_ports      = 8,
2180                 .base_baud      = 460800,
2181                 .uart_offset    = 256,
2182                 .reg_shift      = 4,
2183         },
2184         /*
2185          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2186          *  Only basic 16550A support.
2187          *  XR17C15[24] are not tested, but they should work.
2188          */
2189         [pbn_exar_XR17C152] = {
2190                 .flags          = FL_BASE0,
2191                 .num_ports      = 2,
2192                 .base_baud      = 921600,
2193                 .uart_offset    = 0x200,
2194         },
2195         [pbn_exar_XR17C154] = {
2196                 .flags          = FL_BASE0,
2197                 .num_ports      = 4,
2198                 .base_baud      = 921600,
2199                 .uart_offset    = 0x200,
2200         },
2201         [pbn_exar_XR17C158] = {
2202                 .flags          = FL_BASE0,
2203                 .num_ports      = 8,
2204                 .base_baud      = 921600,
2205                 .uart_offset    = 0x200,
2206         },
2207         [pbn_exar_ibm_saturn] = {
2208                 .flags          = FL_BASE0,
2209                 .num_ports      = 1,
2210                 .base_baud      = 921600,
2211                 .uart_offset    = 0x200,
2212         },
2213
2214         /*
2215          * PA Semi PWRficient PA6T-1682M on-chip UART
2216          */
2217         [pbn_pasemi_1682M] = {
2218                 .flags          = FL_BASE0,
2219                 .num_ports      = 1,
2220                 .base_baud      = 8333333,
2221         },
2222         /*
2223          * National Instruments 843x
2224          */
2225         [pbn_ni8430_16] = {
2226                 .flags          = FL_BASE0,
2227                 .num_ports      = 16,
2228                 .base_baud      = 3686400,
2229                 .uart_offset    = 0x10,
2230                 .first_offset   = 0x800,
2231         },
2232         [pbn_ni8430_8] = {
2233                 .flags          = FL_BASE0,
2234                 .num_ports      = 8,
2235                 .base_baud      = 3686400,
2236                 .uart_offset    = 0x10,
2237                 .first_offset   = 0x800,
2238         },
2239         [pbn_ni8430_4] = {
2240                 .flags          = FL_BASE0,
2241                 .num_ports      = 4,
2242                 .base_baud      = 3686400,
2243                 .uart_offset    = 0x10,
2244                 .first_offset   = 0x800,
2245         },
2246         [pbn_ni8430_2] = {
2247                 .flags          = FL_BASE0,
2248                 .num_ports      = 2,
2249                 .base_baud      = 3686400,
2250                 .uart_offset    = 0x10,
2251                 .first_offset   = 0x800,
2252         },
2253         /*
2254          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2255          */
2256         [pbn_ADDIDATA_PCIe_1_3906250] = {
2257                 .flags          = FL_BASE0,
2258                 .num_ports      = 1,
2259                 .base_baud      = 3906250,
2260                 .uart_offset    = 0x200,
2261                 .first_offset   = 0x1000,
2262         },
2263         [pbn_ADDIDATA_PCIe_2_3906250] = {
2264                 .flags          = FL_BASE0,
2265                 .num_ports      = 2,
2266                 .base_baud      = 3906250,
2267                 .uart_offset    = 0x200,
2268                 .first_offset   = 0x1000,
2269         },
2270         [pbn_ADDIDATA_PCIe_4_3906250] = {
2271                 .flags          = FL_BASE0,
2272                 .num_ports      = 4,
2273                 .base_baud      = 3906250,
2274                 .uart_offset    = 0x200,
2275                 .first_offset   = 0x1000,
2276         },
2277         [pbn_ADDIDATA_PCIe_8_3906250] = {
2278                 .flags          = FL_BASE0,
2279                 .num_ports      = 8,
2280                 .base_baud      = 3906250,
2281                 .uart_offset    = 0x200,
2282                 .first_offset   = 0x1000,
2283         },
2284 };
2285
2286 static const struct pci_device_id softmodem_blacklist[] = {
2287         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2288 };
2289
2290 /*
2291  * Given a complete unknown PCI device, try to use some heuristics to
2292  * guess what the configuration might be, based on the pitiful PCI
2293  * serial specs.  Returns 0 on success, 1 on failure.
2294  */
2295 static int __devinit
2296 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2297 {
2298         const struct pci_device_id *blacklist;
2299         int num_iomem, num_port, first_port = -1, i;
2300
2301         /*
2302          * If it is not a communications device or the programming
2303          * interface is greater than 6, give up.
2304          *
2305          * (Should we try to make guesses for multiport serial devices
2306          * later?)
2307          */
2308         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2309              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2310             (dev->class & 0xff) > 6)
2311                 return -ENODEV;
2312
2313         /*
2314          * Do not access blacklisted devices that are known not to
2315          * feature serial ports.
2316          */
2317         for (blacklist = softmodem_blacklist;
2318              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2319              blacklist++) {
2320                 if (dev->vendor == blacklist->vendor &&
2321                     dev->device == blacklist->device)
2322                         return -ENODEV;
2323         }
2324
2325         num_iomem = num_port = 0;
2326         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2327                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2328                         num_port++;
2329                         if (first_port == -1)
2330                                 first_port = i;
2331                 }
2332                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2333                         num_iomem++;
2334         }
2335
2336         /*
2337          * If there is 1 or 0 iomem regions, and exactly one port,
2338          * use it.  We guess the number of ports based on the IO
2339          * region size.
2340          */
2341         if (num_iomem <= 1 && num_port == 1) {
2342                 board->flags = first_port;
2343                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2344                 return 0;
2345         }
2346
2347         /*
2348          * Now guess if we've got a board which indexes by BARs.
2349          * Each IO BAR should be 8 bytes, and they should follow
2350          * consecutively.
2351          */
2352         first_port = -1;
2353         num_port = 0;
2354         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2355                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2356                     pci_resource_len(dev, i) == 8 &&
2357                     (first_port == -1 || (first_port + num_port) == i)) {
2358                         num_port++;
2359                         if (first_port == -1)
2360                                 first_port = i;
2361                 }
2362         }
2363
2364         if (num_port > 1) {
2365                 board->flags = first_port | FL_BASE_BARS;
2366                 board->num_ports = num_port;
2367                 return 0;
2368         }
2369
2370         return -ENODEV;
2371 }
2372
2373 static inline int
2374 serial_pci_matches(const struct pciserial_board *board,
2375                    const struct pciserial_board *guessed)
2376 {
2377         return
2378             board->num_ports == guessed->num_ports &&
2379             board->base_baud == guessed->base_baud &&
2380             board->uart_offset == guessed->uart_offset &&
2381             board->reg_shift == guessed->reg_shift &&
2382             board->first_offset == guessed->first_offset;
2383 }
2384
2385 struct serial_private *
2386 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2387 {
2388         struct uart_port serial_port;
2389         struct serial_private *priv;
2390         struct pci_serial_quirk *quirk;
2391         int rc, nr_ports, i;
2392
2393         nr_ports = board->num_ports;
2394
2395         /*
2396          * Find an init and setup quirks.
2397          */
2398         quirk = find_quirk(dev);
2399
2400         /*
2401          * Run the new-style initialization function.
2402          * The initialization function returns:
2403          *  <0  - error
2404          *   0  - use board->num_ports
2405          *  >0  - number of ports
2406          */
2407         if (quirk->init) {
2408                 rc = quirk->init(dev);
2409                 if (rc < 0) {
2410                         priv = ERR_PTR(rc);
2411                         goto err_out;
2412                 }
2413                 if (rc)
2414                         nr_ports = rc;
2415         }
2416
2417         priv = kzalloc(sizeof(struct serial_private) +
2418                        sizeof(unsigned int) * nr_ports,
2419                        GFP_KERNEL);
2420         if (!priv) {
2421                 priv = ERR_PTR(-ENOMEM);
2422                 goto err_deinit;
2423         }
2424
2425         priv->dev = dev;
2426         priv->quirk = quirk;
2427
2428         memset(&serial_port, 0, sizeof(struct uart_port));
2429         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2430         serial_port.uartclk = board->base_baud * 16;
2431         serial_port.irq = get_pci_irq(dev, board);
2432         serial_port.dev = &dev->dev;
2433
2434         for (i = 0; i < nr_ports; i++) {
2435                 if (quirk->setup(priv, board, &serial_port, i))
2436                         break;
2437
2438 #ifdef SERIAL_DEBUG_PCI
2439                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2440                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2441 #endif
2442
2443                 priv->line[i] = serial8250_register_port(&serial_port);
2444                 if (priv->line[i] < 0) {
2445                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2446                         break;
2447                 }
2448         }
2449         priv->nr = i;
2450         return priv;
2451
2452 err_deinit:
2453         if (quirk->exit)
2454                 quirk->exit(dev);
2455 err_out:
2456         return priv;
2457 }
2458 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2459
2460 void pciserial_remove_ports(struct serial_private *priv)
2461 {
2462         struct pci_serial_quirk *quirk;
2463         int i;
2464
2465         for (i = 0; i < priv->nr; i++)
2466                 serial8250_unregister_port(priv->line[i]);
2467
2468         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2469                 if (priv->remapped_bar[i])
2470                         iounmap(priv->remapped_bar[i]);
2471                 priv->remapped_bar[i] = NULL;
2472         }
2473
2474         /*
2475          * Find the exit quirks.
2476          */
2477         quirk = find_quirk(priv->dev);
2478         if (quirk->exit)
2479                 quirk->exit(priv->dev);
2480
2481         kfree(priv);
2482 }
2483 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2484
2485 void pciserial_suspend_ports(struct serial_private *priv)
2486 {
2487         int i;
2488
2489         for (i = 0; i < priv->nr; i++)
2490                 if (priv->line[i] >= 0)
2491                         serial8250_suspend_port(priv->line[i]);
2492 }
2493 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2494
2495 void pciserial_resume_ports(struct serial_private *priv)
2496 {
2497         int i;
2498
2499         /*
2500          * Ensure that the board is correctly configured.
2501          */
2502         if (priv->quirk->init)
2503                 priv->quirk->init(priv->dev);
2504
2505         for (i = 0; i < priv->nr; i++)
2506                 if (priv->line[i] >= 0)
2507                         serial8250_resume_port(priv->line[i]);
2508 }
2509 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2510
2511 /*
2512  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2513  * to the arrangement of serial ports on a PCI card.
2514  */
2515 static int __devinit
2516 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2517 {
2518         struct serial_private *priv;
2519         const struct pciserial_board *board;
2520         struct pciserial_board tmp;
2521         int rc;
2522
2523         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2524                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2525                         ent->driver_data);
2526                 return -EINVAL;
2527         }
2528
2529         board = &pci_boards[ent->driver_data];
2530
2531         rc = pci_enable_device(dev);
2532         if (rc)
2533                 return rc;
2534
2535         if (ent->driver_data == pbn_default) {
2536                 /*
2537                  * Use a copy of the pci_board entry for this;
2538                  * avoid changing entries in the table.
2539                  */
2540                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2541                 board = &tmp;
2542
2543                 /*
2544                  * We matched one of our class entries.  Try to
2545                  * determine the parameters of this board.
2546                  */
2547                 rc = serial_pci_guess_board(dev, &tmp);
2548                 if (rc)
2549                         goto disable;
2550         } else {
2551                 /*
2552                  * We matched an explicit entry.  If we are able to
2553                  * detect this boards settings with our heuristic,
2554                  * then we no longer need this entry.
2555                  */
2556                 memcpy(&tmp, &pci_boards[pbn_default],
2557                        sizeof(struct pciserial_board));
2558                 rc = serial_pci_guess_board(dev, &tmp);
2559                 if (rc == 0 && serial_pci_matches(board, &tmp))
2560                         moan_device("Redundant entry in serial pci_table.",
2561                                     dev);
2562         }
2563
2564         priv = pciserial_init_ports(dev, board);
2565         if (!IS_ERR(priv)) {
2566                 pci_set_drvdata(dev, priv);
2567                 return 0;
2568         }
2569
2570         rc = PTR_ERR(priv);
2571
2572  disable:
2573         pci_disable_device(dev);
2574         return rc;
2575 }
2576
2577 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2578 {
2579         struct serial_private *priv = pci_get_drvdata(dev);
2580
2581         pci_set_drvdata(dev, NULL);
2582
2583         pciserial_remove_ports(priv);
2584
2585         pci_disable_device(dev);
2586 }
2587
2588 #ifdef CONFIG_PM
2589 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2590 {
2591         struct serial_private *priv = pci_get_drvdata(dev);
2592
2593         if (priv)
2594                 pciserial_suspend_ports(priv);
2595
2596         pci_save_state(dev);
2597         pci_set_power_state(dev, pci_choose_state(dev, state));
2598         return 0;
2599 }
2600
2601 static int pciserial_resume_one(struct pci_dev *dev)
2602 {
2603         int err;
2604         struct serial_private *priv = pci_get_drvdata(dev);
2605
2606         pci_set_power_state(dev, PCI_D0);
2607         pci_restore_state(dev);
2608
2609         if (priv) {
2610                 /*
2611                  * The device may have been disabled.  Re-enable it.
2612                  */
2613                 err = pci_enable_device(dev);
2614                 /* FIXME: We cannot simply error out here */
2615                 if (err)
2616                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2617                 pciserial_resume_ports(priv);
2618         }
2619         return 0;
2620 }
2621 #endif
2622
2623 static struct pci_device_id serial_pci_tbl[] = {
2624         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2625         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2626                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2627                 pbn_b2_8_921600 },
2628         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2629                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2630                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2631                 pbn_b1_8_1382400 },
2632         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2633                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2634                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2635                 pbn_b1_4_1382400 },
2636         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2637                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2638                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2639                 pbn_b1_2_1382400 },
2640         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2641                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2642                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2643                 pbn_b1_8_1382400 },
2644         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2645                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2646                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2647                 pbn_b1_4_1382400 },
2648         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2649                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2650                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2651                 pbn_b1_2_1382400 },
2652         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2653                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2654                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2655                 pbn_b1_8_921600 },
2656         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2657                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2658                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2659                 pbn_b1_8_921600 },
2660         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2661                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2662                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2663                 pbn_b1_4_921600 },
2664         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2665                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2666                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2667                 pbn_b1_4_921600 },
2668         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2669                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2670                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2671                 pbn_b1_2_921600 },
2672         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2673                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2674                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2675                 pbn_b1_8_921600 },
2676         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2677                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2678                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2679                 pbn_b1_8_921600 },
2680         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2681                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2682                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2683                 pbn_b1_4_921600 },
2684         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2685                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2686                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2687                 pbn_b1_2_1250000 },
2688         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2689                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2690                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2691                 pbn_b0_2_1843200 },
2692         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2693                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2694                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2695                 pbn_b0_4_1843200 },
2696         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2697                 PCI_VENDOR_ID_AFAVLAB,
2698                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2699                 pbn_b0_4_1152000 },
2700         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2701                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2702                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2703                 pbn_b0_2_1843200_200 },
2704         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2705                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2706                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2707                 pbn_b0_4_1843200_200 },
2708         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2709                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2710                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2711                 pbn_b0_8_1843200_200 },
2712         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2713                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2714                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2715                 pbn_b0_2_1843200_200 },
2716         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2717                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2718                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2719                 pbn_b0_4_1843200_200 },
2720         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2721                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2722                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2723                 pbn_b0_8_1843200_200 },
2724         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2725                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2726                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2727                 pbn_b0_2_1843200_200 },
2728         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2729                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2730                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2731                 pbn_b0_4_1843200_200 },
2732         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2733                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2734                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2735                 pbn_b0_8_1843200_200 },
2736         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2737                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2738                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2739                 pbn_b0_2_1843200_200 },
2740         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2741                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2742                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2743                 pbn_b0_4_1843200_200 },
2744         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2745                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2746                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2747                 pbn_b0_8_1843200_200 },
2748         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2749                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2750                 0, 0, pbn_exar_ibm_saturn },
2751
2752         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2753                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2754                 pbn_b2_bt_1_115200 },
2755         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2756                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2757                 pbn_b2_bt_2_115200 },
2758         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2759                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2760                 pbn_b2_bt_4_115200 },
2761         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2762                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2763                 pbn_b2_bt_2_115200 },
2764         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2765                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2766                 pbn_b2_bt_4_115200 },
2767         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2768                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2769                 pbn_b2_8_115200 },
2770         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2771                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2772                 pbn_b2_8_460800 },
2773         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2774                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2775                 pbn_b2_8_115200 },
2776
2777         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2778                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2779                 pbn_b2_bt_2_115200 },
2780         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2781                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2782                 pbn_b2_bt_2_921600 },
2783         /*
2784          * VScom SPCOM800, from sl@s.pl
2785          */
2786         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2787                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2788                 pbn_b2_8_921600 },
2789         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2791                 pbn_b2_4_921600 },
2792         /* Unknown card - subdevice 0x1584 */
2793         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2794                 PCI_VENDOR_ID_PLX,
2795                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2796                 pbn_b0_4_115200 },
2797         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2798                 PCI_SUBVENDOR_ID_KEYSPAN,
2799                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2800                 pbn_panacom },
2801         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803                 pbn_panacom4 },
2804         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806                 pbn_panacom2 },
2807         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2808                 PCI_VENDOR_ID_ESDGMBH,
2809                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2810                 pbn_b2_4_115200 },
2811         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2812                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2813                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2814                 pbn_b2_4_460800 },
2815         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2816                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2817                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2818                 pbn_b2_8_460800 },
2819         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2820                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2821                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2822                 pbn_b2_16_460800 },
2823         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2824                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2825                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2826                 pbn_b2_16_460800 },
2827         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2828                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2829                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2830                 pbn_b2_4_460800 },
2831         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2832                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2833                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2834                 pbn_b2_8_460800 },
2835         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2836                 PCI_SUBVENDOR_ID_EXSYS,
2837                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2838                 pbn_exsys_4055 },
2839         /*
2840          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2841          * (Exoray@isys.ca)
2842          */
2843         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2844                 0x10b5, 0x106a, 0, 0,
2845                 pbn_plx_romulus },
2846         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2848                 pbn_b1_4_115200 },
2849         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2850                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2851                 pbn_b1_2_115200 },
2852         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2853                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2854                 pbn_b1_8_115200 },
2855         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2856                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2857                 pbn_b1_8_115200 },
2858         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2859                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2860                 0, 0,
2861                 pbn_b0_4_921600 },
2862         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2863                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2864                 0, 0,
2865                 pbn_b0_4_1152000 },
2866
2867                 /*
2868                  * The below card is a little controversial since it is the
2869                  * subject of a PCI vendor/device ID clash.  (See
2870                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2871                  * For now just used the hex ID 0x950a.
2872                  */
2873         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2874                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2875                 pbn_b0_2_115200 },
2876         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2877                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2878                 pbn_b0_2_1130000 },
2879         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2880                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2881                 pbn_b0_1_921600 },
2882         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2884                 pbn_b0_4_115200 },
2885         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2886                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887                 pbn_b0_bt_2_921600 },
2888         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2889                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2890                 pbn_b2_8_1152000 },
2891
2892         /*
2893          * Oxford Semiconductor Inc. Tornado PCI express device range.
2894          */
2895         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
2896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897                 pbn_b0_1_4000000 },
2898         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
2899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900                 pbn_b0_1_4000000 },
2901         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
2902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2903                 pbn_oxsemi_1_4000000 },
2904         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
2905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2906                 pbn_oxsemi_1_4000000 },
2907         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
2908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2909                 pbn_b0_1_4000000 },
2910         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
2911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2912                 pbn_b0_1_4000000 },
2913         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
2914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2915                 pbn_oxsemi_1_4000000 },
2916         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
2917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2918                 pbn_oxsemi_1_4000000 },
2919         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
2920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921                 pbn_b0_1_4000000 },
2922         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
2923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2924                 pbn_b0_1_4000000 },
2925         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
2926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2927                 pbn_b0_1_4000000 },
2928         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
2929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2930                 pbn_b0_1_4000000 },
2931         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
2932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2933                 pbn_oxsemi_2_4000000 },
2934         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
2935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2936                 pbn_oxsemi_2_4000000 },
2937         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
2938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2939                 pbn_oxsemi_4_4000000 },
2940         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
2941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2942                 pbn_oxsemi_4_4000000 },
2943         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
2944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2945                 pbn_oxsemi_8_4000000 },
2946         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
2947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2948                 pbn_oxsemi_8_4000000 },
2949         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
2950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2951                 pbn_oxsemi_1_4000000 },
2952         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
2953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2954                 pbn_oxsemi_1_4000000 },
2955         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
2956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2957                 pbn_oxsemi_1_4000000 },
2958         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
2959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2960                 pbn_oxsemi_1_4000000 },
2961         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
2962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2963                 pbn_oxsemi_1_4000000 },
2964         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
2965                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2966                 pbn_oxsemi_1_4000000 },
2967         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
2968                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2969                 pbn_oxsemi_1_4000000 },
2970         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
2971                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2972                 pbn_oxsemi_1_4000000 },
2973         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
2974                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2975                 pbn_oxsemi_1_4000000 },
2976         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
2977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2978                 pbn_oxsemi_1_4000000 },
2979         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
2980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2981                 pbn_oxsemi_1_4000000 },
2982         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
2983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2984                 pbn_oxsemi_1_4000000 },
2985         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
2986                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2987                 pbn_oxsemi_1_4000000 },
2988         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
2989                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2990                 pbn_oxsemi_1_4000000 },
2991         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
2992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993                 pbn_oxsemi_1_4000000 },
2994         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
2995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2996                 pbn_oxsemi_1_4000000 },
2997         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
2998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2999                 pbn_oxsemi_1_4000000 },
3000         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3002                 pbn_oxsemi_1_4000000 },
3003         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3005                 pbn_oxsemi_1_4000000 },
3006         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3008                 pbn_oxsemi_1_4000000 },
3009         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3011                 pbn_oxsemi_1_4000000 },
3012         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3014                 pbn_oxsemi_1_4000000 },
3015         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3017                 pbn_oxsemi_1_4000000 },
3018         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3020                 pbn_oxsemi_1_4000000 },
3021         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3023                 pbn_oxsemi_1_4000000 },
3024         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3025                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3026                 pbn_oxsemi_1_4000000 },
3027         /*
3028          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3029          */
3030         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3031                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3032                 pbn_oxsemi_1_4000000 },
3033         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3034                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3035                 pbn_oxsemi_2_4000000 },
3036         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3037                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3038                 pbn_oxsemi_4_4000000 },
3039         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3040                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3041                 pbn_oxsemi_8_4000000 },
3042         /*
3043          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3044          * from skokodyn@yahoo.com
3045          */
3046         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3047                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3048                 pbn_sbsxrsio },
3049         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3050                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3051                 pbn_sbsxrsio },
3052         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3053                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3054                 pbn_sbsxrsio },
3055         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3056                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3057                 pbn_sbsxrsio },
3058
3059         /*
3060          * Digitan DS560-558, from jimd@esoft.com
3061          */
3062         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3063                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3064                 pbn_b1_1_115200 },
3065
3066         /*
3067          * Titan Electronic cards
3068          *  The 400L and 800L have a custom setup quirk.
3069          */
3070         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3071                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3072                 pbn_b0_1_921600 },
3073         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3075                 pbn_b0_2_921600 },
3076         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3077                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078                 pbn_b0_4_921600 },
3079         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081                 pbn_b0_4_921600 },
3082         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084                 pbn_b1_1_921600 },
3085         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087                 pbn_b1_bt_2_921600 },
3088         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090                 pbn_b0_bt_4_921600 },
3091         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093                 pbn_b0_bt_8_921600 },
3094         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096                 pbn_b4_bt_2_921600 },
3097         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099                 pbn_b4_bt_4_921600 },
3100         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102                 pbn_b4_bt_8_921600 },
3103         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3104                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3105                 pbn_b0_4_921600 },
3106         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3107                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3108                 pbn_b0_4_921600 },
3109         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3110                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3111                 pbn_b0_4_921600 },
3112         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3113                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3114                 pbn_oxsemi_1_4000000 },
3115         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3117                 pbn_oxsemi_2_4000000 },
3118         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120                 pbn_oxsemi_4_4000000 },
3121         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3123                 pbn_oxsemi_8_4000000 },
3124         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3125                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126                 pbn_oxsemi_2_4000000 },
3127         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3128                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129                 pbn_oxsemi_2_4000000 },
3130
3131         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133                 pbn_b2_1_460800 },
3134         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3135                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136                 pbn_b2_1_460800 },
3137         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139                 pbn_b2_1_460800 },
3140         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3141                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142                 pbn_b2_bt_2_921600 },
3143         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3144                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145                 pbn_b2_bt_2_921600 },
3146         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148                 pbn_b2_bt_2_921600 },
3149         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151                 pbn_b2_bt_4_921600 },
3152         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3154                 pbn_b2_bt_4_921600 },
3155         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157                 pbn_b2_bt_4_921600 },
3158         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160                 pbn_b0_1_921600 },
3161         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163                 pbn_b0_1_921600 },
3164         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166                 pbn_b0_1_921600 },
3167         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3169                 pbn_b0_bt_2_921600 },
3170         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172                 pbn_b0_bt_2_921600 },
3173         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175                 pbn_b0_bt_2_921600 },
3176         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178                 pbn_b0_bt_4_921600 },
3179         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181                 pbn_b0_bt_4_921600 },
3182         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184                 pbn_b0_bt_4_921600 },
3185         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187                 pbn_b0_bt_8_921600 },
3188         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190                 pbn_b0_bt_8_921600 },
3191         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193                 pbn_b0_bt_8_921600 },
3194
3195         /*
3196          * Computone devices submitted by Doug McNash dmcnash@computone.com
3197          */
3198         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3199                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3200                 0, 0, pbn_computone_4 },
3201         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3202                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3203                 0, 0, pbn_computone_8 },
3204         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3205                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3206                 0, 0, pbn_computone_6 },
3207
3208         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210                 pbn_oxsemi },
3211         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3212                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3213                 pbn_b0_bt_1_921600 },
3214
3215         /*
3216          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3217          */
3218         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220                 pbn_b0_bt_8_115200 },
3221         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223                 pbn_b0_bt_8_115200 },
3224
3225         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3226                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227                 pbn_b0_bt_2_115200 },
3228         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230                 pbn_b0_bt_2_115200 },
3231         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233                 pbn_b0_bt_2_115200 },
3234         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236                 pbn_b0_bt_2_115200 },
3237         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_b0_bt_2_115200 },
3240         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b0_bt_4_460800 },
3243         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_b0_bt_4_460800 },
3246         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_b0_bt_2_460800 },
3249         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_b0_bt_2_460800 },
3252         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_b0_bt_2_460800 },
3255         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_b0_bt_1_115200 },
3258         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b0_bt_1_460800 },
3261
3262         /*
3263          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3264          * Cards are identified by their subsystem vendor IDs, which
3265          * (in hex) match the model number.
3266          *
3267          * Note that JC140x are RS422/485 cards which require ox950
3268          * ACR = 0x10, and as such are not currently fully supported.
3269          */
3270         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3271                 0x1204, 0x0004, 0, 0,
3272                 pbn_b0_4_921600 },
3273         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3274                 0x1208, 0x0004, 0, 0,
3275                 pbn_b0_4_921600 },
3276 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3277                 0x1402, 0x0002, 0, 0,
3278                 pbn_b0_2_921600 }, */
3279 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3280                 0x1404, 0x0004, 0, 0,
3281                 pbn_b0_4_921600 }, */
3282         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3283                 0x1208, 0x0004, 0, 0,
3284                 pbn_b0_4_921600 },
3285
3286         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3287                 0x1204, 0x0004, 0, 0,
3288                 pbn_b0_4_921600 },
3289         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3290                 0x1208, 0x0004, 0, 0,
3291                 pbn_b0_4_921600 },
3292         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3293                 0x1208, 0x0004, 0, 0,
3294                 pbn_b0_4_921600 },
3295         /*
3296          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3297          */
3298         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300                 pbn_b1_1_1382400 },
3301
3302         /*
3303          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3304          */
3305         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307                 pbn_b1_1_1382400 },
3308
3309         /*
3310          * RAStel 2 port modem, gerg@moreton.com.au
3311          */
3312         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314                 pbn_b2_bt_2_115200 },
3315
3316         /*
3317          * EKF addition for i960 Boards form EKF with serial port
3318          */
3319         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3320                 0xE4BF, PCI_ANY_ID, 0, 0,
3321                 pbn_intel_i960 },
3322
3323         /*
3324          * Xircom Cardbus/Ethernet combos
3325          */
3326         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328                 pbn_b0_1_115200 },
3329         /*
3330          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3331          */
3332         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334                 pbn_b0_1_115200 },
3335
3336         /*
3337          * Untested PCI modems, sent in from various folks...
3338          */
3339
3340         /*
3341          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3342          */
3343         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3344                 0x1048, 0x1500, 0, 0,
3345                 pbn_b1_1_115200 },
3346
3347         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3348                 0xFF00, 0, 0, 0,
3349                 pbn_sgi_ioc3 },
3350
3351         /*
3352          * HP Diva card
3353          */
3354         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3355                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3356                 pbn_b1_1_115200 },
3357         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359                 pbn_b0_5_115200 },
3360         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362                 pbn_b2_1_115200 },
3363
3364         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3365                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3366                 pbn_b3_2_115200 },
3367         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3368                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3369                 pbn_b3_4_115200 },
3370         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3371                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3372                 pbn_b3_8_115200 },
3373
3374         /*
3375          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3376          */
3377         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3378                 PCI_ANY_ID, PCI_ANY_ID,
3379                 0,
3380                 0, pbn_exar_XR17C152 },
3381         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3382                 PCI_ANY_ID, PCI_ANY_ID,
3383                 0,
3384                 0, pbn_exar_XR17C154 },
3385         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3386                 PCI_ANY_ID, PCI_ANY_ID,
3387                 0,
3388                 0, pbn_exar_XR17C158 },
3389
3390         /*
3391          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3392          */
3393         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3394                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3395                 pbn_b0_1_115200 },
3396         /*
3397          * ITE
3398          */
3399         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3400                 PCI_ANY_ID, PCI_ANY_ID,
3401                 0, 0,
3402                 pbn_b1_bt_1_115200 },
3403
3404         /*
3405          * IntaShield IS-200
3406          */
3407         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3409                 pbn_b2_2_115200 },
3410         /*
3411          * IntaShield IS-400
3412          */
3413         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3415                 pbn_b2_4_115200 },
3416         /*
3417          * Perle PCI-RAS cards
3418          */
3419         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3420                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3421                 0, 0, pbn_b2_4_921600 },
3422         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3423                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3424                 0, 0, pbn_b2_8_921600 },
3425
3426         /*
3427          * Mainpine series cards: Fairly standard layout but fools
3428          * parts of the autodetect in some cases and uses otherwise
3429          * unmatched communications subclasses in the PCI Express case
3430          */
3431
3432         {       /* RockForceDUO */
3433                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3434                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3435                 0, 0, pbn_b0_2_115200 },
3436         {       /* RockForceQUATRO */
3437                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3438                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3439                 0, 0, pbn_b0_4_115200 },
3440         {       /* RockForceDUO+ */
3441                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3442                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3443                 0, 0, pbn_b0_2_115200 },
3444         {       /* RockForceQUATRO+ */
3445                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3446                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3447                 0, 0, pbn_b0_4_115200 },
3448         {       /* RockForce+ */
3449                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3450                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3451                 0, 0, pbn_b0_2_115200 },
3452         {       /* RockForce+ */
3453                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3454                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3455                 0, 0, pbn_b0_4_115200 },
3456         {       /* RockForceOCTO+ */
3457                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3458                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3459                 0, 0, pbn_b0_8_115200 },
3460         {       /* RockForceDUO+ */
3461                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3462                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3463                 0, 0, pbn_b0_2_115200 },
3464         {       /* RockForceQUARTRO+ */
3465                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3466                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3467                 0, 0, pbn_b0_4_115200 },
3468         {       /* RockForceOCTO+ */
3469                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3470                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3471                 0, 0, pbn_b0_8_115200 },
3472         {       /* RockForceD1 */
3473                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3474                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3475                 0, 0, pbn_b0_1_115200 },
3476         {       /* RockForceF1 */
3477                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3478                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3479                 0, 0, pbn_b0_1_115200 },
3480         {       /* RockForceD2 */
3481                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3482                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3483                 0, 0, pbn_b0_2_115200 },
3484         {       /* RockForceF2 */
3485                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3486                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3487                 0, 0, pbn_b0_2_115200 },
3488         {       /* RockForceD4 */
3489                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3490                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3491                 0, 0, pbn_b0_4_115200 },
3492         {       /* RockForceF4 */
3493                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3494                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3495                 0, 0, pbn_b0_4_115200 },
3496         {       /* RockForceD8 */
3497                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3498                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3499                 0, 0, pbn_b0_8_115200 },
3500         {       /* RockForceF8 */
3501                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3502                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3503                 0, 0, pbn_b0_8_115200 },
3504         {       /* IQ Express D1 */
3505                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3506                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3507                 0, 0, pbn_b0_1_115200 },
3508         {       /* IQ Express F1 */
3509                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3510                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3511                 0, 0, pbn_b0_1_115200 },
3512         {       /* IQ Express D2 */
3513                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3514                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3515                 0, 0, pbn_b0_2_115200 },
3516         {       /* IQ Express F2 */
3517                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3518                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3519                 0, 0, pbn_b0_2_115200 },
3520         {       /* IQ Express D4 */
3521                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3522                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3523                 0, 0, pbn_b0_4_115200 },
3524         {       /* IQ Express F4 */
3525                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3526                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3527                 0, 0, pbn_b0_4_115200 },
3528         {       /* IQ Express D8 */
3529                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3530                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3531                 0, 0, pbn_b0_8_115200 },
3532         {       /* IQ Express F8 */
3533                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3534                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3535                 0, 0, pbn_b0_8_115200 },
3536
3537
3538         /*
3539          * PA Semi PA6T-1682M on-chip UART
3540          */
3541         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3542                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543                 pbn_pasemi_1682M },
3544
3545         /*
3546          * National Instruments
3547          */
3548         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3550                 pbn_b1_16_115200 },
3551         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3553                 pbn_b1_8_115200 },
3554         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3556                 pbn_b1_bt_4_115200 },
3557         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3558                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3559                 pbn_b1_bt_2_115200 },
3560         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3561                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3562                 pbn_b1_bt_4_115200 },
3563         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3564                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3565                 pbn_b1_bt_2_115200 },
3566         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568                 pbn_b1_16_115200 },
3569         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571                 pbn_b1_8_115200 },
3572         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574                 pbn_b1_bt_4_115200 },
3575         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_b1_bt_2_115200 },
3578         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580                 pbn_b1_bt_4_115200 },
3581         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583                 pbn_b1_bt_2_115200 },
3584         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586                 pbn_ni8430_2 },
3587         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589                 pbn_ni8430_2 },
3590         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592                 pbn_ni8430_4 },
3593         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595                 pbn_ni8430_4 },
3596         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598                 pbn_ni8430_8 },
3599         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601                 pbn_ni8430_8 },
3602         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3603                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604                 pbn_ni8430_16 },
3605         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3606                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607                 pbn_ni8430_16 },
3608         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610                 pbn_ni8430_2 },
3611         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613                 pbn_ni8430_2 },
3614         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616                 pbn_ni8430_4 },
3617         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619                 pbn_ni8430_4 },
3620
3621         /*
3622         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3623         */
3624         {       PCI_VENDOR_ID_ADDIDATA,
3625                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3626                 PCI_ANY_ID,
3627                 PCI_ANY_ID,
3628                 0,
3629                 0,
3630                 pbn_b0_4_115200 },
3631
3632         {       PCI_VENDOR_ID_ADDIDATA,
3633                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3634                 PCI_ANY_ID,
3635                 PCI_ANY_ID,
3636                 0,
3637                 0,
3638                 pbn_b0_2_115200 },
3639
3640         {       PCI_VENDOR_ID_ADDIDATA,
3641                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3642                 PCI_ANY_ID,
3643                 PCI_ANY_ID,
3644                 0,
3645                 0,
3646                 pbn_b0_1_115200 },
3647
3648         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3649                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3650                 PCI_ANY_ID,
3651                 PCI_ANY_ID,
3652                 0,
3653                 0,
3654                 pbn_b1_8_115200 },
3655
3656         {       PCI_VENDOR_ID_ADDIDATA,
3657                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3658                 PCI_ANY_ID,
3659                 PCI_ANY_ID,
3660                 0,
3661                 0,
3662                 pbn_b0_4_115200 },
3663
3664         {       PCI_VENDOR_ID_ADDIDATA,
3665                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3666                 PCI_ANY_ID,
3667                 PCI_ANY_ID,
3668                 0,
3669                 0,
3670                 pbn_b0_2_115200 },
3671
3672         {       PCI_VENDOR_ID_ADDIDATA,
3673                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3674                 PCI_ANY_ID,
3675                 PCI_ANY_ID,
3676                 0,
3677                 0,
3678                 pbn_b0_1_115200 },
3679
3680         {       PCI_VENDOR_ID_ADDIDATA,
3681                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3682                 PCI_ANY_ID,
3683                 PCI_ANY_ID,
3684                 0,
3685                 0,
3686                 pbn_b0_4_115200 },
3687
3688         {       PCI_VENDOR_ID_ADDIDATA,
3689                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3690                 PCI_ANY_ID,
3691                 PCI_ANY_ID,
3692                 0,
3693                 0,
3694                 pbn_b0_2_115200 },
3695
3696         {       PCI_VENDOR_ID_ADDIDATA,
3697                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3698                 PCI_ANY_ID,
3699                 PCI_ANY_ID,
3700                 0,
3701                 0,
3702                 pbn_b0_1_115200 },
3703
3704         {       PCI_VENDOR_ID_ADDIDATA,
3705                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3706                 PCI_ANY_ID,
3707                 PCI_ANY_ID,
3708                 0,
3709                 0,
3710                 pbn_b0_8_115200 },
3711
3712         {       PCI_VENDOR_ID_ADDIDATA,
3713                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3714                 PCI_ANY_ID,
3715                 PCI_ANY_ID,
3716                 0,
3717                 0,
3718                 pbn_ADDIDATA_PCIe_4_3906250 },
3719
3720         {       PCI_VENDOR_ID_ADDIDATA,
3721                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3722                 PCI_ANY_ID,
3723                 PCI_ANY_ID,
3724                 0,
3725                 0,
3726                 pbn_ADDIDATA_PCIe_2_3906250 },
3727
3728         {       PCI_VENDOR_ID_ADDIDATA,
3729                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3730                 PCI_ANY_ID,
3731                 PCI_ANY_ID,
3732                 0,
3733                 0,
3734                 pbn_ADDIDATA_PCIe_1_3906250 },
3735
3736         {       PCI_VENDOR_ID_ADDIDATA,
3737                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3738                 PCI_ANY_ID,
3739                 PCI_ANY_ID,
3740                 0,
3741                 0,
3742                 pbn_ADDIDATA_PCIe_8_3906250 },
3743
3744         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3745                 PCI_VENDOR_ID_IBM, 0x0299,
3746                 0, 0, pbn_b0_bt_2_115200 },
3747
3748         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3749                 0xA000, 0x1000,
3750                 0, 0, pbn_b0_1_115200 },
3751
3752         /*
3753          * Best Connectivity PCI Multi I/O cards
3754          */
3755
3756         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3757                 0xA000, 0x1000,
3758                 0, 0, pbn_b0_1_115200 },
3759
3760         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3761                 0xA000, 0x3004,
3762                 0, 0, pbn_b0_bt_4_115200 },
3763
3764         /*
3765          * These entries match devices with class COMMUNICATION_SERIAL,
3766          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3767          */
3768         {       PCI_ANY_ID, PCI_ANY_ID,
3769                 PCI_ANY_ID, PCI_ANY_ID,
3770                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3771                 0xffff00, pbn_default },
3772         {       PCI_ANY_ID, PCI_ANY_ID,
3773                 PCI_ANY_ID, PCI_ANY_ID,
3774                 PCI_CLASS_COMMUNICATION_MODEM << 8,
3775                 0xffff00, pbn_default },
3776         {       PCI_ANY_ID, PCI_ANY_ID,
3777                 PCI_ANY_ID, PCI_ANY_ID,
3778                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3779                 0xffff00, pbn_default },
3780         { 0, }
3781 };
3782
3783 static struct pci_driver serial_pci_driver = {
3784         .name           = "serial",
3785         .probe          = pciserial_init_one,
3786         .remove         = __devexit_p(pciserial_remove_one),
3787 #ifdef CONFIG_PM
3788         .suspend        = pciserial_suspend_one,
3789         .resume         = pciserial_resume_one,
3790 #endif
3791         .id_table       = serial_pci_tbl,
3792 };
3793
3794 static int __init serial8250_pci_init(void)
3795 {
3796         return pci_register_driver(&serial_pci_driver);
3797 }
3798
3799 static void __exit serial8250_pci_exit(void)
3800 {
3801         pci_unregister_driver(&serial_pci_driver);
3802 }
3803
3804 module_init(serial8250_pci_init);
3805 module_exit(serial8250_pci_exit);
3806
3807 MODULE_LICENSE("GPL");
3808 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3809 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);