drivers/scsi/ufs/ufs-qcom.c

   1 /*
   2  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/time.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/phy/phy.h>
  19
  20 #include "ufshcd.h"
  21 #include "ufshcd-pltfrm.h"
  22 #include "unipro.h"
  23 #include "ufs-qcom.h"
  24 #include "ufshci.h"
  25 #include "ufs_quirks.h"
  26 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  27         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  28
  29 enum {
  30         TSTBUS_UAWM,
  31         TSTBUS_UARM,
  32         TSTBUS_TXUC,
  33         TSTBUS_RXUC,
  34         TSTBUS_DFC,
  35         TSTBUS_TRLUT,
  36         TSTBUS_TMRLUT,
  37         TSTBUS_OCSC,
  38         TSTBUS_UTP_HCI,
  39         TSTBUS_COMBINED,
  40         TSTBUS_WRAPPER,
  41         TSTBUS_UNIPRO,
  42         TSTBUS_MAX,
  43 };
  44
  45 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  46
  47 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
  48 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  49 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  50                                                        u32 clk_cycles);
  51
  52 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  53                                        const char *prefix, void *priv)
  54 {
  55         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  56 }
  57
  58 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  59 {
  60         int err = 0;
  61
  62         err = ufshcd_dme_get(hba,
  63                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  64         if (err)
  65                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  66                                 __func__, err);
  67
  68         return err;
  69 }
  70
  71 static int ufs_qcom_host_clk_get(struct device *dev,
  72                 const char *name, struct clk **clk_out, bool optional)
  73 {
  74         struct clk *clk;
  75         int err = 0;
  76
  77         clk = devm_clk_get(dev, name);
  78         if (!IS_ERR(clk)) {
  79                 *clk_out = clk;
  80                 return 0;
  81         }
  82
  83         err = PTR_ERR(clk);
  84
  85         if (optional && err == -ENOENT) {
  86                 *clk_out = NULL;
  87                 return 0;
  88         }
  89
  90         if (err != -EPROBE_DEFER)
  91                 dev_err(dev, "failed to get %s err %d\n", name, err);
  92
  93         return err;
  94 }
  95
  96 static int ufs_qcom_host_clk_enable(struct device *dev,
  97                 const char *name, struct clk *clk)
  98 {
  99         int err = 0;
 100
 101         err = clk_prepare_enable(clk);
 102         if (err)
 103                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 104
 105         return err;
 106 }
 107
 108 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 109 {
 110         if (!host->is_lane_clks_enabled)
 111                 return;
 112
 113         clk_disable_unprepare(host->tx_l1_sync_clk);
 114         clk_disable_unprepare(host->tx_l0_sync_clk);
 115         clk_disable_unprepare(host->rx_l1_sync_clk);
 116         clk_disable_unprepare(host->rx_l0_sync_clk);
 117
 118         host->is_lane_clks_enabled = false;
 119 }
 120
 121 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 122 {
 123         int err = 0;
 124         struct device *dev = host->hba->dev;
 125
 126         if (host->is_lane_clks_enabled)
 127                 return 0;
 128
 129         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 130                 host->rx_l0_sync_clk);
 131         if (err)
 132                 goto out;
 133
 134         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 135                 host->tx_l0_sync_clk);
 136         if (err)
 137                 goto disable_rx_l0;
 138
 139         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 140                         host->rx_l1_sync_clk);
 141         if (err)
 142                 goto disable_tx_l0;
 143
 144         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 145                         host->tx_l1_sync_clk);
 146         if (err)
 147                 goto disable_rx_l1;
 148
 149         host->is_lane_clks_enabled = true;
 150         goto out;
 151
 152 disable_rx_l1:
 153         clk_disable_unprepare(host->rx_l1_sync_clk);
 154 disable_tx_l0:
 155         clk_disable_unprepare(host->tx_l0_sync_clk);
 156 disable_rx_l0:
 157         clk_disable_unprepare(host->rx_l0_sync_clk);
 158 out:
 159         return err;
 160 }
 161
 162 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 163 {
 164         int err = 0;
 165         struct device *dev = host->hba->dev;
 166
 167         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 168                                         &host->rx_l0_sync_clk, false);
 169         if (err)
 170                 goto out;
 171
 172         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 173                                         &host->tx_l0_sync_clk, false);
 174         if (err)
 175                 goto out;
 176
 177         /* In case of single lane per direction, don't read lane1 clocks */
 178         if (host->hba->lanes_per_direction > 1) {
 179                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 180                         &host->rx_l1_sync_clk, false);
 181                 if (err)
 182                         goto out;
 183
 184                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 185                         &host->tx_l1_sync_clk, true);
 186         }
 187 out:
 188         return err;
 189 }
 190
 191 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 192 {
 193         u32 tx_lanes;
 194
 195         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 196 }
 197
 198 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 199 {
 200         int err;
 201         u32 tx_fsm_val = 0;
 202         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 203
 204         do {
 205                 err = ufshcd_dme_get(hba,
 206                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 207                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 208                                 &tx_fsm_val);
 209                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 210                         break;
 211
 212                 /* sleep for max. 200us */
 213                 usleep_range(100, 200);
 214         } while (time_before(jiffies, timeout));
 215
 216         /*
 217          * we might have scheduled out for long during polling so
 218          * check the state again.
 219          */
 220         if (time_after(jiffies, timeout))
 221                 err = ufshcd_dme_get(hba,
 222                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 223                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 224                                 &tx_fsm_val);
 225
 226         if (err) {
 227                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 228                                 __func__, err);
 229         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 230                 err = tx_fsm_val;
 231                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 232                                 __func__, err);
 233         }
 234
 235         return err;
 236 }
 237
 238 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 239 {
 240         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 241                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 242                    REG_UFS_CFG1);
 243         /* make sure above configuration is applied before we return */
 244         mb();
 245 }
 246
 247 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 248 {
 249         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 250         struct phy *phy = host->generic_phy;
 251         int ret = 0;
 252         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 253                                                         ? true : false;
 254
 255         if (is_rate_B)
 256                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 257
 258         /* Assert PHY reset and apply PHY calibration values */
 259         ufs_qcom_assert_reset(hba);
 260         /* provide 1ms delay to let the reset pulse propagate */
 261         usleep_range(1000, 1100);
 262
 263         /* phy initialization - calibrate the phy */
 264         ret = phy_init(phy);
 265         if (ret) {
 266                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 267                         __func__, ret);
 268                 goto out;
 269         }
 270
 271         /* De-assert PHY reset and start serdes */
 272         ufs_qcom_deassert_reset(hba);
 273
 274         /*
 275          * after reset deassertion, phy will need all ref clocks,
 276          * voltage, current to settle down before starting serdes.
 277          */
 278         usleep_range(1000, 1100);
 279
 280         /* power on phy - start serdes and phy's power and clocks */
 281         ret = phy_power_on(phy);
 282         if (ret) {
 283                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 284                         __func__, ret);
 285                 goto out_disable_phy;
 286         }
 287
 288         ufs_qcom_select_unipro_mode(host);
 289
 290         return 0;
 291
 292 out_disable_phy:
 293         ufs_qcom_assert_reset(hba);
 294         phy_exit(phy);
 295 out:
 296         return ret;
 297 }
 298
 299 /*
 300  * The UTP controller has a number of internal clock gating cells (CGCs).
 301  * Internal hardware sub-modules within the UTP controller control the CGCs.
 302  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 303  * in a specific operation, UTP controller CGCs are by default disabled and
 304  * this function enables them (after every UFS link startup) to save some power
 305  * leakage.
 306  */
 307 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 308 {
 309         ufshcd_writel(hba,
 310                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 311                 REG_UFS_CFG2);
 312
 313         /* Ensure that HW clock gating is enabled before next operations */
 314         mb();
 315 }
 316
 317 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 318                                       enum ufs_notify_change_status status)
 319 {
 320         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 321         int err = 0;
 322
 323         switch (status) {
 324         case PRE_CHANGE:
 325                 ufs_qcom_power_up_sequence(hba);
 326                 /*
 327                  * The PHY PLL output is the source of tx/rx lane symbol
 328                  * clocks, hence, enable the lane clocks only after PHY
 329                  * is initialized.
 330                  */
 331                 err = ufs_qcom_enable_lane_clks(host);
 332                 break;
 333         case POST_CHANGE:
 334                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 335                 err = ufs_qcom_check_hibern8(hba);
 336                 ufs_qcom_enable_hw_clk_gating(hba);
 337
 338                 break;
 339         default:
 340                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 341                 err = -EINVAL;
 342                 break;
 343         }
 344         return err;
 345 }
 346
 347 /**
 348  * Returns zero for success and non-zero in case of a failure
 349  */
 350 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 351                                u32 hs, u32 rate, bool update_link_startup_timer)
 352 {
 353         int ret = 0;
 354         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 355         struct ufs_clk_info *clki;
 356         u32 core_clk_period_in_ns;
 357         u32 tx_clk_cycles_per_us = 0;
 358         unsigned long core_clk_rate = 0;
 359         u32 core_clk_cycles_per_us = 0;
 360
 361         static u32 pwm_fr_table[][2] = {
 362                 {UFS_PWM_G1, 0x1},
 363                 {UFS_PWM_G2, 0x1},
 364                 {UFS_PWM_G3, 0x1},
 365                 {UFS_PWM_G4, 0x1},
 366         };
 367
 368         static u32 hs_fr_table_rA[][2] = {
 369                 {UFS_HS_G1, 0x1F},
 370                 {UFS_HS_G2, 0x3e},
 371                 {UFS_HS_G3, 0x7D},
 372         };
 373
 374         static u32 hs_fr_table_rB[][2] = {
 375                 {UFS_HS_G1, 0x24},
 376                 {UFS_HS_G2, 0x49},
 377                 {UFS_HS_G3, 0x92},
 378         };
 379
 380         /*
 381          * The Qunipro controller does not use following registers:
 382          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 383          * UFS_REG_PA_LINK_STARTUP_TIMER
 384          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 385          * Aggregation logic.
 386         */
 387         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 388                 goto out;
 389
 390         if (gear == 0) {
 391                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 392                 goto out_error;
 393         }
 394
 395         list_for_each_entry(clki, &hba->clk_list_head, list) {
 396                 if (!strcmp(clki->name, "core_clk"))
 397                         core_clk_rate = clk_get_rate(clki->clk);
 398         }
 399
 400         /* If frequency is smaller than 1MHz, set to 1MHz */
 401         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 402                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 403
 404         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 405         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 406                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 407                 /*
 408                  * make sure above write gets applied before we return from
 409                  * this function.
 410                  */
 411                 mb();
 412         }
 413
 414         if (ufs_qcom_cap_qunipro(host))
 415                 goto out;
 416
 417         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 418         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 419         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 420
 421         switch (hs) {
 422         case FASTAUTO_MODE:
 423         case FAST_MODE:
 424                 if (rate == PA_HS_MODE_A) {
 425                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 426                                 dev_err(hba->dev,
 427                                         "%s: index %d exceeds table size %zu\n",
 428                                         __func__, gear,
 429                                         ARRAY_SIZE(hs_fr_table_rA));
 430                                 goto out_error;
 431                         }
 432                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 433                 } else if (rate == PA_HS_MODE_B) {
 434                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 435                                 dev_err(hba->dev,
 436                                         "%s: index %d exceeds table size %zu\n",
 437                                         __func__, gear,
 438                                         ARRAY_SIZE(hs_fr_table_rB));
 439                                 goto out_error;
 440                         }
 441                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 442                 } else {
 443                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 444                                 __func__, rate);
 445                         goto out_error;
 446                 }
 447                 break;
 448         case SLOWAUTO_MODE:
 449         case SLOW_MODE:
 450                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 451                         dev_err(hba->dev,
 452                                         "%s: index %d exceeds table size %zu\n",
 453                                         __func__, gear,
 454                                         ARRAY_SIZE(pwm_fr_table));
 455                         goto out_error;
 456                 }
 457                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 458                 break;
 459         case UNCHANGED:
 460         default:
 461                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 462                 goto out_error;
 463         }
 464
 465         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 466             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 467                 /* this register 2 fields shall be written at once */
 468                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 469                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 470                 /*
 471                  * make sure above write gets applied before we return from
 472                  * this function.
 473                  */
 474                 mb();
 475         }
 476
 477         if (update_link_startup_timer) {
 478                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 479                               REG_UFS_PA_LINK_STARTUP_TIMER);
 480                 /*
 481                  * make sure that this configuration is applied before
 482                  * we return
 483                  */
 484                 mb();
 485         }
 486         goto out;
 487
 488 out_error:
 489         ret = -EINVAL;
 490 out:
 491         return ret;
 492 }
 493
 494 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 495                                         enum ufs_notify_change_status status)
 496 {
 497         int err = 0;
 498         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 499
 500         switch (status) {
 501         case PRE_CHANGE:
 502                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 503                                         0, true)) {
 504                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 505                                 __func__);
 506                         err = -EINVAL;
 507                         goto out;
 508                 }
 509
 510                 if (ufs_qcom_cap_qunipro(host))
 511                         /*
 512                          * set unipro core clock cycles to 150 & clear clock
 513                          * divider
 514                          */
 515                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 516                                                                           150);
 517
 518                 /*
 519                  * Some UFS devices (and may be host) have issues if LCC is
 520                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 521                  * before link startup which will make sure that both host
 522                  * and device TX LCC are disabled once link startup is
 523                  * completed.
 524                  */
 525                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 526                         err = ufshcd_dme_set(hba,
 527                                         UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
 528                                         0);
 529
 530                 break;
 531         case POST_CHANGE:
 532                 ufs_qcom_link_startup_post_change(hba);
 533                 break;
 534         default:
 535                 break;
 536         }
 537
 538 out:
 539         return err;
 540 }
 541
 542 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 543 {
 544         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 545         struct phy *phy = host->generic_phy;
 546         int ret = 0;
 547
 548         if (ufs_qcom_is_link_off(hba)) {
 549                 /*
 550                  * Disable the tx/rx lane symbol clocks before PHY is
 551                  * powered down as the PLL source should be disabled
 552                  * after downstream clocks are disabled.
 553                  */
 554                 ufs_qcom_disable_lane_clks(host);
 555                 phy_power_off(phy);
 556
 557                 /* Assert PHY soft reset */
 558                 ufs_qcom_assert_reset(hba);
 559                 goto out;
 560         }
 561
 562         /*
 563          * If UniPro link is not active, PHY ref_clk, main PHY analog power
 564          * rail and low noise analog power rail for PLL can be switched off.
 565          */
 566         if (!ufs_qcom_is_link_active(hba)) {
 567                 ufs_qcom_disable_lane_clks(host);
 568                 phy_power_off(phy);
 569         }
 570
 571 out:
 572         return ret;
 573 }
 574
 575 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 576 {
 577         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 578         struct phy *phy = host->generic_phy;
 579         int err;
 580
 581         err = phy_power_on(phy);
 582         if (err) {
 583                 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
 584                         __func__, err);
 585                 goto out;
 586         }
 587
 588         err = ufs_qcom_enable_lane_clks(host);
 589         if (err)
 590                 goto out;
 591
 592         hba->is_sys_suspended = false;
 593
 594 out:
 595         return err;
 596 }
 597
 598 struct ufs_qcom_dev_params {
 599         u32 pwm_rx_gear;        /* pwm rx gear to work in */
 600         u32 pwm_tx_gear;        /* pwm tx gear to work in */
 601         u32 hs_rx_gear;         /* hs rx gear to work in */
 602         u32 hs_tx_gear;         /* hs tx gear to work in */
 603         u32 rx_lanes;           /* number of rx lanes */
 604         u32 tx_lanes;           /* number of tx lanes */
 605         u32 rx_pwr_pwm;         /* rx pwm working pwr */
 606         u32 tx_pwr_pwm;         /* tx pwm working pwr */
 607         u32 rx_pwr_hs;          /* rx hs working pwr */
 608         u32 tx_pwr_hs;          /* tx hs working pwr */
 609         u32 hs_rate;            /* rate A/B to work in HS */
 610         u32 desired_working_mode;
 611 };
 612
 613 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
 614                                       struct ufs_pa_layer_attr *dev_max,
 615                                       struct ufs_pa_layer_attr *agreed_pwr)
 616 {
 617         int min_qcom_gear;
 618         int min_dev_gear;
 619         bool is_dev_sup_hs = false;
 620         bool is_qcom_max_hs = false;
 621
 622         if (dev_max->pwr_rx == FAST_MODE)
 623                 is_dev_sup_hs = true;
 624
 625         if (qcom_param->desired_working_mode == FAST) {
 626                 is_qcom_max_hs = true;
 627                 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
 628                                       qcom_param->hs_tx_gear);
 629         } else {
 630                 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
 631                                       qcom_param->pwm_tx_gear);
 632         }
 633
 634         /*
 635          * device doesn't support HS but qcom_param->desired_working_mode is
 636          * HS, thus device and qcom_param don't agree
 637          */
 638         if (!is_dev_sup_hs && is_qcom_max_hs) {
 639                 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
 640                         __func__);
 641                 return -ENOTSUPP;
 642         } else if (is_dev_sup_hs && is_qcom_max_hs) {
 643                 /*
 644                  * since device supports HS, it supports FAST_MODE.
 645                  * since qcom_param->desired_working_mode is also HS
 646                  * then final decision (FAST/FASTAUTO) is done according
 647                  * to qcom_params as it is the restricting factor
 648                  */
 649                 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 650                                                 qcom_param->rx_pwr_hs;
 651         } else {
 652                 /*
 653                  * here qcom_param->desired_working_mode is PWM.
 654                  * it doesn't matter whether device supports HS or PWM,
 655                  * in both cases qcom_param->desired_working_mode will
 656                  * determine the mode
 657                  */
 658                  agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 659                                                 qcom_param->rx_pwr_pwm;
 660         }
 661
 662         /*
 663          * we would like tx to work in the minimum number of lanes
 664          * between device capability and vendor preferences.
 665          * the same decision will be made for rx
 666          */
 667         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 668                                                 qcom_param->tx_lanes);
 669         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 670                                                 qcom_param->rx_lanes);
 671
 672         /* device maximum gear is the minimum between device rx and tx gears */
 673         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 674
 675         /*
 676          * if both device capabilities and vendor pre-defined preferences are
 677          * both HS or both PWM then set the minimum gear to be the chosen
 678          * working gear.
 679          * if one is PWM and one is HS then the one that is PWM get to decide
 680          * what is the gear, as it is the one that also decided previously what
 681          * pwr the device will be configured to.
 682          */
 683         if ((is_dev_sup_hs && is_qcom_max_hs) ||
 684             (!is_dev_sup_hs && !is_qcom_max_hs))
 685                 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
 686                         min_t(u32, min_dev_gear, min_qcom_gear);
 687         else if (!is_dev_sup_hs)
 688                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
 689         else
 690                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
 691
 692         agreed_pwr->hs_rate = qcom_param->hs_rate;
 693         return 0;
 694 }
 695
 696 #ifdef CONFIG_MSM_BUS_SCALING
 697 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
 698                 const char *speed_mode)
 699 {
 700         struct device *dev = host->hba->dev;
 701         struct device_node *np = dev->of_node;
 702         int err;
 703         const char *key = "qcom,bus-vector-names";
 704
 705         if (!speed_mode) {
 706                 err = -EINVAL;
 707                 goto out;
 708         }
 709
 710         if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
 711                 err = of_property_match_string(np, key, "MAX");
 712         else
 713                 err = of_property_match_string(np, key, speed_mode);
 714
 715 out:
 716         if (err < 0)
 717                 dev_err(dev, "%s: Invalid %s mode %d\n",
 718                                 __func__, speed_mode, err);
 719         return err;
 720 }
 721
 722 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
 723 {
 724         int gear = max_t(u32, p->gear_rx, p->gear_tx);
 725         int lanes = max_t(u32, p->lane_rx, p->lane_tx);
 726         int pwr;
 727
 728         /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
 729         if (!gear)
 730                 gear = 1;
 731
 732         if (!lanes)
 733                 lanes = 1;
 734
 735         if (!p->pwr_rx && !p->pwr_tx) {
 736                 pwr = SLOWAUTO_MODE;
 737                 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
 738         } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
 739                  p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
 740                 pwr = FAST_MODE;
 741                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
 742                          p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
 743         } else {
 744                 pwr = SLOW_MODE;
 745                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
 746                          "PWM", gear, lanes);
 747         }
 748 }
 749
 750 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 751 {
 752         int err = 0;
 753
 754         if (vote != host->bus_vote.curr_vote) {
 755                 err = msm_bus_scale_client_update_request(
 756                                 host->bus_vote.client_handle, vote);
 757                 if (err) {
 758                         dev_err(host->hba->dev,
 759                                 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
 760                                 __func__, host->bus_vote.client_handle,
 761                                 vote, err);
 762                         goto out;
 763                 }
 764
 765                 host->bus_vote.curr_vote = vote;
 766         }
 767 out:
 768         return err;
 769 }
 770
 771 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 772 {
 773         int vote;
 774         int err = 0;
 775         char mode[BUS_VECTOR_NAME_LEN];
 776
 777         ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
 778
 779         vote = ufs_qcom_get_bus_vote(host, mode);
 780         if (vote >= 0)
 781                 err = ufs_qcom_set_bus_vote(host, vote);
 782         else
 783                 err = vote;
 784
 785         if (err)
 786                 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
 787         else
 788                 host->bus_vote.saved_vote = vote;
 789         return err;
 790 }
 791
 792 static ssize_t
 793 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 794                         char *buf)
 795 {
 796         struct ufs_hba *hba = dev_get_drvdata(dev);
 797         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 798
 799         return snprintf(buf, PAGE_SIZE, "%u\n",
 800                         host->bus_vote.is_max_bw_needed);
 801 }
 802
 803 static ssize_t
 804 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 805                 const char *buf, size_t count)
 806 {
 807         struct ufs_hba *hba = dev_get_drvdata(dev);
 808         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 809         uint32_t value;
 810
 811         if (!kstrtou32(buf, 0, &value)) {
 812                 host->bus_vote.is_max_bw_needed = !!value;
 813                 ufs_qcom_update_bus_bw_vote(host);
 814         }
 815
 816         return count;
 817 }
 818
 819 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 820 {
 821         int err;
 822         struct msm_bus_scale_pdata *bus_pdata;
 823         struct device *dev = host->hba->dev;
 824         struct platform_device *pdev = to_platform_device(dev);
 825         struct device_node *np = dev->of_node;
 826
 827         bus_pdata = msm_bus_cl_get_pdata(pdev);
 828         if (!bus_pdata) {
 829                 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
 830                 err = -ENODATA;
 831                 goto out;
 832         }
 833
 834         err = of_property_count_strings(np, "qcom,bus-vector-names");
 835         if (err < 0 || err != bus_pdata->num_usecases) {
 836                 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
 837                                 __func__, err);
 838                 goto out;
 839         }
 840
 841         host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
 842         if (!host->bus_vote.client_handle) {
 843                 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
 844                                 __func__);
 845                 err = -EFAULT;
 846                 goto out;
 847         }
 848
 849         /* cache the vote index for minimum and maximum bandwidth */
 850         host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
 851         host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
 852
 853         host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
 854         host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
 855         sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
 856         host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
 857         host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
 858         err = device_create_file(dev, &host->bus_vote.max_bus_bw);
 859 out:
 860         return err;
 861 }
 862 #else /* CONFIG_MSM_BUS_SCALING */
 863 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 864 {
 865         return 0;
 866 }
 867
 868 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 869 {
 870         return 0;
 871 }
 872
 873 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 874 {
 875         return 0;
 876 }
 877 #endif /* CONFIG_MSM_BUS_SCALING */
 878
 879 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 880 {
 881         if (host->dev_ref_clk_ctrl_mmio &&
 882             (enable ^ host->is_dev_ref_clk_enabled)) {
 883                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 884
 885                 if (enable)
 886                         temp |= host->dev_ref_clk_en_mask;
 887                 else
 888                         temp &= ~host->dev_ref_clk_en_mask;
 889
 890                 /*
 891                  * If we are here to disable this clock it might be immediately
 892                  * after entering into hibern8 in which case we need to make
 893                  * sure that device ref_clk is active at least 1us after the
 894                  * hibern8 enter.
 895                  */
 896                 if (!enable)
 897                         udelay(1);
 898
 899                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 900
 901                 /* ensure that ref_clk is enabled/disabled before we return */
 902                 wmb();
 903
 904                 /*
 905                  * If we call hibern8 exit after this, we need to make sure that
 906                  * device ref_clk is stable for at least 1us before the hibern8
 907                  * exit command.
 908                  */
 909                 if (enable)
 910                         udelay(1);
 911
 912                 host->is_dev_ref_clk_enabled = enable;
 913         }
 914 }
 915
 916 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 917                                 enum ufs_notify_change_status status,
 918                                 struct ufs_pa_layer_attr *dev_max_params,
 919                                 struct ufs_pa_layer_attr *dev_req_params)
 920 {
 921         u32 val;
 922         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 923         struct ufs_qcom_dev_params ufs_qcom_cap;
 924         int ret = 0;
 925
 926         if (!dev_req_params) {
 927                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 928                 ret = -EINVAL;
 929                 goto out;
 930         }
 931
 932         switch (status) {
 933         case PRE_CHANGE:
 934                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 935                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 936                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 937                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 938                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 939                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 940                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 941                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 942                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 943                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 944                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 945                 ufs_qcom_cap.desired_working_mode =
 946                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 947
 948                 if (host->hw_ver.major == 0x1) {
 949                         /*
 950                          * HS-G3 operations may not reliably work on legacy QCOM
 951                          * UFS host controller hardware even though capability
 952                          * exchange during link startup phase may end up
 953                          * negotiating maximum supported gear as G3.
 954                          * Hence downgrade the maximum supported gear to HS-G2.
 955                          */
 956                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 957                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 958                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 959                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 960                 }
 961
 962                 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
 963                                                  dev_max_params,
 964                                                  dev_req_params);
 965                 if (ret) {
 966                         pr_err("%s: failed to determine capabilities\n",
 967                                         __func__);
 968                         goto out;
 969                 }
 970
 971                 /* enable the device ref clock before changing to HS mode */
 972                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 973                         ufshcd_is_hs_mode(dev_req_params))
 974                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 975                 break;
 976         case POST_CHANGE:
 977                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 978                                         dev_req_params->pwr_rx,
 979                                         dev_req_params->hs_rate, false)) {
 980                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 981                                 __func__);
 982                         /*
 983                          * we return error code at the end of the routine,
 984                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 985                          * and bus voting as usual
 986                          */
 987                         ret = -EINVAL;
 988                 }
 989
 990                 val = ~(MAX_U32 << dev_req_params->lane_tx);
 991
 992                 /* cache the power mode parameters to use internally */
 993                 memcpy(&host->dev_req_params,
 994                                 dev_req_params, sizeof(*dev_req_params));
 995                 ufs_qcom_update_bus_bw_vote(host);
 996
 997                 /* disable the device ref clock if entered PWM mode */
 998                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 999                         !ufshcd_is_hs_mode(dev_req_params))
1000                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1001                 break;
1002         default:
1003                 ret = -EINVAL;
1004                 break;
1005         }
1006 out:
1007         return ret;
1008 }
1009
1010 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
1011 {
1012         int err;
1013         u32 pa_vs_config_reg1;
1014
1015         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1016                              &pa_vs_config_reg1);
1017         if (err)
1018                 goto out;
1019
1020         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1021         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1022                             (pa_vs_config_reg1 | (1 << 12)));
1023
1024 out:
1025         return err;
1026 }
1027
1028 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1029 {
1030         int err = 0;
1031
1032         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1033                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1034
1035         return err;
1036 }
1037
1038 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1039 {
1040         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1041
1042         if (host->hw_ver.major == 0x1)
1043                 return UFSHCI_VERSION_11;
1044         else
1045                 return UFSHCI_VERSION_20;
1046 }
1047
1048 /**
1049  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1050  * @hba: host controller instance
1051  *
1052  * QCOM UFS host controller might have some non standard behaviours (quirks)
1053  * than what is specified by UFSHCI specification. Advertise all such
1054  * quirks to standard UFS host controller driver so standard takes them into
1055  * account.
1056  */
1057 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1058 {
1059         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1060
1061         if (host->hw_ver.major == 0x01) {
1062                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1063                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1064                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1065
1066                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1067                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1068
1069                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1070         }
1071
1072         if (host->hw_ver.major == 0x2) {
1073                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1074
1075                 if (!ufs_qcom_cap_qunipro(host))
1076                         /* Legacy UniPro mode still need following quirks */
1077                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1078                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1079                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1080         }
1081 }
1082
1083 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1084 {
1085         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1086
1087         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1088         hba->caps |= UFSHCD_CAP_CLK_SCALING;
1089         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1090
1091         if (host->hw_ver.major >= 0x2) {
1092                 host->caps = UFS_QCOM_CAP_QUNIPRO |
1093                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1094         }
1095 }
1096
1097 /**
1098  * ufs_qcom_setup_clocks - enables/disable clocks
1099  * @hba: host controller instance
1100  * @on: If true, enable clocks else disable them.
1101  * @status: PRE_CHANGE or POST_CHANGE notify
1102  *
1103  * Returns 0 on success, non-zero on failure.
1104  */
1105 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1106                                  enum ufs_notify_change_status status)
1107 {
1108         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1109         int err;
1110         int vote = 0;
1111
1112         /*
1113          * In case ufs_qcom_init() is not yet done, simply ignore.
1114          * This ufs_qcom_setup_clocks() shall be called from
1115          * ufs_qcom_init() after init is done.
1116          */
1117         if (!host)
1118                 return 0;
1119
1120         if (on && (status == POST_CHANGE)) {
1121                 phy_power_on(host->generic_phy);
1122
1123                 /* enable the device ref clock for HS mode*/
1124                 if (ufshcd_is_hs_mode(&hba->pwr_info))
1125                         ufs_qcom_dev_ref_clk_ctrl(host, true);
1126                 vote = host->bus_vote.saved_vote;
1127                 if (vote == host->bus_vote.min_bw_vote)
1128                         ufs_qcom_update_bus_bw_vote(host);
1129
1130         } else if (!on && (status == PRE_CHANGE)) {
1131                 if (!ufs_qcom_is_link_active(hba)) {
1132                         /* disable device ref_clk */
1133                         ufs_qcom_dev_ref_clk_ctrl(host, false);
1134
1135                         /* powering off PHY during aggressive clk gating */
1136                         phy_power_off(host->generic_phy);
1137                 }
1138
1139                 vote = host->bus_vote.min_bw_vote;
1140         }
1141
1142         err = ufs_qcom_set_bus_vote(host, vote);
1143         if (err)
1144                 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1145                                 __func__, err);
1146
1147         return err;
1148 }
1149
1150 #define ANDROID_BOOT_DEV_MAX    30
1151 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1152
1153 #ifndef MODULE
1154 static int __init get_android_boot_dev(char *str)
1155 {
1156         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1157         return 1;
1158 }
1159 __setup("androidboot.bootdevice=", get_android_boot_dev);
1160 #endif
1161
1162 /**
1163  * ufs_qcom_init - bind phy with controller
1164  * @hba: host controller instance
1165  *
1166  * Binds PHY with controller and powers up PHY enabling clocks
1167  * and regulators.
1168  *
1169  * Returns -EPROBE_DEFER if binding fails, returns negative error
1170  * on phy power up failure and returns zero on success.
1171  */
1172 static int ufs_qcom_init(struct ufs_hba *hba)
1173 {
1174         int err;
1175         struct device *dev = hba->dev;
1176         struct platform_device *pdev = to_platform_device(dev);
1177         struct ufs_qcom_host *host;
1178         struct resource *res;
1179
1180         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1181                 return -ENODEV;
1182
1183         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1184         if (!host) {
1185                 err = -ENOMEM;
1186                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1187                 goto out;
1188         }
1189
1190         /* Make a two way bind between the qcom host and the hba */
1191         host->hba = hba;
1192         ufshcd_set_variant(hba, host);
1193
1194         /*
1195          * voting/devoting device ref_clk source is time consuming hence
1196          * skip devoting it during aggressive clock gating. This clock
1197          * will still be gated off during runtime suspend.
1198          */
1199         host->generic_phy = devm_phy_get(dev, "ufsphy");
1200
1201         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1202                 /*
1203                  * UFS driver might be probed before the phy driver does.
1204                  * In that case we would like to return EPROBE_DEFER code.
1205                  */
1206                 err = -EPROBE_DEFER;
1207                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1208                         __func__, err);
1209                 goto out_variant_clear;
1210         } else if (IS_ERR(host->generic_phy)) {
1211                 err = PTR_ERR(host->generic_phy);
1212                 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1213                 goto out_variant_clear;
1214         }
1215
1216         err = ufs_qcom_bus_register(host);
1217         if (err)
1218                 goto out_variant_clear;
1219
1220         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1221                 &host->hw_ver.minor, &host->hw_ver.step);
1222
1223         /*
1224          * for newer controllers, device reference clock control bit has
1225          * moved inside UFS controller register address space itself.
1226          */
1227         if (host->hw_ver.major >= 0x02) {
1228                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1229                 host->dev_ref_clk_en_mask = BIT(26);
1230         } else {
1231                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1232                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1233                 if (res) {
1234                         host->dev_ref_clk_ctrl_mmio =
1235                                         devm_ioremap_resource(dev, res);
1236                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1237                                 dev_warn(dev,
1238                                         "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1239                                         __func__,
1240                                         PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1241                                 host->dev_ref_clk_ctrl_mmio = NULL;
1242                         }
1243                         host->dev_ref_clk_en_mask = BIT(5);
1244                 }
1245         }
1246
1247         err = ufs_qcom_init_lane_clks(host);
1248         if (err)
1249                 goto out_variant_clear;
1250
1251         ufs_qcom_set_caps(hba);
1252         ufs_qcom_advertise_quirks(hba);
1253
1254         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1255
1256         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1257                 ufs_qcom_hosts[hba->dev->id] = host;
1258
1259         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1260         ufs_qcom_get_default_testbus_cfg(host);
1261         err = ufs_qcom_testbus_config(host);
1262         if (err) {
1263                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1264                                 __func__, err);
1265                 err = 0;
1266         }
1267
1268         goto out;
1269
1270 out_variant_clear:
1271         ufshcd_set_variant(hba, NULL);
1272 out:
1273         return err;
1274 }
1275
1276 static void ufs_qcom_exit(struct ufs_hba *hba)
1277 {
1278         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1279
1280         ufs_qcom_disable_lane_clks(host);
1281         phy_power_off(host->generic_phy);
1282         phy_exit(host->generic_phy);
1283 }
1284
1285 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1286                                                        u32 clk_cycles)
1287 {
1288         int err;
1289         u32 core_clk_ctrl_reg;
1290
1291         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1292                 return -EINVAL;
1293
1294         err = ufshcd_dme_get(hba,
1295                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1296                             &core_clk_ctrl_reg);
1297         if (err)
1298                 goto out;
1299
1300         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1301         core_clk_ctrl_reg |= clk_cycles;
1302
1303         /* Clear CORE_CLK_DIV_EN */
1304         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1305
1306         err = ufshcd_dme_set(hba,
1307                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1308                             core_clk_ctrl_reg);
1309 out:
1310         return err;
1311 }
1312
1313 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1314 {
1315         /* nothing to do as of now */
1316         return 0;
1317 }
1318
1319 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1320 {
1321         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1322
1323         if (!ufs_qcom_cap_qunipro(host))
1324                 return 0;
1325
1326         /* set unipro core clock cycles to 150 and clear clock divider */
1327         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1328 }
1329
1330 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1331 {
1332         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1333         int err;
1334         u32 core_clk_ctrl_reg;
1335
1336         if (!ufs_qcom_cap_qunipro(host))
1337                 return 0;
1338
1339         err = ufshcd_dme_get(hba,
1340                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1341                             &core_clk_ctrl_reg);
1342
1343         /* make sure CORE_CLK_DIV_EN is cleared */
1344         if (!err &&
1345             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1346                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1347                 err = ufshcd_dme_set(hba,
1348                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1349                                     core_clk_ctrl_reg);
1350         }
1351
1352         return err;
1353 }
1354
1355 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1356 {
1357         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1358
1359         if (!ufs_qcom_cap_qunipro(host))
1360                 return 0;
1361
1362         /* set unipro core clock cycles to 75 and clear clock divider */
1363         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1364 }
1365
1366 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1367                 bool scale_up, enum ufs_notify_change_status status)
1368 {
1369         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1370         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1371         int err = 0;
1372
1373         if (status == PRE_CHANGE) {
1374                 if (scale_up)
1375                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1376                 else
1377                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1378         } else {
1379                 if (scale_up)
1380                         err = ufs_qcom_clk_scale_up_post_change(hba);
1381                 else
1382                         err = ufs_qcom_clk_scale_down_post_change(hba);
1383
1384                 if (err || !dev_req_params)
1385                         goto out;
1386
1387                 ufs_qcom_cfg_timers(hba,
1388                                     dev_req_params->gear_rx,
1389                                     dev_req_params->pwr_rx,
1390                                     dev_req_params->hs_rate,
1391                                     false);
1392                 ufs_qcom_update_bus_bw_vote(host);
1393         }
1394
1395 out:
1396         return err;
1397 }
1398
1399 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1400                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1401                 int offset, int num_regs, const char *str, void *priv))
1402 {
1403         u32 reg;
1404         struct ufs_qcom_host *host;
1405
1406         if (unlikely(!hba)) {
1407                 pr_err("%s: hba is NULL\n", __func__);
1408                 return;
1409         }
1410         if (unlikely(!print_fn)) {
1411                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1412                 return;
1413         }
1414
1415         host = ufshcd_get_variant(hba);
1416         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1417                 return;
1418
1419         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1420         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1421
1422         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1423         reg |= UTP_DBG_RAMS_EN;
1424         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1425
1426         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1427         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1428
1429         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1430         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1431
1432         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1433         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1434
1435         /* clear bit 17 - UTP_DBG_RAMS_EN */
1436         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1437
1438         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1439         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1440
1441         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1442         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1443
1444         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1445         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1446
1447         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1448         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1449
1450         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1451         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1452
1453         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1454         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1455
1456         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1457         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1458 }
1459
1460 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1461 {
1462         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1463                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1464                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1465                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1466         } else {
1467                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1468                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1469         }
1470 }
1471
1472 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1473 {
1474         /* provide a legal default configuration */
1475         host->testbus.select_major = TSTBUS_UNIPRO;
1476         host->testbus.select_minor = 37;
1477 }
1478
1479 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1480 {
1481         if (host->testbus.select_major >= TSTBUS_MAX) {
1482                 dev_err(host->hba->dev,
1483                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1484                         __func__, host->testbus.select_major);
1485                 return false;
1486         }
1487
1488         return true;
1489 }
1490
1491 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1492 {
1493         int reg;
1494         int offset;
1495         u32 mask = TEST_BUS_SUB_SEL_MASK;
1496
1497         if (!host)
1498                 return -EINVAL;
1499
1500         if (!ufs_qcom_testbus_cfg_is_ok(host))
1501                 return -EPERM;
1502
1503         switch (host->testbus.select_major) {
1504         case TSTBUS_UAWM:
1505                 reg = UFS_TEST_BUS_CTRL_0;
1506                 offset = 24;
1507                 break;
1508         case TSTBUS_UARM:
1509                 reg = UFS_TEST_BUS_CTRL_0;
1510                 offset = 16;
1511                 break;
1512         case TSTBUS_TXUC:
1513                 reg = UFS_TEST_BUS_CTRL_0;
1514                 offset = 8;
1515                 break;
1516         case TSTBUS_RXUC:
1517                 reg = UFS_TEST_BUS_CTRL_0;
1518                 offset = 0;
1519                 break;
1520         case TSTBUS_DFC:
1521                 reg = UFS_TEST_BUS_CTRL_1;
1522                 offset = 24;
1523                 break;
1524         case TSTBUS_TRLUT:
1525                 reg = UFS_TEST_BUS_CTRL_1;
1526                 offset = 16;
1527                 break;
1528         case TSTBUS_TMRLUT:
1529                 reg = UFS_TEST_BUS_CTRL_1;
1530                 offset = 8;
1531                 break;
1532         case TSTBUS_OCSC:
1533                 reg = UFS_TEST_BUS_CTRL_1;
1534                 offset = 0;
1535                 break;
1536         case TSTBUS_WRAPPER:
1537                 reg = UFS_TEST_BUS_CTRL_2;
1538                 offset = 16;
1539                 break;
1540         case TSTBUS_COMBINED:
1541                 reg = UFS_TEST_BUS_CTRL_2;
1542                 offset = 8;
1543                 break;
1544         case TSTBUS_UTP_HCI:
1545                 reg = UFS_TEST_BUS_CTRL_2;
1546                 offset = 0;
1547                 break;
1548         case TSTBUS_UNIPRO:
1549                 reg = UFS_UNIPRO_CFG;
1550                 offset = 20;
1551                 mask = 0xFFF;
1552                 break;
1553         /*
1554          * No need for a default case, since
1555          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1556          * is legal
1557          */
1558         }
1559         mask <<= offset;
1560
1561         pm_runtime_get_sync(host->hba->dev);
1562         ufshcd_hold(host->hba, false);
1563         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1564                     (u32)host->testbus.select_major << 19,
1565                     REG_UFS_CFG1);
1566         ufshcd_rmwl(host->hba, mask,
1567                     (u32)host->testbus.select_minor << offset,
1568                     reg);
1569         ufs_qcom_enable_test_bus(host);
1570         /*
1571          * Make sure the test bus configuration is
1572          * committed before returning.
1573          */
1574         mb();
1575         ufshcd_release(host->hba);
1576         pm_runtime_put_sync(host->hba->dev);
1577
1578         return 0;
1579 }
1580
1581 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1582 {
1583         ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1584 }
1585
1586 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1587 {
1588         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1589         u32 *testbus = NULL;
1590         int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1591
1592         testbus = kmalloc(testbus_len, GFP_KERNEL);
1593         if (!testbus)
1594                 return;
1595
1596         host->testbus.select_major = TSTBUS_UNIPRO;
1597         for (i = 0; i < nminor; i++) {
1598                 host->testbus.select_minor = i;
1599                 ufs_qcom_testbus_config(host);
1600                 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1601         }
1602         print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1603                         16, 4, testbus, testbus_len, false);
1604         kfree(testbus);
1605 }
1606
1607 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1608 {
1609         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1610                          "HCI Vendor Specific Registers ");
1611
1612         /* sleep a bit intermittently as we are dumping too much data */
1613         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1614         usleep_range(1000, 1100);
1615         ufs_qcom_testbus_read(hba);
1616         usleep_range(1000, 1100);
1617         ufs_qcom_print_unipro_testbus(hba);
1618         usleep_range(1000, 1100);
1619 }
1620
1621 /**
1622  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1623  *
1624  * The variant operations configure the necessary controller and PHY
1625  * handshake during initialization.
1626  */
1627 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1628         .name                   = "qcom",
1629         .init                   = ufs_qcom_init,
1630         .exit                   = ufs_qcom_exit,
1631         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1632         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1633         .setup_clocks           = ufs_qcom_setup_clocks,
1634         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1635         .link_startup_notify    = ufs_qcom_link_startup_notify,
1636         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1637         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1638         .suspend                = ufs_qcom_suspend,
1639         .resume                 = ufs_qcom_resume,
1640         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1641 };
1642
1643 /**
1644  * ufs_qcom_probe - probe routine of the driver
1645  * @pdev: pointer to Platform device handle
1646  *
1647  * Return zero for success and non-zero for failure
1648  */
1649 static int ufs_qcom_probe(struct platform_device *pdev)
1650 {
1651         int err;
1652         struct device *dev = &pdev->dev;
1653
1654         /* Perform generic probe */
1655         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1656         if (err)
1657                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1658
1659         return err;
1660 }
1661
1662 /**
1663  * ufs_qcom_remove - set driver_data of the device to NULL
1664  * @pdev: pointer to platform device handle
1665  *
1666  * Always returns 0
1667  */
1668 static int ufs_qcom_remove(struct platform_device *pdev)
1669 {
1670         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1671
1672         pm_runtime_get_sync(&(pdev)->dev);
1673         ufshcd_remove(hba);
1674         return 0;
1675 }
1676
1677 static const struct of_device_id ufs_qcom_of_match[] = {
1678         { .compatible = "qcom,ufshc"},
1679         {},
1680 };
1681 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1682
1683 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1684         .suspend        = ufshcd_pltfrm_suspend,
1685         .resume         = ufshcd_pltfrm_resume,
1686         .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1687         .runtime_resume  = ufshcd_pltfrm_runtime_resume,
1688         .runtime_idle    = ufshcd_pltfrm_runtime_idle,
1689 };
1690
1691 static struct platform_driver ufs_qcom_pltform = {
1692         .probe  = ufs_qcom_probe,
1693         .remove = ufs_qcom_remove,
1694         .shutdown = ufshcd_pltfrm_shutdown,
1695         .driver = {
1696                 .name   = "ufshcd-qcom",
1697                 .pm     = &ufs_qcom_pm_ops,
1698                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1699         },
1700 };
1701 module_platform_driver(ufs_qcom_pltform);
1702
1703 MODULE_LICENSE("GPL v2");