drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005, 2006 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/time.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/byteorder.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/scsi_tcq.h>
  35 #include <scsi/scsi_dbg.h>
  36
  37 #define DRV_NAME "stex"
  38 #define ST_DRIVER_VERSION "3.6.0000.1"
  39 #define ST_VER_MAJOR            3
  40 #define ST_VER_MINOR            6
  41 #define ST_OEM                  0
  42 #define ST_BUILD_VER            1
  43
  44 enum {
  45         /* MU register offset */
  46         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  47         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  48         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  49         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  50         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  51         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  52         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  53         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  54         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  55         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  56
  57         /* MU register value */
  58         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  59         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  60         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  61         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  62         MU_INBOUND_DOORBELL_RESET               = 16,
  63
  64         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  65         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  66         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  67         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  68         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  69
  70         /* MU status code */
  71         MU_STATE_STARTING                       = 1,
  72         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  73         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  74         MU_STATE_STARTED                        = 4,
  75         MU_STATE_RESETTING                      = 5,
  76
  77         MU_MAX_DELAY                            = 120,
  78         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  79         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  80         MU_HARD_RESET_WAIT                      = 30000,
  81         HMU_PARTNER_TYPE                        = 2,
  82
  83         /* firmware returned values */
  84         SRB_STATUS_SUCCESS                      = 0x01,
  85         SRB_STATUS_ERROR                        = 0x04,
  86         SRB_STATUS_BUSY                         = 0x05,
  87         SRB_STATUS_INVALID_REQUEST              = 0x06,
  88         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  89         SRB_SEE_SENSE                           = 0x80,
  90
  91         /* task attribute */
  92         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  93         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  94         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  95         TASK_ATTRIBUTE_ACA                      = 0x4,
  96
  97         /* request count, etc. */
  98         MU_MAX_REQUEST                          = 32,
  99
 100         /* one message wasted, use MU_MAX_REQUEST+1
 101                 to handle MU_MAX_REQUEST messages */
 102         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 103         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 104
 105         STEX_CDB_LENGTH                         = MAX_COMMAND_SIZE,
 106         REQ_VARIABLE_LEN                        = 1024,
 107         STATUS_VAR_LEN                          = 128,
 108         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 109         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 110         ST_MAX_SG                               = 32,
 111
 112         /* sg flags */
 113         SG_CF_EOT                               = 0x80, /* end of table */
 114         SG_CF_64B                               = 0x40, /* 64 bit item */
 115         SG_CF_HOST                              = 0x20, /* sg in host memory */
 116
 117         st_shasta                               = 0,
 118         st_vsc                                  = 1,
 119         st_vsc1                                 = 2,
 120         st_yosemite                             = 3,
 121
 122         PASSTHRU_REQ_TYPE                       = 0x00000001,
 123         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 124         ST_INTERNAL_TIMEOUT                     = 30,
 125
 126         ST_TO_CMD                               = 0,
 127         ST_FROM_CMD                             = 1,
 128
 129         /* vendor specific commands of Promise */
 130         MGT_CMD                                 = 0xd8,
 131         SINBAND_MGT_CMD                         = 0xd9,
 132         ARRAY_CMD                               = 0xe0,
 133         CONTROLLER_CMD                          = 0xe1,
 134         DEBUGGING_CMD                           = 0xe2,
 135         PASSTHRU_CMD                            = 0xe3,
 136
 137         PASSTHRU_GET_ADAPTER                    = 0x05,
 138         PASSTHRU_GET_DRVVER                     = 0x10,
 139
 140         CTLR_CONFIG_CMD                         = 0x03,
 141         CTLR_SHUTDOWN                           = 0x0d,
 142
 143         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 144         CTLR_POWER_SAVING                       = 0x01,
 145
 146         PASSTHRU_SIGNATURE                      = 0x4e415041,
 147         MGT_CMD_SIGNATURE                       = 0xba,
 148
 149         INQUIRY_EVPD                            = 0x01,
 150
 151         ST_ADDITIONAL_MEM                       = 0x200000,
 152 };
 153
 154 /* SCSI inquiry data */
 155 typedef struct st_inq {
 156         u8 DeviceType                   :5;
 157         u8 DeviceTypeQualifier          :3;
 158         u8 DeviceTypeModifier           :7;
 159         u8 RemovableMedia               :1;
 160         u8 Versions;
 161         u8 ResponseDataFormat           :4;
 162         u8 HiSupport                    :1;
 163         u8 NormACA                      :1;
 164         u8 ReservedBit                  :1;
 165         u8 AERC                         :1;
 166         u8 AdditionalLength;
 167         u8 Reserved[2];
 168         u8 SoftReset                    :1;
 169         u8 CommandQueue                 :1;
 170         u8 Reserved2                    :1;
 171         u8 LinkedCommands               :1;
 172         u8 Synchronous                  :1;
 173         u8 Wide16Bit                    :1;
 174         u8 Wide32Bit                    :1;
 175         u8 RelativeAddressing           :1;
 176         u8 VendorId[8];
 177         u8 ProductId[16];
 178         u8 ProductRevisionLevel[4];
 179         u8 VendorSpecific[20];
 180         u8 Reserved3[40];
 181 } ST_INQ;
 182
 183 struct st_sgitem {
 184         u8 ctrl;        /* SG_CF_xxx */
 185         u8 reserved[3];
 186         __le32 count;
 187         __le32 addr;
 188         __le32 addr_hi;
 189 };
 190
 191 struct st_sgtable {
 192         __le16 sg_count;
 193         __le16 max_sg_count;
 194         __le32 sz_in_byte;
 195         struct st_sgitem table[ST_MAX_SG];
 196 };
 197
 198 struct handshake_frame {
 199         __le32 rb_phy;          /* request payload queue physical address */
 200         __le32 rb_phy_hi;
 201         __le16 req_sz;          /* size of each request payload */
 202         __le16 req_cnt;         /* count of reqs the buffer can hold */
 203         __le16 status_sz;       /* size of each status payload */
 204         __le16 status_cnt;      /* count of status the buffer can hold */
 205         __le32 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 206         __le32 hosttime_hi;
 207         u8 partner_type;        /* who sends this frame */
 208         u8 reserved0[7];
 209         __le32 partner_ver_major;
 210         __le32 partner_ver_minor;
 211         __le32 partner_ver_oem;
 212         __le32 partner_ver_build;
 213         __le32 extra_offset;    /* NEW */
 214         __le32 extra_size;      /* NEW */
 215         u32 reserved1[2];
 216 };
 217
 218 struct req_msg {
 219         __le16 tag;
 220         u8 lun;
 221         u8 target;
 222         u8 task_attr;
 223         u8 task_manage;
 224         u8 prd_entry;
 225         u8 payload_sz;          /* payload size in 4-byte, not used */
 226         u8 cdb[STEX_CDB_LENGTH];
 227         u8 variable[REQ_VARIABLE_LEN];
 228 };
 229
 230 struct status_msg {
 231         __le16 tag;
 232         u8 lun;
 233         u8 target;
 234         u8 srb_status;
 235         u8 scsi_status;
 236         u8 reserved;
 237         u8 payload_sz;          /* payload size in 4-byte */
 238         u8 variable[STATUS_VAR_LEN];
 239 };
 240
 241 struct ver_info {
 242         u32 major;
 243         u32 minor;
 244         u32 oem;
 245         u32 build;
 246         u32 reserved[2];
 247 };
 248
 249 struct st_frame {
 250         u32 base[6];
 251         u32 rom_addr;
 252
 253         struct ver_info drv_ver;
 254         struct ver_info bios_ver;
 255
 256         u32 bus;
 257         u32 slot;
 258         u32 irq_level;
 259         u32 irq_vec;
 260         u32 id;
 261         u32 subid;
 262
 263         u32 dimm_size;
 264         u8 dimm_type;
 265         u8 reserved[3];
 266
 267         u32 channel;
 268         u32 reserved1;
 269 };
 270
 271 struct st_drvver {
 272         u32 major;
 273         u32 minor;
 274         u32 oem;
 275         u32 build;
 276         u32 signature[2];
 277         u8 console_id;
 278         u8 host_no;
 279         u8 reserved0[2];
 280         u32 reserved[3];
 281 };
 282
 283 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 284 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 285 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 286 #define STEX_EXTRA_SIZE         max(sizeof(struct st_frame), sizeof(ST_INQ))
 287 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
 288
 289 struct st_ccb {
 290         struct req_msg *req;
 291         struct scsi_cmnd *cmd;
 292
 293         void *sense_buffer;
 294         unsigned int sense_bufflen;
 295         int sg_count;
 296
 297         u32 req_type;
 298         u8 srb_status;
 299         u8 scsi_status;
 300 };
 301
 302 struct st_hba {
 303         void __iomem *mmio_base;        /* iomapped PCI memory space */
 304         void *dma_mem;
 305         dma_addr_t dma_handle;
 306         size_t dma_size;
 307
 308         struct Scsi_Host *host;
 309         struct pci_dev *pdev;
 310
 311         u32 req_head;
 312         u32 req_tail;
 313         u32 status_head;
 314         u32 status_tail;
 315
 316         struct status_msg *status_buffer;
 317         void *copy_buffer; /* temp buffer for driver-handled commands */
 318         struct st_ccb ccb[MU_MAX_REQUEST];
 319         struct st_ccb *wait_ccb;
 320         wait_queue_head_t waitq;
 321
 322         unsigned int mu_status;
 323         int out_req_cnt;
 324
 325         unsigned int cardtype;
 326 };
 327
 328 static const char console_inq_page[] =
 329 {
 330         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 331         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 332         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 333         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 334         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 335         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 336         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 337         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 338 };
 339
 340 MODULE_AUTHOR("Ed Lin");
 341 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 342 MODULE_LICENSE("GPL");
 343 MODULE_VERSION(ST_DRIVER_VERSION);
 344
 345 static void stex_gettime(__le32 *time)
 346 {
 347         struct timeval tv;
 348         do_gettimeofday(&tv);
 349
 350         *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
 351         *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
 352 }
 353
 354 static struct status_msg *stex_get_status(struct st_hba *hba)
 355 {
 356         struct status_msg *status =
 357                 hba->status_buffer + hba->status_tail;
 358
 359         ++hba->status_tail;
 360         hba->status_tail %= MU_STATUS_COUNT;
 361
 362         return status;
 363 }
 364
 365 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
 366 {
 367         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 368
 369         cmd->sense_buffer[0] = 0x70;    /* fixed format, current */
 370         cmd->sense_buffer[2] = sk;
 371         cmd->sense_buffer[7] = 18 - 8;  /* additional sense length */
 372         cmd->sense_buffer[12] = asc;
 373         cmd->sense_buffer[13] = ascq;
 374 }
 375
 376 static void stex_invalid_field(struct scsi_cmnd *cmd,
 377                                void (*done)(struct scsi_cmnd *))
 378 {
 379         /* "Invalid field in cbd" */
 380         stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
 381         done(cmd);
 382 }
 383
 384 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 385 {
 386         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 387                 hba->req_head;
 388
 389         ++hba->req_head;
 390         hba->req_head %= MU_REQ_COUNT;
 391
 392         return req;
 393 }
 394
 395 static int stex_map_sg(struct st_hba *hba,
 396         struct req_msg *req, struct st_ccb *ccb)
 397 {
 398         struct pci_dev *pdev = hba->pdev;
 399         struct scsi_cmnd *cmd;
 400         dma_addr_t dma_handle;
 401         struct scatterlist *src;
 402         struct st_sgtable *dst;
 403         int i;
 404
 405         cmd = ccb->cmd;
 406         dst = (struct st_sgtable *)req->variable;
 407         dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
 408         dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
 409
 410         if (cmd->use_sg) {
 411                 int n_elem;
 412
 413                 src = (struct scatterlist *) cmd->request_buffer;
 414                 n_elem = pci_map_sg(pdev, src,
 415                         cmd->use_sg, cmd->sc_data_direction);
 416                 if (n_elem <= 0)
 417                         return -EIO;
 418
 419                 ccb->sg_count = n_elem;
 420                 dst->sg_count = cpu_to_le16((u16)n_elem);
 421
 422                 for (i = 0; i < n_elem; i++, src++) {
 423                         dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
 424                         dst->table[i].addr =
 425                                 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
 426                         dst->table[i].addr_hi =
 427                                 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
 428                         dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 429                 }
 430                 dst->table[--i].ctrl |= SG_CF_EOT;
 431                 return 0;
 432         }
 433
 434         dma_handle = pci_map_single(pdev, cmd->request_buffer,
 435                 cmd->request_bufflen, cmd->sc_data_direction);
 436         cmd->SCp.dma_handle = dma_handle;
 437
 438         ccb->sg_count = 1;
 439         dst->sg_count = cpu_to_le16(1);
 440         dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
 441         dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
 442         dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
 443         dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
 444
 445         return 0;
 446 }
 447
 448 static void stex_internal_copy(struct scsi_cmnd *cmd,
 449         const void *src, size_t *count, int sg_count, int direction)
 450 {
 451         size_t lcount;
 452         size_t len;
 453         void *s, *d, *base = NULL;
 454         if (*count > cmd->request_bufflen)
 455                 *count = cmd->request_bufflen;
 456         lcount = *count;
 457         while (lcount) {
 458                 len = lcount;
 459                 s = (void *)src;
 460                 if (cmd->use_sg) {
 461                         size_t offset = *count - lcount;
 462                         s += offset;
 463                         base = scsi_kmap_atomic_sg(cmd->request_buffer,
 464                                 sg_count, &offset, &len);
 465                         if (base == NULL) {
 466                                 *count -= lcount;
 467                                 return;
 468                         }
 469                         d = base + offset;
 470                 } else
 471                         d = cmd->request_buffer;
 472
 473                 if (direction == ST_TO_CMD)
 474                         memcpy(d, s, len);
 475                 else
 476                         memcpy(s, d, len);
 477
 478                 lcount -= len;
 479                 if (cmd->use_sg)
 480                         scsi_kunmap_atomic_sg(base);
 481         }
 482 }
 483
 484 static int stex_direct_copy(struct scsi_cmnd *cmd,
 485         const void *src, size_t count)
 486 {
 487         struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 488         size_t cp_len = count;
 489         int n_elem = 0;
 490
 491         if (cmd->use_sg) {
 492                 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
 493                         cmd->use_sg, cmd->sc_data_direction);
 494                 if (n_elem <= 0)
 495                         return 0;
 496         }
 497
 498         stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
 499
 500         if (cmd->use_sg)
 501                 pci_unmap_sg(hba->pdev, cmd->request_buffer,
 502                         cmd->use_sg, cmd->sc_data_direction);
 503         return cp_len == count;
 504 }
 505
 506 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 507 {
 508         struct st_frame *p;
 509         size_t count = sizeof(struct st_frame);
 510
 511         p = hba->copy_buffer;
 512         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
 513         memset(p->base, 0, sizeof(u32)*6);
 514         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 515         p->rom_addr = 0;
 516
 517         p->drv_ver.major = ST_VER_MAJOR;
 518         p->drv_ver.minor = ST_VER_MINOR;
 519         p->drv_ver.oem = ST_OEM;
 520         p->drv_ver.build = ST_BUILD_VER;
 521
 522         p->bus = hba->pdev->bus->number;
 523         p->slot = hba->pdev->devfn;
 524         p->irq_level = 0;
 525         p->irq_vec = hba->pdev->irq;
 526         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 527         p->subid =
 528                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 529
 530         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
 531 }
 532
 533 static void
 534 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 535 {
 536         req->tag = cpu_to_le16(tag);
 537         req->task_attr = TASK_ATTRIBUTE_SIMPLE;
 538         req->task_manage = 0; /* not supported yet */
 539
 540         hba->ccb[tag].req = req;
 541         hba->out_req_cnt++;
 542
 543         writel(hba->req_head, hba->mmio_base + IMR0);
 544         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 545         readl(hba->mmio_base + IDBL); /* flush */
 546 }
 547
 548 static int
 549 stex_slave_alloc(struct scsi_device *sdev)
 550 {
 551         /* Cheat: usually extracted from Inquiry data */
 552         sdev->tagged_supported = 1;
 553
 554         scsi_activate_tcq(sdev, sdev->host->can_queue);
 555
 556         return 0;
 557 }
 558
 559 static int
 560 stex_slave_config(struct scsi_device *sdev)
 561 {
 562         sdev->use_10_for_rw = 1;
 563         sdev->use_10_for_ms = 1;
 564         sdev->timeout = 60 * HZ;
 565         sdev->tagged_supported = 1;
 566
 567         return 0;
 568 }
 569
 570 static void
 571 stex_slave_destroy(struct scsi_device *sdev)
 572 {
 573         scsi_deactivate_tcq(sdev, 1);
 574 }
 575
 576 static int
 577 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 578 {
 579         struct st_hba *hba;
 580         struct Scsi_Host *host;
 581         unsigned int id,lun;
 582         struct req_msg *req;
 583         u16 tag;
 584         host = cmd->device->host;
 585         id = cmd->device->id;
 586         lun = cmd->device->lun;
 587         hba = (struct st_hba *) &host->hostdata[0];
 588
 589         switch (cmd->cmnd[0]) {
 590         case MODE_SENSE_10:
 591         {
 592                 static char ms10_caching_page[12] =
 593                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 594                 unsigned char page;
 595                 page = cmd->cmnd[2] & 0x3f;
 596                 if (page == 0x8 || page == 0x3f) {
 597                         stex_direct_copy(cmd, ms10_caching_page,
 598                                         sizeof(ms10_caching_page));
 599                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 600                         done(cmd);
 601                 } else
 602                         stex_invalid_field(cmd, done);
 603                 return 0;
 604         }
 605         case REPORT_LUNS:
 606                 /*
 607                  * The shasta firmware does not report actual luns in the
 608                  * target, so fail the command to force sequential lun scan.
 609                  * Also, the console device does not support this command.
 610                  */
 611                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 612                         stex_invalid_field(cmd, done);
 613                         return 0;
 614                 }
 615                 break;
 616         case TEST_UNIT_READY:
 617                 if (id == host->max_id - 1) {
 618                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 619                         done(cmd);
 620                         return 0;
 621                 }
 622                 break;
 623         case INQUIRY:
 624                 if (id != host->max_id - 1)
 625                         break;
 626                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 627                         stex_direct_copy(cmd, console_inq_page,
 628                                 sizeof(console_inq_page));
 629                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 630                         done(cmd);
 631                 } else
 632                         stex_invalid_field(cmd, done);
 633                 return 0;
 634         case PASSTHRU_CMD:
 635                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 636                         struct st_drvver ver;
 637                         ver.major = ST_VER_MAJOR;
 638                         ver.minor = ST_VER_MINOR;
 639                         ver.oem = ST_OEM;
 640                         ver.build = ST_BUILD_VER;
 641                         ver.signature[0] = PASSTHRU_SIGNATURE;
 642                         ver.console_id = host->max_id - 1;
 643                         ver.host_no = hba->host->host_no;
 644                         cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
 645                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 646                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 647                         done(cmd);
 648                         return 0;
 649                 }
 650         default:
 651                 break;
 652         }
 653
 654         cmd->scsi_done = done;
 655
 656         tag = cmd->request->tag;
 657
 658         if (unlikely(tag >= host->can_queue))
 659                 return SCSI_MLQUEUE_HOST_BUSY;
 660
 661         req = stex_alloc_req(hba);
 662
 663         req->lun = lun;
 664         req->target = id;
 665
 666         /* cdb */
 667         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 668
 669         hba->ccb[tag].cmd = cmd;
 670         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 671         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 672         hba->ccb[tag].req_type = 0;
 673
 674         if (cmd->sc_data_direction != DMA_NONE)
 675                 stex_map_sg(hba, req, &hba->ccb[tag]);
 676
 677         stex_send_cmd(hba, req, tag);
 678         return 0;
 679 }
 680
 681 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
 682 {
 683         if (cmd->sc_data_direction != DMA_NONE) {
 684                 if (cmd->use_sg)
 685                         pci_unmap_sg(hba->pdev, cmd->request_buffer,
 686                                 cmd->use_sg, cmd->sc_data_direction);
 687                 else
 688                         pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
 689                                 cmd->request_bufflen, cmd->sc_data_direction);
 690         }
 691 }
 692
 693 static void stex_scsi_done(struct st_ccb *ccb)
 694 {
 695         struct scsi_cmnd *cmd = ccb->cmd;
 696         int result;
 697
 698         if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
 699                 result = ccb->scsi_status;
 700                 switch (ccb->scsi_status) {
 701                 case SAM_STAT_GOOD:
 702                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 703                         break;
 704                 case SAM_STAT_CHECK_CONDITION:
 705                         result |= DRIVER_SENSE << 24;
 706                         break;
 707                 case SAM_STAT_BUSY:
 708                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 709                         break;
 710                 default:
 711                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 712                         break;
 713                 }
 714         }
 715         else if (ccb->srb_status & SRB_SEE_SENSE)
 716                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 717         else switch (ccb->srb_status) {
 718                 case SRB_STATUS_SELECTION_TIMEOUT:
 719                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 720                         break;
 721                 case SRB_STATUS_BUSY:
 722                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 723                         break;
 724                 case SRB_STATUS_INVALID_REQUEST:
 725                 case SRB_STATUS_ERROR:
 726                 default:
 727                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 728                         break;
 729         }
 730
 731         cmd->result = result;
 732         cmd->scsi_done(cmd);
 733 }
 734
 735 static void stex_copy_data(struct st_ccb *ccb,
 736         struct status_msg *resp, unsigned int variable)
 737 {
 738         size_t count = variable;
 739         if (resp->scsi_status != SAM_STAT_GOOD) {
 740                 if (ccb->sense_buffer != NULL)
 741                         memcpy(ccb->sense_buffer, resp->variable,
 742                                 min(variable, ccb->sense_bufflen));
 743                 return;
 744         }
 745
 746         if (ccb->cmd == NULL)
 747                 return;
 748         stex_internal_copy(ccb->cmd,
 749                 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
 750 }
 751
 752 static void stex_ys_commands(struct st_hba *hba,
 753         struct st_ccb *ccb, struct status_msg *resp)
 754 {
 755         size_t count;
 756
 757         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 758                 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
 759                 ccb->cmd->request_bufflen =
 760                         le32_to_cpu(*(__le32 *)&resp->variable[0]);
 761                 return;
 762         }
 763
 764         if (resp->srb_status != 0)
 765                 return;
 766
 767         /* determine inquiry command status by DeviceTypeQualifier */
 768         if (ccb->cmd->cmnd[0] == INQUIRY &&
 769                 resp->scsi_status == SAM_STAT_GOOD) {
 770                 ST_INQ *inq_data;
 771
 772                 count = STEX_EXTRA_SIZE;
 773                 stex_internal_copy(ccb->cmd, hba->copy_buffer,
 774                         &count, ccb->sg_count, ST_FROM_CMD);
 775                 inq_data = (ST_INQ *)hba->copy_buffer;
 776                 if (inq_data->DeviceTypeQualifier != 0)
 777                         ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
 778                 else
 779                         ccb->srb_status = SRB_STATUS_SUCCESS;
 780         }
 781 }
 782
 783 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 784 {
 785         void __iomem *base = hba->mmio_base;
 786         struct status_msg *resp;
 787         struct st_ccb *ccb;
 788         unsigned int size;
 789         u16 tag;
 790
 791         if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
 792                 return;
 793
 794         /* status payloads */
 795         hba->status_head = readl(base + OMR1);
 796         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 797                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 798                         pci_name(hba->pdev));
 799                 return;
 800         }
 801
 802         /*
 803          * it's not a valid status payload if:
 804          * 1. there are no pending requests(e.g. during init stage)
 805          * 2. there are some pending requests, but the controller is in
 806          *     reset status, and its type is not st_yosemite
 807          * firmware of st_yosemite in reset status will return pending requests
 808          * to driver, so we allow it to pass
 809          */
 810         if (unlikely(hba->out_req_cnt <= 0 ||
 811                         (hba->mu_status == MU_STATE_RESETTING &&
 812                          hba->cardtype != st_yosemite))) {
 813                 hba->status_tail = hba->status_head;
 814                 goto update_status;
 815         }
 816
 817         while (hba->status_tail != hba->status_head) {
 818                 resp = stex_get_status(hba);
 819                 tag = le16_to_cpu(resp->tag);
 820                 if (unlikely(tag >= hba->host->can_queue)) {
 821                         printk(KERN_WARNING DRV_NAME
 822                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 823                         continue;
 824                 }
 825
 826                 ccb = &hba->ccb[tag];
 827                 if (hba->wait_ccb == ccb)
 828                         hba->wait_ccb = NULL;
 829                 if (unlikely(ccb->req == NULL)) {
 830                         printk(KERN_WARNING DRV_NAME
 831                                 "(%s): lagging req\n", pci_name(hba->pdev));
 832                         hba->out_req_cnt--;
 833                         continue;
 834                 }
 835
 836                 size = resp->payload_sz * sizeof(u32); /* payload size */
 837                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 838                         size > sizeof(*resp))) {
 839                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 840                                 pci_name(hba->pdev));
 841                 } else {
 842                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 843                         if (size)
 844                                 stex_copy_data(ccb, resp, size);
 845                 }
 846
 847                 ccb->srb_status = resp->srb_status;
 848                 ccb->scsi_status = resp->scsi_status;
 849
 850                 if (likely(ccb->cmd != NULL)) {
 851                         if (hba->cardtype == st_yosemite)
 852                                 stex_ys_commands(hba, ccb, resp);
 853
 854                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 855                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 856                                 stex_controller_info(hba, ccb);
 857
 858                         stex_unmap_sg(hba, ccb->cmd);
 859                         stex_scsi_done(ccb);
 860                         hba->out_req_cnt--;
 861                 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
 862                         hba->out_req_cnt--;
 863                         if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
 864                                 ccb->req_type = 0;
 865                                 continue;
 866                         }
 867                         ccb->req_type = 0;
 868                         if (waitqueue_active(&hba->waitq))
 869                                 wake_up(&hba->waitq);
 870                 }
 871         }
 872
 873 update_status:
 874         writel(hba->status_head, base + IMR1);
 875         readl(base + IMR1); /* flush */
 876 }
 877
 878 static irqreturn_t stex_intr(int irq, void *__hba)
 879 {
 880         struct st_hba *hba = __hba;
 881         void __iomem *base = hba->mmio_base;
 882         u32 data;
 883         unsigned long flags;
 884         int handled = 0;
 885
 886         spin_lock_irqsave(hba->host->host_lock, flags);
 887
 888         data = readl(base + ODBL);
 889
 890         if (data && data != 0xffffffff) {
 891                 /* clear the interrupt */
 892                 writel(data, base + ODBL);
 893                 readl(base + ODBL); /* flush */
 894                 stex_mu_intr(hba, data);
 895                 handled = 1;
 896         }
 897
 898         spin_unlock_irqrestore(hba->host->host_lock, flags);
 899
 900         return IRQ_RETVAL(handled);
 901 }
 902
 903 static int stex_handshake(struct st_hba *hba)
 904 {
 905         void __iomem *base = hba->mmio_base;
 906         struct handshake_frame *h;
 907         dma_addr_t status_phys;
 908         u32 data;
 909         unsigned long before;
 910
 911         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 912                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 913                 readl(base + IDBL);
 914                 before = jiffies;
 915                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 916                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 917                                 printk(KERN_ERR DRV_NAME
 918                                         "(%s): no handshake signature\n",
 919                                         pci_name(hba->pdev));
 920                                 return -1;
 921                         }
 922                         rmb();
 923                         msleep(1);
 924                 }
 925         }
 926
 927         udelay(10);
 928
 929         data = readl(base + OMR1);
 930         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 931                 data &= 0x0000ffff;
 932                 if (hba->host->can_queue > data)
 933                         hba->host->can_queue = data;
 934         }
 935
 936         h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
 937         h->rb_phy = cpu_to_le32(hba->dma_handle);
 938         h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
 939         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 940         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 941         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 942         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 943         stex_gettime(&h->hosttime);
 944         h->partner_type = HMU_PARTNER_TYPE;
 945         if (hba->dma_size > STEX_BUFFER_SIZE) {
 946                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
 947                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
 948         } else
 949                 h->extra_offset = h->extra_size = 0;
 950
 951         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 952         writel(status_phys, base + IMR0);
 953         readl(base + IMR0);
 954         writel((status_phys >> 16) >> 16, base + IMR1);
 955         readl(base + IMR1);
 956
 957         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 958         readl(base + OMR0);
 959         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 960         readl(base + IDBL); /* flush */
 961
 962         udelay(10);
 963         before = jiffies;
 964         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 965                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 966                         printk(KERN_ERR DRV_NAME
 967                                 "(%s): no signature after handshake frame\n",
 968                                 pci_name(hba->pdev));
 969                         return -1;
 970                 }
 971                 rmb();
 972                 msleep(1);
 973         }
 974
 975         writel(0, base + IMR0);
 976         readl(base + IMR0);
 977         writel(0, base + OMR0);
 978         readl(base + OMR0);
 979         writel(0, base + IMR1);
 980         readl(base + IMR1);
 981         writel(0, base + OMR1);
 982         readl(base + OMR1); /* flush */
 983         hba->mu_status = MU_STATE_STARTED;
 984         return 0;
 985 }
 986
 987 static int stex_abort(struct scsi_cmnd *cmd)
 988 {
 989         struct Scsi_Host *host = cmd->device->host;
 990         struct st_hba *hba = (struct st_hba *)host->hostdata;
 991         u16 tag = cmd->request->tag;
 992         void __iomem *base;
 993         u32 data;
 994         int result = SUCCESS;
 995         unsigned long flags;
 996
 997         printk(KERN_INFO DRV_NAME
 998                 "(%s): aborting command\n", pci_name(hba->pdev));
 999         scsi_print_command(cmd);
1000
1001         base = hba->mmio_base;
1002         spin_lock_irqsave(host->host_lock, flags);
1003         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
1004                 hba->wait_ccb = &hba->ccb[tag];
1005         else {
1006                 for (tag = 0; tag < host->can_queue; tag++)
1007                         if (hba->ccb[tag].cmd == cmd) {
1008                                 hba->wait_ccb = &hba->ccb[tag];
1009                                 break;
1010                         }
1011                 if (tag >= host->can_queue)
1012                         goto out;
1013         }
1014
1015         data = readl(base + ODBL);
1016         if (data == 0 || data == 0xffffffff)
1017                 goto fail_out;
1018
1019         writel(data, base + ODBL);
1020         readl(base + ODBL); /* flush */
1021
1022         stex_mu_intr(hba, data);
1023
1024         if (hba->wait_ccb == NULL) {
1025                 printk(KERN_WARNING DRV_NAME
1026                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1027                 goto out;
1028         }
1029
1030 fail_out:
1031         stex_unmap_sg(hba, cmd);
1032         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1033         hba->wait_ccb = NULL;
1034         result = FAILED;
1035 out:
1036         spin_unlock_irqrestore(host->host_lock, flags);
1037         return result;
1038 }
1039
1040 static void stex_hard_reset(struct st_hba *hba)
1041 {
1042         struct pci_bus *bus;
1043         int i;
1044         u16 pci_cmd;
1045         u8 pci_bctl;
1046
1047         for (i = 0; i < 16; i++)
1048                 pci_read_config_dword(hba->pdev, i * 4,
1049                         &hba->pdev->saved_config_space[i]);
1050
1051         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1052            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1053         bus = hba->pdev->bus;
1054         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1055         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1056         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1057
1058         /*
1059          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1060          * require more time to finish bus reset. Use 100 ms here for safety
1061          */
1062         msleep(100);
1063         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1064         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1065
1066         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1067                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1068                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1069                         break;
1070                 msleep(1);
1071         }
1072
1073         ssleep(5);
1074         for (i = 0; i < 16; i++)
1075                 pci_write_config_dword(hba->pdev, i * 4,
1076                         hba->pdev->saved_config_space[i]);
1077 }
1078
1079 static int stex_reset(struct scsi_cmnd *cmd)
1080 {
1081         struct st_hba *hba;
1082         unsigned long flags;
1083         unsigned long before;
1084         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1085
1086         printk(KERN_INFO DRV_NAME
1087                 "(%s): resetting host\n", pci_name(hba->pdev));
1088         scsi_print_command(cmd);
1089
1090         hba->mu_status = MU_STATE_RESETTING;
1091
1092         if (hba->cardtype == st_shasta)
1093                 stex_hard_reset(hba);
1094
1095         if (hba->cardtype != st_yosemite) {
1096                 if (stex_handshake(hba)) {
1097                         printk(KERN_WARNING DRV_NAME
1098                                 "(%s): resetting: handshake failed\n",
1099                                 pci_name(hba->pdev));
1100                         return FAILED;
1101                 }
1102                 spin_lock_irqsave(hba->host->host_lock, flags);
1103                 hba->req_head = 0;
1104                 hba->req_tail = 0;
1105                 hba->status_head = 0;
1106                 hba->status_tail = 0;
1107                 hba->out_req_cnt = 0;
1108                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1109                 return SUCCESS;
1110         }
1111
1112         /* st_yosemite */
1113         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1114         readl(hba->mmio_base + IDBL); /* flush */
1115         before = jiffies;
1116         while (hba->out_req_cnt > 0) {
1117                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1118                         printk(KERN_WARNING DRV_NAME
1119                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1120                         return FAILED;
1121                 }
1122                 msleep(1);
1123         }
1124
1125         hba->mu_status = MU_STATE_STARTED;
1126         return SUCCESS;
1127 }
1128
1129 static int stex_biosparam(struct scsi_device *sdev,
1130         struct block_device *bdev, sector_t capacity, int geom[])
1131 {
1132         int heads = 255, sectors = 63;
1133
1134         if (capacity < 0x200000) {
1135                 heads = 64;
1136                 sectors = 32;
1137         }
1138
1139         sector_div(capacity, heads * sectors);
1140
1141         geom[0] = heads;
1142         geom[1] = sectors;
1143         geom[2] = capacity;
1144
1145         return 0;
1146 }
1147
1148 static struct scsi_host_template driver_template = {
1149         .module                         = THIS_MODULE,
1150         .name                           = DRV_NAME,
1151         .proc_name                      = DRV_NAME,
1152         .bios_param                     = stex_biosparam,
1153         .queuecommand                   = stex_queuecommand,
1154         .slave_alloc                    = stex_slave_alloc,
1155         .slave_configure                = stex_slave_config,
1156         .slave_destroy                  = stex_slave_destroy,
1157         .eh_abort_handler               = stex_abort,
1158         .eh_host_reset_handler          = stex_reset,
1159         .can_queue                      = ST_CAN_QUEUE,
1160         .this_id                        = -1,
1161         .sg_tablesize                   = ST_MAX_SG,
1162         .cmd_per_lun                    = ST_CMD_PER_LUN,
1163 };
1164
1165 static int stex_set_dma_mask(struct pci_dev * pdev)
1166 {
1167         int ret;
1168         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1169                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1170                 return 0;
1171         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1172         if (!ret)
1173                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1174         return ret;
1175 }
1176
1177 static int __devinit
1178 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1179 {
1180         struct st_hba *hba;
1181         struct Scsi_Host *host;
1182         int err;
1183
1184         err = pci_enable_device(pdev);
1185         if (err)
1186                 return err;
1187
1188         pci_set_master(pdev);
1189
1190         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1191
1192         if (!host) {
1193                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1194                         pci_name(pdev));
1195                 err = -ENOMEM;
1196                 goto out_disable;
1197         }
1198
1199         hba = (struct st_hba *)host->hostdata;
1200         memset(hba, 0, sizeof(struct st_hba));
1201
1202         err = pci_request_regions(pdev, DRV_NAME);
1203         if (err < 0) {
1204                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1205                         pci_name(pdev));
1206                 goto out_scsi_host_put;
1207         }
1208
1209         hba->mmio_base = ioremap_nocache(pci_resource_start(pdev, 0),
1210                 pci_resource_len(pdev, 0));
1211         if ( !hba->mmio_base) {
1212                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1213                         pci_name(pdev));
1214                 err = -ENOMEM;
1215                 goto out_release_regions;
1216         }
1217
1218         err = stex_set_dma_mask(pdev);
1219         if (err) {
1220                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1221                         pci_name(pdev));
1222                 goto out_iounmap;
1223         }
1224
1225         hba->cardtype = (unsigned int) id->driver_data;
1226         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1227                 hba->cardtype = st_vsc1;
1228         hba->dma_size = (hba->cardtype == st_vsc1) ?
1229                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1230         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1231                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1232         if (!hba->dma_mem) {
1233                 err = -ENOMEM;
1234                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1235                         pci_name(pdev));
1236                 goto out_iounmap;
1237         }
1238
1239         hba->status_buffer =
1240                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1241         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1242         hba->mu_status = MU_STATE_STARTING;
1243
1244         if (hba->cardtype == st_shasta) {
1245                 host->max_lun = 8;
1246                 host->max_id = 16 + 1;
1247         } else if (hba->cardtype == st_yosemite) {
1248                 host->max_lun = 128;
1249                 host->max_id = 1 + 1;
1250         } else {
1251                 /* st_vsc and st_vsc1 */
1252                 host->max_lun = 1;
1253                 host->max_id = 128 + 1;
1254         }
1255         host->max_channel = 0;
1256         host->unique_id = host->host_no;
1257         host->max_cmd_len = STEX_CDB_LENGTH;
1258
1259         hba->host = host;
1260         hba->pdev = pdev;
1261         init_waitqueue_head(&hba->waitq);
1262
1263         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1264         if (err) {
1265                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1266                         pci_name(pdev));
1267                 goto out_pci_free;
1268         }
1269
1270         err = stex_handshake(hba);
1271         if (err)
1272                 goto out_free_irq;
1273
1274         err = scsi_init_shared_tag_map(host, host->can_queue);
1275         if (err) {
1276                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1277                         pci_name(pdev));
1278                 goto out_free_irq;
1279         }
1280
1281         pci_set_drvdata(pdev, hba);
1282
1283         err = scsi_add_host(host, &pdev->dev);
1284         if (err) {
1285                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1286                         pci_name(pdev));
1287                 goto out_free_irq;
1288         }
1289
1290         scsi_scan_host(host);
1291
1292         return 0;
1293
1294 out_free_irq:
1295         free_irq(pdev->irq, hba);
1296 out_pci_free:
1297         dma_free_coherent(&pdev->dev, hba->dma_size,
1298                           hba->dma_mem, hba->dma_handle);
1299 out_iounmap:
1300         iounmap(hba->mmio_base);
1301 out_release_regions:
1302         pci_release_regions(pdev);
1303 out_scsi_host_put:
1304         scsi_host_put(host);
1305 out_disable:
1306         pci_disable_device(pdev);
1307
1308         return err;
1309 }
1310
1311 static void stex_hba_stop(struct st_hba *hba)
1312 {
1313         struct req_msg *req;
1314         unsigned long flags;
1315         unsigned long before;
1316         u16 tag = 0;
1317
1318         spin_lock_irqsave(hba->host->host_lock, flags);
1319         req = stex_alloc_req(hba);
1320         memset(req->cdb, 0, STEX_CDB_LENGTH);
1321
1322         if (hba->cardtype == st_yosemite) {
1323                 req->cdb[0] = MGT_CMD;
1324                 req->cdb[1] = MGT_CMD_SIGNATURE;
1325                 req->cdb[2] = CTLR_CONFIG_CMD;
1326                 req->cdb[3] = CTLR_SHUTDOWN;
1327         } else {
1328                 req->cdb[0] = CONTROLLER_CMD;
1329                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1330                 req->cdb[2] = CTLR_POWER_SAVING;
1331         }
1332
1333         hba->ccb[tag].cmd = NULL;
1334         hba->ccb[tag].sg_count = 0;
1335         hba->ccb[tag].sense_bufflen = 0;
1336         hba->ccb[tag].sense_buffer = NULL;
1337         hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1338
1339         stex_send_cmd(hba, req, tag);
1340         spin_unlock_irqrestore(hba->host->host_lock, flags);
1341
1342         before = jiffies;
1343         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1344                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1345                         return;
1346                 msleep(10);
1347         }
1348 }
1349
1350 static void stex_hba_free(struct st_hba *hba)
1351 {
1352         free_irq(hba->pdev->irq, hba);
1353
1354         iounmap(hba->mmio_base);
1355
1356         pci_release_regions(hba->pdev);
1357
1358         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1359                           hba->dma_mem, hba->dma_handle);
1360 }
1361
1362 static void stex_remove(struct pci_dev *pdev)
1363 {
1364         struct st_hba *hba = pci_get_drvdata(pdev);
1365
1366         scsi_remove_host(hba->host);
1367
1368         pci_set_drvdata(pdev, NULL);
1369
1370         stex_hba_stop(hba);
1371
1372         stex_hba_free(hba);
1373
1374         scsi_host_put(hba->host);
1375
1376         pci_disable_device(pdev);
1377 }
1378
1379 static void stex_shutdown(struct pci_dev *pdev)
1380 {
1381         struct st_hba *hba = pci_get_drvdata(pdev);
1382
1383         stex_hba_stop(hba);
1384 }
1385
1386 static struct pci_device_id stex_pci_tbl[] = {
1387         /* st_shasta */
1388         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1389                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1390         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1391                 st_shasta }, /* SuperTrak EX12350 */
1392         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1393                 st_shasta }, /* SuperTrak EX4350 */
1394         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1395                 st_shasta }, /* SuperTrak EX24350 */
1396
1397         /* st_vsc */
1398         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1399
1400         /* st_yosemite */
1401         { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1402                 st_yosemite }, /* SuperTrak EX4650 */
1403         { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1404                 st_yosemite }, /* SuperTrak EX4650o */
1405         { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1406                 st_yosemite }, /* SuperTrak EX8650EL */
1407         { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1408                 st_yosemite }, /* SuperTrak EX8650 */
1409         { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1410                 st_yosemite }, /* SuperTrak EX8654 */
1411         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1412                 st_yosemite }, /* generic st_yosemite */
1413         { }     /* terminate list */
1414 };
1415 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1416
1417 static struct pci_driver stex_pci_driver = {
1418         .name           = DRV_NAME,
1419         .id_table       = stex_pci_tbl,
1420         .probe          = stex_probe,
1421         .remove         = __devexit_p(stex_remove),
1422         .shutdown       = stex_shutdown,
1423 };
1424
1425 static int __init stex_init(void)
1426 {
1427         printk(KERN_INFO DRV_NAME
1428                 ": Promise SuperTrak EX Driver version: %s\n",
1429                  ST_DRIVER_VERSION);
1430
1431         return pci_register_driver(&stex_pci_driver);
1432 }
1433
1434 static void __exit stex_exit(void)
1435 {
1436         pci_unregister_driver(&stex_pci_driver);
1437 }
1438
1439 module_init(stex_init);
1440 module_exit(stex_exit);