2 * sata_svw.c - ServerWorks / Apple K2 SATA
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This driver probably works with non-Apple versions of the
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING. If not, write to
29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
32 * libata documentation is available via 'make {ps|pdf}docs',
33 * as Documentation/DocBook/libata.*
35 * Hardware documentation available under NDA.
39 #include <linux/config.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/blkdev.h>
45 #include <linux/delay.h>
46 #include <linux/interrupt.h>
47 #include <linux/device.h>
48 #include <scsi/scsi_host.h>
49 #include <linux/libata.h>
53 #include <asm/pci-bridge.h>
54 #endif /* CONFIG_PPC_OF */
56 #define DRV_NAME "sata_svw"
57 #define DRV_VERSION "1.07"
60 /* Taskfile registers offsets */
61 K2_SATA_TF_CMD_OFFSET = 0x00,
62 K2_SATA_TF_DATA_OFFSET = 0x00,
63 K2_SATA_TF_ERROR_OFFSET = 0x04,
64 K2_SATA_TF_NSECT_OFFSET = 0x08,
65 K2_SATA_TF_LBAL_OFFSET = 0x0c,
66 K2_SATA_TF_LBAM_OFFSET = 0x10,
67 K2_SATA_TF_LBAH_OFFSET = 0x14,
68 K2_SATA_TF_DEVICE_OFFSET = 0x18,
69 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
70 K2_SATA_TF_CTL_OFFSET = 0x20,
73 K2_SATA_DMA_CMD_OFFSET = 0x30,
76 K2_SATA_SCR_STATUS_OFFSET = 0x40,
77 K2_SATA_SCR_ERROR_OFFSET = 0x44,
78 K2_SATA_SCR_CONTROL_OFFSET = 0x48,
81 K2_SATA_SICR1_OFFSET = 0x80,
82 K2_SATA_SICR2_OFFSET = 0x84,
83 K2_SATA_SIM_OFFSET = 0x88,
86 K2_SATA_PORT_OFFSET = 0x100,
89 static u8 k2_stat_check_status(struct ata_port *ap);
92 static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
94 if (sc_reg > SCR_CONTROL)
96 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
100 static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
103 if (sc_reg > SCR_CONTROL)
105 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
109 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
111 struct ata_ioports *ioaddr = &ap->ioaddr;
112 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
114 if (tf->ctl != ap->last_ctl) {
115 writeb(tf->ctl, ioaddr->ctl_addr);
116 ap->last_ctl = tf->ctl;
119 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
120 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
121 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
122 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
123 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
124 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
125 } else if (is_addr) {
126 writew(tf->feature, ioaddr->feature_addr);
127 writew(tf->nsect, ioaddr->nsect_addr);
128 writew(tf->lbal, ioaddr->lbal_addr);
129 writew(tf->lbam, ioaddr->lbam_addr);
130 writew(tf->lbah, ioaddr->lbah_addr);
133 if (tf->flags & ATA_TFLAG_DEVICE)
134 writeb(tf->device, ioaddr->device_addr);
140 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
142 struct ata_ioports *ioaddr = &ap->ioaddr;
143 u16 nsect, lbal, lbam, lbah, feature;
145 tf->command = k2_stat_check_status(ap);
146 tf->device = readw(ioaddr->device_addr);
147 feature = readw(ioaddr->error_addr);
148 nsect = readw(ioaddr->nsect_addr);
149 lbal = readw(ioaddr->lbal_addr);
150 lbam = readw(ioaddr->lbam_addr);
151 lbah = readw(ioaddr->lbah_addr);
153 tf->feature = feature;
159 if (tf->flags & ATA_TFLAG_LBA48) {
160 tf->hob_feature = feature >> 8;
161 tf->hob_nsect = nsect >> 8;
162 tf->hob_lbal = lbal >> 8;
163 tf->hob_lbam = lbam >> 8;
164 tf->hob_lbah = lbah >> 8;
169 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
170 * @qc: Info associated with this ATA transaction.
173 * spin_lock_irqsave(host_set lock)
176 static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
178 struct ata_port *ap = qc->ap;
179 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
181 void *mmio = (void *) ap->ioaddr.bmdma_addr;
182 /* load PRD table addr. */
183 mb(); /* make sure PRD table writes are visible to controller */
184 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
186 /* specify data direction, triple-check start bit is clear */
187 dmactl = readb(mmio + ATA_DMA_CMD);
188 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
190 dmactl |= ATA_DMA_WR;
191 writeb(dmactl, mmio + ATA_DMA_CMD);
193 /* issue r/w command if this is not a ATA DMA command*/
194 if (qc->tf.protocol != ATA_PROT_DMA)
195 ap->ops->exec_command(ap, &qc->tf);
199 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
200 * @qc: Info associated with this ATA transaction.
203 * spin_lock_irqsave(host_set lock)
206 static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
208 struct ata_port *ap = qc->ap;
209 void *mmio = (void *) ap->ioaddr.bmdma_addr;
212 /* start host DMA transaction */
213 dmactl = readb(mmio + ATA_DMA_CMD);
214 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
215 /* There is a race condition in certain SATA controllers that can
216 be seen when the r/w command is given to the controller before the
217 host DMA is started. On a Read command, the controller would initiate
218 the command to the drive even before it sees the DMA start. When there
219 are very fast drives connected to the controller, or when the data request
220 hits in the drive cache, there is the possibility that the drive returns a part
221 or all of the requested data to the controller before the DMA start is issued.
222 In this case, the controller would become confused as to what to do with the data.
223 In the worst case when all the data is returned back to the controller, the
224 controller could hang. In other cases it could return partial data returning
225 in data corruption. This problem has been seen in PPC systems and can also appear
226 on an system with very fast disks, where the SATA controller is sitting behind a
227 number of bridges, and hence there is significant latency between the r/w command
228 and the start command. */
229 /* issue r/w command if the access is to ATA*/
230 if (qc->tf.protocol == ATA_PROT_DMA)
231 ap->ops->exec_command(ap, &qc->tf);
235 static u8 k2_stat_check_status(struct ata_port *ap)
237 return readl((void *) ap->ioaddr.status_addr);
243 * inout : decides on the direction of the dataflow and the meaning of the
245 * buffer: If inout==FALSE data is being written to it else read from it
246 * *start: If inout==FALSE start of the valid data in the buffer
247 * offset: If inout==FALSE offset from the beginning of the imaginary file
248 * from which we start writing into the buffer
249 * length: If inout==FALSE max number of bytes to be written into the buffer
250 * else number of bytes in the buffer
252 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
253 off_t offset, int count, int inout)
256 struct device_node *np;
259 /* Find the ata_port */
260 ap = (struct ata_port *) &shost->hostdata[0];
264 /* Find the OF node for the PCI device proper */
265 np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
269 /* Match it to a port node */
270 index = (ap == ap->host_set->ports[0]) ? 0 : 1;
271 for (np = np->child; np != NULL; np = np->sibling) {
272 u32 *reg = (u32 *)get_property(np, "reg", NULL);
281 len = sprintf(page, "devspec: %s\n", np->full_name);
285 #endif /* CONFIG_PPC_OF */
288 static struct scsi_host_template k2_sata_sht = {
289 .module = THIS_MODULE,
291 .ioctl = ata_scsi_ioctl,
292 .queuecommand = ata_scsi_queuecmd,
293 .eh_timed_out = ata_scsi_timed_out,
294 .eh_strategy_handler = ata_scsi_error,
295 .can_queue = ATA_DEF_QUEUE,
296 .this_id = ATA_SHT_THIS_ID,
297 .sg_tablesize = LIBATA_MAX_PRD,
298 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
299 .emulated = ATA_SHT_EMULATED,
300 .use_clustering = ATA_SHT_USE_CLUSTERING,
301 .proc_name = DRV_NAME,
302 .dma_boundary = ATA_DMA_BOUNDARY,
303 .slave_configure = ata_scsi_slave_config,
305 .proc_info = k2_sata_proc_info,
307 .bios_param = ata_std_bios_param,
311 static const struct ata_port_operations k2_sata_ops = {
312 .port_disable = ata_port_disable,
313 .tf_load = k2_sata_tf_load,
314 .tf_read = k2_sata_tf_read,
315 .check_status = k2_stat_check_status,
316 .exec_command = ata_exec_command,
317 .dev_select = ata_std_dev_select,
318 .phy_reset = sata_phy_reset,
319 .bmdma_setup = k2_bmdma_setup_mmio,
320 .bmdma_start = k2_bmdma_start_mmio,
321 .bmdma_stop = ata_bmdma_stop,
322 .bmdma_status = ata_bmdma_status,
323 .qc_prep = ata_qc_prep,
324 .qc_issue = ata_qc_issue_prot,
325 .eng_timeout = ata_eng_timeout,
326 .irq_handler = ata_interrupt,
327 .irq_clear = ata_bmdma_irq_clear,
328 .scr_read = k2_sata_scr_read,
329 .scr_write = k2_sata_scr_write,
330 .port_start = ata_port_start,
331 .port_stop = ata_port_stop,
332 .host_stop = ata_pci_host_stop,
335 static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
337 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
338 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
340 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
341 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
342 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
343 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
344 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
345 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
347 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
348 port->altstatus_addr =
349 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
350 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
351 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
355 static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
357 static int printed_version;
358 struct ata_probe_ent *probe_ent = NULL;
360 void __iomem *mmio_base;
361 int pci_dev_busy = 0;
365 if (!printed_version++)
366 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
369 * If this driver happens to only be useful on Apple's K2, then
370 * we should check that here as it has a normal Serverworks ID
372 rc = pci_enable_device(pdev);
376 * Check if we have resources mapped at all (second function may
377 * have been disabled by firmware)
379 if (pci_resource_len(pdev, 5) == 0)
382 /* Request PCI regions */
383 rc = pci_request_regions(pdev, DRV_NAME);
389 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
391 goto err_out_regions;
392 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
394 goto err_out_regions;
396 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
397 if (probe_ent == NULL) {
399 goto err_out_regions;
402 memset(probe_ent, 0, sizeof(*probe_ent));
403 probe_ent->dev = pci_dev_to_dev(pdev);
404 INIT_LIST_HEAD(&probe_ent->node);
406 mmio_base = pci_iomap(pdev, 5, 0);
407 if (mmio_base == NULL) {
409 goto err_out_free_ent;
411 base = (unsigned long) mmio_base;
413 /* Clear a magic bit in SCR1 according to Darwin, those help
414 * some funky seagate drives (though so far, those were already
415 * set by the firmware on the machines I had access to)
417 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
418 mmio_base + K2_SATA_SICR1_OFFSET);
420 /* Clear SATA error & interrupts we don't use */
421 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
422 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
424 probe_ent->sht = &k2_sata_sht;
425 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
426 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
427 probe_ent->port_ops = &k2_sata_ops;
428 probe_ent->n_ports = 4;
429 probe_ent->irq = pdev->irq;
430 probe_ent->irq_flags = SA_SHIRQ;
431 probe_ent->mmio_base = mmio_base;
433 /* We don't care much about the PIO/UDMA masks, but the core won't like us
434 * if we don't fill these
436 probe_ent->pio_mask = 0x1f;
437 probe_ent->mwdma_mask = 0x7;
438 probe_ent->udma_mask = 0x7f;
440 /* different controllers have different number of ports - currently 4 or 8 */
441 /* All ports are on the same function. Multi-function device is no
442 * longer available. This should not be seen in any system. */
443 for (i = 0; i < ent->driver_data; i++)
444 k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
446 pci_set_master(pdev);
448 /* FIXME: check ata_device_add return value */
449 ata_device_add(probe_ent);
457 pci_release_regions(pdev);
460 pci_disable_device(pdev);
464 /* 0x240 is device ID for Apple K2 device
465 * 0x241 is device ID for Serverworks Frodo4
466 * 0x242 is device ID for Serverworks Frodo8
467 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
470 static const struct pci_device_id k2_sata_pci_tbl[] = {
471 { 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
472 { 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
473 { 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
474 { 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
475 { 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
480 static struct pci_driver k2_sata_pci_driver = {
482 .id_table = k2_sata_pci_tbl,
483 .probe = k2_sata_init_one,
484 .remove = ata_pci_remove_one,
488 static int __init k2_sata_init(void)
490 return pci_module_init(&k2_sata_pci_driver);
494 static void __exit k2_sata_exit(void)
496 pci_unregister_driver(&k2_sata_pci_driver);
500 MODULE_AUTHOR("Benjamin Herrenschmidt");
501 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
502 MODULE_LICENSE("GPL");
503 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
504 MODULE_VERSION(DRV_VERSION);
506 module_init(k2_sata_init);
507 module_exit(k2_sata_exit);