Merge tag 'dm-4.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/device...
[sfrench/cifs-2.6.git] / drivers / scsi / qla2xxx / qla_init.c
1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c)  2003-2014 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #include "qla_def.h"
8 #include "qla_gbl.h"
9
10 #include <linux/delay.h>
11 #include <linux/slab.h>
12 #include <linux/vmalloc.h>
13
14 #include "qla_devtbl.h"
15
16 #ifdef CONFIG_SPARC
17 #include <asm/prom.h>
18 #endif
19
20 #include <target/target_core_base.h>
21 #include "qla_target.h"
22
23 /*
24 *  QLogic ISP2x00 Hardware Support Function Prototypes.
25 */
26 static int qla2x00_isp_firmware(scsi_qla_host_t *);
27 static int qla2x00_setup_chip(scsi_qla_host_t *);
28 static int qla2x00_fw_ready(scsi_qla_host_t *);
29 static int qla2x00_configure_hba(scsi_qla_host_t *);
30 static int qla2x00_configure_loop(scsi_qla_host_t *);
31 static int qla2x00_configure_local_loop(scsi_qla_host_t *);
32 static int qla2x00_configure_fabric(scsi_qla_host_t *);
33 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
34 static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35     uint16_t *);
36
37 static int qla2x00_restart_isp(scsi_qla_host_t *);
38
39 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40 static int qla84xx_init_chip(scsi_qla_host_t *);
41 static int qla25xx_init_queues(struct qla_hw_data *);
42
43 /* SRB Extensions ---------------------------------------------------------- */
44
45 void
46 qla2x00_sp_timeout(unsigned long __data)
47 {
48         srb_t *sp = (srb_t *)__data;
49         struct srb_iocb *iocb;
50         fc_port_t *fcport = sp->fcport;
51         struct qla_hw_data *ha = fcport->vha->hw;
52         struct req_que *req;
53         unsigned long flags;
54
55         spin_lock_irqsave(&ha->hardware_lock, flags);
56         req = ha->req_q_map[0];
57         req->outstanding_cmds[sp->handle] = NULL;
58         iocb = &sp->u.iocb_cmd;
59         iocb->timeout(sp);
60         sp->free(fcport->vha, sp);
61         spin_unlock_irqrestore(&ha->hardware_lock, flags);
62 }
63
64 void
65 qla2x00_sp_free(void *data, void *ptr)
66 {
67         srb_t *sp = (srb_t *)ptr;
68         struct srb_iocb *iocb = &sp->u.iocb_cmd;
69         struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
70
71         del_timer(&iocb->timer);
72         qla2x00_rel_sp(vha, sp);
73 }
74
75 /* Asynchronous Login/Logout Routines -------------------------------------- */
76
77 unsigned long
78 qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79 {
80         unsigned long tmo;
81         struct qla_hw_data *ha = vha->hw;
82
83         /* Firmware should use switch negotiated r_a_tov for timeout. */
84         tmo = ha->r_a_tov / 10 * 2;
85         if (IS_QLAFX00(ha)) {
86                 tmo = FX00_DEF_RATOV * 2;
87         } else if (!IS_FWI2_CAPABLE(ha)) {
88                 /*
89                  * Except for earlier ISPs where the timeout is seeded from the
90                  * initialization control block.
91                  */
92                 tmo = ha->login_timeout;
93         }
94         return tmo;
95 }
96
97 static void
98 qla2x00_async_iocb_timeout(void *data)
99 {
100         srb_t *sp = (srb_t *)data;
101         fc_port_t *fcport = sp->fcport;
102
103         ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
104             "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
105             sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
106             fcport->d_id.b.al_pa);
107
108         fcport->flags &= ~FCF_ASYNC_SENT;
109         if (sp->type == SRB_LOGIN_CMD) {
110                 struct srb_iocb *lio = &sp->u.iocb_cmd;
111                 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
112                 /* Retry as needed. */
113                 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114                 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115                         QLA_LOGIO_LOGIN_RETRIED : 0;
116                 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117                         lio->u.logio.data);
118         } else if (sp->type == SRB_LOGOUT_CMD) {
119                 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
120         }
121 }
122
123 static void
124 qla2x00_async_login_sp_done(void *data, void *ptr, int res)
125 {
126         srb_t *sp = (srb_t *)ptr;
127         struct srb_iocb *lio = &sp->u.iocb_cmd;
128         struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
129
130         if (!test_bit(UNLOADING, &vha->dpc_flags))
131                 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
132                     lio->u.logio.data);
133         sp->free(sp->fcport->vha, sp);
134 }
135
136 int
137 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
138     uint16_t *data)
139 {
140         srb_t *sp;
141         struct srb_iocb *lio;
142         int rval;
143
144         rval = QLA_FUNCTION_FAILED;
145         sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
146         if (!sp)
147                 goto done;
148
149         sp->type = SRB_LOGIN_CMD;
150         sp->name = "login";
151         qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
152
153         lio = &sp->u.iocb_cmd;
154         lio->timeout = qla2x00_async_iocb_timeout;
155         sp->done = qla2x00_async_login_sp_done;
156         lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
157         if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
158                 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
159         rval = qla2x00_start_sp(sp);
160         if (rval != QLA_SUCCESS) {
161                 fcport->flags &= ~FCF_ASYNC_SENT;
162                 fcport->flags |= FCF_LOGIN_NEEDED;
163                 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
164                 goto done_free_sp;
165         }
166
167         ql_dbg(ql_dbg_disc, vha, 0x2072,
168             "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
169             "retries=%d.\n", sp->handle, fcport->loop_id,
170             fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
171             fcport->login_retry);
172         return rval;
173
174 done_free_sp:
175         sp->free(fcport->vha, sp);
176 done:
177         return rval;
178 }
179
180 static void
181 qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
182 {
183         srb_t *sp = (srb_t *)ptr;
184         struct srb_iocb *lio = &sp->u.iocb_cmd;
185         struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
186
187         if (!test_bit(UNLOADING, &vha->dpc_flags))
188                 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
189                     lio->u.logio.data);
190         sp->free(sp->fcport->vha, sp);
191 }
192
193 int
194 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
195 {
196         srb_t *sp;
197         struct srb_iocb *lio;
198         int rval;
199
200         rval = QLA_FUNCTION_FAILED;
201         sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
202         if (!sp)
203                 goto done;
204
205         sp->type = SRB_LOGOUT_CMD;
206         sp->name = "logout";
207         qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
208
209         lio = &sp->u.iocb_cmd;
210         lio->timeout = qla2x00_async_iocb_timeout;
211         sp->done = qla2x00_async_logout_sp_done;
212         rval = qla2x00_start_sp(sp);
213         if (rval != QLA_SUCCESS)
214                 goto done_free_sp;
215
216         ql_dbg(ql_dbg_disc, vha, 0x2070,
217             "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
218             sp->handle, fcport->loop_id, fcport->d_id.b.domain,
219             fcport->d_id.b.area, fcport->d_id.b.al_pa);
220         return rval;
221
222 done_free_sp:
223         sp->free(fcport->vha, sp);
224 done:
225         return rval;
226 }
227
228 static void
229 qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
230 {
231         srb_t *sp = (srb_t *)ptr;
232         struct srb_iocb *lio = &sp->u.iocb_cmd;
233         struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
234
235         if (!test_bit(UNLOADING, &vha->dpc_flags))
236                 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
237                     lio->u.logio.data);
238         sp->free(sp->fcport->vha, sp);
239 }
240
241 int
242 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
243     uint16_t *data)
244 {
245         srb_t *sp;
246         struct srb_iocb *lio;
247         int rval;
248
249         rval = QLA_FUNCTION_FAILED;
250         sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
251         if (!sp)
252                 goto done;
253
254         sp->type = SRB_ADISC_CMD;
255         sp->name = "adisc";
256         qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
257
258         lio = &sp->u.iocb_cmd;
259         lio->timeout = qla2x00_async_iocb_timeout;
260         sp->done = qla2x00_async_adisc_sp_done;
261         if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
262                 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
263         rval = qla2x00_start_sp(sp);
264         if (rval != QLA_SUCCESS)
265                 goto done_free_sp;
266
267         ql_dbg(ql_dbg_disc, vha, 0x206f,
268             "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
269             sp->handle, fcport->loop_id, fcport->d_id.b.domain,
270             fcport->d_id.b.area, fcport->d_id.b.al_pa);
271         return rval;
272
273 done_free_sp:
274         sp->free(fcport->vha, sp);
275 done:
276         return rval;
277 }
278
279 static void
280 qla2x00_tmf_iocb_timeout(void *data)
281 {
282         srb_t *sp = (srb_t *)data;
283         struct srb_iocb *tmf = &sp->u.iocb_cmd;
284
285         tmf->u.tmf.comp_status = CS_TIMEOUT;
286         complete(&tmf->u.tmf.comp);
287 }
288
289 static void
290 qla2x00_tmf_sp_done(void *data, void *ptr, int res)
291 {
292         srb_t *sp = (srb_t *)ptr;
293         struct srb_iocb *tmf = &sp->u.iocb_cmd;
294         complete(&tmf->u.tmf.comp);
295 }
296
297 int
298 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
299         uint32_t tag)
300 {
301         struct scsi_qla_host *vha = fcport->vha;
302         struct srb_iocb *tm_iocb;
303         srb_t *sp;
304         int rval = QLA_FUNCTION_FAILED;
305
306         sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
307         if (!sp)
308                 goto done;
309
310         tm_iocb = &sp->u.iocb_cmd;
311         sp->type = SRB_TM_CMD;
312         sp->name = "tmf";
313         qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
314         tm_iocb->u.tmf.flags = flags;
315         tm_iocb->u.tmf.lun = lun;
316         tm_iocb->u.tmf.data = tag;
317         sp->done = qla2x00_tmf_sp_done;
318         tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
319         init_completion(&tm_iocb->u.tmf.comp);
320
321         rval = qla2x00_start_sp(sp);
322         if (rval != QLA_SUCCESS)
323                 goto done_free_sp;
324
325         ql_dbg(ql_dbg_taskm, vha, 0x802f,
326             "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
327             sp->handle, fcport->loop_id, fcport->d_id.b.domain,
328             fcport->d_id.b.area, fcport->d_id.b.al_pa);
329
330         wait_for_completion(&tm_iocb->u.tmf.comp);
331
332         rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
333             QLA_SUCCESS : QLA_FUNCTION_FAILED;
334
335         if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
336                 ql_dbg(ql_dbg_taskm, vha, 0x8030,
337                     "TM IOCB failed (%x).\n", rval);
338         }
339
340         if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
341                 flags = tm_iocb->u.tmf.flags;
342                 lun = (uint16_t)tm_iocb->u.tmf.lun;
343
344                 /* Issue Marker IOCB */
345                 qla2x00_marker(vha, vha->hw->req_q_map[0],
346                     vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
347                     flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
348         }
349
350 done_free_sp:
351         sp->free(vha, sp);
352 done:
353         return rval;
354 }
355
356 static void
357 qla24xx_abort_iocb_timeout(void *data)
358 {
359         srb_t *sp = (srb_t *)data;
360         struct srb_iocb *abt = &sp->u.iocb_cmd;
361
362         abt->u.abt.comp_status = CS_TIMEOUT;
363         complete(&abt->u.abt.comp);
364 }
365
366 static void
367 qla24xx_abort_sp_done(void *data, void *ptr, int res)
368 {
369         srb_t *sp = (srb_t *)ptr;
370         struct srb_iocb *abt = &sp->u.iocb_cmd;
371
372         complete(&abt->u.abt.comp);
373 }
374
375 static int
376 qla24xx_async_abort_cmd(srb_t *cmd_sp)
377 {
378         scsi_qla_host_t *vha = cmd_sp->fcport->vha;
379         fc_port_t *fcport = cmd_sp->fcport;
380         struct srb_iocb *abt_iocb;
381         srb_t *sp;
382         int rval = QLA_FUNCTION_FAILED;
383
384         sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
385         if (!sp)
386                 goto done;
387
388         abt_iocb = &sp->u.iocb_cmd;
389         sp->type = SRB_ABT_CMD;
390         sp->name = "abort";
391         qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
392         abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
393         sp->done = qla24xx_abort_sp_done;
394         abt_iocb->timeout = qla24xx_abort_iocb_timeout;
395         init_completion(&abt_iocb->u.abt.comp);
396
397         rval = qla2x00_start_sp(sp);
398         if (rval != QLA_SUCCESS)
399                 goto done_free_sp;
400
401         ql_dbg(ql_dbg_async, vha, 0x507c,
402             "Abort command issued - hdl=%x, target_id=%x\n",
403             cmd_sp->handle, fcport->tgt_id);
404
405         wait_for_completion(&abt_iocb->u.abt.comp);
406
407         rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
408             QLA_SUCCESS : QLA_FUNCTION_FAILED;
409
410 done_free_sp:
411         sp->free(vha, sp);
412 done:
413         return rval;
414 }
415
416 int
417 qla24xx_async_abort_command(srb_t *sp)
418 {
419         unsigned long   flags = 0;
420
421         uint32_t        handle;
422         fc_port_t       *fcport = sp->fcport;
423         struct scsi_qla_host *vha = fcport->vha;
424         struct qla_hw_data *ha = vha->hw;
425         struct req_que *req = vha->req;
426
427         spin_lock_irqsave(&ha->hardware_lock, flags);
428         for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
429                 if (req->outstanding_cmds[handle] == sp)
430                         break;
431         }
432         spin_unlock_irqrestore(&ha->hardware_lock, flags);
433         if (handle == req->num_outstanding_cmds) {
434                 /* Command not found. */
435                 return QLA_FUNCTION_FAILED;
436         }
437         if (sp->type == SRB_FXIOCB_DCMD)
438                 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
439                     FXDISC_ABORT_IOCTL);
440
441         return qla24xx_async_abort_cmd(sp);
442 }
443
444 void
445 qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
446     uint16_t *data)
447 {
448         int rval;
449
450         switch (data[0]) {
451         case MBS_COMMAND_COMPLETE:
452                 /*
453                  * Driver must validate login state - If PRLI not complete,
454                  * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
455                  * requests.
456                  */
457                 rval = qla2x00_get_port_database(vha, fcport, 0);
458                 if (rval == QLA_NOT_LOGGED_IN) {
459                         fcport->flags &= ~FCF_ASYNC_SENT;
460                         fcport->flags |= FCF_LOGIN_NEEDED;
461                         set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
462                         break;
463                 }
464
465                 if (rval != QLA_SUCCESS) {
466                         qla2x00_post_async_logout_work(vha, fcport, NULL);
467                         qla2x00_post_async_login_work(vha, fcport, NULL);
468                         break;
469                 }
470                 if (fcport->flags & FCF_FCP2_DEVICE) {
471                         qla2x00_post_async_adisc_work(vha, fcport, data);
472                         break;
473                 }
474                 qla2x00_update_fcport(vha, fcport);
475                 break;
476         case MBS_COMMAND_ERROR:
477                 fcport->flags &= ~FCF_ASYNC_SENT;
478                 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
479                         set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
480                 else
481                         qla2x00_mark_device_lost(vha, fcport, 1, 0);
482                 break;
483         case MBS_PORT_ID_USED:
484                 fcport->loop_id = data[1];
485                 qla2x00_post_async_logout_work(vha, fcport, NULL);
486                 qla2x00_post_async_login_work(vha, fcport, NULL);
487                 break;
488         case MBS_LOOP_ID_USED:
489                 fcport->loop_id++;
490                 rval = qla2x00_find_new_loop_id(vha, fcport);
491                 if (rval != QLA_SUCCESS) {
492                         fcport->flags &= ~FCF_ASYNC_SENT;
493                         qla2x00_mark_device_lost(vha, fcport, 1, 0);
494                         break;
495                 }
496                 qla2x00_post_async_login_work(vha, fcport, NULL);
497                 break;
498         }
499         return;
500 }
501
502 void
503 qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
504     uint16_t *data)
505 {
506         /* Don't re-login in target mode */
507         if (!fcport->tgt_session)
508                 qla2x00_mark_device_lost(vha, fcport, 1, 0);
509         qlt_logo_completion_handler(fcport, data[0]);
510         return;
511 }
512
513 void
514 qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
515     uint16_t *data)
516 {
517         if (data[0] == MBS_COMMAND_COMPLETE) {
518                 qla2x00_update_fcport(vha, fcport);
519
520                 return;
521         }
522
523         /* Retry login. */
524         fcport->flags &= ~FCF_ASYNC_SENT;
525         if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
526                 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
527         else
528                 qla2x00_mark_device_lost(vha, fcport, 1, 0);
529
530         return;
531 }
532
533 /****************************************************************************/
534 /*                QLogic ISP2x00 Hardware Support Functions.                */
535 /****************************************************************************/
536
537 static int
538 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
539 {
540         int rval = QLA_SUCCESS;
541         struct qla_hw_data *ha = vha->hw;
542         uint32_t idc_major_ver, idc_minor_ver;
543         uint16_t config[4];
544
545         qla83xx_idc_lock(vha, 0);
546
547         /* SV: TODO: Assign initialization timeout from
548          * flash-info / other param
549          */
550         ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
551         ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
552
553         /* Set our fcoe function presence */
554         if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
555                 ql_dbg(ql_dbg_p3p, vha, 0xb077,
556                     "Error while setting DRV-Presence.\n");
557                 rval = QLA_FUNCTION_FAILED;
558                 goto exit;
559         }
560
561         /* Decide the reset ownership */
562         qla83xx_reset_ownership(vha);
563
564         /*
565          * On first protocol driver load:
566          * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
567          * register.
568          * Others: Check compatibility with current IDC Major version.
569          */
570         qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
571         if (ha->flags.nic_core_reset_owner) {
572                 /* Set IDC Major version */
573                 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
574                 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
575
576                 /* Clearing IDC-Lock-Recovery register */
577                 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
578         } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
579                 /*
580                  * Clear further IDC participation if we are not compatible with
581                  * the current IDC Major Version.
582                  */
583                 ql_log(ql_log_warn, vha, 0xb07d,
584                     "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
585                     idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
586                 __qla83xx_clear_drv_presence(vha);
587                 rval = QLA_FUNCTION_FAILED;
588                 goto exit;
589         }
590         /* Each function sets its supported Minor version. */
591         qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
592         idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
593         qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
594
595         if (ha->flags.nic_core_reset_owner) {
596                 memset(config, 0, sizeof(config));
597                 if (!qla81xx_get_port_config(vha, config))
598                         qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
599                             QLA8XXX_DEV_READY);
600         }
601
602         rval = qla83xx_idc_state_handler(vha);
603
604 exit:
605         qla83xx_idc_unlock(vha, 0);
606
607         return rval;
608 }
609
610 /*
611 * qla2x00_initialize_adapter
612 *      Initialize board.
613 *
614 * Input:
615 *      ha = adapter block pointer.
616 *
617 * Returns:
618 *      0 = success
619 */
620 int
621 qla2x00_initialize_adapter(scsi_qla_host_t *vha)
622 {
623         int     rval;
624         struct qla_hw_data *ha = vha->hw;
625         struct req_que *req = ha->req_q_map[0];
626
627         memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
628         memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
629
630         /* Clear adapter flags. */
631         vha->flags.online = 0;
632         ha->flags.chip_reset_done = 0;
633         vha->flags.reset_active = 0;
634         ha->flags.pci_channel_io_perm_failure = 0;
635         ha->flags.eeh_busy = 0;
636         vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
637         atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
638         atomic_set(&vha->loop_state, LOOP_DOWN);
639         vha->device_flags = DFLG_NO_CABLE;
640         vha->dpc_flags = 0;
641         vha->flags.management_server_logged_in = 0;
642         vha->marker_needed = 0;
643         ha->isp_abort_cnt = 0;
644         ha->beacon_blink_led = 0;
645
646         set_bit(0, ha->req_qid_map);
647         set_bit(0, ha->rsp_qid_map);
648
649         ql_dbg(ql_dbg_init, vha, 0x0040,
650             "Configuring PCI space...\n");
651         rval = ha->isp_ops->pci_config(vha);
652         if (rval) {
653                 ql_log(ql_log_warn, vha, 0x0044,
654                     "Unable to configure PCI space.\n");
655                 return (rval);
656         }
657
658         ha->isp_ops->reset_chip(vha);
659
660         rval = qla2xxx_get_flash_info(vha);
661         if (rval) {
662                 ql_log(ql_log_fatal, vha, 0x004f,
663                     "Unable to validate FLASH data.\n");
664                 return rval;
665         }
666
667         if (IS_QLA8044(ha)) {
668                 qla8044_read_reset_template(vha);
669
670                 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
671                  * If DONRESET_BIT0 is set, drivers should not set dev_state
672                  * to NEED_RESET. But if NEED_RESET is set, drivers should
673                  * should honor the reset. */
674                 if (ql2xdontresethba == 1)
675                         qla8044_set_idc_dontreset(vha);
676         }
677
678         ha->isp_ops->get_flash_version(vha, req->ring);
679         ql_dbg(ql_dbg_init, vha, 0x0061,
680             "Configure NVRAM parameters...\n");
681
682         ha->isp_ops->nvram_config(vha);
683
684         if (ha->flags.disable_serdes) {
685                 /* Mask HBA via NVRAM settings? */
686                 ql_log(ql_log_info, vha, 0x0077,
687                     "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
688                 return QLA_FUNCTION_FAILED;
689         }
690
691         ql_dbg(ql_dbg_init, vha, 0x0078,
692             "Verifying loaded RISC code...\n");
693
694         if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
695                 rval = ha->isp_ops->chip_diag(vha);
696                 if (rval)
697                         return (rval);
698                 rval = qla2x00_setup_chip(vha);
699                 if (rval)
700                         return (rval);
701         }
702
703         if (IS_QLA84XX(ha)) {
704                 ha->cs84xx = qla84xx_get_chip(vha);
705                 if (!ha->cs84xx) {
706                         ql_log(ql_log_warn, vha, 0x00d0,
707                             "Unable to configure ISP84XX.\n");
708                         return QLA_FUNCTION_FAILED;
709                 }
710         }
711
712         if (qla_ini_mode_enabled(vha))
713                 rval = qla2x00_init_rings(vha);
714
715         ha->flags.chip_reset_done = 1;
716
717         if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
718                 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
719                 rval = qla84xx_init_chip(vha);
720                 if (rval != QLA_SUCCESS) {
721                         ql_log(ql_log_warn, vha, 0x00d4,
722                             "Unable to initialize ISP84XX.\n");
723                         qla84xx_put_chip(vha);
724                 }
725         }
726
727         /* Load the NIC Core f/w if we are the first protocol driver. */
728         if (IS_QLA8031(ha)) {
729                 rval = qla83xx_nic_core_fw_load(vha);
730                 if (rval)
731                         ql_log(ql_log_warn, vha, 0x0124,
732                             "Error in initializing NIC Core f/w.\n");
733         }
734
735         if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
736                 qla24xx_read_fcp_prio_cfg(vha);
737
738         if (IS_P3P_TYPE(ha))
739                 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
740         else
741                 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
742
743         return (rval);
744 }
745
746 /**
747  * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
748  * @ha: HA context
749  *
750  * Returns 0 on success.
751  */
752 int
753 qla2100_pci_config(scsi_qla_host_t *vha)
754 {
755         uint16_t w;
756         unsigned long flags;
757         struct qla_hw_data *ha = vha->hw;
758         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
759
760         pci_set_master(ha->pdev);
761         pci_try_set_mwi(ha->pdev);
762
763         pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
764         w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
765         pci_write_config_word(ha->pdev, PCI_COMMAND, w);
766
767         pci_disable_rom(ha->pdev);
768
769         /* Get PCI bus information. */
770         spin_lock_irqsave(&ha->hardware_lock, flags);
771         ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
772         spin_unlock_irqrestore(&ha->hardware_lock, flags);
773
774         return QLA_SUCCESS;
775 }
776
777 /**
778  * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
779  * @ha: HA context
780  *
781  * Returns 0 on success.
782  */
783 int
784 qla2300_pci_config(scsi_qla_host_t *vha)
785 {
786         uint16_t        w;
787         unsigned long   flags = 0;
788         uint32_t        cnt;
789         struct qla_hw_data *ha = vha->hw;
790         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
791
792         pci_set_master(ha->pdev);
793         pci_try_set_mwi(ha->pdev);
794
795         pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
796         w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
797
798         if (IS_QLA2322(ha) || IS_QLA6322(ha))
799                 w &= ~PCI_COMMAND_INTX_DISABLE;
800         pci_write_config_word(ha->pdev, PCI_COMMAND, w);
801
802         /*
803          * If this is a 2300 card and not 2312, reset the
804          * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
805          * the 2310 also reports itself as a 2300 so we need to get the
806          * fb revision level -- a 6 indicates it really is a 2300 and
807          * not a 2310.
808          */
809         if (IS_QLA2300(ha)) {
810                 spin_lock_irqsave(&ha->hardware_lock, flags);
811
812                 /* Pause RISC. */
813                 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
814                 for (cnt = 0; cnt < 30000; cnt++) {
815                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
816                                 break;
817
818                         udelay(10);
819                 }
820
821                 /* Select FPM registers. */
822                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
823                 RD_REG_WORD(&reg->ctrl_status);
824
825                 /* Get the fb rev level */
826                 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
827
828                 if (ha->fb_rev == FPM_2300)
829                         pci_clear_mwi(ha->pdev);
830
831                 /* Deselect FPM registers. */
832                 WRT_REG_WORD(&reg->ctrl_status, 0x0);
833                 RD_REG_WORD(&reg->ctrl_status);
834
835                 /* Release RISC module. */
836                 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
837                 for (cnt = 0; cnt < 30000; cnt++) {
838                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
839                                 break;
840
841                         udelay(10);
842                 }
843
844                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
845         }
846
847         pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
848
849         pci_disable_rom(ha->pdev);
850
851         /* Get PCI bus information. */
852         spin_lock_irqsave(&ha->hardware_lock, flags);
853         ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
854         spin_unlock_irqrestore(&ha->hardware_lock, flags);
855
856         return QLA_SUCCESS;
857 }
858
859 /**
860  * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
861  * @ha: HA context
862  *
863  * Returns 0 on success.
864  */
865 int
866 qla24xx_pci_config(scsi_qla_host_t *vha)
867 {
868         uint16_t w;
869         unsigned long flags = 0;
870         struct qla_hw_data *ha = vha->hw;
871         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
872
873         pci_set_master(ha->pdev);
874         pci_try_set_mwi(ha->pdev);
875
876         pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
877         w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
878         w &= ~PCI_COMMAND_INTX_DISABLE;
879         pci_write_config_word(ha->pdev, PCI_COMMAND, w);
880
881         pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
882
883         /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
884         if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
885                 pcix_set_mmrbc(ha->pdev, 2048);
886
887         /* PCIe -- adjust Maximum Read Request Size (2048). */
888         if (pci_is_pcie(ha->pdev))
889                 pcie_set_readrq(ha->pdev, 4096);
890
891         pci_disable_rom(ha->pdev);
892
893         ha->chip_revision = ha->pdev->revision;
894
895         /* Get PCI bus information. */
896         spin_lock_irqsave(&ha->hardware_lock, flags);
897         ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
898         spin_unlock_irqrestore(&ha->hardware_lock, flags);
899
900         return QLA_SUCCESS;
901 }
902
903 /**
904  * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
905  * @ha: HA context
906  *
907  * Returns 0 on success.
908  */
909 int
910 qla25xx_pci_config(scsi_qla_host_t *vha)
911 {
912         uint16_t w;
913         struct qla_hw_data *ha = vha->hw;
914
915         pci_set_master(ha->pdev);
916         pci_try_set_mwi(ha->pdev);
917
918         pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
919         w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
920         w &= ~PCI_COMMAND_INTX_DISABLE;
921         pci_write_config_word(ha->pdev, PCI_COMMAND, w);
922
923         /* PCIe -- adjust Maximum Read Request Size (2048). */
924         if (pci_is_pcie(ha->pdev))
925                 pcie_set_readrq(ha->pdev, 4096);
926
927         pci_disable_rom(ha->pdev);
928
929         ha->chip_revision = ha->pdev->revision;
930
931         return QLA_SUCCESS;
932 }
933
934 /**
935  * qla2x00_isp_firmware() - Choose firmware image.
936  * @ha: HA context
937  *
938  * Returns 0 on success.
939  */
940 static int
941 qla2x00_isp_firmware(scsi_qla_host_t *vha)
942 {
943         int  rval;
944         uint16_t loop_id, topo, sw_cap;
945         uint8_t domain, area, al_pa;
946         struct qla_hw_data *ha = vha->hw;
947
948         /* Assume loading risc code */
949         rval = QLA_FUNCTION_FAILED;
950
951         if (ha->flags.disable_risc_code_load) {
952                 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
953
954                 /* Verify checksum of loaded RISC code. */
955                 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
956                 if (rval == QLA_SUCCESS) {
957                         /* And, verify we are not in ROM code. */
958                         rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
959                             &area, &domain, &topo, &sw_cap);
960                 }
961         }
962
963         if (rval)
964                 ql_dbg(ql_dbg_init, vha, 0x007a,
965                     "**** Load RISC code ****.\n");
966
967         return (rval);
968 }
969
970 /**
971  * qla2x00_reset_chip() - Reset ISP chip.
972  * @ha: HA context
973  *
974  * Returns 0 on success.
975  */
976 void
977 qla2x00_reset_chip(scsi_qla_host_t *vha)
978 {
979         unsigned long   flags = 0;
980         struct qla_hw_data *ha = vha->hw;
981         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
982         uint32_t        cnt;
983         uint16_t        cmd;
984
985         if (unlikely(pci_channel_offline(ha->pdev)))
986                 return;
987
988         ha->isp_ops->disable_intrs(ha);
989
990         spin_lock_irqsave(&ha->hardware_lock, flags);
991
992         /* Turn off master enable */
993         cmd = 0;
994         pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
995         cmd &= ~PCI_COMMAND_MASTER;
996         pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
997
998         if (!IS_QLA2100(ha)) {
999                 /* Pause RISC. */
1000                 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1001                 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
1002                         for (cnt = 0; cnt < 30000; cnt++) {
1003                                 if ((RD_REG_WORD(&reg->hccr) &
1004                                     HCCR_RISC_PAUSE) != 0)
1005                                         break;
1006                                 udelay(100);
1007                         }
1008                 } else {
1009                         RD_REG_WORD(&reg->hccr);        /* PCI Posting. */
1010                         udelay(10);
1011                 }
1012
1013                 /* Select FPM registers. */
1014                 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1015                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1016
1017                 /* FPM Soft Reset. */
1018                 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
1019                 RD_REG_WORD(&reg->fpm_diag_config);     /* PCI Posting. */
1020
1021                 /* Toggle Fpm Reset. */
1022                 if (!IS_QLA2200(ha)) {
1023                         WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
1024                         RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
1025                 }
1026
1027                 /* Select frame buffer registers. */
1028                 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1029                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1030
1031                 /* Reset frame buffer FIFOs. */
1032                 if (IS_QLA2200(ha)) {
1033                         WRT_FB_CMD_REG(ha, reg, 0xa000);
1034                         RD_FB_CMD_REG(ha, reg);         /* PCI Posting. */
1035                 } else {
1036                         WRT_FB_CMD_REG(ha, reg, 0x00fc);
1037
1038                         /* Read back fb_cmd until zero or 3 seconds max */
1039                         for (cnt = 0; cnt < 3000; cnt++) {
1040                                 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
1041                                         break;
1042                                 udelay(100);
1043                         }
1044                 }
1045
1046                 /* Select RISC module registers. */
1047                 WRT_REG_WORD(&reg->ctrl_status, 0);
1048                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1049
1050                 /* Reset RISC processor. */
1051                 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1052                 RD_REG_WORD(&reg->hccr);                /* PCI Posting. */
1053
1054                 /* Release RISC processor. */
1055                 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1056                 RD_REG_WORD(&reg->hccr);                /* PCI Posting. */
1057         }
1058
1059         WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
1060         WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
1061
1062         /* Reset ISP chip. */
1063         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1064
1065         /* Wait for RISC to recover from reset. */
1066         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1067                 /*
1068                  * It is necessary to for a delay here since the card doesn't
1069                  * respond to PCI reads during a reset. On some architectures
1070                  * this will result in an MCA.
1071                  */
1072                 udelay(20);
1073                 for (cnt = 30000; cnt; cnt--) {
1074                         if ((RD_REG_WORD(&reg->ctrl_status) &
1075                             CSR_ISP_SOFT_RESET) == 0)
1076                                 break;
1077                         udelay(100);
1078                 }
1079         } else
1080                 udelay(10);
1081
1082         /* Reset RISC processor. */
1083         WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1084
1085         WRT_REG_WORD(&reg->semaphore, 0);
1086
1087         /* Release RISC processor. */
1088         WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1089         RD_REG_WORD(&reg->hccr);                        /* PCI Posting. */
1090
1091         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1092                 for (cnt = 0; cnt < 30000; cnt++) {
1093                         if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1094                                 break;
1095
1096                         udelay(100);
1097                 }
1098         } else
1099                 udelay(100);
1100
1101         /* Turn on master enable */
1102         cmd |= PCI_COMMAND_MASTER;
1103         pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
1104
1105         /* Disable RISC pause on FPM parity error. */
1106         if (!IS_QLA2100(ha)) {
1107                 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
1108                 RD_REG_WORD(&reg->hccr);                /* PCI Posting. */
1109         }
1110
1111         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1112 }
1113
1114 /**
1115  * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
1116  *
1117  * Returns 0 on success.
1118  */
1119 static int
1120 qla81xx_reset_mpi(scsi_qla_host_t *vha)
1121 {
1122         uint16_t mb[4] = {0x1010, 0, 1, 0};
1123
1124         if (!IS_QLA81XX(vha->hw))
1125                 return QLA_SUCCESS;
1126
1127         return qla81xx_write_mpi_register(vha, mb);
1128 }
1129
1130 /**
1131  * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
1132  * @ha: HA context
1133  *
1134  * Returns 0 on success.
1135  */
1136 static inline int
1137 qla24xx_reset_risc(scsi_qla_host_t *vha)
1138 {
1139         unsigned long flags = 0;
1140         struct qla_hw_data *ha = vha->hw;
1141         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1142         uint32_t cnt;
1143         uint16_t wd;
1144         static int abts_cnt; /* ISP abort retry counts */
1145         int rval = QLA_SUCCESS;
1146
1147         spin_lock_irqsave(&ha->hardware_lock, flags);
1148
1149         /* Reset RISC. */
1150         WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1151         for (cnt = 0; cnt < 30000; cnt++) {
1152                 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1153                         break;
1154
1155                 udelay(10);
1156         }
1157
1158         if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
1159                 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
1160
1161         ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
1162             "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
1163             RD_REG_DWORD(&reg->hccr),
1164             RD_REG_DWORD(&reg->ctrl_status),
1165             (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
1166
1167         WRT_REG_DWORD(&reg->ctrl_status,
1168             CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1169         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1170
1171         udelay(100);
1172
1173         /* Wait for firmware to complete NVRAM accesses. */
1174         RD_REG_WORD(&reg->mailbox0);
1175         for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1176             rval == QLA_SUCCESS; cnt--) {
1177                 barrier();
1178                 if (cnt)
1179                         udelay(5);
1180                 else
1181                         rval = QLA_FUNCTION_TIMEOUT;
1182         }
1183
1184         if (rval == QLA_SUCCESS)
1185                 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
1186
1187         ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
1188             "HCCR: 0x%x, MailBox0 Status 0x%x\n",
1189             RD_REG_DWORD(&reg->hccr),
1190             RD_REG_DWORD(&reg->mailbox0));
1191
1192         /* Wait for soft-reset to complete. */
1193         RD_REG_DWORD(&reg->ctrl_status);
1194         for (cnt = 0; cnt < 60; cnt++) {
1195                 barrier();
1196                 if ((RD_REG_DWORD(&reg->ctrl_status) &
1197                     CSRX_ISP_SOFT_RESET) == 0)
1198                         break;
1199
1200                 udelay(5);
1201         }
1202         if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
1203                 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
1204
1205         ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
1206             "HCCR: 0x%x, Soft Reset status: 0x%x\n",
1207             RD_REG_DWORD(&reg->hccr),
1208             RD_REG_DWORD(&reg->ctrl_status));
1209
1210         /* If required, do an MPI FW reset now */
1211         if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1212                 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1213                         if (++abts_cnt < 5) {
1214                                 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1215                                 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1216                         } else {
1217                                 /*
1218                                  * We exhausted the ISP abort retries. We have to
1219                                  * set the board offline.
1220                                  */
1221                                 abts_cnt = 0;
1222                                 vha->flags.online = 0;
1223                         }
1224                 }
1225         }
1226
1227         WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1228         RD_REG_DWORD(&reg->hccr);
1229
1230         WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1231         RD_REG_DWORD(&reg->hccr);
1232
1233         WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1234         RD_REG_DWORD(&reg->hccr);
1235
1236         RD_REG_WORD(&reg->mailbox0);
1237         for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
1238             rval == QLA_SUCCESS; cnt--) {
1239                 barrier();
1240                 if (cnt)
1241                         udelay(5);
1242                 else
1243                         rval = QLA_FUNCTION_TIMEOUT;
1244         }
1245         if (rval == QLA_SUCCESS)
1246                 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
1247
1248         ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
1249             "Host Risc 0x%x, mailbox0 0x%x\n",
1250             RD_REG_DWORD(&reg->hccr),
1251              RD_REG_WORD(&reg->mailbox0));
1252
1253         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1254
1255         ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
1256             "Driver in %s mode\n",
1257             IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
1258
1259         if (IS_NOPOLLING_TYPE(ha))
1260                 ha->isp_ops->enable_intrs(ha);
1261
1262         return rval;
1263 }
1264
1265 static void
1266 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1267 {
1268         struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1269
1270         WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1271         *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1272
1273 }
1274
1275 static void
1276 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1277 {
1278         struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1279
1280         WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1281         WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1282 }
1283
1284 static void
1285 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1286 {
1287         uint32_t wd32 = 0;
1288         uint delta_msec = 100;
1289         uint elapsed_msec = 0;
1290         uint timeout_msec;
1291         ulong n;
1292
1293         if (vha->hw->pdev->subsystem_device != 0x0175 &&
1294             vha->hw->pdev->subsystem_device != 0x0240)
1295                 return;
1296
1297         WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
1298         udelay(100);
1299
1300 attempt:
1301         timeout_msec = TIMEOUT_SEMAPHORE;
1302         n = timeout_msec / delta_msec;
1303         while (n--) {
1304                 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1305                 qla25xx_read_risc_sema_reg(vha, &wd32);
1306                 if (wd32 & RISC_SEMAPHORE)
1307                         break;
1308                 msleep(delta_msec);
1309                 elapsed_msec += delta_msec;
1310                 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1311                         goto force;
1312         }
1313
1314         if (!(wd32 & RISC_SEMAPHORE))
1315                 goto force;
1316
1317         if (!(wd32 & RISC_SEMAPHORE_FORCE))
1318                 goto acquired;
1319
1320         qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1321         timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1322         n = timeout_msec / delta_msec;
1323         while (n--) {
1324                 qla25xx_read_risc_sema_reg(vha, &wd32);
1325                 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1326                         break;
1327                 msleep(delta_msec);
1328                 elapsed_msec += delta_msec;
1329                 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1330                         goto force;
1331         }
1332
1333         if (wd32 & RISC_SEMAPHORE_FORCE)
1334                 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1335
1336         goto attempt;
1337
1338 force:
1339         qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1340
1341 acquired:
1342         return;
1343 }
1344
1345 /**
1346  * qla24xx_reset_chip() - Reset ISP24xx chip.
1347  * @ha: HA context
1348  *
1349  * Returns 0 on success.
1350  */
1351 void
1352 qla24xx_reset_chip(scsi_qla_host_t *vha)
1353 {
1354         struct qla_hw_data *ha = vha->hw;
1355
1356         if (pci_channel_offline(ha->pdev) &&
1357             ha->flags.pci_channel_io_perm_failure) {
1358                 return;
1359         }
1360
1361         ha->isp_ops->disable_intrs(ha);
1362
1363         qla25xx_manipulate_risc_semaphore(vha);
1364
1365         /* Perform RISC reset. */
1366         qla24xx_reset_risc(vha);
1367 }
1368
1369 /**
1370  * qla2x00_chip_diag() - Test chip for proper operation.
1371  * @ha: HA context
1372  *
1373  * Returns 0 on success.
1374  */
1375 int
1376 qla2x00_chip_diag(scsi_qla_host_t *vha)
1377 {
1378         int             rval;
1379         struct qla_hw_data *ha = vha->hw;
1380         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1381         unsigned long   flags = 0;
1382         uint16_t        data;
1383         uint32_t        cnt;
1384         uint16_t        mb[5];
1385         struct req_que *req = ha->req_q_map[0];
1386
1387         /* Assume a failed state */
1388         rval = QLA_FUNCTION_FAILED;
1389
1390         ql_dbg(ql_dbg_init, vha, 0x007b,
1391             "Testing device at %lx.\n", (u_long)&reg->flash_address);
1392
1393         spin_lock_irqsave(&ha->hardware_lock, flags);
1394
1395         /* Reset ISP chip. */
1396         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1397
1398         /*
1399          * We need to have a delay here since the card will not respond while
1400          * in reset causing an MCA on some architectures.
1401          */
1402         udelay(20);
1403         data = qla2x00_debounce_register(&reg->ctrl_status);
1404         for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1405                 udelay(5);
1406                 data = RD_REG_WORD(&reg->ctrl_status);
1407                 barrier();
1408         }
1409
1410         if (!cnt)
1411                 goto chip_diag_failed;
1412
1413         ql_dbg(ql_dbg_init, vha, 0x007c,
1414             "Reset register cleared by chip reset.\n");
1415
1416         /* Reset RISC processor. */
1417         WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1418         WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1419
1420         /* Workaround for QLA2312 PCI parity error */
1421         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1422                 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1423                 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1424                         udelay(5);
1425                         data = RD_MAILBOX_REG(ha, reg, 0);
1426                         barrier();
1427                 }
1428         } else
1429                 udelay(10);
1430
1431         if (!cnt)
1432                 goto chip_diag_failed;
1433
1434         /* Check product ID of chip */
1435         ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1436
1437         mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1438         mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1439         mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1440         mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1441         if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1442             mb[3] != PROD_ID_3) {
1443                 ql_log(ql_log_warn, vha, 0x0062,
1444                     "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1445                     mb[1], mb[2], mb[3]);
1446
1447                 goto chip_diag_failed;
1448         }
1449         ha->product_id[0] = mb[1];
1450         ha->product_id[1] = mb[2];
1451         ha->product_id[2] = mb[3];
1452         ha->product_id[3] = mb[4];
1453
1454         /* Adjust fw RISC transfer size */
1455         if (req->length > 1024)
1456                 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1457         else
1458                 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
1459                     req->length;
1460
1461         if (IS_QLA2200(ha) &&
1462             RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1463                 /* Limit firmware transfer size with a 2200A */
1464                 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1465
1466                 ha->device_type |= DT_ISP2200A;
1467                 ha->fw_transfer_size = 128;
1468         }
1469
1470         /* Wrap Incoming Mailboxes Test. */
1471         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1472
1473         ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
1474         rval = qla2x00_mbx_reg_test(vha);
1475         if (rval)
1476                 ql_log(ql_log_warn, vha, 0x0080,
1477                     "Failed mailbox send register test.\n");
1478         else
1479                 /* Flag a successful rval */
1480                 rval = QLA_SUCCESS;
1481         spin_lock_irqsave(&ha->hardware_lock, flags);
1482
1483 chip_diag_failed:
1484         if (rval)
1485                 ql_log(ql_log_info, vha, 0x0081,
1486                     "Chip diagnostics **** FAILED ****.\n");
1487
1488         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1489
1490         return (rval);
1491 }
1492
1493 /**
1494  * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1495  * @ha: HA context
1496  *
1497  * Returns 0 on success.
1498  */
1499 int
1500 qla24xx_chip_diag(scsi_qla_host_t *vha)
1501 {
1502         int rval;
1503         struct qla_hw_data *ha = vha->hw;
1504         struct req_que *req = ha->req_q_map[0];
1505
1506         if (IS_P3P_TYPE(ha))
1507                 return QLA_SUCCESS;
1508
1509         ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
1510
1511         rval = qla2x00_mbx_reg_test(vha);
1512         if (rval) {
1513                 ql_log(ql_log_warn, vha, 0x0082,
1514                     "Failed mailbox send register test.\n");
1515         } else {
1516                 /* Flag a successful rval */
1517                 rval = QLA_SUCCESS;
1518         }
1519
1520         return rval;
1521 }
1522
1523 void
1524 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1525 {
1526         int rval;
1527         uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
1528             eft_size, fce_size, mq_size;
1529         dma_addr_t tc_dma;
1530         void *tc;
1531         struct qla_hw_data *ha = vha->hw;
1532         struct req_que *req = ha->req_q_map[0];
1533         struct rsp_que *rsp = ha->rsp_q_map[0];
1534
1535         if (ha->fw_dump) {
1536                 ql_dbg(ql_dbg_init, vha, 0x00bd,
1537                     "Firmware dump already allocated.\n");
1538                 return;
1539         }
1540
1541         ha->fw_dumped = 0;
1542         ha->fw_dump_cap_flags = 0;
1543         dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1544         req_q_size = rsp_q_size = 0;
1545
1546         if (IS_QLA27XX(ha))
1547                 goto try_fce;
1548
1549         if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
1550                 fixed_size = sizeof(struct qla2100_fw_dump);
1551         } else if (IS_QLA23XX(ha)) {
1552                 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1553                 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1554                     sizeof(uint16_t);
1555         } else if (IS_FWI2_CAPABLE(ha)) {
1556                 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
1557                         fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1558                 else if (IS_QLA81XX(ha))
1559                         fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1560                 else if (IS_QLA25XX(ha))
1561                         fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1562                 else
1563                         fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
1564
1565                 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1566                     sizeof(uint32_t);
1567                 if (ha->mqenable) {
1568                         if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
1569                                 mq_size = sizeof(struct qla2xxx_mq_chain);
1570                         /*
1571                          * Allocate maximum buffer size for all queues.
1572                          * Resizing must be done at end-of-dump processing.
1573                          */
1574                         mq_size += ha->max_req_queues *
1575                             (req->length * sizeof(request_t));
1576                         mq_size += ha->max_rsp_queues *
1577                             (rsp->length * sizeof(response_t));
1578                 }
1579                 if (ha->tgt.atio_ring)
1580                         mq_size += ha->tgt.atio_q_length * sizeof(request_t);
1581                 /* Allocate memory for Fibre Channel Event Buffer. */
1582                 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1583                     !IS_QLA27XX(ha))
1584                         goto try_eft;
1585
1586 try_fce:
1587                 if (ha->fce)
1588                         dma_free_coherent(&ha->pdev->dev,
1589                             FCE_SIZE, ha->fce, ha->fce_dma);
1590
1591                 /* Allocate memory for Fibre Channel Event Buffer. */
1592                 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1593                                          GFP_KERNEL);
1594                 if (!tc) {
1595                         ql_log(ql_log_warn, vha, 0x00be,
1596                             "Unable to allocate (%d KB) for FCE.\n",
1597                             FCE_SIZE / 1024);
1598                         goto try_eft;
1599                 }
1600
1601                 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
1602                     ha->fce_mb, &ha->fce_bufs);
1603                 if (rval) {
1604                         ql_log(ql_log_warn, vha, 0x00bf,
1605                             "Unable to initialize FCE (%d).\n", rval);
1606                         dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1607                             tc_dma);
1608                         ha->flags.fce_enabled = 0;
1609                         goto try_eft;
1610                 }
1611                 ql_dbg(ql_dbg_init, vha, 0x00c0,
1612                     "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
1613
1614                 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
1615                 ha->flags.fce_enabled = 1;
1616                 ha->fce_dma = tc_dma;
1617                 ha->fce = tc;
1618
1619 try_eft:
1620                 if (ha->eft)
1621                         dma_free_coherent(&ha->pdev->dev,
1622                             EFT_SIZE, ha->eft, ha->eft_dma);
1623
1624                 /* Allocate memory for Extended Trace Buffer. */
1625                 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1626                                          GFP_KERNEL);
1627                 if (!tc) {
1628                         ql_log(ql_log_warn, vha, 0x00c1,
1629                             "Unable to allocate (%d KB) for EFT.\n",
1630                             EFT_SIZE / 1024);
1631                         goto cont_alloc;
1632                 }
1633
1634                 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
1635                 if (rval) {
1636                         ql_log(ql_log_warn, vha, 0x00c2,
1637                             "Unable to initialize EFT (%d).\n", rval);
1638                         dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1639                             tc_dma);
1640                         goto cont_alloc;
1641                 }
1642                 ql_dbg(ql_dbg_init, vha, 0x00c3,
1643                     "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
1644
1645                 eft_size = EFT_SIZE;
1646                 ha->eft_dma = tc_dma;
1647                 ha->eft = tc;
1648         }
1649
1650 cont_alloc:
1651         if (IS_QLA27XX(ha)) {
1652                 if (!ha->fw_dump_template) {
1653                         ql_log(ql_log_warn, vha, 0x00ba,
1654                             "Failed missing fwdump template\n");
1655                         return;
1656                 }
1657                 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
1658                 ql_dbg(ql_dbg_init, vha, 0x00fa,
1659                     "-> allocating fwdump (%x bytes)...\n", dump_size);
1660                 goto allocate;
1661         }
1662
1663         req_q_size = req->length * sizeof(request_t);
1664         rsp_q_size = rsp->length * sizeof(response_t);
1665         dump_size = offsetof(struct qla2xxx_fw_dump, isp);
1666         dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
1667         ha->chain_offset = dump_size;
1668         dump_size += mq_size + fce_size;
1669
1670 allocate:
1671         ha->fw_dump = vmalloc(dump_size);
1672         if (!ha->fw_dump) {
1673                 ql_log(ql_log_warn, vha, 0x00c4,
1674                     "Unable to allocate (%d KB) for firmware dump.\n",
1675                     dump_size / 1024);
1676
1677                 if (ha->fce) {
1678                         dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1679                             ha->fce_dma);
1680                         ha->fce = NULL;
1681                         ha->fce_dma = 0;
1682                 }
1683
1684                 if (ha->eft) {
1685                         dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1686                             ha->eft_dma);
1687                         ha->eft = NULL;
1688                         ha->eft_dma = 0;
1689                 }
1690                 return;
1691         }
1692         ha->fw_dump_len = dump_size;
1693         ql_dbg(ql_dbg_init, vha, 0x00c5,
1694             "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
1695
1696         if (IS_QLA27XX(ha))
1697                 return;
1698
1699         ha->fw_dump->signature[0] = 'Q';
1700         ha->fw_dump->signature[1] = 'L';
1701         ha->fw_dump->signature[2] = 'G';
1702         ha->fw_dump->signature[3] = 'C';
1703         ha->fw_dump->version = htonl(1);
1704
1705         ha->fw_dump->fixed_size = htonl(fixed_size);
1706         ha->fw_dump->mem_size = htonl(mem_size);
1707         ha->fw_dump->req_q_size = htonl(req_q_size);
1708         ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1709
1710         ha->fw_dump->eft_size = htonl(eft_size);
1711         ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1712         ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1713
1714         ha->fw_dump->header_size =
1715             htonl(offsetof(struct qla2xxx_fw_dump, isp));
1716 }
1717
1718 static int
1719 qla81xx_mpi_sync(scsi_qla_host_t *vha)
1720 {
1721 #define MPS_MASK        0xe0
1722         int rval;
1723         uint16_t dc;
1724         uint32_t dw;
1725
1726         if (!IS_QLA81XX(vha->hw))
1727                 return QLA_SUCCESS;
1728
1729         rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1730         if (rval != QLA_SUCCESS) {
1731                 ql_log(ql_log_warn, vha, 0x0105,
1732                     "Unable to acquire semaphore.\n");
1733                 goto done;
1734         }
1735
1736         pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1737         rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1738         if (rval != QLA_SUCCESS) {
1739                 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
1740                 goto done_release;
1741         }
1742
1743         dc &= MPS_MASK;
1744         if (dc == (dw & MPS_MASK))
1745                 goto done_release;
1746
1747         dw &= ~MPS_MASK;
1748         dw |= dc;
1749         rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1750         if (rval != QLA_SUCCESS) {
1751                 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
1752         }
1753
1754 done_release:
1755         rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1756         if (rval != QLA_SUCCESS) {
1757                 ql_log(ql_log_warn, vha, 0x006d,
1758                     "Unable to release semaphore.\n");
1759         }
1760
1761 done:
1762         return rval;
1763 }
1764
1765 int
1766 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1767 {
1768         /* Don't try to reallocate the array */
1769         if (req->outstanding_cmds)
1770                 return QLA_SUCCESS;
1771
1772         if (!IS_FWI2_CAPABLE(ha))
1773                 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1774         else {
1775                 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
1776                         req->num_outstanding_cmds = ha->cur_fw_xcb_count;
1777                 else
1778                         req->num_outstanding_cmds = ha->cur_fw_iocb_count;
1779         }
1780
1781         req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1782             req->num_outstanding_cmds, GFP_KERNEL);
1783
1784         if (!req->outstanding_cmds) {
1785                 /*
1786                  * Try to allocate a minimal size just so we can get through
1787                  * initialization.
1788                  */
1789                 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1790                 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1791                     req->num_outstanding_cmds, GFP_KERNEL);
1792
1793                 if (!req->outstanding_cmds) {
1794                         ql_log(ql_log_fatal, NULL, 0x0126,
1795                             "Failed to allocate memory for "
1796                             "outstanding_cmds for req_que %p.\n", req);
1797                         req->num_outstanding_cmds = 0;
1798                         return QLA_FUNCTION_FAILED;
1799                 }
1800         }
1801
1802         return QLA_SUCCESS;
1803 }
1804
1805 /**
1806  * qla2x00_setup_chip() - Load and start RISC firmware.
1807  * @ha: HA context
1808  *
1809  * Returns 0 on success.
1810  */
1811 static int
1812 qla2x00_setup_chip(scsi_qla_host_t *vha)
1813 {
1814         int rval;
1815         uint32_t srisc_address = 0;
1816         struct qla_hw_data *ha = vha->hw;
1817         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1818         unsigned long flags;
1819         uint16_t fw_major_version;
1820
1821         if (IS_P3P_TYPE(ha)) {
1822                 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1823                 if (rval == QLA_SUCCESS) {
1824                         qla2x00_stop_firmware(vha);
1825                         goto enable_82xx_npiv;
1826                 } else
1827                         goto failed;
1828         }
1829
1830         if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1831                 /* Disable SRAM, Instruction RAM and GP RAM parity.  */
1832                 spin_lock_irqsave(&ha->hardware_lock, flags);
1833                 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1834                 RD_REG_WORD(&reg->hccr);
1835                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1836         }
1837
1838         qla81xx_mpi_sync(vha);
1839
1840         /* Load firmware sequences */
1841         rval = ha->isp_ops->load_risc(vha, &srisc_address);
1842         if (rval == QLA_SUCCESS) {
1843                 ql_dbg(ql_dbg_init, vha, 0x00c9,
1844                     "Verifying Checksum of loaded RISC code.\n");
1845
1846                 rval = qla2x00_verify_checksum(vha, srisc_address);
1847                 if (rval == QLA_SUCCESS) {
1848                         /* Start firmware execution. */
1849                         ql_dbg(ql_dbg_init, vha, 0x00ca,
1850                             "Starting firmware.\n");
1851
1852                         if (ql2xexlogins)
1853                                 ha->flags.exlogins_enabled = 1;
1854
1855                         if (ql2xexchoffld)
1856                                 ha->flags.exchoffld_enabled = 1;
1857
1858                         rval = qla2x00_execute_fw(vha, srisc_address);
1859                         /* Retrieve firmware information. */
1860                         if (rval == QLA_SUCCESS) {
1861                                 rval = qla2x00_set_exlogins_buffer(vha);
1862                                 if (rval != QLA_SUCCESS)
1863                                         goto failed;
1864
1865                                 rval = qla2x00_set_exchoffld_buffer(vha);
1866                                 if (rval != QLA_SUCCESS)
1867                                         goto failed;
1868
1869 enable_82xx_npiv:
1870                                 fw_major_version = ha->fw_major_version;
1871                                 if (IS_P3P_TYPE(ha))
1872                                         qla82xx_check_md_needed(vha);
1873                                 else
1874                                         rval = qla2x00_get_fw_version(vha);
1875                                 if (rval != QLA_SUCCESS)
1876                                         goto failed;
1877                                 ha->flags.npiv_supported = 0;
1878                                 if (IS_QLA2XXX_MIDTYPE(ha) &&
1879                                          (ha->fw_attributes & BIT_2)) {
1880                                         ha->flags.npiv_supported = 1;
1881                                         if ((!ha->max_npiv_vports) ||
1882                                             ((ha->max_npiv_vports + 1) %
1883                                             MIN_MULTI_ID_FABRIC))
1884                                                 ha->max_npiv_vports =
1885                                                     MIN_MULTI_ID_FABRIC - 1;
1886                                 }
1887                                 qla2x00_get_resource_cnts(vha);
1888
1889                                 /*
1890                                  * Allocate the array of outstanding commands
1891                                  * now that we know the firmware resources.
1892                                  */
1893                                 rval = qla2x00_alloc_outstanding_cmds(ha,
1894                                     vha->req);
1895                                 if (rval != QLA_SUCCESS)
1896                                         goto failed;
1897
1898                                 if (!fw_major_version && ql2xallocfwdump
1899                                     && !(IS_P3P_TYPE(ha)))
1900                                         qla2x00_alloc_fw_dump(vha);
1901                         } else {
1902                                 goto failed;
1903                         }
1904                 } else {
1905                         ql_log(ql_log_fatal, vha, 0x00cd,
1906                             "ISP Firmware failed checksum.\n");
1907                         goto failed;
1908                 }
1909         } else
1910                 goto failed;
1911
1912         if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1913                 /* Enable proper parity. */
1914                 spin_lock_irqsave(&ha->hardware_lock, flags);
1915                 if (IS_QLA2300(ha))
1916                         /* SRAM parity */
1917                         WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1918                 else
1919                         /* SRAM, Instruction RAM and GP RAM parity */
1920                         WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1921                 RD_REG_WORD(&reg->hccr);
1922                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1923         }
1924
1925         if (IS_QLA27XX(ha))
1926                 ha->flags.fac_supported = 1;
1927         else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1928                 uint32_t size;
1929
1930                 rval = qla81xx_fac_get_sector_size(vha, &size);
1931                 if (rval == QLA_SUCCESS) {
1932                         ha->flags.fac_supported = 1;
1933                         ha->fdt_block_size = size << 2;
1934                 } else {
1935                         ql_log(ql_log_warn, vha, 0x00ce,
1936                             "Unsupported FAC firmware (%d.%02d.%02d).\n",
1937                             ha->fw_major_version, ha->fw_minor_version,
1938                             ha->fw_subminor_version);
1939
1940                         if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
1941                                 ha->flags.fac_supported = 0;
1942                                 rval = QLA_SUCCESS;
1943                         }
1944                 }
1945         }
1946 failed:
1947         if (rval) {
1948                 ql_log(ql_log_fatal, vha, 0x00cf,
1949                     "Setup chip ****FAILED****.\n");
1950         }
1951
1952         return (rval);
1953 }
1954
1955 /**
1956  * qla2x00_init_response_q_entries() - Initializes response queue entries.
1957  * @ha: HA context
1958  *
1959  * Beginning of request ring has initialization control block already built
1960  * by nvram config routine.
1961  *
1962  * Returns 0 on success.
1963  */
1964 void
1965 qla2x00_init_response_q_entries(struct rsp_que *rsp)
1966 {
1967         uint16_t cnt;
1968         response_t *pkt;
1969
1970         rsp->ring_ptr = rsp->ring;
1971         rsp->ring_index    = 0;
1972         rsp->status_srb = NULL;
1973         pkt = rsp->ring_ptr;
1974         for (cnt = 0; cnt < rsp->length; cnt++) {
1975                 pkt->signature = RESPONSE_PROCESSED;
1976                 pkt++;
1977         }
1978 }
1979
1980 /**
1981  * qla2x00_update_fw_options() - Read and process firmware options.
1982  * @ha: HA context
1983  *
1984  * Returns 0 on success.
1985  */
1986 void
1987 qla2x00_update_fw_options(scsi_qla_host_t *vha)
1988 {
1989         uint16_t swing, emphasis, tx_sens, rx_sens;
1990         struct qla_hw_data *ha = vha->hw;
1991
1992         memset(ha->fw_options, 0, sizeof(ha->fw_options));
1993         qla2x00_get_fw_options(vha, ha->fw_options);
1994
1995         if (IS_QLA2100(ha) || IS_QLA2200(ha))
1996                 return;
1997
1998         /* Serial Link options. */
1999         ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
2000             "Serial link options.\n");
2001         ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
2002             (uint8_t *)&ha->fw_seriallink_options,
2003             sizeof(ha->fw_seriallink_options));
2004
2005         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
2006         if (ha->fw_seriallink_options[3] & BIT_2) {
2007                 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
2008
2009                 /*  1G settings */
2010                 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
2011                 emphasis = (ha->fw_seriallink_options[2] &
2012                     (BIT_4 | BIT_3)) >> 3;
2013                 tx_sens = ha->fw_seriallink_options[0] &
2014                     (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2015                 rx_sens = (ha->fw_seriallink_options[0] &
2016                     (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2017                 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
2018                 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2019                         if (rx_sens == 0x0)
2020                                 rx_sens = 0x3;
2021                         ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
2022                 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2023                         ha->fw_options[10] |= BIT_5 |
2024                             ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2025                             (tx_sens & (BIT_1 | BIT_0));
2026
2027                 /*  2G settings */
2028                 swing = (ha->fw_seriallink_options[2] &
2029                     (BIT_7 | BIT_6 | BIT_5)) >> 5;
2030                 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
2031                 tx_sens = ha->fw_seriallink_options[1] &
2032                     (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2033                 rx_sens = (ha->fw_seriallink_options[1] &
2034                     (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
2035                 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
2036                 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
2037                         if (rx_sens == 0x0)
2038                                 rx_sens = 0x3;
2039                         ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
2040                 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
2041                         ha->fw_options[11] |= BIT_5 |
2042                             ((rx_sens & (BIT_1 | BIT_0)) << 2) |
2043                             (tx_sens & (BIT_1 | BIT_0));
2044         }
2045
2046         /* FCP2 options. */
2047         /*  Return command IOCBs without waiting for an ABTS to complete. */
2048         ha->fw_options[3] |= BIT_13;
2049
2050         /* LED scheme. */
2051         if (ha->flags.enable_led_scheme)
2052                 ha->fw_options[2] |= BIT_12;
2053
2054         /* Detect ISP6312. */
2055         if (IS_QLA6312(ha))
2056                 ha->fw_options[2] |= BIT_13;
2057
2058         /* Set Retry FLOGI in case of P2P connection */
2059         if (ha->operating_mode == P2P) {
2060                 ha->fw_options[2] |= BIT_3;
2061                 ql_dbg(ql_dbg_disc, vha, 0x2100,
2062                     "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2063                         __func__, ha->fw_options[2]);
2064         }
2065
2066         /* Update firmware options. */
2067         qla2x00_set_fw_options(vha, ha->fw_options);
2068 }
2069
2070 void
2071 qla24xx_update_fw_options(scsi_qla_host_t *vha)
2072 {
2073         int rval;
2074         struct qla_hw_data *ha = vha->hw;
2075
2076         if (IS_P3P_TYPE(ha))
2077                 return;
2078
2079         /*  Hold status IOCBs until ABTS response received. */
2080         if (ql2xfwholdabts)
2081                 ha->fw_options[3] |= BIT_12;
2082
2083         /* Set Retry FLOGI in case of P2P connection */
2084         if (ha->operating_mode == P2P) {
2085                 ha->fw_options[2] |= BIT_3;
2086                 ql_dbg(ql_dbg_disc, vha, 0x2101,
2087                     "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
2088                         __func__, ha->fw_options[2]);
2089         }
2090
2091         /* Update Serial Link options. */
2092         if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
2093                 return;
2094
2095         rval = qla2x00_set_serdes_params(vha,
2096             le16_to_cpu(ha->fw_seriallink_options24[1]),
2097             le16_to_cpu(ha->fw_seriallink_options24[2]),
2098             le16_to_cpu(ha->fw_seriallink_options24[3]));
2099         if (rval != QLA_SUCCESS) {
2100                 ql_log(ql_log_warn, vha, 0x0104,
2101                     "Unable to update Serial Link options (%x).\n", rval);
2102         }
2103 }
2104
2105 void
2106 qla2x00_config_rings(struct scsi_qla_host *vha)
2107 {
2108         struct qla_hw_data *ha = vha->hw;
2109         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2110         struct req_que *req = ha->req_q_map[0];
2111         struct rsp_que *rsp = ha->rsp_q_map[0];
2112
2113         /* Setup ring parameters in initialization control block. */
2114         ha->init_cb->request_q_outpointer = cpu_to_le16(0);
2115         ha->init_cb->response_q_inpointer = cpu_to_le16(0);
2116         ha->init_cb->request_q_length = cpu_to_le16(req->length);
2117         ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
2118         ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2119         ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2120         ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2121         ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
2122
2123         WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
2124         WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
2125         WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
2126         WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
2127         RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg));            /* PCI Posting. */
2128 }
2129
2130 void
2131 qla24xx_config_rings(struct scsi_qla_host *vha)
2132 {
2133         struct qla_hw_data *ha = vha->hw;
2134         device_reg_t *reg = ISP_QUE_REG(ha, 0);
2135         struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
2136         struct qla_msix_entry *msix;
2137         struct init_cb_24xx *icb;
2138         uint16_t rid = 0;
2139         struct req_que *req = ha->req_q_map[0];
2140         struct rsp_que *rsp = ha->rsp_q_map[0];
2141
2142         /* Setup ring parameters in initialization control block. */
2143         icb = (struct init_cb_24xx *)ha->init_cb;
2144         icb->request_q_outpointer = cpu_to_le16(0);
2145         icb->response_q_inpointer = cpu_to_le16(0);
2146         icb->request_q_length = cpu_to_le16(req->length);
2147         icb->response_q_length = cpu_to_le16(rsp->length);
2148         icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
2149         icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
2150         icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
2151         icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
2152
2153         /* Setup ATIO queue dma pointers for target mode */
2154         icb->atio_q_inpointer = cpu_to_le16(0);
2155         icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
2156         icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
2157         icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
2158
2159         if (IS_SHADOW_REG_CAPABLE(ha))
2160                 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
2161
2162         if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2163                 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
2164                 icb->rid = cpu_to_le16(rid);
2165                 if (ha->flags.msix_enabled) {
2166                         msix = &ha->msix_entries[1];
2167                         ql_dbg(ql_dbg_init, vha, 0x00fd,
2168                             "Registering vector 0x%x for base que.\n",
2169                             msix->entry);
2170                         icb->msix = cpu_to_le16(msix->entry);
2171                 }
2172                 /* Use alternate PCI bus number */
2173                 if (MSB(rid))
2174                         icb->firmware_options_2 |= cpu_to_le32(BIT_19);
2175                 /* Use alternate PCI devfn */
2176                 if (LSB(rid))
2177                         icb->firmware_options_2 |= cpu_to_le32(BIT_18);
2178
2179                 /* Use Disable MSIX Handshake mode for capable adapters */
2180                 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
2181                     (ha->flags.msix_enabled)) {
2182                         icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
2183                         ha->flags.disable_msix_handshake = 1;
2184                         ql_dbg(ql_dbg_init, vha, 0x00fe,
2185                             "MSIX Handshake Disable Mode turned on.\n");
2186                 } else {
2187                         icb->firmware_options_2 |= cpu_to_le32(BIT_22);
2188                 }
2189                 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
2190
2191                 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
2192                 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
2193                 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
2194                 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
2195         } else {
2196                 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
2197                 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
2198                 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
2199                 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
2200         }
2201         qlt_24xx_config_rings(vha);
2202
2203         /* PCI posting */
2204         RD_REG_DWORD(&ioreg->hccr);
2205 }
2206
2207 /**
2208  * qla2x00_init_rings() - Initializes firmware.
2209  * @ha: HA context
2210  *
2211  * Beginning of request ring has initialization control block already built
2212  * by nvram config routine.
2213  *
2214  * Returns 0 on success.
2215  */
2216 int
2217 qla2x00_init_rings(scsi_qla_host_t *vha)
2218 {
2219         int     rval;
2220         unsigned long flags = 0;
2221         int cnt, que;
2222         struct qla_hw_data *ha = vha->hw;
2223         struct req_que *req;
2224         struct rsp_que *rsp;
2225         struct mid_init_cb_24xx *mid_init_cb =
2226             (struct mid_init_cb_24xx *) ha->init_cb;
2227
2228         spin_lock_irqsave(&ha->hardware_lock, flags);
2229
2230         /* Clear outstanding commands array. */
2231         for (que = 0; que < ha->max_req_queues; que++) {
2232                 req = ha->req_q_map[que];
2233                 if (!req || !test_bit(que, ha->req_qid_map))
2234                         continue;
2235                 req->out_ptr = (void *)(req->ring + req->length);
2236                 *req->out_ptr = 0;
2237                 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
2238                         req->outstanding_cmds[cnt] = NULL;
2239
2240                 req->current_outstanding_cmd = 1;
2241
2242                 /* Initialize firmware. */
2243                 req->ring_ptr  = req->ring;
2244                 req->ring_index    = 0;
2245                 req->cnt      = req->length;
2246         }
2247
2248         for (que = 0; que < ha->max_rsp_queues; que++) {
2249                 rsp = ha->rsp_q_map[que];
2250                 if (!rsp || !test_bit(que, ha->rsp_qid_map))
2251                         continue;
2252                 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
2253                 *rsp->in_ptr = 0;
2254                 /* Initialize response queue entries */
2255                 if (IS_QLAFX00(ha))
2256                         qlafx00_init_response_q_entries(rsp);
2257                 else
2258                         qla2x00_init_response_q_entries(rsp);
2259         }
2260
2261         ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2262         ha->tgt.atio_ring_index = 0;
2263         /* Initialize ATIO queue entries */
2264         qlt_init_atio_q_entries(vha);
2265
2266         ha->isp_ops->config_rings(vha);
2267
2268         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2269
2270         ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2271
2272         if (IS_QLAFX00(ha)) {
2273                 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2274                 goto next_check;
2275         }
2276
2277         /* Update any ISP specific firmware options before initialization. */
2278         ha->isp_ops->update_fw_options(vha);
2279
2280         if (ha->flags.npiv_supported) {
2281                 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
2282                         ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
2283                 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
2284         }
2285
2286         if (IS_FWI2_CAPABLE(ha)) {
2287                 mid_init_cb->options = cpu_to_le16(BIT_1);
2288                 mid_init_cb->init_cb.execution_throttle =
2289                     cpu_to_le16(ha->cur_fw_xcb_count);
2290                 ha->flags.dport_enabled =
2291                     (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
2292                 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
2293                     (ha->flags.dport_enabled) ? "enabled" : "disabled");
2294                 /* FA-WWPN Status */
2295                 ha->flags.fawwpn_enabled =
2296                     (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
2297                 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n",
2298                     (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
2299         }
2300
2301         rval = qla2x00_init_firmware(vha, ha->init_cb_size);
2302 next_check:
2303         if (rval) {
2304                 ql_log(ql_log_fatal, vha, 0x00d2,
2305                     "Init Firmware **** FAILED ****.\n");
2306         } else {
2307                 ql_dbg(ql_dbg_init, vha, 0x00d3,
2308                     "Init Firmware -- success.\n");
2309         }
2310
2311         return (rval);
2312 }
2313
2314 /**
2315  * qla2x00_fw_ready() - Waits for firmware ready.
2316  * @ha: HA context
2317  *
2318  * Returns 0 on success.
2319  */
2320 static int
2321 qla2x00_fw_ready(scsi_qla_host_t *vha)
2322 {
2323         int             rval;
2324         unsigned long   wtime, mtime, cs84xx_time;
2325         uint16_t        min_wait;       /* Minimum wait time if loop is down */
2326         uint16_t        wait_time;      /* Wait time if loop is coming ready */
2327         uint16_t        state[6];
2328         struct qla_hw_data *ha = vha->hw;
2329
2330         if (IS_QLAFX00(vha->hw))
2331                 return qlafx00_fw_ready(vha);
2332
2333         rval = QLA_SUCCESS;
2334
2335         /* Time to wait for loop down */
2336         if (IS_P3P_TYPE(ha))
2337                 min_wait = 30;
2338         else
2339                 min_wait = 20;
2340
2341         /*
2342          * Firmware should take at most one RATOV to login, plus 5 seconds for
2343          * our own processing.
2344          */
2345         if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2346                 wait_time = min_wait;
2347         }
2348
2349         /* Min wait time if loop down */
2350         mtime = jiffies + (min_wait * HZ);
2351
2352         /* wait time before firmware ready */
2353         wtime = jiffies + (wait_time * HZ);
2354
2355         /* Wait for ISP to finish LIP */
2356         if (!vha->flags.init_done)
2357                 ql_log(ql_log_info, vha, 0x801e,
2358                     "Waiting for LIP to complete.\n");
2359
2360         do {
2361                 memset(state, -1, sizeof(state));
2362                 rval = qla2x00_get_firmware_state(vha, state);
2363                 if (rval == QLA_SUCCESS) {
2364                         if (state[0] < FSTATE_LOSS_OF_SYNC) {
2365                                 vha->device_flags &= ~DFLG_NO_CABLE;
2366                         }
2367                         if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
2368                                 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2369                                     "fw_state=%x 84xx=%x.\n", state[0],
2370                                     state[2]);
2371                                 if ((state[2] & FSTATE_LOGGED_IN) &&
2372                                      (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
2373                                         ql_dbg(ql_dbg_taskm, vha, 0x8028,
2374                                             "Sending verify iocb.\n");
2375
2376                                         cs84xx_time = jiffies;
2377                                         rval = qla84xx_init_chip(vha);
2378                                         if (rval != QLA_SUCCESS) {
2379                                                 ql_log(ql_log_warn,
2380                                                     vha, 0x8007,
2381                                                     "Init chip failed.\n");
2382                                                 break;
2383                                         }
2384
2385                                         /* Add time taken to initialize. */
2386                                         cs84xx_time = jiffies - cs84xx_time;
2387                                         wtime += cs84xx_time;
2388                                         mtime += cs84xx_time;
2389                                         ql_dbg(ql_dbg_taskm, vha, 0x8008,
2390                                             "Increasing wait time by %ld. "
2391                                             "New time %ld.\n", cs84xx_time,
2392                                             wtime);
2393                                 }
2394                         } else if (state[0] == FSTATE_READY) {
2395                                 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2396                                     "F/W Ready - OK.\n");
2397
2398                                 qla2x00_get_retry_cnt(vha, &ha->retry_count,
2399                                     &ha->login_timeout, &ha->r_a_tov);
2400
2401                                 rval = QLA_SUCCESS;
2402                                 break;
2403                         }
2404
2405                         rval = QLA_FUNCTION_FAILED;
2406
2407                         if (atomic_read(&vha->loop_down_timer) &&
2408                             state[0] != FSTATE_READY) {
2409                                 /* Loop down. Timeout on min_wait for states
2410                                  * other than Wait for Login.
2411                                  */
2412                                 if (time_after_eq(jiffies, mtime)) {
2413                                         ql_log(ql_log_info, vha, 0x8038,
2414                                             "Cable is unplugged...\n");
2415
2416                                         vha->device_flags |= DFLG_NO_CABLE;
2417                                         break;
2418                                 }
2419                         }
2420                 } else {
2421                         /* Mailbox cmd failed. Timeout on min_wait. */
2422                         if (time_after_eq(jiffies, mtime) ||
2423                                 ha->flags.isp82xx_fw_hung)
2424                                 break;
2425                 }
2426
2427                 if (time_after_eq(jiffies, wtime))
2428                         break;
2429
2430                 /* Delay for a while */
2431                 msleep(500);
2432         } while (1);
2433
2434         ql_dbg(ql_dbg_taskm, vha, 0x803a,
2435             "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
2436             state[1], state[2], state[3], state[4], state[5], jiffies);
2437
2438         if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
2439                 ql_log(ql_log_warn, vha, 0x803b,
2440                     "Firmware ready **** FAILED ****.\n");
2441         }
2442
2443         return (rval);
2444 }
2445
2446 /*
2447 *  qla2x00_configure_hba
2448 *      Setup adapter context.
2449 *
2450 * Input:
2451 *      ha = adapter state pointer.
2452 *
2453 * Returns:
2454 *      0 = success
2455 *
2456 * Context:
2457 *      Kernel context.
2458 */
2459 static int
2460 qla2x00_configure_hba(scsi_qla_host_t *vha)
2461 {
2462         int       rval;
2463         uint16_t      loop_id;
2464         uint16_t      topo;
2465         uint16_t      sw_cap;
2466         uint8_t       al_pa;
2467         uint8_t       area;
2468         uint8_t       domain;
2469         char            connect_type[22];
2470         struct qla_hw_data *ha = vha->hw;
2471         unsigned long flags;
2472         scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2473
2474         /* Get host addresses. */
2475         rval = qla2x00_get_adapter_id(vha,
2476             &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
2477         if (rval != QLA_SUCCESS) {
2478                 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
2479                     IS_CNA_CAPABLE(ha) ||
2480                     (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
2481                         ql_dbg(ql_dbg_disc, vha, 0x2008,
2482                             "Loop is in a transition state.\n");
2483                 } else {
2484                         ql_log(ql_log_warn, vha, 0x2009,
2485                             "Unable to get host loop ID.\n");
2486                         if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2487                             (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2488                                 ql_log(ql_log_warn, vha, 0x1151,
2489                                     "Doing link init.\n");
2490                                 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2491                                         return rval;
2492                         }
2493                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2494                 }
2495                 return (rval);
2496         }
2497
2498         if (topo == 4) {
2499                 ql_log(ql_log_info, vha, 0x200a,
2500                     "Cannot get topology - retrying.\n");
2501                 return (QLA_FUNCTION_FAILED);
2502         }
2503
2504         vha->loop_id = loop_id;
2505
2506         /* initialize */
2507         ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2508         ha->operating_mode = LOOP;
2509         ha->switch_cap = 0;
2510
2511         switch (topo) {
2512         case 0:
2513                 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
2514                 ha->current_topology = ISP_CFG_NL;
2515                 strcpy(connect_type, "(Loop)");
2516                 break;
2517
2518         case 1:
2519                 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2520                 ha->switch_cap = sw_cap;
2521                 ha->current_topology = ISP_CFG_FL;
2522                 strcpy(connect_type, "(FL_Port)");
2523                 break;
2524
2525         case 2:
2526                 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
2527                 ha->operating_mode = P2P;
2528                 ha->current_topology = ISP_CFG_N;
2529                 strcpy(connect_type, "(N_Port-to-N_Port)");
2530                 break;
2531
2532         case 3:
2533                 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2534                 ha->switch_cap = sw_cap;
2535                 ha->operating_mode = P2P;
2536                 ha->current_topology = ISP_CFG_F;
2537                 strcpy(connect_type, "(F_Port)");
2538                 break;
2539
2540         default:
2541                 ql_dbg(ql_dbg_disc, vha, 0x200f,
2542                     "HBA in unknown topology %x, using NL.\n", topo);
2543                 ha->current_topology = ISP_CFG_NL;
2544                 strcpy(connect_type, "(Loop)");
2545                 break;
2546         }
2547
2548         /* Save Host port and loop ID. */
2549         /* byte order - Big Endian */
2550         vha->d_id.b.domain = domain;
2551         vha->d_id.b.area = area;
2552         vha->d_id.b.al_pa = al_pa;
2553
2554         spin_lock_irqsave(&ha->vport_slock, flags);
2555         qlt_update_vp_map(vha, SET_AL_PA);
2556         spin_unlock_irqrestore(&ha->vport_slock, flags);
2557
2558         if (!vha->flags.init_done)
2559                 ql_log(ql_log_info, vha, 0x2010,
2560                     "Topology - %s, Host Loop address 0x%x.\n",
2561                     connect_type, vha->loop_id);
2562
2563         return(rval);
2564 }
2565
2566 inline void
2567 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2568         char *def)
2569 {
2570         char *st, *en;
2571         uint16_t index;
2572         struct qla_hw_data *ha = vha->hw;
2573         int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
2574             !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
2575
2576         if (memcmp(model, BINZERO, len) != 0) {
2577                 strncpy(ha->model_number, model, len);
2578                 st = en = ha->model_number;
2579                 en += len - 1;
2580                 while (en > st) {
2581                         if (*en != 0x20 && *en != 0x00)
2582                                 break;
2583                         *en-- = '\0';
2584                 }
2585
2586                 index = (ha->pdev->subsystem_device & 0xff);
2587                 if (use_tbl &&
2588                     ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2589                     index < QLA_MODEL_NAMES)
2590                         strncpy(ha->model_desc,
2591                             qla2x00_model_name[index * 2 + 1],
2592                             sizeof(ha->model_desc) - 1);
2593         } else {
2594                 index = (ha->pdev->subsystem_device & 0xff);
2595                 if (use_tbl &&
2596                     ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2597                     index < QLA_MODEL_NAMES) {
2598                         strcpy(ha->model_number,
2599                             qla2x00_model_name[index * 2]);
2600                         strncpy(ha->model_desc,
2601                             qla2x00_model_name[index * 2 + 1],
2602                             sizeof(ha->model_desc) - 1);
2603                 } else {
2604                         strcpy(ha->model_number, def);
2605                 }
2606         }
2607         if (IS_FWI2_CAPABLE(ha))
2608                 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
2609                     sizeof(ha->model_desc));
2610 }
2611
2612 /* On sparc systems, obtain port and node WWN from firmware
2613  * properties.
2614  */
2615 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
2616 {
2617 #ifdef CONFIG_SPARC
2618         struct qla_hw_data *ha = vha->hw;
2619         struct pci_dev *pdev = ha->pdev;
2620         struct device_node *dp = pci_device_to_OF_node(pdev);
2621         const u8 *val;
2622         int len;
2623
2624         val = of_get_property(dp, "port-wwn", &len);
2625         if (val && len >= WWN_SIZE)
2626                 memcpy(nv->port_name, val, WWN_SIZE);
2627
2628         val = of_get_property(dp, "node-wwn", &len);
2629         if (val && len >= WWN_SIZE)
2630                 memcpy(nv->node_name, val, WWN_SIZE);
2631 #endif
2632 }
2633
2634 /*
2635 * NVRAM configuration for ISP 2xxx
2636 *
2637 * Input:
2638 *      ha                = adapter block pointer.
2639 *
2640 * Output:
2641 *      initialization control block in response_ring
2642 *      host adapters parameters in host adapter block
2643 *
2644 * Returns:
2645 *      0 = success.
2646 */
2647 int
2648 qla2x00_nvram_config(scsi_qla_host_t *vha)
2649 {
2650         int             rval;
2651         uint8_t         chksum = 0;
2652         uint16_t        cnt;
2653         uint8_t         *dptr1, *dptr2;
2654         struct qla_hw_data *ha = vha->hw;
2655         init_cb_t       *icb = ha->init_cb;
2656         nvram_t         *nv = ha->nvram;
2657         uint8_t         *ptr = ha->nvram;
2658         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2659
2660         rval = QLA_SUCCESS;
2661
2662         /* Determine NVRAM starting address. */
2663         ha->nvram_size = sizeof(nvram_t);
2664         ha->nvram_base = 0;
2665         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2666                 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2667                         ha->nvram_base = 0x80;
2668
2669         /* Get NVRAM data and calculate checksum. */
2670         ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
2671         for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2672                 chksum += *ptr++;
2673
2674         ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2675             "Contents of NVRAM.\n");
2676         ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2677             (uint8_t *)nv, ha->nvram_size);
2678
2679         /* Bad NVRAM data, set defaults parameters. */
2680         if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2681             nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2682                 /* Reset NVRAM data. */
2683                 ql_log(ql_log_warn, vha, 0x0064,
2684                     "Inconsistent NVRAM "
2685                     "detected: checksum=0x%x id=%c version=0x%x.\n",
2686                     chksum, nv->id[0], nv->nvram_version);
2687                 ql_log(ql_log_warn, vha, 0x0065,
2688                     "Falling back to "
2689                     "functioning (yet invalid -- WWPN) defaults.\n");
2690
2691                 /*
2692                  * Set default initialization control block.
2693                  */
2694                 memset(nv, 0, ha->nvram_size);
2695                 nv->parameter_block_version = ICB_VERSION;
2696
2697                 if (IS_QLA23XX(ha)) {
2698                         nv->firmware_options[0] = BIT_2 | BIT_1;
2699                         nv->firmware_options[1] = BIT_7 | BIT_5;
2700                         nv->add_firmware_options[0] = BIT_5;
2701                         nv->add_firmware_options[1] = BIT_5 | BIT_4;
2702                         nv->frame_payload_size = 2048;
2703                         nv->special_options[1] = BIT_7;
2704                 } else if (IS_QLA2200(ha)) {
2705                         nv->firmware_options[0] = BIT_2 | BIT_1;
2706                         nv->firmware_options[1] = BIT_7 | BIT_5;
2707                         nv->add_firmware_options[0] = BIT_5;
2708                         nv->add_firmware_options[1] = BIT_5 | BIT_4;
2709                         nv->frame_payload_size = 1024;
2710                 } else if (IS_QLA2100(ha)) {
2711                         nv->firmware_options[0] = BIT_3 | BIT_1;
2712                         nv->firmware_options[1] = BIT_5;
2713                         nv->frame_payload_size = 1024;
2714                 }
2715
2716                 nv->max_iocb_allocation = cpu_to_le16(256);
2717                 nv->execution_throttle = cpu_to_le16(16);
2718                 nv->retry_count = 8;
2719                 nv->retry_delay = 1;
2720
2721                 nv->port_name[0] = 33;
2722                 nv->port_name[3] = 224;
2723                 nv->port_name[4] = 139;
2724
2725                 qla2xxx_nvram_wwn_from_ofw(vha, nv);
2726
2727                 nv->login_timeout = 4;
2728
2729                 /*
2730                  * Set default host adapter parameters
2731                  */
2732                 nv->host_p[1] = BIT_2;
2733                 nv->reset_delay = 5;
2734                 nv->port_down_retry_count = 8;
2735                 nv->max_luns_per_target = cpu_to_le16(8);
2736                 nv->link_down_timeout = 60;
2737
2738                 rval = 1;
2739         }
2740
2741 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2742         /*
2743          * The SN2 does not provide BIOS emulation which means you can't change
2744          * potentially bogus BIOS settings. Force the use of default settings
2745          * for link rate and frame size.  Hope that the rest of the settings
2746          * are valid.
2747          */
2748         if (ia64_platform_is("sn2")) {
2749                 nv->frame_payload_size = 2048;
2750                 if (IS_QLA23XX(ha))
2751                         nv->special_options[1] = BIT_7;
2752         }
2753 #endif
2754
2755         /* Reset Initialization control block */
2756         memset(icb, 0, ha->init_cb_size);
2757
2758         /*
2759          * Setup driver NVRAM options.
2760          */
2761         nv->firmware_options[0] |= (BIT_6 | BIT_1);
2762         nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2763         nv->firmware_options[1] |= (BIT_5 | BIT_0);
2764         nv->firmware_options[1] &= ~BIT_4;
2765
2766         if (IS_QLA23XX(ha)) {
2767                 nv->firmware_options[0] |= BIT_2;
2768                 nv->firmware_options[0] &= ~BIT_3;
2769                 nv->special_options[0] &= ~BIT_6;
2770                 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
2771
2772                 if (IS_QLA2300(ha)) {
2773                         if (ha->fb_rev == FPM_2310) {
2774                                 strcpy(ha->model_number, "QLA2310");
2775                         } else {
2776                                 strcpy(ha->model_number, "QLA2300");
2777                         }
2778                 } else {
2779                         qla2x00_set_model_info(vha, nv->model_number,
2780                             sizeof(nv->model_number), "QLA23xx");
2781                 }
2782         } else if (IS_QLA2200(ha)) {
2783                 nv->firmware_options[0] |= BIT_2;
2784                 /*
2785                  * 'Point-to-point preferred, else loop' is not a safe
2786                  * connection mode setting.
2787                  */
2788                 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2789                     (BIT_5 | BIT_4)) {
2790                         /* Force 'loop preferred, else point-to-point'. */
2791                         nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2792                         nv->add_firmware_options[0] |= BIT_5;
2793                 }
2794                 strcpy(ha->model_number, "QLA22xx");
2795         } else /*if (IS_QLA2100(ha))*/ {
2796                 strcpy(ha->model_number, "QLA2100");
2797         }
2798
2799         /*
2800          * Copy over NVRAM RISC parameter block to initialization control block.
2801          */
2802         dptr1 = (uint8_t *)icb;
2803         dptr2 = (uint8_t *)&nv->parameter_block_version;
2804         cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2805         while (cnt--)
2806                 *dptr1++ = *dptr2++;
2807
2808         /* Copy 2nd half. */
2809         dptr1 = (uint8_t *)icb->add_firmware_options;
2810         cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2811         while (cnt--)
2812                 *dptr1++ = *dptr2++;
2813
2814         /* Use alternate WWN? */
2815         if (nv->host_p[1] & BIT_7) {
2816                 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2817                 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2818         }
2819
2820         /* Prepare nodename */
2821         if ((icb->firmware_options[1] & BIT_6) == 0) {
2822                 /*
2823                  * Firmware will apply the following mask if the nodename was
2824                  * not provided.
2825                  */
2826                 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2827                 icb->node_name[0] &= 0xF0;
2828         }
2829
2830         /*
2831          * Set host adapter parameters.
2832          */
2833
2834         /*
2835          * BIT_7 in the host-parameters section allows for modification to
2836          * internal driver logging.
2837          */
2838         if (nv->host_p[0] & BIT_7)
2839                 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2840         ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2841         /* Always load RISC code on non ISP2[12]00 chips. */
2842         if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2843                 ha->flags.disable_risc_code_load = 0;
2844         ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2845         ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2846         ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
2847         ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
2848         ha->flags.disable_serdes = 0;
2849
2850         ha->operating_mode =
2851             (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2852
2853         memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2854             sizeof(ha->fw_seriallink_options));
2855
2856         /* save HBA serial number */
2857         ha->serial0 = icb->port_name[5];
2858         ha->serial1 = icb->port_name[6];
2859         ha->serial2 = icb->port_name[7];
2860         memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2861         memcpy(vha->port_name, icb->port_name, WWN_SIZE);
2862
2863         icb->execution_throttle = cpu_to_le16(0xFFFF);
2864
2865         ha->retry_count = nv->retry_count;
2866
2867         /* Set minimum login_timeout to 4 seconds. */
2868         if (nv->login_timeout != ql2xlogintimeout)
2869                 nv->login_timeout = ql2xlogintimeout;
2870         if (nv->login_timeout < 4)
2871                 nv->login_timeout = 4;
2872         ha->login_timeout = nv->login_timeout;
2873
2874         /* Set minimum RATOV to 100 tenths of a second. */
2875         ha->r_a_tov = 100;
2876
2877         ha->loop_reset_delay = nv->reset_delay;
2878
2879         /* Link Down Timeout = 0:
2880          *
2881          *      When Port Down timer expires we will start returning
2882          *      I/O's to OS with "DID_NO_CONNECT".
2883          *
2884          * Link Down Timeout != 0:
2885          *
2886          *       The driver waits for the link to come up after link down
2887          *       before returning I/Os to OS with "DID_NO_CONNECT".
2888          */
2889         if (nv->link_down_timeout == 0) {
2890                 ha->loop_down_abort_time =
2891                     (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
2892         } else {
2893                 ha->link_down_timeout =  nv->link_down_timeout;
2894                 ha->loop_down_abort_time =
2895                     (LOOP_DOWN_TIME - ha->link_down_timeout);
2896         }
2897
2898         /*
2899          * Need enough time to try and get the port back.
2900          */
2901         ha->port_down_retry_count = nv->port_down_retry_count;
2902         if (qlport_down_retry)
2903                 ha->port_down_retry_count = qlport_down_retry;
2904         /* Set login_retry_count */
2905         ha->login_retry_count  = nv->retry_count;
2906         if (ha->port_down_retry_count == nv->port_down_retry_count &&
2907             ha->port_down_retry_count > 3)
2908                 ha->login_retry_count = ha->port_down_retry_count;
2909         else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2910                 ha->login_retry_count = ha->port_down_retry_count;
2911         if (ql2xloginretrycount)
2912                 ha->login_retry_count = ql2xloginretrycount;
2913
2914         icb->lun_enables = cpu_to_le16(0);
2915         icb->command_resource_count = 0;
2916         icb->immediate_notify_resource_count = 0;
2917         icb->timeout = cpu_to_le16(0);
2918
2919         if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2920                 /* Enable RIO */
2921                 icb->firmware_options[0] &= ~BIT_3;
2922                 icb->add_firmware_options[0] &=
2923                     ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2924                 icb->add_firmware_options[0] |= BIT_2;
2925                 icb->response_accumulation_timer = 3;
2926                 icb->interrupt_delay_timer = 5;
2927
2928                 vha->flags.process_response_queue = 1;
2929         } else {
2930                 /* Enable ZIO. */
2931                 if (!vha->flags.init_done) {
2932                         ha->zio_mode = icb->add_firmware_options[0] &
2933                             (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2934                         ha->zio_timer = icb->interrupt_delay_timer ?
2935                             icb->interrupt_delay_timer: 2;
2936                 }
2937                 icb->add_firmware_options[0] &=
2938                     ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2939                 vha->flags.process_response_queue = 0;
2940                 if (ha->zio_mode != QLA_ZIO_DISABLED) {
2941                         ha->zio_mode = QLA_ZIO_MODE_6;
2942
2943                         ql_log(ql_log_info, vha, 0x0068,
2944                             "ZIO mode %d enabled; timer delay (%d us).\n",
2945                             ha->zio_mode, ha->zio_timer * 100);
2946
2947                         icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2948                         icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
2949                         vha->flags.process_response_queue = 1;
2950                 }
2951         }
2952
2953         if (rval) {
2954                 ql_log(ql_log_warn, vha, 0x0069,
2955                     "NVRAM configuration failed.\n");
2956         }
2957         return (rval);
2958 }
2959
2960 static void
2961 qla2x00_rport_del(void *data)
2962 {
2963         fc_port_t *fcport = data;
2964         struct fc_rport *rport;
2965         unsigned long flags;
2966
2967         spin_lock_irqsave(fcport->vha->host->host_lock, flags);
2968         rport = fcport->drport ? fcport->drport: fcport->rport;
2969         fcport->drport = NULL;
2970         spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2971         if (rport)
2972                 fc_remote_port_delete(rport);
2973 }
2974
2975 /**
2976  * qla2x00_alloc_fcport() - Allocate a generic fcport.
2977  * @ha: HA context
2978  * @flags: allocation flags
2979  *
2980  * Returns a pointer to the allocated fcport, or NULL, if none available.
2981  */
2982 fc_port_t *
2983 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
2984 {
2985         fc_port_t *fcport;
2986
2987         fcport = kzalloc(sizeof(fc_port_t), flags);
2988         if (!fcport)
2989                 return NULL;
2990
2991         /* Setup fcport template structure. */
2992         fcport->vha = vha;
2993         fcport->port_type = FCT_UNKNOWN;
2994         fcport->loop_id = FC_NO_LOOP_ID;
2995         qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
2996         fcport->supported_classes = FC_COS_UNSPECIFIED;
2997
2998         return fcport;
2999 }
3000
3001 /*
3002  * qla2x00_configure_loop
3003  *      Updates Fibre Channel Device Database with what is actually on loop.
3004  *
3005  * Input:
3006  *      ha                = adapter block pointer.
3007  *
3008  * Returns:
3009  *      0 = success.
3010  *      1 = error.
3011  *      2 = database was full and device was not configured.
3012  */
3013 static int
3014 qla2x00_configure_loop(scsi_qla_host_t *vha)
3015 {
3016         int  rval;
3017         unsigned long flags, save_flags;
3018         struct qla_hw_data *ha = vha->hw;
3019         rval = QLA_SUCCESS;
3020
3021         /* Get Initiator ID */
3022         if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
3023                 rval = qla2x00_configure_hba(vha);
3024                 if (rval != QLA_SUCCESS) {
3025                         ql_dbg(ql_dbg_disc, vha, 0x2013,
3026                             "Unable to configure HBA.\n");
3027                         return (rval);
3028                 }
3029         }
3030
3031         save_flags = flags = vha->dpc_flags;
3032         ql_dbg(ql_dbg_disc, vha, 0x2014,
3033             "Configure loop -- dpc flags = 0x%lx.\n", flags);
3034
3035         /*
3036          * If we have both an RSCN and PORT UPDATE pending then handle them
3037          * both at the same time.
3038          */
3039         clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3040         clear_bit(RSCN_UPDATE, &vha->dpc_flags);
3041
3042         qla2x00_get_data_rate(vha);
3043
3044         /* Determine what we need to do */
3045         if (ha->current_topology == ISP_CFG_FL &&
3046             (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3047
3048                 set_bit(RSCN_UPDATE, &flags);
3049
3050         } else if (ha->current_topology == ISP_CFG_F &&
3051             (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
3052
3053                 set_bit(RSCN_UPDATE, &flags);
3054                 clear_bit(LOCAL_LOOP_UPDATE, &flags);
3055
3056         } else if (ha->current_topology == ISP_CFG_N) {
3057                 clear_bit(RSCN_UPDATE, &flags);
3058
3059         } else if (!vha->flags.online ||
3060             (test_bit(ABORT_ISP_ACTIVE, &flags))) {
3061
3062                 set_bit(RSCN_UPDATE, &flags);
3063                 set_bit(LOCAL_LOOP_UPDATE, &flags);
3064         }
3065
3066         if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
3067                 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3068                         ql_dbg(ql_dbg_disc, vha, 0x2015,
3069                             "Loop resync needed, failing.\n");
3070                         rval = QLA_FUNCTION_FAILED;
3071                 } else
3072                         rval = qla2x00_configure_local_loop(vha);
3073         }
3074
3075         if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
3076                 if (LOOP_TRANSITION(vha)) {
3077                         ql_dbg(ql_dbg_disc, vha, 0x201e,
3078                             "Needs RSCN update and loop transition.\n");
3079                         rval = QLA_FUNCTION_FAILED;
3080                 }
3081                 else
3082                         rval = qla2x00_configure_fabric(vha);
3083         }
3084
3085         if (rval == QLA_SUCCESS) {
3086                 if (atomic_read(&vha->loop_down_timer) ||
3087                     test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
3088                         rval = QLA_FUNCTION_FAILED;
3089                 } else {
3090                         atomic_set(&vha->loop_state, LOOP_READY);
3091                         ql_dbg(ql_dbg_disc, vha, 0x2069,
3092                             "LOOP READY.\n");
3093
3094                         /*
3095                          * Process any ATIO queue entries that came in
3096                          * while we weren't online.
3097                          */
3098                         if (qla_tgt_mode_enabled(vha)) {
3099                                 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
3100                                         spin_lock_irqsave(&ha->tgt.atio_lock,
3101                                             flags);
3102                                         qlt_24xx_process_atio_queue(vha, 0);
3103                                         spin_unlock_irqrestore(
3104                                             &ha->tgt.atio_lock, flags);
3105                                 } else {
3106                                         spin_lock_irqsave(&ha->hardware_lock,
3107                                             flags);
3108                                         qlt_24xx_process_atio_queue(vha, 1);
3109                                         spin_unlock_irqrestore(
3110                                             &ha->hardware_lock, flags);