drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

   1 /*
   2  * Copyright (c) 2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include "hisi_sas.h"
  12 #define DRV_NAME "hisi_sas_v3_hw"
  13
  14 /* global registers need init*/
  15 #define DLVRY_QUEUE_ENABLE              0x0
  16 #define IOST_BASE_ADDR_LO               0x8
  17 #define IOST_BASE_ADDR_HI               0xc
  18 #define ITCT_BASE_ADDR_LO               0x10
  19 #define ITCT_BASE_ADDR_HI               0x14
  20 #define IO_BROKEN_MSG_ADDR_LO           0x18
  21 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  22 #define PHY_CONTEXT                     0x20
  23 #define PHY_STATE                       0x24
  24 #define PHY_PORT_NUM_MA                 0x28
  25 #define PHY_CONN_RATE                   0x30
  26 #define ITCT_CLR                        0x44
  27 #define ITCT_CLR_EN_OFF                 16
  28 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  29 #define ITCT_DEV_OFF                    0
  30 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  31 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  32 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  33 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  34 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  35 #define CFG_MAX_TAG                     0x68
  36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  37 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  38 #define HGC_GET_ITV_TIME                0x90
  39 #define DEVICE_MSG_WORK_MODE            0x94
  40 #define OPENA_WT_CONTI_TIME             0x9c
  41 #define I_T_NEXUS_LOSS_TIME             0xa0
  42 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  43 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  44 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  45 #define CQ_INT_CONVERGE_EN              0xb0
  46 #define CFG_AGING_TIME                  0xbc
  47 #define HGC_DFX_CFG2                    0xc0
  48 #define CFG_ABT_SET_QUERY_IPTT  0xd4
  49 #define CFG_SET_ABORTED_IPTT_OFF        0
  50 #define CFG_SET_ABORTED_IPTT_MSK        (0xfff << CFG_SET_ABORTED_IPTT_OFF)
  51 #define CFG_SET_ABORTED_EN_OFF  12
  52 #define CFG_ABT_SET_IPTT_DONE   0xd8
  53 #define CFG_ABT_SET_IPTT_DONE_OFF       0
  54 #define HGC_IOMB_PROC1_STATUS   0x104
  55 #define CHNL_INT_STATUS                 0x148
  56 #define HGC_AXI_FIFO_ERR_INFO  0x154
  57 #define AXI_ERR_INFO_OFF               0
  58 #define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
  59 #define FIFO_ERR_INFO_OFF              8
  60 #define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
  61 #define INT_COAL_EN                     0x19c
  62 #define OQ_INT_COAL_TIME                0x1a0
  63 #define OQ_INT_COAL_CNT                 0x1a4
  64 #define ENT_INT_COAL_TIME               0x1a8
  65 #define ENT_INT_COAL_CNT                0x1ac
  66 #define OQ_INT_SRC                      0x1b0
  67 #define OQ_INT_SRC_MSK                  0x1b4
  68 #define ENT_INT_SRC1                    0x1b8
  69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  73 #define ENT_INT_SRC2                    0x1bc
  74 #define ENT_INT_SRC3                    0x1c0
  75 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
  76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
  77 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
  78 #define ENT_INT_SRC3_AXI_OFF                    11
  79 #define ENT_INT_SRC3_FIFO_OFF                   12
  80 #define ENT_INT_SRC3_LM_OFF                             14
  81 #define ENT_INT_SRC3_ITC_INT_OFF        15
  82 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  83 #define ENT_INT_SRC3_ABT_OFF            16
  84 #define ENT_INT_SRC_MSK1                0x1c4
  85 #define ENT_INT_SRC_MSK2                0x1c8
  86 #define ENT_INT_SRC_MSK3                0x1cc
  87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  88 #define CHNL_PHYUPDOWN_INT_MSK          0x1d0
  89 #define CHNL_ENT_INT_MSK                        0x1d4
  90 #define HGC_COM_INT_MSK                         0x1d8
  91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  92 #define SAS_ECC_INTR                    0x1e8
  93 #define SAS_ECC_INTR_MSK                0x1ec
  94 #define HGC_ERR_STAT_EN                 0x238
  95 #define CQE_SEND_CNT                    0x248
  96 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  97 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  98 #define DLVRY_Q_0_DEPTH                 0x268
  99 #define DLVRY_Q_0_WR_PTR                0x26c
 100 #define DLVRY_Q_0_RD_PTR                0x270
 101 #define HYPER_STREAM_ID_EN_CFG          0xc80
 102 #define OQ0_INT_SRC_MSK                 0xc90
 103 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 104 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 105 #define COMPL_Q_0_DEPTH                 0x4e8
 106 #define COMPL_Q_0_WR_PTR                0x4ec
 107 #define COMPL_Q_0_RD_PTR                0x4f0
 108 #define AWQOS_AWCACHE_CFG       0xc84
 109 #define ARQOS_ARCACHE_CFG       0xc88
 110 #define HILINK_ERR_DFX          0xe04
 111 #define SAS_GPIO_CFG_0          0x1000
 112 #define SAS_GPIO_CFG_1          0x1004
 113 #define SAS_GPIO_TX_0_1 0x1040
 114 #define SAS_CFG_DRIVE_VLD       0x1070
 115
 116 /* phy registers requiring init */
 117 #define PORT_BASE                       (0x2000)
 118 #define PHY_CFG                         (PORT_BASE + 0x0)
 119 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 120 #define PHY_CFG_ENA_OFF                 0
 121 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 122 #define PHY_CFG_DC_OPT_OFF              2
 123 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 124 #define PHY_CFG_PHY_RST_OFF             3
 125 #define PHY_CFG_PHY_RST_MSK             (0x1 << PHY_CFG_PHY_RST_OFF)
 126 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 127 #define PHY_CTRL                        (PORT_BASE + 0x14)
 128 #define PHY_CTRL_RESET_OFF              0
 129 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 130 #define CMD_HDR_PIR_OFF                 8
 131 #define CMD_HDR_PIR_MSK                 (0x1 << CMD_HDR_PIR_OFF)
 132 #define SL_CFG                          (PORT_BASE + 0x84)
 133 #define AIP_LIMIT                       (PORT_BASE + 0x90)
 134 #define SL_CONTROL                      (PORT_BASE + 0x94)
 135 #define SL_CONTROL_NOTIFY_EN_OFF        0
 136 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 137 #define SL_CTA_OFF              17
 138 #define SL_CTA_MSK              (0x1 << SL_CTA_OFF)
 139 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 140 #define RX_BCAST_CHG_OFF                1
 141 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 142 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 143 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 144 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 145 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 146 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 147 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 148 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 149 #define TXID_AUTO                               (PORT_BASE + 0xb8)
 150 #define CT3_OFF         1
 151 #define CT3_MSK         (0x1 << CT3_OFF)
 152 #define TX_HARDRST_OFF          2
 153 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
 154 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 155 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 156 #define STP_LINK_TIMER                  (PORT_BASE + 0x120)
 157 #define STP_LINK_TIMEOUT_STATE          (PORT_BASE + 0x124)
 158 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
 159 #define SAS_SSP_CON_TIMER_CFG           (PORT_BASE + 0x134)
 160 #define SAS_SMP_CON_TIMER_CFG           (PORT_BASE + 0x138)
 161 #define SAS_STP_CON_TIMER_CFG           (PORT_BASE + 0x13c)
 162 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 163 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 164 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 165 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 166 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 167 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 168 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 169 #define CHL_INT0_NOT_RDY_OFF            4
 170 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 171 #define CHL_INT0_PHY_RDY_OFF            5
 172 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 173 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 174 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 175 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 176 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 177 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 178 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 179 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 180 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 181 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 182 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 183 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 184 #define CHL_INT2_RX_INVLD_DW_OFF        30
 185 #define CHL_INT2_STP_LINK_TIMEOUT_OFF   31
 186 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 187 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 188 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 189 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 190 #define SAS_RX_TRAIN_TIMER              (PORT_BASE + 0x2a4)
 191 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 192 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 193 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 194 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 195 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 196 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 197 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 198 #define DMA_TX_STATUS_BUSY_OFF          0
 199 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 200 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 201 #define DMA_RX_STATUS_BUSY_OFF          0
 202 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 203
 204 #define COARSETUNE_TIME                 (PORT_BASE + 0x304)
 205 #define ERR_CNT_DWS_LOST                (PORT_BASE + 0x380)
 206 #define ERR_CNT_RESET_PROB              (PORT_BASE + 0x384)
 207 #define ERR_CNT_INVLD_DW                (PORT_BASE + 0x390)
 208 #define ERR_CNT_DISP_ERR                (PORT_BASE + 0x398)
 209
 210 #define DEFAULT_ITCT_HW         2048 /* reset value, not reprogrammed */
 211 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
 212 #error Max ITCT exceeded
 213 #endif
 214
 215 #define AXI_MASTER_CFG_BASE             (0x5000)
 216 #define AM_CTRL_GLOBAL                  (0x0)
 217 #define AM_CTRL_SHUTDOWN_REQ_OFF        0
 218 #define AM_CTRL_SHUTDOWN_REQ_MSK        (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
 219 #define AM_CURR_TRANS_RETURN    (0x150)
 220
 221 #define AM_CFG_MAX_TRANS                (0x5010)
 222 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 223 #define AXI_CFG                                 (0x5100)
 224 #define AM_ROB_ECC_ERR_ADDR             (0x510c)
 225 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF  0
 226 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
 227 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF  8
 228 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK  (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
 229
 230 /* RAS registers need init */
 231 #define RAS_BASE                (0x6000)
 232 #define SAS_RAS_INTR0                   (RAS_BASE)
 233 #define SAS_RAS_INTR1                   (RAS_BASE + 0x04)
 234 #define SAS_RAS_INTR0_MASK              (RAS_BASE + 0x08)
 235 #define SAS_RAS_INTR1_MASK              (RAS_BASE + 0x0c)
 236 #define CFG_SAS_RAS_INTR_MASK           (RAS_BASE + 0x1c)
 237 #define SAS_RAS_INTR2                   (RAS_BASE + 0x20)
 238 #define SAS_RAS_INTR2_MASK              (RAS_BASE + 0x24)
 239
 240 /* HW dma structures */
 241 /* Delivery queue header */
 242 /* dw0 */
 243 #define CMD_HDR_ABORT_FLAG_OFF          0
 244 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 245 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 246 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 247 #define CMD_HDR_RESP_REPORT_OFF         5
 248 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 249 #define CMD_HDR_TLR_CTRL_OFF            6
 250 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 251 #define CMD_HDR_PORT_OFF                18
 252 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 253 #define CMD_HDR_PRIORITY_OFF            27
 254 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 255 #define CMD_HDR_CMD_OFF                 29
 256 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 257 /* dw1 */
 258 #define CMD_HDR_UNCON_CMD_OFF   3
 259 #define CMD_HDR_DIR_OFF                 5
 260 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 261 #define CMD_HDR_RESET_OFF               7
 262 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 263 #define CMD_HDR_VDTL_OFF                10
 264 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 265 #define CMD_HDR_FRAME_TYPE_OFF          11
 266 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 267 #define CMD_HDR_DEV_ID_OFF              16
 268 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 269 /* dw2 */
 270 #define CMD_HDR_CFL_OFF                 0
 271 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 272 #define CMD_HDR_NCQ_TAG_OFF             10
 273 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 274 #define CMD_HDR_MRFL_OFF                15
 275 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 276 #define CMD_HDR_SG_MOD_OFF              24
 277 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 278 /* dw3 */
 279 #define CMD_HDR_IPTT_OFF                0
 280 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 281 /* dw6 */
 282 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 283 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 284 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 285 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 286 /* dw7 */
 287 #define CMD_HDR_ADDR_MODE_SEL_OFF               15
 288 #define CMD_HDR_ADDR_MODE_SEL_MSK               (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
 289 #define CMD_HDR_ABORT_IPTT_OFF          16
 290 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 291
 292 /* Completion header */
 293 /* dw0 */
 294 #define CMPLT_HDR_CMPLT_OFF             0
 295 #define CMPLT_HDR_CMPLT_MSK             (0x3 << CMPLT_HDR_CMPLT_OFF)
 296 #define CMPLT_HDR_ERROR_PHASE_OFF   2
 297 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
 298 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 299 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 300 #define CMPLT_HDR_ERX_OFF               12
 301 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 302 #define CMPLT_HDR_ABORT_STAT_OFF        13
 303 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 304 /* abort_stat */
 305 #define STAT_IO_NOT_VALID               0x1
 306 #define STAT_IO_NO_DEVICE               0x2
 307 #define STAT_IO_COMPLETE                0x3
 308 #define STAT_IO_ABORTED                 0x4
 309 /* dw1 */
 310 #define CMPLT_HDR_IPTT_OFF              0
 311 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 312 #define CMPLT_HDR_DEV_ID_OFF            16
 313 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 314 /* dw3 */
 315 #define CMPLT_HDR_IO_IN_TARGET_OFF      17
 316 #define CMPLT_HDR_IO_IN_TARGET_MSK      (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
 317
 318 /* ITCT header */
 319 /* qw0 */
 320 #define ITCT_HDR_DEV_TYPE_OFF           0
 321 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 322 #define ITCT_HDR_VALID_OFF              2
 323 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 324 #define ITCT_HDR_MCR_OFF                5
 325 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 326 #define ITCT_HDR_VLN_OFF                9
 327 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 328 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 329 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 330 #define ITCT_HDR_PORT_ID_OFF            28
 331 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 332 /* qw2 */
 333 #define ITCT_HDR_INLT_OFF               0
 334 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 335 #define ITCT_HDR_RTOLT_OFF              48
 336 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 337
 338 struct hisi_sas_protect_iu_v3_hw {
 339         u32 dw0;
 340         u32 lbrtcv;
 341         u32 lbrtgv;
 342         u32 dw3;
 343         u32 dw4;
 344         u32 dw5;
 345         u32 rsv;
 346 };
 347
 348 struct hisi_sas_complete_v3_hdr {
 349         __le32 dw0;
 350         __le32 dw1;
 351         __le32 act;
 352         __le32 dw3;
 353 };
 354
 355 struct hisi_sas_err_record_v3 {
 356         /* dw0 */
 357         __le32 trans_tx_fail_type;
 358
 359         /* dw1 */
 360         __le32 trans_rx_fail_type;
 361
 362         /* dw2 */
 363         __le16 dma_tx_err_type;
 364         __le16 sipc_rx_err_type;
 365
 366         /* dw3 */
 367         __le32 dma_rx_err_type;
 368 };
 369
 370 #define RX_DATA_LEN_UNDERFLOW_OFF       6
 371 #define RX_DATA_LEN_UNDERFLOW_MSK       (1 << RX_DATA_LEN_UNDERFLOW_OFF)
 372
 373 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
 374 #define HISI_SAS_MSI_COUNT_V3_HW 32
 375
 376 #define DIR_NO_DATA 0
 377 #define DIR_TO_INI 1
 378 #define DIR_TO_DEVICE 2
 379 #define DIR_RESERVED 3
 380
 381 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
 382         ((fis.command == ATA_CMD_READ_LOG_EXT) || \
 383         (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
 384         ((fis.command == ATA_CMD_DEV_RESET) && \
 385         ((fis.control & ATA_SRST) != 0)))
 386
 387 #define T10_INSRT_EN_OFF    0
 388 #define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
 389 #define T10_RMV_EN_OFF      1
 390 #define T10_RMV_EN_MSK      (1 << T10_RMV_EN_OFF)
 391 #define T10_RPLC_EN_OFF     2
 392 #define T10_RPLC_EN_MSK     (1 << T10_RPLC_EN_OFF)
 393 #define T10_CHK_EN_OFF      3
 394 #define T10_CHK_EN_MSK      (1 << T10_CHK_EN_OFF)
 395 #define INCR_LBRT_OFF       5
 396 #define INCR_LBRT_MSK       (1 << INCR_LBRT_OFF)
 397 #define USR_DATA_BLOCK_SZ_OFF   20
 398 #define USR_DATA_BLOCK_SZ_MSK   (0x3 << USR_DATA_BLOCK_SZ_OFF)
 399 #define T10_CHK_MSK_OFF     16
 400
 401 static bool hisi_sas_intr_conv;
 402 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
 403
 404 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
 405 static int prot_mask;
 406 module_param(prot_mask, int, 0);
 407 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
 408
 409 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 410 {
 411         void __iomem *regs = hisi_hba->regs + off;
 412
 413         return readl(regs);
 414 }
 415
 416 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 417 {
 418         void __iomem *regs = hisi_hba->regs + off;
 419
 420         return readl_relaxed(regs);
 421 }
 422
 423 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 424 {
 425         void __iomem *regs = hisi_hba->regs + off;
 426
 427         writel(val, regs);
 428 }
 429
 430 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 431                                  u32 off, u32 val)
 432 {
 433         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 434
 435         writel(val, regs);
 436 }
 437
 438 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 439                                       int phy_no, u32 off)
 440 {
 441         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 442
 443         return readl(regs);
 444 }
 445
 446 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,          \
 447                                      timeout_us)                        \
 448 ({                                                                      \
 449         void __iomem *regs = hisi_hba->regs + off;                      \
 450         readl_poll_timeout(regs, val, cond, delay_us, timeout_us);      \
 451 })
 452
 453 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,   \
 454                                             timeout_us)                 \
 455 ({                                                                      \
 456         void __iomem *regs = hisi_hba->regs + off;                      \
 457         readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
 458 })
 459
 460 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
 461 {
 462         struct pci_dev *pdev = hisi_hba->pci_dev;
 463         int i;
 464
 465         /* Global registers init */
 466         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 467                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 468         hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
 469         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 470         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 471         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 472         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 473         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 474         hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
 475                          hisi_sas_intr_conv);
 476         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
 477         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 478         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 479         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 480         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
 481         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
 482         if (pdev->revision >= 0x21)
 483                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff);
 484         else
 485                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff);
 486         hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
 487         hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
 488         hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
 489         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
 490         hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
 491         hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
 492         for (i = 0; i < hisi_hba->queue_count; i++)
 493                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 494
 495         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 496
 497         for (i = 0; i < hisi_hba->n_phy; i++) {
 498                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 499                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 500                 u32 prog_phy_link_rate = 0x800;
 501
 502                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
 503                                 SAS_LINK_RATE_1_5_GBPS)) {
 504                         prog_phy_link_rate = 0x855;
 505                 } else {
 506                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
 507
 508                         prog_phy_link_rate =
 509                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
 510                                 0x800;
 511                 }
 512                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
 513                         prog_phy_link_rate);
 514                 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
 515                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 516                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 517                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 518                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 519                 if (pdev->revision >= 0x21)
 520                         hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
 521                                         0xffffffff);
 522                 else
 523                         hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK,
 524                                         0xff87ffff);
 525                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
 526                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 527                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 528                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 529                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 530                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 531                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
 532                 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
 533                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
 534                 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
 535                 /* used for 12G negotiate */
 536                 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
 537                 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
 538         }
 539
 540         for (i = 0; i < hisi_hba->queue_count; i++) {
 541                 /* Delivery queue */
 542                 hisi_sas_write32(hisi_hba,
 543                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 544                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 545
 546                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 547                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 548
 549                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 550                                  HISI_SAS_QUEUE_SLOTS);
 551
 552                 /* Completion queue */
 553                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 554                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 555
 556                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 557                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 558
 559                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 560                                  HISI_SAS_QUEUE_SLOTS);
 561         }
 562
 563         /* itct */
 564         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 565                          lower_32_bits(hisi_hba->itct_dma));
 566
 567         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 568                          upper_32_bits(hisi_hba->itct_dma));
 569
 570         /* iost */
 571         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 572                          lower_32_bits(hisi_hba->iost_dma));
 573
 574         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 575                          upper_32_bits(hisi_hba->iost_dma));
 576
 577         /* breakpoint */
 578         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 579                          lower_32_bits(hisi_hba->breakpoint_dma));
 580
 581         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 582                          upper_32_bits(hisi_hba->breakpoint_dma));
 583
 584         /* SATA broken msg */
 585         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 586                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 587
 588         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 589                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 590
 591         /* SATA initial fis */
 592         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 593                          lower_32_bits(hisi_hba->initial_fis_dma));
 594
 595         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 596                          upper_32_bits(hisi_hba->initial_fis_dma));
 597
 598         /* RAS registers init */
 599         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
 600         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
 601         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
 602         hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
 603
 604         /* LED registers init */
 605         hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
 606         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
 607         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
 608         /* Configure blink generator rate A to 1Hz and B to 4Hz */
 609         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
 610         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
 611 }
 612
 613 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 614 {
 615         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 616
 617         cfg &= ~PHY_CFG_DC_OPT_MSK;
 618         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 619         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 620 }
 621
 622 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 623 {
 624         struct sas_identify_frame identify_frame;
 625         u32 *identify_buffer;
 626
 627         memset(&identify_frame, 0, sizeof(identify_frame));
 628         identify_frame.dev_type = SAS_END_DEVICE;
 629         identify_frame.frame_type = 0;
 630         identify_frame._un1 = 1;
 631         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 632         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 633         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 634         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 635         identify_frame.phy_id = phy_no;
 636         identify_buffer = (u32 *)(&identify_frame);
 637
 638         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 639                         __swab32(identify_buffer[0]));
 640         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 641                         __swab32(identify_buffer[1]));
 642         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 643                         __swab32(identify_buffer[2]));
 644         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 645                         __swab32(identify_buffer[3]));
 646         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 647                         __swab32(identify_buffer[4]));
 648         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 649                         __swab32(identify_buffer[5]));
 650 }
 651
 652 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
 653                              struct hisi_sas_device *sas_dev)
 654 {
 655         struct domain_device *device = sas_dev->sas_device;
 656         struct device *dev = hisi_hba->dev;
 657         u64 qw0, device_id = sas_dev->device_id;
 658         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 659         struct domain_device *parent_dev = device->parent;
 660         struct asd_sas_port *sas_port = device->port;
 661         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 662         u64 sas_addr;
 663
 664         memset(itct, 0, sizeof(*itct));
 665
 666         /* qw0 */
 667         qw0 = 0;
 668         switch (sas_dev->dev_type) {
 669         case SAS_END_DEVICE:
 670         case SAS_EDGE_EXPANDER_DEVICE:
 671         case SAS_FANOUT_EXPANDER_DEVICE:
 672                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 673                 break;
 674         case SAS_SATA_DEV:
 675         case SAS_SATA_PENDING:
 676                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 677                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 678                 else
 679                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 680                 break;
 681         default:
 682                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 683                          sas_dev->dev_type);
 684         }
 685
 686         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 687                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 688                 (1 << ITCT_HDR_VLN_OFF) |
 689                 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
 690                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 691                 (port->id << ITCT_HDR_PORT_ID_OFF));
 692         itct->qw0 = cpu_to_le64(qw0);
 693
 694         /* qw1 */
 695         memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 696         itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 697
 698         /* qw2 */
 699         if (!dev_is_sata(device))
 700                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 701                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 702 }
 703
 704 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba,
 705                               struct hisi_sas_device *sas_dev)
 706 {
 707         DECLARE_COMPLETION_ONSTACK(completion);
 708         u64 dev_id = sas_dev->device_id;
 709         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 710         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 711
 712         sas_dev->completion = &completion;
 713
 714         /* clear the itct interrupt state */
 715         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 716                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 717                                  ENT_INT_SRC3_ITC_INT_MSK);
 718
 719         /* clear the itct table*/
 720         reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 721         hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 722
 723         wait_for_completion(sas_dev->completion);
 724         memset(itct, 0, sizeof(struct hisi_sas_itct));
 725 }
 726
 727 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
 728                                 struct domain_device *device)
 729 {
 730         struct hisi_sas_slot *slot, *slot2;
 731         struct hisi_sas_device *sas_dev = device->lldd_dev;
 732         u32 cfg_abt_set_query_iptt;
 733
 734         cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
 735                 CFG_ABT_SET_QUERY_IPTT);
 736         list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
 737                 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
 738                 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
 739                         (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
 740                 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 741                         cfg_abt_set_query_iptt);
 742         }
 743         cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
 744         hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
 745                 cfg_abt_set_query_iptt);
 746         hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
 747                                         1 << CFG_ABT_SET_IPTT_DONE_OFF);
 748 }
 749
 750 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
 751 {
 752         struct device *dev = hisi_hba->dev;
 753         int ret;
 754         u32 val;
 755
 756         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 757
 758         /* Disable all of the PHYs */
 759         hisi_sas_stop_phys(hisi_hba);
 760         udelay(50);
 761
 762         /* Ensure axi bus idle */
 763         ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
 764                                            20000, 1000000);
 765         if (ret) {
 766                 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
 767                 return -EIO;
 768         }
 769
 770         if (ACPI_HANDLE(dev)) {
 771                 acpi_status s;
 772
 773                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 774                 if (ACPI_FAILURE(s)) {
 775                         dev_err(dev, "Reset failed\n");
 776                         return -EIO;
 777                 }
 778         } else {
 779                 dev_err(dev, "no reset method!\n");
 780                 return -EINVAL;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
 787 {
 788         struct device *dev = hisi_hba->dev;
 789         int rc;
 790
 791         rc = reset_hw_v3_hw(hisi_hba);
 792         if (rc) {
 793                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 794                 return rc;
 795         }
 796
 797         msleep(100);
 798         init_reg_v3_hw(hisi_hba);
 799
 800         return 0;
 801 }
 802
 803 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 804 {
 805         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 806
 807         cfg |= PHY_CFG_ENA_MSK;
 808         cfg &= ~PHY_CFG_PHY_RST_MSK;
 809         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 810 }
 811
 812 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 813 {
 814         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 815         u32 state;
 816
 817         cfg &= ~PHY_CFG_ENA_MSK;
 818         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 819
 820         mdelay(50);
 821
 822         state = hisi_sas_read32(hisi_hba, PHY_STATE);
 823         if (state & BIT(phy_no)) {
 824                 cfg |= PHY_CFG_PHY_RST_MSK;
 825                 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 826         }
 827 }
 828
 829 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 830 {
 831         config_id_frame_v3_hw(hisi_hba, phy_no);
 832         config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
 833         enable_phy_v3_hw(hisi_hba, phy_no);
 834 }
 835
 836 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 837 {
 838         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
 839         u32 txid_auto;
 840
 841         disable_phy_v3_hw(hisi_hba, phy_no);
 842         if (phy->identify.device_type == SAS_END_DEVICE) {
 843                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
 844                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
 845                                         txid_auto | TX_HARDRST_MSK);
 846         }
 847         msleep(100);
 848         start_phy_v3_hw(hisi_hba, phy_no);
 849 }
 850
 851 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
 852 {
 853         return SAS_LINK_RATE_12_0_GBPS;
 854 }
 855
 856 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
 857 {
 858         int i;
 859
 860         for (i = 0; i < hisi_hba->n_phy; i++) {
 861                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
 862                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
 863
 864                 if (!sas_phy->phy->enabled)
 865                         continue;
 866
 867                 start_phy_v3_hw(hisi_hba, i);
 868         }
 869 }
 870
 871 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
 872 {
 873         u32 sl_control;
 874
 875         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 876         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 877         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 878         msleep(1);
 879         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 880         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 881         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 882 }
 883
 884 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
 885 {
 886         int i, bitmap = 0;
 887         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 888         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 889
 890         for (i = 0; i < hisi_hba->n_phy; i++)
 891                 if (phy_state & BIT(i))
 892                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 893                                 bitmap |= BIT(i);
 894
 895         return bitmap;
 896 }
 897
 898 /**
 899  * The callpath to this function and upto writing the write
 900  * queue pointer should be safe from interruption.
 901  */
 902 static int
 903 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
 904 {
 905         struct device *dev = hisi_hba->dev;
 906         int queue = dq->id;
 907         u32 r, w;
 908
 909         w = dq->wr_point;
 910         r = hisi_sas_read32_relaxed(hisi_hba,
 911                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
 912         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 913                 dev_warn(dev, "full queue=%d r=%d w=%d\n",
 914                                 queue, r, w);
 915                 return -EAGAIN;
 916         }
 917
 918         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
 919
 920         return w;
 921 }
 922
 923 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
 924 {
 925         struct hisi_hba *hisi_hba = dq->hisi_hba;
 926         struct hisi_sas_slot *s, *s1, *s2 = NULL;
 927         int dlvry_queue = dq->id;
 928         int wp;
 929
 930         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
 931                 if (!s->ready)
 932                         break;
 933                 s2 = s;
 934                 list_del(&s->delivery);
 935         }
 936
 937         if (!s2)
 938                 return;
 939
 940         /*
 941          * Ensure that memories for slots built on other CPUs is observed.
 942          */
 943         smp_rmb();
 944         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
 945
 946         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
 947 }
 948
 949 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
 950                               struct hisi_sas_slot *slot,
 951                               struct hisi_sas_cmd_hdr *hdr,
 952                               struct scatterlist *scatter,
 953                               int n_elem)
 954 {
 955         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
 956         struct scatterlist *sg;
 957         int i;
 958
 959         for_each_sg(scatter, sg, n_elem, i) {
 960                 struct hisi_sas_sge *entry = &sge_page->sge[i];
 961
 962                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 963                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 964                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 965                 entry->data_off = 0;
 966         }
 967
 968         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
 969
 970         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 971 }
 972
 973 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
 974 {
 975         unsigned char prot_flags = scsi_cmnd->prot_flags;
 976
 977         if (prot_flags & SCSI_PROT_TRANSFER_PI) {
 978                 if (prot_flags & SCSI_PROT_REF_CHECK)
 979                         return 0xc << 16;
 980                 return 0xfc << 16;
 981         }
 982         return 0;
 983 }
 984
 985 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
 986                             struct hisi_sas_protect_iu_v3_hw *prot)
 987 {
 988         unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
 989         unsigned int interval = scsi_prot_interval(scsi_cmnd);
 990         u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
 991
 992         switch (prot_op) {
 993         case SCSI_PROT_READ_STRIP:
 994                 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
 995                 prot->lbrtcv = lbrt_chk_val;
 996                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
 997                 break;
 998         case SCSI_PROT_WRITE_INSERT:
 999                 prot->dw0 |= T10_INSRT_EN_MSK;
1000                 prot->lbrtgv = lbrt_chk_val;
1001                 break;
1002         default:
1003                 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1004                 break;
1005         }
1006
1007         switch (interval) {
1008         case 512:
1009                 break;
1010         case 4096:
1011                 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1012                 break;
1013         case 520:
1014                 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1015                 break;
1016         default:
1017                 WARN(1, "protection interval (0x%x) invalid\n",
1018                      interval);
1019                 break;
1020         }
1021
1022         prot->dw0 |= INCR_LBRT_MSK;
1023 }
1024
1025 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1026                           struct hisi_sas_slot *slot)
1027 {
1028         struct sas_task *task = slot->task;
1029         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1030         struct domain_device *device = task->dev;
1031         struct hisi_sas_device *sas_dev = device->lldd_dev;
1032         struct hisi_sas_port *port = slot->port;
1033         struct sas_ssp_task *ssp_task = &task->ssp_task;
1034         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1035         struct hisi_sas_tmf_task *tmf = slot->tmf;
1036         unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1037         int has_data = 0, priority = !!tmf;
1038         u8 *buf_cmd;
1039         u32 dw1 = 0, dw2 = 0, len = 0;
1040
1041         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1042                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1043                                (port->id << CMD_HDR_PORT_OFF) |
1044                                (priority << CMD_HDR_PRIORITY_OFF) |
1045                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1046
1047         dw1 = 1 << CMD_HDR_VDTL_OFF;
1048         if (tmf) {
1049                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1050                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1051         } else {
1052                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1053                 switch (scsi_cmnd->sc_data_direction) {
1054                 case DMA_TO_DEVICE:
1055                         has_data = 1;
1056                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1057                         break;
1058                 case DMA_FROM_DEVICE:
1059                         has_data = 1;
1060                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1061                         break;
1062                 default:
1063                         dw1 &= ~CMD_HDR_DIR_MSK;
1064                 }
1065         }
1066
1067         /* map itct entry */
1068         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1069
1070         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1071               + 3) / 4) << CMD_HDR_CFL_OFF) |
1072               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1073               (2 << CMD_HDR_SG_MOD_OFF);
1074         hdr->dw2 = cpu_to_le32(dw2);
1075         hdr->transfer_tags = cpu_to_le32(slot->idx);
1076
1077         if (has_data)
1078                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1079                                         slot->n_elem);
1080
1081         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1082         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1083
1084         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1085                 sizeof(struct ssp_frame_hdr);
1086
1087         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1088         if (!tmf) {
1089                 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1090                 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1091         } else {
1092                 buf_cmd[10] = tmf->tmf;
1093                 switch (tmf->tmf) {
1094                 case TMF_ABORT_TASK:
1095                 case TMF_QUERY_TASK:
1096                         buf_cmd[12] =
1097                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1098                         buf_cmd[13] =
1099                                 tmf->tag_of_task_to_be_managed & 0xff;
1100                         break;
1101                 default:
1102                         break;
1103                 }
1104         }
1105
1106         if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1107                 struct hisi_sas_protect_iu_v3_hw prot;
1108                 u8 *buf_cmd_prot;
1109
1110                 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1111                 dw1 |= CMD_HDR_PIR_MSK;
1112                 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1113                                sizeof(struct ssp_frame_hdr) +
1114                                sizeof(struct ssp_command_iu);
1115
1116                 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1117                 fill_prot_v3_hw(scsi_cmnd, &prot);
1118                 memcpy(buf_cmd_prot, &prot,
1119                        sizeof(struct hisi_sas_protect_iu_v3_hw));
1120
1121                 /*
1122                  * For READ, we need length of info read to memory, while for
1123                  * WRITE we need length of data written to the disk.
1124                  */
1125                 if (prot_op == SCSI_PROT_WRITE_INSERT) {
1126                         unsigned int interval = scsi_prot_interval(scsi_cmnd);
1127                         unsigned int ilog2_interval = ilog2(interval);
1128
1129                         len = (task->total_xfer_len >> ilog2_interval) * 8;
1130                 }
1131
1132         }
1133
1134         hdr->dw1 = cpu_to_le32(dw1);
1135
1136         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1137 }
1138
1139 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1140                           struct hisi_sas_slot *slot)
1141 {
1142         struct sas_task *task = slot->task;
1143         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1144         struct domain_device *device = task->dev;
1145         struct hisi_sas_port *port = slot->port;
1146         struct scatterlist *sg_req;
1147         struct hisi_sas_device *sas_dev = device->lldd_dev;
1148         dma_addr_t req_dma_addr;
1149         unsigned int req_len;
1150
1151         /* req */
1152         sg_req = &task->smp_task.smp_req;
1153         req_len = sg_dma_len(sg_req);
1154         req_dma_addr = sg_dma_address(sg_req);
1155
1156         /* create header */
1157         /* dw0 */
1158         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1159                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1160                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1161
1162         /* map itct entry */
1163         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1164                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1165                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1166
1167         /* dw2 */
1168         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1169                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1170                                CMD_HDR_MRFL_OFF));
1171
1172         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1173
1174         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1175         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1176
1177 }
1178
1179 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1180                           struct hisi_sas_slot *slot)
1181 {
1182         struct sas_task *task = slot->task;
1183         struct domain_device *device = task->dev;
1184         struct domain_device *parent_dev = device->parent;
1185         struct hisi_sas_device *sas_dev = device->lldd_dev;
1186         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1187         struct asd_sas_port *sas_port = device->port;
1188         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1189         u8 *buf_cmd;
1190         int has_data = 0, hdr_tag = 0;
1191         u32 dw1 = 0, dw2 = 0;
1192
1193         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1194         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1195                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1196         else
1197                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1198
1199         switch (task->data_dir) {
1200         case DMA_TO_DEVICE:
1201                 has_data = 1;
1202                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1203                 break;
1204         case DMA_FROM_DEVICE:
1205                 has_data = 1;
1206                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1207                 break;
1208         default:
1209                 dw1 &= ~CMD_HDR_DIR_MSK;
1210         }
1211
1212         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1213                         (task->ata_task.fis.control & ATA_SRST))
1214                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1215
1216         dw1 |= (hisi_sas_get_ata_protocol(
1217                 &task->ata_task.fis, task->data_dir))
1218                 << CMD_HDR_FRAME_TYPE_OFF;
1219         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1220
1221         if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1222                 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1223
1224         hdr->dw1 = cpu_to_le32(dw1);
1225
1226         /* dw2 */
1227         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1228                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1229                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1230         }
1231
1232         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1233                         2 << CMD_HDR_SG_MOD_OFF;
1234         hdr->dw2 = cpu_to_le32(dw2);
1235
1236         /* dw3 */
1237         hdr->transfer_tags = cpu_to_le32(slot->idx);
1238
1239         if (has_data)
1240                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1241                                         slot->n_elem);
1242
1243         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1244         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1245         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1246
1247         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1248
1249         if (likely(!task->ata_task.device_control_reg_update))
1250                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1251         /* fill in command FIS */
1252         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1253 }
1254
1255 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1256                 struct hisi_sas_slot *slot,
1257                 int device_id, int abort_flag, int tag_to_abort)
1258 {
1259         struct sas_task *task = slot->task;
1260         struct domain_device *dev = task->dev;
1261         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1262         struct hisi_sas_port *port = slot->port;
1263
1264         /* dw0 */
1265         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1266                                (port->id << CMD_HDR_PORT_OFF) |
1267                                    (dev_is_sata(dev)
1268                                         << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1269                                         (abort_flag
1270                                          << CMD_HDR_ABORT_FLAG_OFF));
1271
1272         /* dw1 */
1273         hdr->dw1 = cpu_to_le32(device_id
1274                         << CMD_HDR_DEV_ID_OFF);
1275
1276         /* dw7 */
1277         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1278         hdr->transfer_tags = cpu_to_le32(slot->idx);
1279
1280 }
1281
1282 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1283 {
1284         int i, res;
1285         u32 context, port_id, link_rate;
1286         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1287         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1288         struct device *dev = hisi_hba->dev;
1289         unsigned long flags;
1290
1291         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1292
1293         port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1294         port_id = (port_id >> (4 * phy_no)) & 0xf;
1295         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1296         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1297
1298         if (port_id == 0xf) {
1299                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1300                 res = IRQ_NONE;
1301                 goto end;
1302         }
1303         sas_phy->linkrate = link_rate;
1304         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1305
1306         /* Check for SATA dev */
1307         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1308         if (context & (1 << phy_no)) {
1309                 struct hisi_sas_initial_fis *initial_fis;
1310                 struct dev_to_host_fis *fis;
1311                 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1312
1313                 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1314                 initial_fis = &hisi_hba->initial_fis[phy_no];
1315                 fis = &initial_fis->fis;
1316
1317                 /* check ERR bit of Status Register */
1318                 if (fis->status & ATA_ERR) {
1319                         dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1320                                  phy_no, fis->status);
1321                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1322                         res = IRQ_NONE;
1323                         goto end;
1324                 }
1325
1326                 sas_phy->oob_mode = SATA_OOB_MODE;
1327                 attached_sas_addr[0] = 0x50;
1328                 attached_sas_addr[7] = phy_no;
1329                 memcpy(sas_phy->attached_sas_addr,
1330                        attached_sas_addr,
1331                        SAS_ADDR_SIZE);
1332                 memcpy(sas_phy->frame_rcvd, fis,
1333                        sizeof(struct dev_to_host_fis));
1334                 phy->phy_type |= PORT_TYPE_SATA;
1335                 phy->identify.device_type = SAS_SATA_DEV;
1336                 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1337                 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1338         } else {
1339                 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1340                 struct sas_identify_frame *id =
1341                         (struct sas_identify_frame *)frame_rcvd;
1342
1343                 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1344                 for (i = 0; i < 6; i++) {
1345                         u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1346                                                RX_IDAF_DWORD0 + (i * 4));
1347                         frame_rcvd[i] = __swab32(idaf);
1348                 }
1349                 sas_phy->oob_mode = SAS_OOB_MODE;
1350                 memcpy(sas_phy->attached_sas_addr,
1351                        &id->sas_addr,
1352                        SAS_ADDR_SIZE);
1353                 phy->phy_type |= PORT_TYPE_SAS;
1354                 phy->identify.device_type = id->dev_type;
1355                 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1356                 if (phy->identify.device_type == SAS_END_DEVICE)
1357                         phy->identify.target_port_protocols =
1358                                 SAS_PROTOCOL_SSP;
1359                 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1360                         phy->identify.target_port_protocols =
1361                                 SAS_PROTOCOL_SMP;
1362         }
1363
1364         phy->port_id = port_id;
1365         phy->phy_attached = 1;
1366         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1367         res = IRQ_HANDLED;
1368         spin_lock_irqsave(&phy->lock, flags);
1369         if (phy->reset_completion) {
1370                 phy->in_reset = 0;
1371                 complete(phy->reset_completion);
1372         }
1373         spin_unlock_irqrestore(&phy->lock, flags);
1374 end:
1375         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1376                              CHL_INT0_SL_PHY_ENABLE_MSK);
1377         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1378
1379         return res;
1380 }
1381
1382 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1383 {
1384         u32 phy_state, sl_ctrl, txid_auto;
1385         struct device *dev = hisi_hba->dev;
1386
1387         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1388
1389         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1390         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1391         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1392
1393         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1394         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1395                                                 sl_ctrl&(~SL_CTA_MSK));
1396
1397         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1398         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1399                                                 txid_auto | CT3_MSK);
1400
1401         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1402         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1403
1404         return IRQ_HANDLED;
1405 }
1406
1407 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1408 {
1409         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1410         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1411         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1412         u32 bcast_status;
1413
1414         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1415         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1416         if ((bcast_status & RX_BCAST_CHG_MSK) &&
1417             !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1418                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1419         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1420                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1421         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1422
1423         return IRQ_HANDLED;
1424 }
1425
1426 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1427 {
1428         struct hisi_hba *hisi_hba = p;
1429         u32 irq_msk;
1430         int phy_no = 0;
1431         irqreturn_t res = IRQ_NONE;
1432
1433         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1434                                 & 0x11111111;
1435         while (irq_msk) {
1436                 if (irq_msk  & 1) {
1437                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1438                                                             CHL_INT0);
1439                         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1440                         int rdy = phy_state & (1 << phy_no);
1441
1442                         if (rdy) {
1443                                 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1444                                         /* phy up */
1445                                         if (phy_up_v3_hw(phy_no, hisi_hba)
1446                                                         == IRQ_HANDLED)
1447                                                 res = IRQ_HANDLED;
1448                                 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1449                                         /* phy bcast */
1450                                         if (phy_bcast_v3_hw(phy_no, hisi_hba)
1451                                                         == IRQ_HANDLED)
1452                                                 res = IRQ_HANDLED;
1453                         } else {
1454                                 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1455                                         /* phy down */
1456                                         if (phy_down_v3_hw(phy_no, hisi_hba)
1457                                                         == IRQ_HANDLED)
1458                                                 res = IRQ_HANDLED;
1459                         }
1460                 }
1461                 irq_msk >>= 4;
1462                 phy_no++;
1463         }
1464
1465         return res;
1466 }
1467
1468 static const struct hisi_sas_hw_error port_axi_error[] = {
1469         {
1470                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1471                 .msg = "dma_tx_axi_wr_err",
1472         },
1473         {
1474                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1475                 .msg = "dma_tx_axi_rd_err",
1476         },
1477         {
1478                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1479                 .msg = "dma_rx_axi_wr_err",
1480         },
1481         {
1482                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1483                 .msg = "dma_rx_axi_rd_err",
1484         },
1485 };
1486
1487 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1488 {
1489         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1490         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1491         struct device *dev = hisi_hba->dev;
1492         int i;
1493
1494         irq_value &= ~irq_msk;
1495         if (!irq_value)
1496                 return;
1497
1498         for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1499                 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1500
1501                 if (!(irq_value & error->irq_msk))
1502                         continue;
1503
1504                 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1505                         error->msg, phy_no, irq_value);
1506                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1507         }
1508
1509         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1510 }
1511
1512 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1513 {
1514         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1515         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1516         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1517         struct pci_dev *pci_dev = hisi_hba->pci_dev;
1518         struct device *dev = hisi_hba->dev;
1519
1520         irq_value &= ~irq_msk;
1521         if (!irq_value)
1522                 return;
1523
1524         if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1525                 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1526                 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1527         }
1528
1529         if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1530                 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1531                                 STP_LINK_TIMEOUT_STATE);
1532
1533                 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1534                          phy_no, reg_value);
1535                 if (reg_value & BIT(4))
1536                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1537         }
1538
1539         if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1540             (pci_dev->revision == 0x20)) {
1541                 u32 reg_value;
1542                 int rc;
1543
1544                 rc = hisi_sas_read32_poll_timeout_atomic(
1545                                 HILINK_ERR_DFX, reg_value,
1546                                 !((reg_value >> 8) & BIT(phy_no)),
1547                                 1000, 10000);
1548                 if (rc)
1549                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1550         }
1551
1552         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1553 }
1554
1555 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1556 {
1557         struct hisi_hba *hisi_hba = p;
1558         u32 irq_msk;
1559         int phy_no = 0;
1560
1561         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1562                                 & 0xeeeeeeee;
1563
1564         while (irq_msk) {
1565                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1566                                                      CHL_INT0);
1567
1568                 if (irq_msk & (4 << (phy_no * 4)))
1569                         handle_chl_int1_v3_hw(hisi_hba, phy_no);
1570
1571                 if (irq_msk & (8 << (phy_no * 4)))
1572                         handle_chl_int2_v3_hw(hisi_hba, phy_no);
1573
1574                 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1575                         hisi_sas_phy_write32(hisi_hba, phy_no,
1576                                         CHL_INT0, irq_value0
1577                                         & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1578                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1579                                         & (~CHL_INT0_NOT_RDY_MSK));
1580                 }
1581                 irq_msk &= ~(0xe << (phy_no * 4));
1582                 phy_no++;
1583         }
1584
1585         return IRQ_HANDLED;
1586 }
1587
1588 static const struct hisi_sas_hw_error axi_error[] = {
1589         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1590         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1591         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1592         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1593         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1594         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1595         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1596         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1597         {},
1598 };
1599
1600 static const struct hisi_sas_hw_error fifo_error[] = {
1601         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
1602         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
1603         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1604         { .msk = BIT(11), .msg = "CMDP_FIFO" },
1605         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1606         {},
1607 };
1608
1609 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1610         {
1611                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1612                 .msg = "write pointer and depth",
1613         },
1614         {
1615                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1616                 .msg = "iptt no match slot",
1617         },
1618         {
1619                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
1620                 .msg = "read pointer and depth",
1621         },
1622         {
1623                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
1624                 .reg = HGC_AXI_FIFO_ERR_INFO,
1625                 .sub = axi_error,
1626         },
1627         {
1628                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
1629                 .reg = HGC_AXI_FIFO_ERR_INFO,
1630                 .sub = fifo_error,
1631         },
1632         {
1633                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
1634                 .msg = "LM add/fetch list",
1635         },
1636         {
1637                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
1638                 .msg = "SAS_HGC_ABT fetch LM list",
1639         },
1640 };
1641
1642 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
1643 {
1644         u32 irq_value, irq_msk;
1645         struct hisi_hba *hisi_hba = p;
1646         struct device *dev = hisi_hba->dev;
1647         int i;
1648
1649         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1650         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
1651
1652         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
1653         irq_value &= ~irq_msk;
1654
1655         for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
1656                 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
1657
1658                 if (!(irq_value & error->irq_msk))
1659                         continue;
1660
1661                 if (error->sub) {
1662                         const struct hisi_sas_hw_error *sub = error->sub;
1663                         u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
1664
1665                         for (; sub->msk || sub->msg; sub++) {
1666                                 if (!(err_value & sub->msk))
1667                                         continue;
1668
1669                                 dev_err(dev, "%s error (0x%x) found!\n",
1670                                         sub->msg, irq_value);
1671                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1672                         }
1673                 } else {
1674                         dev_err(dev, "%s error (0x%x) found!\n",
1675                                 error->msg, irq_value);
1676                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1677                 }
1678         }
1679
1680         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
1681                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
1682                 u32 dev_id = reg_val & ITCT_DEV_MSK;
1683                 struct hisi_sas_device *sas_dev =
1684                                 &hisi_hba->devices[dev_id];
1685
1686                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
1687                 dev_dbg(dev, "clear ITCT ok\n");
1688                 complete(sas_dev->completion);
1689         }
1690
1691         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
1692         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
1693
1694         return IRQ_HANDLED;
1695 }
1696
1697 static void
1698 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1699                struct hisi_sas_slot *slot)
1700 {
1701         struct task_status_struct *ts = &task->task_status;
1702         struct hisi_sas_complete_v3_hdr *complete_queue =
1703                         hisi_hba->complete_hdr[slot->cmplt_queue];
1704         struct hisi_sas_complete_v3_hdr *complete_hdr =
1705                         &complete_queue[slot->cmplt_queue_slot];
1706         struct hisi_sas_err_record_v3 *record =
1707                         hisi_sas_status_buf_addr_mem(slot);
1708         u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
1709         u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
1710         u32 dw3 = le32_to_cpu(complete_hdr->dw3);
1711
1712         switch (task->task_proto) {
1713         case SAS_PROTOCOL_SSP:
1714                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1715                         ts->residual = trans_tx_fail_type;
1716                         ts->stat = SAS_DATA_UNDERRUN;
1717                 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1718                         ts->stat = SAS_QUEUE_FULL;
1719                         slot->abort = 1;
1720                 } else {
1721                         ts->stat = SAS_OPEN_REJECT;
1722                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1723                 }
1724                 break;
1725         case SAS_PROTOCOL_SATA:
1726         case SAS_PROTOCOL_STP:
1727         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1728                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1729                         ts->residual = trans_tx_fail_type;
1730                         ts->stat = SAS_DATA_UNDERRUN;
1731                 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1732                         ts->stat = SAS_PHY_DOWN;
1733                         slot->abort = 1;
1734                 } else {
1735                         ts->stat = SAS_OPEN_REJECT;
1736                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1737                 }
1738                 hisi_sas_sata_done(task, slot);
1739                 break;
1740         case SAS_PROTOCOL_SMP:
1741                 ts->stat = SAM_STAT_CHECK_CONDITION;
1742                 break;
1743         default:
1744                 break;
1745         }
1746 }
1747
1748 static int
1749 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1750 {
1751         struct sas_task *task = slot->task;
1752         struct hisi_sas_device *sas_dev;
1753         struct device *dev = hisi_hba->dev;
1754         struct task_status_struct *ts;
1755         struct domain_device *device;
1756         struct sas_ha_struct *ha;
1757         enum exec_status sts;
1758         struct hisi_sas_complete_v3_hdr *complete_queue =
1759                         hisi_hba->complete_hdr[slot->cmplt_queue];
1760         struct hisi_sas_complete_v3_hdr *complete_hdr =
1761                         &complete_queue[slot->cmplt_queue_slot];
1762         unsigned long flags;
1763         bool is_internal = slot->is_internal;
1764         u32 dw0, dw1, dw3;
1765
1766         if (unlikely(!task || !task->lldd_task || !task->dev))
1767                 return -EINVAL;
1768
1769         ts = &task->task_status;
1770         device = task->dev;
1771         ha = device->port->ha;
1772         sas_dev = device->lldd_dev;
1773
1774         spin_lock_irqsave(&task->task_state_lock, flags);
1775         task->task_state_flags &=
1776                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1777         spin_unlock_irqrestore(&task->task_state_lock, flags);
1778
1779         memset(ts, 0, sizeof(*ts));
1780         ts->resp = SAS_TASK_COMPLETE;
1781
1782         if (unlikely(!sas_dev)) {
1783                 dev_dbg(dev, "slot complete: port has not device\n");
1784                 ts->stat = SAS_PHY_DOWN;
1785                 goto out;
1786         }
1787
1788         dw0 = le32_to_cpu(complete_hdr->dw0);
1789         dw1 = le32_to_cpu(complete_hdr->dw1);
1790         dw3 = le32_to_cpu(complete_hdr->dw3);
1791
1792         /*
1793          * Use SAS+TMF status codes
1794          */
1795         switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
1796         case STAT_IO_ABORTED:
1797                 /* this IO has been aborted by abort command */
1798                 ts->stat = SAS_ABORTED_TASK;
1799                 goto out;
1800         case STAT_IO_COMPLETE:
1801                 /* internal abort command complete */
1802                 ts->stat = TMF_RESP_FUNC_SUCC;
1803                 goto out;
1804         case STAT_IO_NO_DEVICE:
1805                 ts->stat = TMF_RESP_FUNC_COMPLETE;
1806                 goto out;
1807         case STAT_IO_NOT_VALID:
1808                 /*
1809                  * abort single IO, the controller can't find the IO
1810                  */
1811                 ts->stat = TMF_RESP_FUNC_FAILED;
1812                 goto out;
1813         default:
1814                 break;
1815         }
1816
1817         /* check for erroneous completion */
1818         if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1819                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
1820
1821                 slot_err_v3_hw(hisi_hba, task, slot);
1822                 if (ts->stat != SAS_DATA_UNDERRUN)
1823                         dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
1824                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
1825                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
1826                                 slot->idx, task, sas_dev->device_id,
1827                                 dw0, dw1, complete_hdr->act, dw3,
1828                                 error_info[0], error_info[1],
1829                                 error_info[2], error_info[3]);
1830                 if (unlikely(slot->abort))
1831                         return ts->stat;
1832                 goto out;
1833         }
1834
1835         switch (task->task_proto) {
1836         case SAS_PROTOCOL_SSP: {
1837                 struct ssp_response_iu *iu =
1838                         hisi_sas_status_buf_addr_mem(slot) +
1839                         sizeof(struct hisi_sas_err_record);
1840
1841                 sas_ssp_task_response(dev, task, iu);
1842                 break;
1843         }
1844         case SAS_PROTOCOL_SMP: {
1845                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1846                 void *to;
1847
1848                 ts->stat = SAM_STAT_GOOD;
1849                 to = kmap_atomic(sg_page(sg_resp));
1850
1851                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1852                              DMA_FROM_DEVICE);
1853                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1854                              DMA_TO_DEVICE);
1855                 memcpy(to + sg_resp->offset,
1856                         hisi_sas_status_buf_addr_mem(slot) +
1857                        sizeof(struct hisi_sas_err_record),
1858                        sg_dma_len(sg_resp));
1859                 kunmap_atomic(to);
1860                 break;
1861         }
1862         case SAS_PROTOCOL_SATA:
1863         case SAS_PROTOCOL_STP:
1864         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1865                 ts->stat = SAM_STAT_GOOD;
1866                 hisi_sas_sata_done(task, slot);
1867                 break;
1868         default:
1869                 ts->stat = SAM_STAT_CHECK_CONDITION;
1870                 break;
1871         }
1872
1873         if (!slot->port->port_attached) {
1874                 dev_warn(dev, "slot complete: port %d has removed\n",
1875                         slot->port->sas_port.id);
1876                 ts->stat = SAS_PHY_DOWN;
1877         }
1878
1879 out:
1880         sts = ts->stat;
1881         spin_lock_irqsave(&task->task_state_lock, flags);
1882         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
1883                 spin_unlock_irqrestore(&task->task_state_lock, flags);
1884                 dev_info(dev, "slot complete: task(%p) aborted\n", task);
1885                 return SAS_ABORTED_TASK;
1886         }
1887         task->task_state_flags |= SAS_TASK_STATE_DONE;
1888         spin_unlock_irqrestore(&task->task_state_lock, flags);
1889         hisi_sas_slot_task_free(hisi_hba, task, slot);
1890
1891         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
1892                 spin_lock_irqsave(&device->done_lock, flags);
1893                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
1894                         spin_unlock_irqrestore(&device->done_lock, flags);
1895                         dev_info(dev, "slot complete: task(%p) ignored\n ",
1896                                  task);
1897                         return sts;
1898                 }
1899                 spin_unlock_irqrestore(&device->done_lock, flags);
1900         }
1901
1902         if (task->task_done)
1903                 task->task_done(task);
1904
1905         return sts;
1906 }
1907
1908 static void cq_tasklet_v3_hw(unsigned long val)
1909 {
1910         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1911         struct hisi_hba *hisi_hba = cq->hisi_hba;
1912         struct hisi_sas_slot *slot;
1913         struct hisi_sas_complete_v3_hdr *complete_queue;
1914         u32 rd_point = cq->rd_point, wr_point;
1915         int queue = cq->id;
1916
1917         complete_queue = hisi_hba->complete_hdr[queue];
1918
1919         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1920                                    (0x14 * queue));
1921
1922         while (rd_point != wr_point) {
1923                 struct hisi_sas_complete_v3_hdr *complete_hdr;
1924                 struct device *dev = hisi_hba->dev;
1925                 u32 dw1;
1926                 int iptt;
1927
1928                 complete_hdr = &complete_queue[rd_point];
1929                 dw1 = le32_to_cpu(complete_hdr->dw1);
1930
1931                 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
1932                 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
1933                         slot = &hisi_hba->slot_info[iptt];
1934                         slot->cmplt_queue_slot = rd_point;
1935                         slot->cmplt_queue = queue;
1936                         slot_complete_v3_hw(hisi_hba, slot);
1937                 } else
1938                         dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
1939
1940                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1941                         rd_point = 0;
1942         }
1943
1944         /* update rd_point */
1945         cq->rd_point = rd_point;
1946         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1947 }
1948
1949 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1950 {
1951         struct hisi_sas_cq *cq = p;
1952         struct hisi_hba *hisi_hba = cq->hisi_hba;
1953         int queue = cq->id;
1954
1955         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1956
1957         tasklet_schedule(&cq->tasklet);
1958
1959         return IRQ_HANDLED;
1960 }
1961
1962 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1963 {
1964         struct device *dev = hisi_hba->dev;
1965         struct pci_dev *pdev = hisi_hba->pci_dev;
1966         int vectors, rc;
1967         int i, k;
1968         int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1969
1970         vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1971                                         max_msi, PCI_IRQ_MSI);
1972         if (vectors < max_msi) {
1973                 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1974                 return -ENOENT;
1975         }
1976
1977         rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1978                               int_phy_up_down_bcast_v3_hw, 0,
1979                               DRV_NAME " phy", hisi_hba);
1980         if (rc) {
1981                 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1982                 rc = -ENOENT;
1983                 goto free_irq_vectors;
1984         }
1985
1986         rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1987                               int_chnl_int_v3_hw, 0,
1988                               DRV_NAME " channel", hisi_hba);
1989         if (rc) {
1990                 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1991                 rc = -ENOENT;
1992                 goto free_phy_irq;
1993         }
1994
1995         rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
1996                               fatal_axi_int_v3_hw, 0,
1997                               DRV_NAME " fatal", hisi_hba);
1998         if (rc) {
1999                 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2000                 rc = -ENOENT;
2001                 goto free_chnl_interrupt;
2002         }
2003
2004         /* Init tasklets for cq only */
2005         for (i = 0; i < hisi_hba->queue_count; i++) {
2006                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2007                 struct tasklet_struct *t = &cq->tasklet;
2008                 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2009                 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0;
2010
2011                 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr),
2012                                       cq_interrupt_v3_hw, irqflags,
2013                                       DRV_NAME " cq", cq);
2014                 if (rc) {
2015                         dev_err(dev,
2016                                 "could not request cq%d interrupt, rc=%d\n",
2017                                 i, rc);
2018                         rc = -ENOENT;
2019                         goto free_cq_irqs;
2020                 }
2021
2022                 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
2023         }
2024
2025         return 0;
2026
2027 free_cq_irqs:
2028         for (k = 0; k < i; k++) {
2029                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
2030                 int nr = hisi_sas_intr_conv ? 16 : 16 + k;
2031
2032                 free_irq(pci_irq_vector(pdev, nr), cq);
2033         }
2034         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2035 free_chnl_interrupt:
2036         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2037 free_phy_irq:
2038         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2039 free_irq_vectors:
2040         pci_free_irq_vectors(pdev);
2041         return rc;
2042 }
2043
2044 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2045 {
2046         int rc;
2047
2048         rc = hw_init_v3_hw(hisi_hba);
2049         if (rc)
2050                 return rc;
2051
2052         rc = interrupt_init_v3_hw(hisi_hba);
2053         if (rc)
2054                 return rc;
2055
2056         return 0;
2057 }
2058
2059 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2060                 struct sas_phy_linkrates *r)
2061 {
2062         enum sas_linkrate max = r->maximum_linkrate;
2063         u32 prog_phy_link_rate = 0x800;
2064
2065         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2066         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2067                              prog_phy_link_rate);
2068 }
2069
2070 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2071 {
2072         struct pci_dev *pdev = hisi_hba->pci_dev;
2073         int i;
2074
2075         synchronize_irq(pci_irq_vector(pdev, 1));
2076         synchronize_irq(pci_irq_vector(pdev, 2));
2077         synchronize_irq(pci_irq_vector(pdev, 11));
2078         for (i = 0; i < hisi_hba->queue_count; i++) {
2079                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2080                 synchronize_irq(pci_irq_vector(pdev, i + 16));
2081         }
2082
2083         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2084         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2085         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2086         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2087
2088         for (i = 0; i < hisi_hba->n_phy; i++) {
2089                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2090                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2091                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2092                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2093                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2094         }
2095 }
2096
2097 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2098 {
2099         return hisi_sas_read32(hisi_hba, PHY_STATE);
2100 }
2101
2102 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
2103 {
2104         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2105         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2106         struct sas_phy *sphy = sas_phy->phy;
2107         u32 reg_value;
2108
2109         /* loss dword sync */
2110         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
2111         sphy->loss_of_dword_sync_count += reg_value;
2112
2113         /* phy reset problem */
2114         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
2115         sphy->phy_reset_problem_count += reg_value;
2116
2117         /* invalid dword */
2118         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
2119         sphy->invalid_dword_count += reg_value;
2120
2121         /* disparity err */
2122         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
2123         sphy->running_disparity_error_count += reg_value;
2124
2125 }
2126
2127 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2128 {
2129         struct device *dev = hisi_hba->dev;
2130         u32 status, reg_val;
2131         int rc;
2132
2133         interrupt_disable_v3_hw(hisi_hba);
2134         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2135         hisi_sas_kill_tasklets(hisi_hba);
2136
2137         hisi_sas_stop_phys(hisi_hba);
2138
2139         mdelay(10);
2140
2141         reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2142                                   AM_CTRL_GLOBAL);
2143         reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2144         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2145                          AM_CTRL_GLOBAL, reg_val);
2146
2147         /* wait until bus idle */
2148         rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2149                                           AM_CURR_TRANS_RETURN, status,
2150                                           status == 0x3, 10, 100);
2151         if (rc) {
2152                 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2153                 return rc;
2154         }
2155
2156         return 0;
2157 }
2158
2159 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2160 {
2161         struct device *dev = hisi_hba->dev;
2162         int rc;
2163
2164         rc = disable_host_v3_hw(hisi_hba);
2165         if (rc) {
2166                 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2167                 return rc;
2168         }
2169
2170         hisi_sas_init_mem(hisi_hba);
2171
2172         return hw_init_v3_hw(hisi_hba);
2173 }
2174
2175 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2176                         u8 reg_index, u8 reg_count, u8 *write_data)
2177 {
2178         struct device *dev = hisi_hba->dev;
2179         u32 *data = (u32 *)write_data;
2180         int i;
2181
2182         switch (reg_type) {
2183         case SAS_GPIO_REG_TX:
2184                 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2185                         dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2186                                 reg_index, reg_index + reg_count - 1);
2187                         return -EINVAL;
2188                 }
2189
2190                 for (i = 0; i < reg_count; i++)
2191                         hisi_sas_write32(hisi_hba,
2192                                          SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2193                                          data[i]);
2194                 break;
2195         default:
2196                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2197                                 reg_type);
2198                 return -EINVAL;
2199         }
2200
2201         return 0;
2202 }
2203
2204 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2205                                              int delay_ms, int timeout_ms)
2206 {
2207         struct device *dev = hisi_hba->dev;
2208         int entries, entries_old = 0, time;
2209
2210         for (time = 0; time < timeout_ms; time += delay_ms) {
2211                 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2212                 if (entries == entries_old)
2213                         break;
2214
2215                 entries_old = entries;
2216                 msleep(delay_ms);
2217         }
2218
2219         dev_dbg(dev, "wait commands complete %dms\n", time);
2220 }
2221
2222 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2223                                     struct device_attribute *attr, char *buf)
2224 {
2225         return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2226 }
2227 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2228
2229 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2230 {
2231         /* config those registers between enable and disable PHYs */
2232         hisi_sas_stop_phys(hisi_hba);
2233
2234         if (hisi_hba->intr_coal_ticks == 0 ||
2235             hisi_hba->intr_coal_count == 0) {
2236                 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2237                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2238                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2239         } else {
2240                 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2241                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2242                                  hisi_hba->intr_coal_ticks);
2243                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2244                                  hisi_hba->intr_coal_count);
2245         }
2246         phys_init_v3_hw(hisi_hba);
2247 }
2248
2249 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2250                                           struct device_attribute *attr,
2251                                           char *buf)
2252 {
2253         struct Scsi_Host *shost = class_to_shost(dev);
2254         struct hisi_hba *hisi_hba = shost_priv(shost);
2255
2256         return scnprintf(buf, PAGE_SIZE, "%u\n",
2257                          hisi_hba->intr_coal_ticks);
2258 }
2259
2260 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2261                                            struct device_attribute *attr,
2262                                            const char *buf, size_t count)
2263 {
2264         struct Scsi_Host *shost = class_to_shost(dev);
2265         struct hisi_hba *hisi_hba = shost_priv(shost);
2266         u32 intr_coal_ticks;
2267         int ret;
2268
2269         ret = kstrtou32(buf, 10, &intr_coal_ticks);
2270         if (ret) {
2271                 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2272                 return -EINVAL;
2273         }
2274
2275         if (intr_coal_ticks >= BIT(24)) {
2276                 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2277                 return -EINVAL;
2278         }
2279
2280         hisi_hba->intr_coal_ticks = intr_coal_ticks;
2281
2282         config_intr_coal_v3_hw(hisi_hba);
2283
2284         return count;
2285 }
2286 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2287
2288 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2289                                           struct device_attribute
2290                                           *attr, char *buf)
2291 {
2292         struct Scsi_Host *shost = class_to_shost(dev);
2293         struct hisi_hba *hisi_hba = shost_priv(shost);
2294
2295         return scnprintf(buf, PAGE_SIZE, "%u\n",
2296                          hisi_hba->intr_coal_count);
2297 }
2298
2299 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2300                 struct device_attribute
2301                 *attr, const char *buf, size_t count)
2302 {
2303         struct Scsi_Host *shost = class_to_shost(dev);
2304         struct hisi_hba *hisi_hba = shost_priv(shost);
2305         u32 intr_coal_count;
2306         int ret;
2307
2308         ret = kstrtou32(buf, 10, &intr_coal_count);
2309         if (ret) {
2310                 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2311                 return -EINVAL;
2312         }
2313
2314         if (intr_coal_count >= BIT(8)) {
2315                 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2316                 return -EINVAL;
2317         }
2318
2319         hisi_hba->intr_coal_count = intr_coal_count;
2320
2321         config_intr_coal_v3_hw(hisi_hba);
2322
2323         return count;
2324 }
2325 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2326
2327 static struct device_attribute *host_attrs_v3_hw[] = {
2328         &dev_attr_phy_event_threshold,
2329         &dev_attr_intr_conv_v3_hw,
2330         &dev_attr_intr_coal_ticks_v3_hw,
2331         &dev_attr_intr_coal_count_v3_hw,
2332         NULL
2333 };
2334
2335 static struct scsi_host_template sht_v3_hw = {
2336         .name                   = DRV_NAME,
2337         .module                 = THIS_MODULE,
2338         .queuecommand           = sas_queuecommand,
2339         .target_alloc           = sas_target_alloc,
2340         .slave_configure        = hisi_sas_slave_configure,
2341         .scan_finished          = hisi_sas_scan_finished,
2342         .scan_start             = hisi_sas_scan_start,
2343         .change_queue_depth     = sas_change_queue_depth,
2344         .bios_param             = sas_bios_param,
2345         .this_id                = -1,
2346         .sg_tablesize           = HISI_SAS_SGE_PAGE_CNT,
2347         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
2348         .eh_device_reset_handler = sas_eh_device_reset_handler,
2349         .eh_target_reset_handler = sas_eh_target_reset_handler,
2350         .target_destroy         = sas_target_destroy,
2351         .ioctl                  = sas_ioctl,
2352         .shost_attrs            = host_attrs_v3_hw,
2353         .tag_alloc_policy       = BLK_TAG_ALLOC_RR,
2354 };
2355
2356 static const struct hisi_sas_hw hisi_sas_v3_hw = {
2357         .hw_init = hisi_sas_v3_init,
2358         .setup_itct = setup_itct_v3_hw,
2359         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
2360         .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
2361         .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
2362         .clear_itct = clear_itct_v3_hw,
2363         .sl_notify = sl_notify_v3_hw,
2364         .prep_ssp = prep_ssp_v3_hw,
2365         .prep_smp = prep_smp_v3_hw,
2366         .prep_stp = prep_ata_v3_hw,
2367         .prep_abort = prep_abort_v3_hw,
2368         .get_free_slot = get_free_slot_v3_hw,
2369         .start_delivery = start_delivery_v3_hw,
2370         .slot_complete = slot_complete_v3_hw,
2371         .phys_init = phys_init_v3_hw,
2372         .phy_start = start_phy_v3_hw,
2373         .phy_disable = disable_phy_v3_hw,
2374         .phy_hard_reset = phy_hard_reset_v3_hw,
2375         .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
2376         .phy_set_linkrate = phy_set_linkrate_v3_hw,
2377         .dereg_device = dereg_device_v3_hw,
2378         .soft_reset = soft_reset_v3_hw,
2379         .get_phys_state = get_phys_state_v3_hw,
2380         .get_events = phy_get_events_v3_hw,
2381         .write_gpio = write_gpio_v3_hw,
2382         .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
2383 };
2384
2385 static struct Scsi_Host *
2386 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
2387 {
2388         struct Scsi_Host *shost;
2389         struct hisi_hba *hisi_hba;
2390         struct device *dev = &pdev->dev;
2391
2392         shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
2393         if (!shost) {
2394                 dev_err(dev, "shost alloc failed\n");
2395                 return NULL;
2396         }
2397         hisi_hba = shost_priv(shost);
2398
2399         INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2400         hisi_hba->hw = &hisi_sas_v3_hw;
2401         hisi_hba->pci_dev = pdev;
2402         hisi_hba->dev = dev;
2403         hisi_hba->shost = shost;
2404         SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2405
2406         if (prot_mask & ~HISI_SAS_PROT_MASK)
2407                 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
2408                         prot_mask);
2409         else
2410                 hisi_hba->prot_mask = prot_mask;
2411
2412         timer_setup(&hisi_hba->timer, NULL, 0);
2413
2414         if (hisi_sas_get_fw_info(hisi_hba) < 0)
2415                 goto err_out;
2416
2417         if (hisi_sas_alloc(hisi_hba, shost)) {
2418                 hisi_sas_free(hisi_hba);
2419                 goto err_out;
2420         }
2421
2422         return shost;
2423 err_out:
2424         scsi_host_put(shost);
2425         dev_err(dev, "shost alloc failed\n");
2426         return NULL;
2427 }
2428
2429 static int
2430 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2431 {
2432         struct Scsi_Host *shost;
2433         struct hisi_hba *hisi_hba;
2434         struct device *dev = &pdev->dev;
2435         struct asd_sas_phy **arr_phy;
2436         struct asd_sas_port **arr_port;
2437         struct sas_ha_struct *sha;
2438         int rc, phy_nr, port_nr, i;
2439
2440         rc = pci_enable_device(pdev);
2441         if (rc)
2442                 goto err_out;
2443
2444         pci_set_master(pdev);
2445
2446         rc = pci_request_regions(pdev, DRV_NAME);
2447         if (rc)
2448                 goto err_out_disable_device;
2449
2450         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) ||
2451             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
2452                 dev_err(dev, "No usable DMA addressing method\n");
2453                 rc = -EIO;
2454                 goto err_out_regions;
2455         }
2456
2457         shost = hisi_sas_shost_alloc_pci(pdev);
2458         if (!shost) {
2459                 rc = -ENOMEM;
2460                 goto err_out_regions;
2461         }
2462
2463         sha = SHOST_TO_SAS_HA(shost);
2464         hisi_hba = shost_priv(shost);
2465         dev_set_drvdata(dev, sha);
2466
2467         hisi_hba->regs = pcim_iomap(pdev, 5, 0);
2468         if (!hisi_hba->regs) {
2469                 dev_err(dev, "cannot map register.\n");
2470                 rc = -ENOMEM;
2471                 goto err_out_ha;
2472         }
2473
2474         phy_nr = port_nr = hisi_hba->n_phy;
2475
2476         arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2477         arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
2478         if (!arr_phy || !arr_port) {
2479                 rc = -ENOMEM;
2480                 goto err_out_ha;
2481         }
2482
2483         sha->sas_phy = arr_phy;
2484         sha->sas_port = arr_port;
2485         sha->core.shost = shost;
2486         sha->lldd_ha = hisi_hba;
2487
2488         shost->transportt = hisi_sas_stt;
2489         shost->max_id = HISI_SAS_MAX_DEVICES;
2490         shost->max_lun = ~0;
2491         shost->max_channel = 1;
2492         shost->max_cmd_len = 16;
2493         shost->can_queue = hisi_hba->hw->max_command_entries -
2494                 HISI_SAS_RESERVED_IPTT_CNT;
2495         shost->cmd_per_lun = hisi_hba->hw->max_command_entries -
2496                 HISI_SAS_RESERVED_IPTT_CNT;
2497
2498         sha->sas_ha_name = DRV_NAME;
2499         sha->dev = dev;
2500         sha->lldd_module = THIS_MODULE;
2501         sha->sas_addr = &hisi_hba->sas_addr[0];
2502         sha->num_phys = hisi_hba->n_phy;
2503         sha->core.shost = hisi_hba->shost;
2504
2505         for (i = 0; i < hisi_hba->n_phy; i++) {
2506                 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2507                 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2508         }
2509
2510         if (hisi_hba->prot_mask) {
2511                 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
2512                          prot_mask);
2513                 scsi_host_set_prot(hisi_hba->shost, prot_mask);
2514         }
2515
2516         rc = scsi_add_host(shost, dev);
2517         if (rc)
2518                 goto err_out_ha;
2519
2520         rc = sas_register_ha(sha);
2521         if (rc)
2522                 goto err_out_register_ha;
2523
2524         rc = hisi_hba->hw->hw_init(hisi_hba);
2525         if (rc)
2526                 goto err_out_register_ha;
2527
2528         scsi_scan_host(shost);
2529
2530         return 0;
2531
2532 err_out_register_ha:
2533         scsi_remove_host(shost);
2534 err_out_ha:
2535         scsi_host_put(shost);
2536 err_out_regions:
2537         pci_release_regions(pdev);
2538 err_out_disable_device:
2539         pci_disable_device(pdev);
2540 err_out:
2541         return rc;
2542 }
2543
2544 static void
2545 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
2546 {
2547         int i;
2548
2549         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
2550         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
2551         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
2552         for (i = 0; i < hisi_hba->queue_count; i++) {
2553                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2554                 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2555
2556                 free_irq(pci_irq_vector(pdev, nr), cq);
2557         }
2558         pci_free_irq_vectors(pdev);
2559 }
2560
2561 static void hisi_sas_v3_remove(struct pci_dev *pdev)
2562 {
2563         struct device *dev = &pdev->dev;
2564         struct sas_ha_struct *sha = dev_get_drvdata(dev);
2565         struct hisi_hba *hisi_hba = sha->lldd_ha;
2566         struct Scsi_Host *shost = sha->core.shost;
2567
2568         if (timer_pending(&hisi_hba->timer))
2569                 del_timer(&hisi_hba->timer);
2570
2571         sas_unregister_ha(sha);
2572         sas_remove_host(sha->core.shost);
2573
2574         hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
2575         hisi_sas_kill_tasklets(hisi_hba);
2576         pci_release_regions(pdev);
2577         pci_disable_device(pdev);
2578         hisi_sas_free(hisi_hba);
2579         scsi_host_put(shost);
2580 }
2581
2582 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = {
2583         { .irq_msk = BIT(19), .msg = "HILINK_INT" },
2584         { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" },
2585         { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" },
2586         { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" },
2587         { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" },
2588         { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" },
2589         { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" },
2590         { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" },
2591         { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" },
2592         { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" },
2593         { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" },
2594         { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" },
2595         { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" },
2596 };
2597
2598 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = {
2599         { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" },
2600         { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" },
2601         { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" },
2602         { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" },
2603         { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" },
2604         { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" },
2605         { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" },
2606         { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" },
2607         { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" },
2608         { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" },
2609         { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" },
2610         { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" },
2611         { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" },
2612         { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" },
2613         { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" },
2614         { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" },
2615         { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" },
2616         { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" },
2617         { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" },
2618         { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" },
2619         { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" },
2620         { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" },
2621         { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" },
2622         { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" },
2623         { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" },
2624         { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" },
2625         { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" },
2626         { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" },
2627         { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" },
2628         { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" },
2629         { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" },
2630 };
2631
2632 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = {
2633         { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" },
2634         { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" },
2635         { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" },
2636         { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" },
2637         { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" },
2638         { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" },
2639         { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" },
2640         { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" },
2641         { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" },
2642         { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" },
2643         { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" },
2644         { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" },
2645         { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" },
2646         { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" },
2647         { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" },
2648         { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" },
2649         { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" },
2650         { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" },
2651         { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" },
2652         { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" },
2653 };
2654
2655 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba)
2656 {
2657         struct device *dev = hisi_hba->dev;
2658         const struct hisi_sas_hw_error *ras_error;
2659         bool need_reset = false;
2660         u32 irq_value;
2661         int i;
2662
2663         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0);
2664         for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) {
2665                 ras_error = &sas_ras_intr0_nfe[i];
2666                 if (ras_error->irq_msk & irq_value) {
2667                         dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n",
2668                                         ras_error->msg, irq_value);
2669                         need_reset = true;
2670                 }
2671         }
2672         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value);
2673
2674         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1);
2675         for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) {
2676                 ras_error = &sas_ras_intr1_nfe[i];
2677                 if (ras_error->irq_msk & irq_value) {
2678                         dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n",
2679                                         ras_error->msg, irq_value);
2680                         need_reset = true;
2681                 }
2682         }
2683         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value);
2684
2685         irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2);
2686         for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) {
2687                 ras_error = &sas_ras_intr2_nfe[i];
2688                 if (ras_error->irq_msk & irq_value) {
2689                         dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n",
2690                                         ras_error->msg, irq_value);
2691                         need_reset = true;
2692                 }
2693         }
2694         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value);
2695
2696         return need_reset;
2697 }
2698
2699 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev,
2700                 pci_channel_state_t state)
2701 {
2702         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2703         struct hisi_hba *hisi_hba = sha->lldd_ha;
2704         struct device *dev = hisi_hba->dev;
2705
2706         dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state);
2707         if (state == pci_channel_io_perm_failure)
2708                 return PCI_ERS_RESULT_DISCONNECT;
2709
2710         if (process_non_fatal_error_v3_hw(hisi_hba))
2711                 return PCI_ERS_RESULT_NEED_RESET;
2712
2713         return PCI_ERS_RESULT_CAN_RECOVER;
2714 }
2715
2716 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev)
2717 {
2718         return PCI_ERS_RESULT_RECOVERED;
2719 }
2720
2721 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev)
2722 {
2723         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2724         struct hisi_hba *hisi_hba = sha->lldd_ha;
2725         struct device *dev = hisi_hba->dev;
2726         HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
2727
2728         dev_info(dev, "PCI error: slot reset callback!!\n");
2729         queue_work(hisi_hba->wq, &r.work);
2730         wait_for_completion(r.completion);
2731         if (r.done)
2732                 return PCI_ERS_RESULT_RECOVERED;
2733
2734         return PCI_ERS_RESULT_DISCONNECT;
2735 }
2736
2737 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
2738 {
2739         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2740         struct hisi_hba *hisi_hba = sha->lldd_ha;
2741         struct device *dev = hisi_hba->dev;
2742         int rc;
2743
2744         dev_info(dev, "FLR prepare\n");
2745         set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2746         hisi_sas_controller_reset_prepare(hisi_hba);
2747
2748         rc = disable_host_v3_hw(hisi_hba);
2749         if (rc)
2750                 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
2751 }
2752
2753 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
2754 {
2755         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2756         struct hisi_hba *hisi_hba = sha->lldd_ha;
2757         struct device *dev = hisi_hba->dev;
2758         int rc;
2759
2760         hisi_sas_init_mem(hisi_hba);
2761
2762         rc = hw_init_v3_hw(hisi_hba);
2763         if (rc) {
2764                 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
2765                 return;
2766         }
2767
2768         hisi_sas_controller_reset_done(hisi_hba);
2769         dev_info(dev, "FLR done\n");
2770 }
2771
2772 enum {
2773         /* instances of the controller */
2774         hip08,
2775 };
2776
2777 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
2778 {
2779         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2780         struct hisi_hba *hisi_hba = sha->lldd_ha;
2781         struct device *dev = hisi_hba->dev;
2782         struct Scsi_Host *shost = hisi_hba->shost;
2783         pci_power_t device_state;
2784         int rc;
2785
2786         if (!pdev->pm_cap) {
2787                 dev_err(dev, "PCI PM not supported\n");
2788                 return -ENODEV;
2789         }
2790
2791         if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2792                 return -1;
2793
2794         scsi_block_requests(shost);
2795         set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2796         flush_workqueue(hisi_hba->wq);
2797
2798         rc = disable_host_v3_hw(hisi_hba);
2799         if (rc) {
2800                 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
2801                 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2802                 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2803                 scsi_unblock_requests(shost);
2804                 return rc;
2805         }
2806
2807         hisi_sas_init_mem(hisi_hba);
2808
2809         device_state = pci_choose_state(pdev, state);
2810         dev_warn(dev, "entering operating state [D%d]\n",
2811                         device_state);
2812         pci_save_state(pdev);
2813         pci_disable_device(pdev);
2814         pci_set_power_state(pdev, device_state);
2815
2816         hisi_sas_release_tasks(hisi_hba);
2817
2818         sas_suspend_ha(sha);
2819         return 0;
2820 }
2821
2822 static int hisi_sas_v3_resume(struct pci_dev *pdev)
2823 {
2824         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
2825         struct hisi_hba *hisi_hba = sha->lldd_ha;
2826         struct Scsi_Host *shost = hisi_hba->shost;
2827         struct device *dev = hisi_hba->dev;
2828         unsigned int rc;
2829         pci_power_t device_state = pdev->current_state;
2830
2831         dev_warn(dev, "resuming from operating state [D%d]\n",
2832                         device_state);
2833         pci_set_power_state(pdev, PCI_D0);
2834         pci_enable_wake(pdev, PCI_D0, 0);
2835         pci_restore_state(pdev);
2836         rc = pci_enable_device(pdev);
2837         if (rc)
2838                 dev_err(dev, "enable device failed during resume (%d)\n", rc);
2839
2840         pci_set_master(pdev);
2841         scsi_unblock_requests(shost);
2842         clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2843
2844         sas_prep_resume_ha(sha);
2845         init_reg_v3_hw(hisi_hba);
2846         hisi_hba->hw->phys_init(hisi_hba);
2847         sas_resume_ha(sha);
2848         clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
2849
2850         return 0;
2851 }
2852
2853 static const struct pci_device_id sas_v3_pci_table[] = {
2854         { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
2855         {}
2856 };
2857 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
2858
2859 static const struct pci_error_handlers hisi_sas_err_handler = {
2860         .error_detected = hisi_sas_error_detected_v3_hw,
2861         .mmio_enabled   = hisi_sas_mmio_enabled_v3_hw,
2862         .slot_reset     = hisi_sas_slot_reset_v3_hw,
2863         .reset_prepare  = hisi_sas_reset_prepare_v3_hw,
2864         .reset_done     = hisi_sas_reset_done_v3_hw,
2865 };
2866
2867 static struct pci_driver sas_v3_pci_driver = {
2868         .name           = DRV_NAME,
2869         .id_table       = sas_v3_pci_table,
2870         .probe          = hisi_sas_v3_probe,
2871         .remove         = hisi_sas_v3_remove,
2872         .suspend        = hisi_sas_v3_suspend,
2873         .resume         = hisi_sas_v3_resume,
2874         .err_handler    = &hisi_sas_err_handler,
2875 };
2876
2877 module_pci_driver(sas_v3_pci_driver);
2878 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
2879
2880 MODULE_LICENSE("GPL");
2881 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2882 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2883 MODULE_ALIAS("pci:" DRV_NAME);