drivers/rtc/rtc-omap.c

   1 /*
   2  * TI OMAP Real Time Clock interface for Linux
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
   6  *
   7  * Copyright (C) 2006 David Brownell (new RTC framework)
   8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <linux/bcd.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/ioport.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinconf.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/rtc.h>
  33
  34 /*
  35  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
  36  * with century-range alarm matching, driven by the 32kHz clock.
  37  *
  38  * The main user-visible ways it differs from PC RTCs are by omitting
  39  * "don't care" alarm fields and sub-second periodic IRQs, and having
  40  * an autoadjust mechanism to calibrate to the true oscillator rate.
  41  *
  42  * Board-specific wiring options include using split power mode with
  43  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  44  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
  45  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
  46  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  47  */
  48
  49 /* RTC registers */
  50 #define OMAP_RTC_SECONDS_REG            0x00
  51 #define OMAP_RTC_MINUTES_REG            0x04
  52 #define OMAP_RTC_HOURS_REG              0x08
  53 #define OMAP_RTC_DAYS_REG               0x0C
  54 #define OMAP_RTC_MONTHS_REG             0x10
  55 #define OMAP_RTC_YEARS_REG              0x14
  56 #define OMAP_RTC_WEEKS_REG              0x18
  57
  58 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
  59 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
  60 #define OMAP_RTC_ALARM_HOURS_REG        0x28
  61 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
  62 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
  63 #define OMAP_RTC_ALARM_YEARS_REG        0x34
  64
  65 #define OMAP_RTC_CTRL_REG               0x40
  66 #define OMAP_RTC_STATUS_REG             0x44
  67 #define OMAP_RTC_INTERRUPTS_REG         0x48
  68
  69 #define OMAP_RTC_COMP_LSB_REG           0x4c
  70 #define OMAP_RTC_COMP_MSB_REG           0x50
  71 #define OMAP_RTC_OSC_REG                0x54
  72
  73 #define OMAP_RTC_KICK0_REG              0x6c
  74 #define OMAP_RTC_KICK1_REG              0x70
  75
  76 #define OMAP_RTC_IRQWAKEEN              0x7c
  77
  78 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
  79 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
  80 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
  81 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
  82 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
  83 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
  84
  85 #define OMAP_RTC_PMIC_REG               0x98
  86
  87 /* OMAP_RTC_CTRL_REG bit fields: */
  88 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
  89 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
  90 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
  91 #define OMAP_RTC_CTRL_TEST              BIT(4)
  92 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
  93 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
  94 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
  95 #define OMAP_RTC_CTRL_STOP              BIT(0)
  96
  97 /* OMAP_RTC_STATUS_REG bit fields: */
  98 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
  99 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
 100 #define OMAP_RTC_STATUS_ALARM           BIT(6)
 101 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
 102 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
 103 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
 104 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
 105 #define OMAP_RTC_STATUS_RUN             BIT(1)
 106 #define OMAP_RTC_STATUS_BUSY            BIT(0)
 107
 108 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
 109 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
 110 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
 111 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
 112
 113 /* OMAP_RTC_OSC_REG bit fields: */
 114 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
 115 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
 116 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE  BIT(4)
 117
 118 /* OMAP_RTC_IRQWAKEEN bit fields: */
 119 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
 120
 121 /* OMAP_RTC_PMIC bit fields: */
 122 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
 123 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x)    BIT(x)
 124 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x)   BIT(4 + x)
 125
 126 /* OMAP_RTC_KICKER values */
 127 #define KICK0_VALUE                     0x83e70b13
 128 #define KICK1_VALUE                     0x95a4f1e0
 129
 130 struct omap_rtc;
 131
 132 struct omap_rtc_device_type {
 133         bool has_32kclk_en;
 134         bool has_irqwakeen;
 135         bool has_pmic_mode;
 136         bool has_power_up_reset;
 137         void (*lock)(struct omap_rtc *rtc);
 138         void (*unlock)(struct omap_rtc *rtc);
 139 };
 140
 141 struct omap_rtc {
 142         struct rtc_device *rtc;
 143         void __iomem *base;
 144         struct clk *clk;
 145         int irq_alarm;
 146         int irq_timer;
 147         u8 interrupts_reg;
 148         bool is_pmic_controller;
 149         bool has_ext_clk;
 150         bool is_suspending;
 151         const struct omap_rtc_device_type *type;
 152         struct pinctrl_dev *pctldev;
 153 };
 154
 155 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
 156 {
 157         return readb(rtc->base + reg);
 158 }
 159
 160 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
 161 {
 162         return readl(rtc->base + reg);
 163 }
 164
 165 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
 166 {
 167         writeb(val, rtc->base + reg);
 168 }
 169
 170 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
 171 {
 172         writel(val, rtc->base + reg);
 173 }
 174
 175 static void am3352_rtc_unlock(struct omap_rtc *rtc)
 176 {
 177         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
 178         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
 179 }
 180
 181 static void am3352_rtc_lock(struct omap_rtc *rtc)
 182 {
 183         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
 184         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
 185 }
 186
 187 static void default_rtc_unlock(struct omap_rtc *rtc)
 188 {
 189 }
 190
 191 static void default_rtc_lock(struct omap_rtc *rtc)
 192 {
 193 }
 194
 195 /*
 196  * We rely on the rtc framework to handle locking (rtc->ops_lock),
 197  * so the only other requirement is that register accesses which
 198  * require BUSY to be clear are made with IRQs locally disabled
 199  */
 200 static void rtc_wait_not_busy(struct omap_rtc *rtc)
 201 {
 202         int count;
 203         u8 status;
 204
 205         /* BUSY may stay active for 1/32768 second (~30 usec) */
 206         for (count = 0; count < 50; count++) {
 207                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 208                 if (!(status & OMAP_RTC_STATUS_BUSY))
 209                         break;
 210                 udelay(1);
 211         }
 212         /* now we have ~15 usec to read/write various registers */
 213 }
 214
 215 static irqreturn_t rtc_irq(int irq, void *dev_id)
 216 {
 217         struct omap_rtc *rtc = dev_id;
 218         unsigned long events = 0;
 219         u8 irq_data;
 220
 221         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 222
 223         /* alarm irq? */
 224         if (irq_data & OMAP_RTC_STATUS_ALARM) {
 225                 rtc->type->unlock(rtc);
 226                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
 227                 rtc->type->lock(rtc);
 228                 events |= RTC_IRQF | RTC_AF;
 229         }
 230
 231         /* 1/sec periodic/update irq? */
 232         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
 233                 events |= RTC_IRQF | RTC_UF;
 234
 235         rtc_update_irq(rtc->rtc, 1, events);
 236
 237         return IRQ_HANDLED;
 238 }
 239
 240 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 241 {
 242         struct omap_rtc *rtc = dev_get_drvdata(dev);
 243         u8 reg, irqwake_reg = 0;
 244
 245         local_irq_disable();
 246         rtc_wait_not_busy(rtc);
 247         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 248         if (rtc->type->has_irqwakeen)
 249                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 250
 251         if (enabled) {
 252                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 253                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 254         } else {
 255                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 256                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 257         }
 258         rtc_wait_not_busy(rtc);
 259         rtc->type->unlock(rtc);
 260         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 261         if (rtc->type->has_irqwakeen)
 262                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 263         rtc->type->lock(rtc);
 264         local_irq_enable();
 265
 266         return 0;
 267 }
 268
 269 /* this hardware doesn't support "don't care" alarm fields */
 270 static int tm2bcd(struct rtc_time *tm)
 271 {
 272         if (rtc_valid_tm(tm) != 0)
 273                 return -EINVAL;
 274
 275         tm->tm_sec = bin2bcd(tm->tm_sec);
 276         tm->tm_min = bin2bcd(tm->tm_min);
 277         tm->tm_hour = bin2bcd(tm->tm_hour);
 278         tm->tm_mday = bin2bcd(tm->tm_mday);
 279
 280         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
 281
 282         /* epoch == 1900 */
 283         if (tm->tm_year < 100 || tm->tm_year > 199)
 284                 return -EINVAL;
 285         tm->tm_year = bin2bcd(tm->tm_year - 100);
 286
 287         return 0;
 288 }
 289
 290 static void bcd2tm(struct rtc_time *tm)
 291 {
 292         tm->tm_sec = bcd2bin(tm->tm_sec);
 293         tm->tm_min = bcd2bin(tm->tm_min);
 294         tm->tm_hour = bcd2bin(tm->tm_hour);
 295         tm->tm_mday = bcd2bin(tm->tm_mday);
 296         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
 297         /* epoch == 1900 */
 298         tm->tm_year = bcd2bin(tm->tm_year) + 100;
 299 }
 300
 301 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
 302 {
 303         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
 304         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
 305         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
 306         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
 307         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
 308         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
 309 }
 310
 311 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
 312 {
 313         struct omap_rtc *rtc = dev_get_drvdata(dev);
 314
 315         /* we don't report wday/yday/isdst ... */
 316         local_irq_disable();
 317         rtc_wait_not_busy(rtc);
 318         omap_rtc_read_time_raw(rtc, tm);
 319         local_irq_enable();
 320
 321         bcd2tm(tm);
 322
 323         return 0;
 324 }
 325
 326 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
 327 {
 328         struct omap_rtc *rtc = dev_get_drvdata(dev);
 329
 330         if (tm2bcd(tm) < 0)
 331                 return -EINVAL;
 332
 333         local_irq_disable();
 334         rtc_wait_not_busy(rtc);
 335
 336         rtc->type->unlock(rtc);
 337         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
 338         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
 339         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
 340         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
 341         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
 342         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
 343         rtc->type->lock(rtc);
 344
 345         local_irq_enable();
 346
 347         return 0;
 348 }
 349
 350 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 351 {
 352         struct omap_rtc *rtc = dev_get_drvdata(dev);
 353         u8 interrupts;
 354
 355         local_irq_disable();
 356         rtc_wait_not_busy(rtc);
 357
 358         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
 359         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
 360         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
 361         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
 362         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
 363         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
 364
 365         local_irq_enable();
 366
 367         bcd2tm(&alm->time);
 368
 369         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 370         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
 371
 372         return 0;
 373 }
 374
 375 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 376 {
 377         struct omap_rtc *rtc = dev_get_drvdata(dev);
 378         u8 reg, irqwake_reg = 0;
 379
 380         if (tm2bcd(&alm->time) < 0)
 381                 return -EINVAL;
 382
 383         local_irq_disable();
 384         rtc_wait_not_busy(rtc);
 385
 386         rtc->type->unlock(rtc);
 387         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
 388         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
 389         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
 390         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
 391         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
 392         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
 393
 394         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 395         if (rtc->type->has_irqwakeen)
 396                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 397
 398         if (alm->enabled) {
 399                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 400                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 401         } else {
 402                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 403                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 404         }
 405         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 406         if (rtc->type->has_irqwakeen)
 407                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 408         rtc->type->lock(rtc);
 409
 410         local_irq_enable();
 411
 412         return 0;
 413 }
 414
 415 static struct omap_rtc *omap_rtc_power_off_rtc;
 416
 417 /*
 418  * omap_rtc_poweroff: RTC-controlled power off
 419  *
 420  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
 421  * which can be configured to transition to OFF on ALARM2 events.
 422  *
 423  * Notes:
 424  * The two-second alarm offset is the shortest offset possible as the alarm
 425  * registers must be set before the next timer update and the offset
 426  * calculation is too heavy for everything to be done within a single access
 427  * period (~15 us).
 428  *
 429  * Called with local interrupts disabled.
 430  */
 431 static void omap_rtc_power_off(void)
 432 {
 433         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
 434         struct rtc_time tm;
 435         unsigned long now;
 436         u32 val;
 437
 438         rtc->type->unlock(rtc);
 439         /* enable pmic_power_en control */
 440         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 441         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
 442
 443         /* set alarm two seconds from now */
 444         omap_rtc_read_time_raw(rtc, &tm);
 445         bcd2tm(&tm);
 446         rtc_tm_to_time(&tm, &now);
 447         rtc_time_to_tm(now + 2, &tm);
 448
 449         if (tm2bcd(&tm) < 0) {
 450                 dev_err(&rtc->rtc->dev, "power off failed\n");
 451                 return;
 452         }
 453
 454         rtc_wait_not_busy(rtc);
 455
 456         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
 457         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
 458         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
 459         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
 460         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
 461         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
 462
 463         /*
 464          * enable ALARM2 interrupt
 465          *
 466          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
 467          */
 468         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 469         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
 470                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
 471         rtc->type->lock(rtc);
 472
 473         /*
 474          * Wait for alarm to trigger (within two seconds) and external PMIC to
 475          * power off the system. Add a 500 ms margin for external latencies
 476          * (e.g. debounce circuits).
 477          */
 478         mdelay(2500);
 479 }
 480
 481 static const struct rtc_class_ops omap_rtc_ops = {
 482         .read_time      = omap_rtc_read_time,
 483         .set_time       = omap_rtc_set_time,
 484         .read_alarm     = omap_rtc_read_alarm,
 485         .set_alarm      = omap_rtc_set_alarm,
 486         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
 487 };
 488
 489 static const struct omap_rtc_device_type omap_rtc_default_type = {
 490         .has_power_up_reset = true,
 491         .lock           = default_rtc_lock,
 492         .unlock         = default_rtc_unlock,
 493 };
 494
 495 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
 496         .has_32kclk_en  = true,
 497         .has_irqwakeen  = true,
 498         .has_pmic_mode  = true,
 499         .lock           = am3352_rtc_lock,
 500         .unlock         = am3352_rtc_unlock,
 501 };
 502
 503 static const struct omap_rtc_device_type omap_rtc_da830_type = {
 504         .lock           = am3352_rtc_lock,
 505         .unlock         = am3352_rtc_unlock,
 506 };
 507
 508 static const struct platform_device_id omap_rtc_id_table[] = {
 509         {
 510                 .name   = "omap_rtc",
 511                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
 512         }, {
 513                 .name   = "am3352-rtc",
 514                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
 515         }, {
 516                 .name   = "da830-rtc",
 517                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
 518         }, {
 519                 /* sentinel */
 520         }
 521 };
 522 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
 523
 524 static const struct of_device_id omap_rtc_of_match[] = {
 525         {
 526                 .compatible     = "ti,am3352-rtc",
 527                 .data           = &omap_rtc_am3352_type,
 528         }, {
 529                 .compatible     = "ti,da830-rtc",
 530                 .data           = &omap_rtc_da830_type,
 531         }, {
 532                 /* sentinel */
 533         }
 534 };
 535 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
 536
 537 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
 538         PINCTRL_PIN(0, "ext_wakeup0"),
 539         PINCTRL_PIN(1, "ext_wakeup1"),
 540         PINCTRL_PIN(2, "ext_wakeup2"),
 541         PINCTRL_PIN(3, "ext_wakeup3"),
 542 };
 543
 544 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 545 {
 546         return 0;
 547 }
 548
 549 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 550                                         unsigned int group)
 551 {
 552         return NULL;
 553 }
 554
 555 static const struct pinctrl_ops rtc_pinctrl_ops = {
 556         .get_groups_count = rtc_pinctrl_get_groups_count,
 557         .get_group_name = rtc_pinctrl_get_group_name,
 558         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 559         .dt_free_map = pinconf_generic_dt_free_map,
 560 };
 561
 562 enum rtc_pin_config_param {
 563         PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1,
 564 };
 565
 566 static const struct pinconf_generic_params rtc_params[] = {
 567         {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
 568 };
 569
 570 #ifdef CONFIG_DEBUG_FS
 571 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
 572         PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
 573 };
 574 #endif
 575
 576 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
 577                         unsigned int pin, unsigned long *config)
 578 {
 579         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
 580         unsigned int param = pinconf_to_config_param(*config);
 581         u32 val;
 582         u16 arg = 0;
 583
 584         rtc->type->unlock(rtc);
 585         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 586         rtc->type->lock(rtc);
 587
 588         switch (param) {
 589         case PIN_CONFIG_INPUT_ENABLE:
 590                 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
 591                         return -EINVAL;
 592                 break;
 593         case PIN_CONFIG_ACTIVE_HIGH:
 594                 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
 595                         return -EINVAL;
 596                 break;
 597         default:
 598                 return -ENOTSUPP;
 599         };
 600
 601         *config = pinconf_to_config_packed(param, arg);
 602
 603         return 0;
 604 }
 605
 606 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
 607                         unsigned int pin, unsigned long *configs,
 608                         unsigned int num_configs)
 609 {
 610         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
 611         u32 val;
 612         unsigned int param;
 613         u16 param_val;
 614         int i;
 615
 616         rtc->type->unlock(rtc);
 617         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 618         rtc->type->lock(rtc);
 619
 620         /* active low by default */
 621         val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
 622
 623         for (i = 0; i < num_configs; i++) {
 624                 param = pinconf_to_config_param(configs[i]);
 625                 param_val = pinconf_to_config_argument(configs[i]);
 626
 627                 switch (param) {
 628                 case PIN_CONFIG_INPUT_ENABLE:
 629                         if (param_val)
 630                                 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
 631                         else
 632                                 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
 633                         break;
 634                 case PIN_CONFIG_ACTIVE_HIGH:
 635                         val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
 636                         break;
 637                 default:
 638                         dev_err(&rtc->rtc->dev, "Property %u not supported\n",
 639                                 param);
 640                         return -ENOTSUPP;
 641                 }
 642         }
 643
 644         rtc->type->unlock(rtc);
 645         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
 646         rtc->type->lock(rtc);
 647
 648         return 0;
 649 }
 650
 651 static const struct pinconf_ops rtc_pinconf_ops = {
 652         .is_generic = true,
 653         .pin_config_get = rtc_pinconf_get,
 654         .pin_config_set = rtc_pinconf_set,
 655 };
 656
 657 static struct pinctrl_desc rtc_pinctrl_desc = {
 658         .pins = rtc_pins_desc,
 659         .npins = ARRAY_SIZE(rtc_pins_desc),
 660         .pctlops = &rtc_pinctrl_ops,
 661         .confops = &rtc_pinconf_ops,
 662         .custom_params = rtc_params,
 663         .num_custom_params = ARRAY_SIZE(rtc_params),
 664 #ifdef CONFIG_DEBUG_FS
 665         .custom_conf_items = rtc_conf_items,
 666 #endif
 667         .owner = THIS_MODULE,
 668 };
 669
 670 static int omap_rtc_probe(struct platform_device *pdev)
 671 {
 672         struct omap_rtc *rtc;
 673         struct resource *res;
 674         u8 reg, mask, new_ctrl;
 675         const struct platform_device_id *id_entry;
 676         const struct of_device_id *of_id;
 677         int ret;
 678
 679         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 680         if (!rtc)
 681                 return -ENOMEM;
 682
 683         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
 684         if (of_id) {
 685                 rtc->type = of_id->data;
 686                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
 687                                 of_property_read_bool(pdev->dev.of_node,
 688                                                 "system-power-controller");
 689         } else {
 690                 id_entry = platform_get_device_id(pdev);
 691                 rtc->type = (void *)id_entry->driver_data;
 692         }
 693
 694         rtc->irq_timer = platform_get_irq(pdev, 0);
 695         if (rtc->irq_timer <= 0)
 696                 return -ENOENT;
 697
 698         rtc->irq_alarm = platform_get_irq(pdev, 1);
 699         if (rtc->irq_alarm <= 0)
 700                 return -ENOENT;
 701
 702         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
 703         if (!IS_ERR(rtc->clk))
 704                 rtc->has_ext_clk = true;
 705         else
 706                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
 707
 708         if (!IS_ERR(rtc->clk))
 709                 clk_prepare_enable(rtc->clk);
 710
 711         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 712         rtc->base = devm_ioremap_resource(&pdev->dev, res);
 713         if (IS_ERR(rtc->base))
 714                 return PTR_ERR(rtc->base);
 715
 716         platform_set_drvdata(pdev, rtc);
 717
 718         /* Enable the clock/module so that we can access the registers */
 719         pm_runtime_enable(&pdev->dev);
 720         pm_runtime_get_sync(&pdev->dev);
 721
 722         rtc->type->unlock(rtc);
 723
 724         /*
 725          * disable interrupts
 726          *
 727          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
 728          */
 729         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 730
 731         /* enable RTC functional clock */
 732         if (rtc->type->has_32kclk_en) {
 733                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 734                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
 735                                 reg | OMAP_RTC_OSC_32KCLK_EN);
 736         }
 737
 738         /* clear old status */
 739         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 740
 741         mask = OMAP_RTC_STATUS_ALARM;
 742
 743         if (rtc->type->has_pmic_mode)
 744                 mask |= OMAP_RTC_STATUS_ALARM2;
 745
 746         if (rtc->type->has_power_up_reset) {
 747                 mask |= OMAP_RTC_STATUS_POWER_UP;
 748                 if (reg & OMAP_RTC_STATUS_POWER_UP)
 749                         dev_info(&pdev->dev, "RTC power up reset detected\n");
 750         }
 751
 752         if (reg & mask)
 753                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
 754
 755         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
 756         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
 757         if (reg & OMAP_RTC_CTRL_STOP)
 758                 dev_info(&pdev->dev, "already running\n");
 759
 760         /* force to 24 hour mode */
 761         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
 762         new_ctrl |= OMAP_RTC_CTRL_STOP;
 763
 764         /*
 765          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
 766          *
 767          *  - Device wake-up capability setting should come through chip
 768          *    init logic. OMAP1 boards should initialize the "wakeup capable"
 769          *    flag in the platform device if the board is wired right for
 770          *    being woken up by RTC alarm. For OMAP-L138, this capability
 771          *    is built into the SoC by the "Deep Sleep" capability.
 772          *
 773          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
 774          *    rather than nPWRON_RESET, should forcibly enable split
 775          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
 776          *    is write-only, and always reads as zero...)
 777          */
 778
 779         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
 780                 dev_info(&pdev->dev, "split power mode\n");
 781
 782         if (reg != new_ctrl)
 783                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
 784
 785         /*
 786          * If we have the external clock then switch to it so we can keep
 787          * ticking across suspend.
 788          */
 789         if (rtc->has_ext_clk) {
 790                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 791                 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
 792                 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
 793                 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
 794         }
 795
 796         rtc->type->lock(rtc);
 797
 798         device_init_wakeup(&pdev->dev, true);
 799
 800         rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 801                         &omap_rtc_ops, THIS_MODULE);
 802         if (IS_ERR(rtc->rtc)) {
 803                 ret = PTR_ERR(rtc->rtc);
 804                 goto err;
 805         }
 806
 807         /* handle periodic and alarm irqs */
 808         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
 809                         dev_name(&rtc->rtc->dev), rtc);
 810         if (ret)
 811                 goto err;
 812
 813         if (rtc->irq_timer != rtc->irq_alarm) {
 814                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
 815                                 dev_name(&rtc->rtc->dev), rtc);
 816                 if (ret)
 817                         goto err;
 818         }
 819
 820         if (rtc->is_pmic_controller) {
 821                 if (!pm_power_off) {
 822                         omap_rtc_power_off_rtc = rtc;
 823                         pm_power_off = omap_rtc_power_off;
 824                 }
 825         }
 826
 827         /* Support ext_wakeup pinconf */
 828         rtc_pinctrl_desc.name = dev_name(&pdev->dev);
 829
 830         rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
 831         if (IS_ERR(rtc->pctldev)) {
 832                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 833                 return PTR_ERR(rtc->pctldev);
 834         }
 835
 836         return 0;
 837
 838 err:
 839         device_init_wakeup(&pdev->dev, false);
 840         rtc->type->lock(rtc);
 841         pm_runtime_put_sync(&pdev->dev);
 842         pm_runtime_disable(&pdev->dev);
 843
 844         return ret;
 845 }
 846
 847 static int __exit omap_rtc_remove(struct platform_device *pdev)
 848 {
 849         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 850         u8 reg;
 851
 852         if (pm_power_off == omap_rtc_power_off &&
 853                         omap_rtc_power_off_rtc == rtc) {
 854                 pm_power_off = NULL;
 855                 omap_rtc_power_off_rtc = NULL;
 856         }
 857
 858         device_init_wakeup(&pdev->dev, 0);
 859
 860         if (!IS_ERR(rtc->clk))
 861                 clk_disable_unprepare(rtc->clk);
 862
 863         rtc->type->unlock(rtc);
 864         /* leave rtc running, but disable irqs */
 865         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 866
 867         if (rtc->has_ext_clk) {
 868                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 869                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
 870                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
 871         }
 872
 873         rtc->type->lock(rtc);
 874
 875         /* Disable the clock/module */
 876         pm_runtime_put_sync(&pdev->dev);
 877         pm_runtime_disable(&pdev->dev);
 878
 879         /* Remove ext_wakeup pinconf */
 880         pinctrl_unregister(rtc->pctldev);
 881
 882         return 0;
 883 }
 884
 885 #ifdef CONFIG_PM_SLEEP
 886 static int omap_rtc_suspend(struct device *dev)
 887 {
 888         struct omap_rtc *rtc = dev_get_drvdata(dev);
 889
 890         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 891
 892         rtc->type->unlock(rtc);
 893         /*
 894          * FIXME: the RTC alarm is not currently acting as a wakeup event
 895          * source on some platforms, and in fact this enable() call is just
 896          * saving a flag that's never used...
 897          */
 898         if (device_may_wakeup(dev))
 899                 enable_irq_wake(rtc->irq_alarm);
 900         else
 901                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 902         rtc->type->lock(rtc);
 903
 904         rtc->is_suspending = true;
 905
 906         return 0;
 907 }
 908
 909 static int omap_rtc_resume(struct device *dev)
 910 {
 911         struct omap_rtc *rtc = dev_get_drvdata(dev);
 912
 913         rtc->type->unlock(rtc);
 914         if (device_may_wakeup(dev))
 915                 disable_irq_wake(rtc->irq_alarm);
 916         else
 917                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
 918         rtc->type->lock(rtc);
 919
 920         rtc->is_suspending = false;
 921
 922         return 0;
 923 }
 924 #endif
 925
 926 #ifdef CONFIG_PM
 927 static int omap_rtc_runtime_suspend(struct device *dev)
 928 {
 929         struct omap_rtc *rtc = dev_get_drvdata(dev);
 930
 931         if (rtc->is_suspending && !rtc->has_ext_clk)
 932                 return -EBUSY;
 933
 934         return 0;
 935 }
 936
 937 static int omap_rtc_runtime_resume(struct device *dev)
 938 {
 939         return 0;
 940 }
 941 #endif
 942
 943 static const struct dev_pm_ops omap_rtc_pm_ops = {
 944         SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
 945         SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend,
 946                            omap_rtc_runtime_resume, NULL)
 947 };
 948
 949 static void omap_rtc_shutdown(struct platform_device *pdev)
 950 {
 951         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 952         u8 mask;
 953
 954         /*
 955          * Keep the ALARM interrupt enabled to allow the system to power up on
 956          * alarm events.
 957          */
 958         rtc->type->unlock(rtc);
 959         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 960         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
 961         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
 962         rtc->type->lock(rtc);
 963 }
 964
 965 static struct platform_driver omap_rtc_driver = {
 966         .probe          = omap_rtc_probe,
 967         .remove         = __exit_p(omap_rtc_remove),
 968         .shutdown       = omap_rtc_shutdown,
 969         .driver         = {
 970                 .name   = "omap_rtc",
 971                 .pm     = &omap_rtc_pm_ops,
 972                 .of_match_table = omap_rtc_of_match,
 973         },
 974         .id_table       = omap_rtc_id_table,
 975 };
 976
 977 module_platform_driver(omap_rtc_driver);
 978
 979 MODULE_ALIAS("platform:omap_rtc");
 980 MODULE_AUTHOR("George G. Davis (and others)");
 981 MODULE_LICENSE("GPL");