drivers/rtc/rtc-ds1307.c

   1 /*
   2  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
   3  *
   4  *  Copyright (C) 2005 James Chapman (ds1337 core)
   5  *  Copyright (C) 2006 David Brownell
   6  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
   7  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/bcd.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/rtc/ds1307.h>
  21 #include <linux/rtc.h>
  22 #include <linux/slab.h>
  23 #include <linux/string.h>
  24 #include <linux/hwmon.h>
  25 #include <linux/hwmon-sysfs.h>
  26 #include <linux/clk-provider.h>
  27 #include <linux/regmap.h>
  28
  29 /*
  30  * We can't determine type by probing, but if we expect pre-Linux code
  31  * to have set the chip up as a clock (turning on the oscillator and
  32  * setting the date and time), Linux can ignore the non-clock features.
  33  * That's a natural job for a factory or repair bench.
  34  */
  35 enum ds_type {
  36         ds_1307,
  37         ds_1308,
  38         ds_1337,
  39         ds_1338,
  40         ds_1339,
  41         ds_1340,
  42         ds_1341,
  43         ds_1388,
  44         ds_3231,
  45         m41t0,
  46         m41t00,
  47         m41t11,
  48         mcp794xx,
  49         rx_8025,
  50         rx_8130,
  51         last_ds_type /* always last */
  52         /* rs5c372 too?  different address... */
  53 };
  54
  55 /* RTC registers don't differ much, except for the century flag */
  56 #define DS1307_REG_SECS         0x00    /* 00-59 */
  57 #       define DS1307_BIT_CH            0x80
  58 #       define DS1340_BIT_nEOSC         0x80
  59 #       define MCP794XX_BIT_ST          0x80
  60 #define DS1307_REG_MIN          0x01    /* 00-59 */
  61 #       define M41T0_BIT_OF             0x80
  62 #define DS1307_REG_HOUR         0x02    /* 00-23, or 1-12{am,pm} */
  63 #       define DS1307_BIT_12HR          0x40    /* in REG_HOUR */
  64 #       define DS1307_BIT_PM            0x20    /* in REG_HOUR */
  65 #       define DS1340_BIT_CENTURY_EN    0x80    /* in REG_HOUR */
  66 #       define DS1340_BIT_CENTURY       0x40    /* in REG_HOUR */
  67 #define DS1307_REG_WDAY         0x03    /* 01-07 */
  68 #       define MCP794XX_BIT_VBATEN      0x08
  69 #define DS1307_REG_MDAY         0x04    /* 01-31 */
  70 #define DS1307_REG_MONTH        0x05    /* 01-12 */
  71 #       define DS1337_BIT_CENTURY       0x80    /* in REG_MONTH */
  72 #define DS1307_REG_YEAR         0x06    /* 00-99 */
  73
  74 /*
  75  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  76  * start at 7, and they differ a LOT. Only control and status matter for
  77  * basic RTC date and time functionality; be careful using them.
  78  */
  79 #define DS1307_REG_CONTROL      0x07            /* or ds1338 */
  80 #       define DS1307_BIT_OUT           0x80
  81 #       define DS1338_BIT_OSF           0x20
  82 #       define DS1307_BIT_SQWE          0x10
  83 #       define DS1307_BIT_RS1           0x02
  84 #       define DS1307_BIT_RS0           0x01
  85 #define DS1337_REG_CONTROL      0x0e
  86 #       define DS1337_BIT_nEOSC         0x80
  87 #       define DS1339_BIT_BBSQI         0x20
  88 #       define DS3231_BIT_BBSQW         0x40 /* same as BBSQI */
  89 #       define DS1337_BIT_RS2           0x10
  90 #       define DS1337_BIT_RS1           0x08
  91 #       define DS1337_BIT_INTCN         0x04
  92 #       define DS1337_BIT_A2IE          0x02
  93 #       define DS1337_BIT_A1IE          0x01
  94 #define DS1340_REG_CONTROL      0x07
  95 #       define DS1340_BIT_OUT           0x80
  96 #       define DS1340_BIT_FT            0x40
  97 #       define DS1340_BIT_CALIB_SIGN    0x20
  98 #       define DS1340_M_CALIBRATION     0x1f
  99 #define DS1340_REG_FLAG         0x09
 100 #       define DS1340_BIT_OSF           0x80
 101 #define DS1337_REG_STATUS       0x0f
 102 #       define DS1337_BIT_OSF           0x80
 103 #       define DS3231_BIT_EN32KHZ       0x08
 104 #       define DS1337_BIT_A2I           0x02
 105 #       define DS1337_BIT_A1I           0x01
 106 #define DS1339_REG_ALARM1_SECS  0x07
 107
 108 #define DS13XX_TRICKLE_CHARGER_MAGIC    0xa0
 109
 110 #define RX8025_REG_CTRL1        0x0e
 111 #       define RX8025_BIT_2412          0x20
 112 #define RX8025_REG_CTRL2        0x0f
 113 #       define RX8025_BIT_PON           0x10
 114 #       define RX8025_BIT_VDET          0x40
 115 #       define RX8025_BIT_XST           0x20
 116
 117 #define RX8130_REG_ALARM_MIN            0x17
 118 #define RX8130_REG_ALARM_HOUR           0x18
 119 #define RX8130_REG_ALARM_WEEK_OR_DAY    0x19
 120 #define RX8130_REG_EXTENSION            0x1c
 121 #define RX8130_REG_EXTENSION_WADA       BIT(3)
 122 #define RX8130_REG_FLAG                 0x1d
 123 #define RX8130_REG_FLAG_VLF             BIT(1)
 124 #define RX8130_REG_FLAG_AF              BIT(3)
 125 #define RX8130_REG_CONTROL0             0x1e
 126 #define RX8130_REG_CONTROL0_AIE         BIT(3)
 127
 128 #define MCP794XX_REG_CONTROL            0x07
 129 #       define MCP794XX_BIT_ALM0_EN     0x10
 130 #       define MCP794XX_BIT_ALM1_EN     0x20
 131 #define MCP794XX_REG_ALARM0_BASE        0x0a
 132 #define MCP794XX_REG_ALARM0_CTRL        0x0d
 133 #define MCP794XX_REG_ALARM1_BASE        0x11
 134 #define MCP794XX_REG_ALARM1_CTRL        0x14
 135 #       define MCP794XX_BIT_ALMX_IF     BIT(3)
 136 #       define MCP794XX_BIT_ALMX_C0     BIT(4)
 137 #       define MCP794XX_BIT_ALMX_C1     BIT(5)
 138 #       define MCP794XX_BIT_ALMX_C2     BIT(6)
 139 #       define MCP794XX_BIT_ALMX_POL    BIT(7)
 140 #       define MCP794XX_MSK_ALMX_MATCH  (MCP794XX_BIT_ALMX_C0 | \
 141                                          MCP794XX_BIT_ALMX_C1 | \
 142                                          MCP794XX_BIT_ALMX_C2)
 143
 144 #define M41TXX_REG_CONTROL      0x07
 145 #       define M41TXX_BIT_OUT           BIT(7)
 146 #       define M41TXX_BIT_FT            BIT(6)
 147 #       define M41TXX_BIT_CALIB_SIGN    BIT(5)
 148 #       define M41TXX_M_CALIBRATION     GENMASK(4, 0)
 149
 150 /* negative offset step is -2.034ppm */
 151 #define M41TXX_NEG_OFFSET_STEP_PPB      2034
 152 /* positive offset step is +4.068ppm */
 153 #define M41TXX_POS_OFFSET_STEP_PPB      4068
 154 /* Min and max values supported with 'offset' interface by M41TXX */
 155 #define M41TXX_MIN_OFFSET       ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
 156 #define M41TXX_MAX_OFFSET       ((31) * M41TXX_POS_OFFSET_STEP_PPB)
 157
 158 struct ds1307 {
 159         enum ds_type            type;
 160         unsigned long           flags;
 161 #define HAS_NVRAM       0               /* bit 0 == sysfs file active */
 162 #define HAS_ALARM       1               /* bit 1 == irq claimed */
 163         struct device           *dev;
 164         struct regmap           *regmap;
 165         const char              *name;
 166         struct rtc_device       *rtc;
 167 #ifdef CONFIG_COMMON_CLK
 168         struct clk_hw           clks[2];
 169 #endif
 170 };
 171
 172 struct chip_desc {
 173         unsigned                alarm:1;
 174         u16                     nvram_offset;
 175         u16                     nvram_size;
 176         u8                      offset; /* register's offset */
 177         u8                      century_reg;
 178         u8                      century_enable_bit;
 179         u8                      century_bit;
 180         u8                      bbsqi_bit;
 181         irq_handler_t           irq_handler;
 182         const struct rtc_class_ops *rtc_ops;
 183         u16                     trickle_charger_reg;
 184         u8                      (*do_trickle_setup)(struct ds1307 *, u32,
 185                                                     bool);
 186 };
 187
 188 static const struct chip_desc chips[last_ds_type];
 189
 190 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
 191 {
 192         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 193         int             tmp, ret;
 194         const struct chip_desc *chip = &chips[ds1307->type];
 195         u8 regs[7];
 196
 197         if (ds1307->type == rx_8130) {
 198                 unsigned int regflag;
 199                 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
 200                 if (ret) {
 201                         dev_err(dev, "%s error %d\n", "read", ret);
 202                         return ret;
 203                 }
 204
 205                 if (regflag & RX8130_REG_FLAG_VLF) {
 206                         dev_warn_once(dev, "oscillator failed, set time!\n");
 207                         return -EINVAL;
 208                 }
 209         }
 210
 211         /* read the RTC date and time registers all at once */
 212         ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
 213                                sizeof(regs));
 214         if (ret) {
 215                 dev_err(dev, "%s error %d\n", "read", ret);
 216                 return ret;
 217         }
 218
 219         dev_dbg(dev, "%s: %7ph\n", "read", regs);
 220
 221         /* if oscillator fail bit is set, no data can be trusted */
 222         if (ds1307->type == m41t0 &&
 223             regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
 224                 dev_warn_once(dev, "oscillator failed, set time!\n");
 225                 return -EINVAL;
 226         }
 227
 228         tmp = regs[DS1307_REG_SECS];
 229         switch (ds1307->type) {
 230         case ds_1307:
 231         case m41t0:
 232         case m41t00:
 233         case m41t11:
 234                 if (tmp & DS1307_BIT_CH)
 235                         return -EINVAL;
 236                 break;
 237         case ds_1308:
 238         case ds_1338:
 239                 if (tmp & DS1307_BIT_CH)
 240                         return -EINVAL;
 241
 242                 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
 243                 if (ret)
 244                         return ret;
 245                 if (tmp & DS1338_BIT_OSF)
 246                         return -EINVAL;
 247                 break;
 248         case ds_1340:
 249                 if (tmp & DS1340_BIT_nEOSC)
 250                         return -EINVAL;
 251
 252                 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
 253                 if (ret)
 254                         return ret;
 255                 if (tmp & DS1340_BIT_OSF)
 256                         return -EINVAL;
 257                 break;
 258         case mcp794xx:
 259                 if (!(tmp & MCP794XX_BIT_ST))
 260                         return -EINVAL;
 261
 262                 break;
 263         default:
 264                 break;
 265         }
 266
 267         t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
 268         t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
 269         tmp = regs[DS1307_REG_HOUR] & 0x3f;
 270         t->tm_hour = bcd2bin(tmp);
 271         t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
 272         t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
 273         tmp = regs[DS1307_REG_MONTH] & 0x1f;
 274         t->tm_mon = bcd2bin(tmp) - 1;
 275         t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
 276
 277         if (regs[chip->century_reg] & chip->century_bit &&
 278             IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
 279                 t->tm_year += 100;
 280
 281         dev_dbg(dev, "%s secs=%d, mins=%d, "
 282                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 283                 "read", t->tm_sec, t->tm_min,
 284                 t->tm_hour, t->tm_mday,
 285                 t->tm_mon, t->tm_year, t->tm_wday);
 286
 287         return 0;
 288 }
 289
 290 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
 291 {
 292         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 293         const struct chip_desc *chip = &chips[ds1307->type];
 294         int             result;
 295         int             tmp;
 296         u8              regs[7];
 297
 298         dev_dbg(dev, "%s secs=%d, mins=%d, "
 299                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 300                 "write", t->tm_sec, t->tm_min,
 301                 t->tm_hour, t->tm_mday,
 302                 t->tm_mon, t->tm_year, t->tm_wday);
 303
 304         if (t->tm_year < 100)
 305                 return -EINVAL;
 306
 307 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
 308         if (t->tm_year > (chip->century_bit ? 299 : 199))
 309                 return -EINVAL;
 310 #else
 311         if (t->tm_year > 199)
 312                 return -EINVAL;
 313 #endif
 314
 315         regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
 316         regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
 317         regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
 318         regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
 319         regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
 320         regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
 321
 322         /* assume 20YY not 19YY */
 323         tmp = t->tm_year - 100;
 324         regs[DS1307_REG_YEAR] = bin2bcd(tmp);
 325
 326         if (chip->century_enable_bit)
 327                 regs[chip->century_reg] |= chip->century_enable_bit;
 328         if (t->tm_year > 199 && chip->century_bit)
 329                 regs[chip->century_reg] |= chip->century_bit;
 330
 331         switch (ds1307->type) {
 332         case ds_1308:
 333         case ds_1338:
 334                 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
 335                                    DS1338_BIT_OSF, 0);
 336                 break;
 337         case ds_1340:
 338                 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
 339                                    DS1340_BIT_OSF, 0);
 340                 break;
 341         case mcp794xx:
 342                 /*
 343                  * these bits were cleared when preparing the date/time
 344                  * values and need to be set again before writing the
 345                  * regsfer out to the device.
 346                  */
 347                 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
 348                 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
 349                 break;
 350         default:
 351                 break;
 352         }
 353
 354         dev_dbg(dev, "%s: %7ph\n", "write", regs);
 355
 356         result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
 357                                    sizeof(regs));
 358         if (result) {
 359                 dev_err(dev, "%s error %d\n", "write", result);
 360                 return result;
 361         }
 362
 363         if (ds1307->type == rx_8130) {
 364                 /* clear Voltage Loss Flag as data is available now */
 365                 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
 366                                       ~(u8)RX8130_REG_FLAG_VLF);
 367                 if (result) {
 368                         dev_err(dev, "%s error %d\n", "write", result);
 369                         return result;
 370                 }
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 377 {
 378         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 379         int                     ret;
 380         u8                      regs[9];
 381
 382         if (!test_bit(HAS_ALARM, &ds1307->flags))
 383                 return -EINVAL;
 384
 385         /* read all ALARM1, ALARM2, and status registers at once */
 386         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
 387                                regs, sizeof(regs));
 388         if (ret) {
 389                 dev_err(dev, "%s error %d\n", "alarm read", ret);
 390                 return ret;
 391         }
 392
 393         dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
 394                 &regs[0], &regs[4], &regs[7]);
 395
 396         /*
 397          * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
 398          * and that all four fields are checked matches
 399          */
 400         t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
 401         t->time.tm_min = bcd2bin(regs[1] & 0x7f);
 402         t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
 403         t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
 404
 405         /* ... and status */
 406         t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
 407         t->pending = !!(regs[8] & DS1337_BIT_A1I);
 408
 409         dev_dbg(dev, "%s secs=%d, mins=%d, "
 410                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 411                 "alarm read", t->time.tm_sec, t->time.tm_min,
 412                 t->time.tm_hour, t->time.tm_mday,
 413                 t->enabled, t->pending);
 414
 415         return 0;
 416 }
 417
 418 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 419 {
 420         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 421         unsigned char           regs[9];
 422         u8                      control, status;
 423         int                     ret;
 424
 425         if (!test_bit(HAS_ALARM, &ds1307->flags))
 426                 return -EINVAL;
 427
 428         dev_dbg(dev, "%s secs=%d, mins=%d, "
 429                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 430                 "alarm set", t->time.tm_sec, t->time.tm_min,
 431                 t->time.tm_hour, t->time.tm_mday,
 432                 t->enabled, t->pending);
 433
 434         /* read current status of both alarms and the chip */
 435         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 436                                sizeof(regs));
 437         if (ret) {
 438                 dev_err(dev, "%s error %d\n", "alarm write", ret);
 439                 return ret;
 440         }
 441         control = regs[7];
 442         status = regs[8];
 443
 444         dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
 445                 &regs[0], &regs[4], control, status);
 446
 447         /* set ALARM1, using 24 hour and day-of-month modes */
 448         regs[0] = bin2bcd(t->time.tm_sec);
 449         regs[1] = bin2bcd(t->time.tm_min);
 450         regs[2] = bin2bcd(t->time.tm_hour);
 451         regs[3] = bin2bcd(t->time.tm_mday);
 452
 453         /* set ALARM2 to non-garbage */
 454         regs[4] = 0;
 455         regs[5] = 0;
 456         regs[6] = 0;
 457
 458         /* disable alarms */
 459         regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
 460         regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
 461
 462         ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 463                                 sizeof(regs));
 464         if (ret) {
 465                 dev_err(dev, "can't set alarm time\n");
 466                 return ret;
 467         }
 468
 469         /* optionally enable ALARM1 */
 470         if (t->enabled) {
 471                 dev_dbg(dev, "alarm IRQ armed\n");
 472                 regs[7] |= DS1337_BIT_A1IE;     /* only ALARM1 is used */
 473                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
 480 {
 481         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 482
 483         if (!test_bit(HAS_ALARM, &ds1307->flags))
 484                 return -ENOTTY;
 485
 486         return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 487                                   DS1337_BIT_A1IE,
 488                                   enabled ? DS1337_BIT_A1IE : 0);
 489 }
 490
 491 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
 492 {
 493         u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
 494                 DS1307_TRICKLE_CHARGER_NO_DIODE;
 495
 496         switch (ohms) {
 497         case 250:
 498                 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
 499                 break;
 500         case 2000:
 501                 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
 502                 break;
 503         case 4000:
 504                 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
 505                 break;
 506         default:
 507                 dev_warn(ds1307->dev,
 508                          "Unsupported ohm value %u in dt\n", ohms);
 509                 return 0;
 510         }
 511         return setup;
 512 }
 513
 514 static irqreturn_t rx8130_irq(int irq, void *dev_id)
 515 {
 516         struct ds1307           *ds1307 = dev_id;
 517         struct mutex            *lock = &ds1307->rtc->ops_lock;
 518         u8 ctl[3];
 519         int ret;
 520
 521         mutex_lock(lock);
 522
 523         /* Read control registers. */
 524         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 525                                sizeof(ctl));
 526         if (ret < 0)
 527                 goto out;
 528         if (!(ctl[1] & RX8130_REG_FLAG_AF))
 529                 goto out;
 530         ctl[1] &= ~RX8130_REG_FLAG_AF;
 531         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 532
 533         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 534                                 sizeof(ctl));
 535         if (ret < 0)
 536                 goto out;
 537
 538         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 539
 540 out:
 541         mutex_unlock(lock);
 542
 543         return IRQ_HANDLED;
 544 }
 545
 546 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 547 {
 548         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 549         u8 ald[3], ctl[3];
 550         int ret;
 551
 552         if (!test_bit(HAS_ALARM, &ds1307->flags))
 553                 return -EINVAL;
 554
 555         /* Read alarm registers. */
 556         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 557                                sizeof(ald));
 558         if (ret < 0)
 559                 return ret;
 560
 561         /* Read control registers. */
 562         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 563                                sizeof(ctl));
 564         if (ret < 0)
 565                 return ret;
 566
 567         t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
 568         t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
 569
 570         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 571         t->time.tm_sec = -1;
 572         t->time.tm_min = bcd2bin(ald[0] & 0x7f);
 573         t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
 574         t->time.tm_wday = -1;
 575         t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
 576         t->time.tm_mon = -1;
 577         t->time.tm_year = -1;
 578         t->time.tm_yday = -1;
 579         t->time.tm_isdst = -1;
 580
 581         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
 582                 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 583                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
 584
 585         return 0;
 586 }
 587
 588 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 589 {
 590         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 591         u8 ald[3], ctl[3];
 592         int ret;
 593
 594         if (!test_bit(HAS_ALARM, &ds1307->flags))
 595                 return -EINVAL;
 596
 597         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 598                 "enabled=%d pending=%d\n", __func__,
 599                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 600                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 601                 t->enabled, t->pending);
 602
 603         /* Read control registers. */
 604         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 605                                sizeof(ctl));
 606         if (ret < 0)
 607                 return ret;
 608
 609         ctl[0] &= RX8130_REG_EXTENSION_WADA;
 610         ctl[1] &= ~RX8130_REG_FLAG_AF;
 611         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 612
 613         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 614                                 sizeof(ctl));
 615         if (ret < 0)
 616                 return ret;
 617
 618         /* Hardware alarm precision is 1 minute! */
 619         ald[0] = bin2bcd(t->time.tm_min);
 620         ald[1] = bin2bcd(t->time.tm_hour);
 621         ald[2] = bin2bcd(t->time.tm_mday);
 622
 623         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 624                                 sizeof(ald));
 625         if (ret < 0)
 626                 return ret;
 627
 628         if (!t->enabled)
 629                 return 0;
 630
 631         ctl[2] |= RX8130_REG_CONTROL0_AIE;
 632
 633         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
 634 }
 635
 636 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
 637 {
 638         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 639         int ret, reg;
 640
 641         if (!test_bit(HAS_ALARM, &ds1307->flags))
 642                 return -EINVAL;
 643
 644         ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
 645         if (ret < 0)
 646                 return ret;
 647
 648         if (enabled)
 649                 reg |= RX8130_REG_CONTROL0_AIE;
 650         else
 651                 reg &= ~RX8130_REG_CONTROL0_AIE;
 652
 653         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
 654 }
 655
 656 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
 657 {
 658         struct ds1307           *ds1307 = dev_id;
 659         struct mutex            *lock = &ds1307->rtc->ops_lock;
 660         int reg, ret;
 661
 662         mutex_lock(lock);
 663
 664         /* Check and clear alarm 0 interrupt flag. */
 665         ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
 666         if (ret)
 667                 goto out;
 668         if (!(reg & MCP794XX_BIT_ALMX_IF))
 669                 goto out;
 670         reg &= ~MCP794XX_BIT_ALMX_IF;
 671         ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
 672         if (ret)
 673                 goto out;
 674
 675         /* Disable alarm 0. */
 676         ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 677                                  MCP794XX_BIT_ALM0_EN, 0);
 678         if (ret)
 679                 goto out;
 680
 681         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 682
 683 out:
 684         mutex_unlock(lock);
 685
 686         return IRQ_HANDLED;
 687 }
 688
 689 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 690 {
 691         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 692         u8 regs[10];
 693         int ret;
 694
 695         if (!test_bit(HAS_ALARM, &ds1307->flags))
 696                 return -EINVAL;
 697
 698         /* Read control and alarm 0 registers. */
 699         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 700                                sizeof(regs));
 701         if (ret)
 702                 return ret;
 703
 704         t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
 705
 706         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 707         t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
 708         t->time.tm_min = bcd2bin(regs[4] & 0x7f);
 709         t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
 710         t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
 711         t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
 712         t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
 713         t->time.tm_year = -1;
 714         t->time.tm_yday = -1;
 715         t->time.tm_isdst = -1;
 716
 717         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 718                 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
 719                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 720                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
 721                 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
 722                 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
 723                 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
 724
 725         return 0;
 726 }
 727
 728 /*
 729  * We may have a random RTC weekday, therefore calculate alarm weekday based
 730  * on current weekday we read from the RTC timekeeping regs
 731  */
 732 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
 733 {
 734         struct rtc_time tm_now;
 735         int days_now, days_alarm, ret;
 736
 737         ret = ds1307_get_time(dev, &tm_now);
 738         if (ret)
 739                 return ret;
 740
 741         days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
 742         days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
 743
 744         return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
 745 }
 746
 747 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 748 {
 749         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 750         unsigned char regs[10];
 751         int wday, ret;
 752
 753         if (!test_bit(HAS_ALARM, &ds1307->flags))
 754                 return -EINVAL;
 755
 756         wday = mcp794xx_alm_weekday(dev, &t->time);
 757         if (wday < 0)
 758                 return wday;
 759
 760         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 761                 "enabled=%d pending=%d\n", __func__,
 762                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 763                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 764                 t->enabled, t->pending);
 765
 766         /* Read control and alarm 0 registers. */
 767         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 768                                sizeof(regs));
 769         if (ret)
 770                 return ret;
 771
 772         /* Set alarm 0, using 24-hour and day-of-month modes. */
 773         regs[3] = bin2bcd(t->time.tm_sec);
 774         regs[4] = bin2bcd(t->time.tm_min);
 775         regs[5] = bin2bcd(t->time.tm_hour);
 776         regs[6] = wday;
 777         regs[7] = bin2bcd(t->time.tm_mday);
 778         regs[8] = bin2bcd(t->time.tm_mon + 1);
 779
 780         /* Clear the alarm 0 interrupt flag. */
 781         regs[6] &= ~MCP794XX_BIT_ALMX_IF;
 782         /* Set alarm match: second, minute, hour, day, date, month. */
 783         regs[6] |= MCP794XX_MSK_ALMX_MATCH;
 784         /* Disable interrupt. We will not enable until completely programmed */
 785         regs[0] &= ~MCP794XX_BIT_ALM0_EN;
 786
 787         ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 788                                 sizeof(regs));
 789         if (ret)
 790                 return ret;
 791
 792         if (!t->enabled)
 793                 return 0;
 794         regs[0] |= MCP794XX_BIT_ALM0_EN;
 795         return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
 796 }
 797
 798 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 799 {
 800         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 801
 802         if (!test_bit(HAS_ALARM, &ds1307->flags))
 803                 return -EINVAL;
 804
 805         return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 806                                   MCP794XX_BIT_ALM0_EN,
 807                                   enabled ? MCP794XX_BIT_ALM0_EN : 0);
 808 }
 809
 810 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
 811 {
 812         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 813         unsigned int ctrl_reg;
 814         u8 val;
 815
 816         regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
 817
 818         val = ctrl_reg & M41TXX_M_CALIBRATION;
 819
 820         /* check if positive */
 821         if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
 822                 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
 823         else
 824                 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
 825
 826         return 0;
 827 }
 828
 829 static int m41txx_rtc_set_offset(struct device *dev, long offset)
 830 {
 831         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 832         unsigned int ctrl_reg;
 833
 834         if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
 835                 return -ERANGE;
 836
 837         if (offset >= 0) {
 838                 ctrl_reg = DIV_ROUND_CLOSEST(offset,
 839                                              M41TXX_POS_OFFSET_STEP_PPB);
 840                 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
 841         } else {
 842                 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
 843                                              M41TXX_NEG_OFFSET_STEP_PPB);
 844         }
 845
 846         return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
 847                                   M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
 848                                   ctrl_reg);
 849 }
 850
 851 static const struct rtc_class_ops rx8130_rtc_ops = {
 852         .read_time      = ds1307_get_time,
 853         .set_time       = ds1307_set_time,
 854         .read_alarm     = rx8130_read_alarm,
 855         .set_alarm      = rx8130_set_alarm,
 856         .alarm_irq_enable = rx8130_alarm_irq_enable,
 857 };
 858
 859 static const struct rtc_class_ops mcp794xx_rtc_ops = {
 860         .read_time      = ds1307_get_time,
 861         .set_time       = ds1307_set_time,
 862         .read_alarm     = mcp794xx_read_alarm,
 863         .set_alarm      = mcp794xx_set_alarm,
 864         .alarm_irq_enable = mcp794xx_alarm_irq_enable,
 865 };
 866
 867 static const struct rtc_class_ops m41txx_rtc_ops = {
 868         .read_time      = ds1307_get_time,
 869         .set_time       = ds1307_set_time,
 870         .read_alarm     = ds1337_read_alarm,
 871         .set_alarm      = ds1337_set_alarm,
 872         .alarm_irq_enable = ds1307_alarm_irq_enable,
 873         .read_offset    = m41txx_rtc_read_offset,
 874         .set_offset     = m41txx_rtc_set_offset,
 875 };
 876
 877 static const struct chip_desc chips[last_ds_type] = {
 878         [ds_1307] = {
 879                 .nvram_offset   = 8,
 880                 .nvram_size     = 56,
 881         },
 882         [ds_1308] = {
 883                 .nvram_offset   = 8,
 884                 .nvram_size     = 56,
 885         },
 886         [ds_1337] = {
 887                 .alarm          = 1,
 888                 .century_reg    = DS1307_REG_MONTH,
 889                 .century_bit    = DS1337_BIT_CENTURY,
 890         },
 891         [ds_1338] = {
 892                 .nvram_offset   = 8,
 893                 .nvram_size     = 56,
 894         },
 895         [ds_1339] = {
 896                 .alarm          = 1,
 897                 .century_reg    = DS1307_REG_MONTH,
 898                 .century_bit    = DS1337_BIT_CENTURY,
 899                 .bbsqi_bit      = DS1339_BIT_BBSQI,
 900                 .trickle_charger_reg = 0x10,
 901                 .do_trickle_setup = &do_trickle_setup_ds1339,
 902         },
 903         [ds_1340] = {
 904                 .century_reg    = DS1307_REG_HOUR,
 905                 .century_enable_bit = DS1340_BIT_CENTURY_EN,
 906                 .century_bit    = DS1340_BIT_CENTURY,
 907                 .do_trickle_setup = &do_trickle_setup_ds1339,
 908                 .trickle_charger_reg = 0x08,
 909         },
 910         [ds_1341] = {
 911                 .century_reg    = DS1307_REG_MONTH,
 912                 .century_bit    = DS1337_BIT_CENTURY,
 913         },
 914         [ds_1388] = {
 915                 .offset         = 1,
 916                 .trickle_charger_reg = 0x0a,
 917         },
 918         [ds_3231] = {
 919                 .alarm          = 1,
 920                 .century_reg    = DS1307_REG_MONTH,
 921                 .century_bit    = DS1337_BIT_CENTURY,
 922                 .bbsqi_bit      = DS3231_BIT_BBSQW,
 923         },
 924         [rx_8130] = {
 925                 .alarm          = 1,
 926                 /* this is battery backed SRAM */
 927                 .nvram_offset   = 0x20,
 928                 .nvram_size     = 4,    /* 32bit (4 word x 8 bit) */
 929                 .offset         = 0x10,
 930                 .irq_handler = rx8130_irq,
 931                 .rtc_ops = &rx8130_rtc_ops,
 932         },
 933         [m41t0] = {
 934                 .rtc_ops        = &m41txx_rtc_ops,
 935         },
 936         [m41t00] = {
 937                 .rtc_ops        = &m41txx_rtc_ops,
 938         },
 939         [m41t11] = {
 940                 /* this is battery backed SRAM */
 941                 .nvram_offset   = 8,
 942                 .nvram_size     = 56,
 943                 .rtc_ops        = &m41txx_rtc_ops,
 944         },
 945         [mcp794xx] = {
 946                 .alarm          = 1,
 947                 /* this is battery backed SRAM */
 948                 .nvram_offset   = 0x20,
 949                 .nvram_size     = 0x40,
 950                 .irq_handler = mcp794xx_irq,
 951                 .rtc_ops = &mcp794xx_rtc_ops,
 952         },
 953 };
 954
 955 static const struct i2c_device_id ds1307_id[] = {
 956         { "ds1307", ds_1307 },
 957         { "ds1308", ds_1308 },
 958         { "ds1337", ds_1337 },
 959         { "ds1338", ds_1338 },
 960         { "ds1339", ds_1339 },
 961         { "ds1388", ds_1388 },
 962         { "ds1340", ds_1340 },
 963         { "ds1341", ds_1341 },
 964         { "ds3231", ds_3231 },
 965         { "m41t0", m41t0 },
 966         { "m41t00", m41t00 },
 967         { "m41t11", m41t11 },
 968         { "mcp7940x", mcp794xx },
 969         { "mcp7941x", mcp794xx },
 970         { "pt7c4338", ds_1307 },
 971         { "rx8025", rx_8025 },
 972         { "isl12057", ds_1337 },
 973         { "rx8130", rx_8130 },
 974         { }
 975 };
 976 MODULE_DEVICE_TABLE(i2c, ds1307_id);
 977
 978 #ifdef CONFIG_OF
 979 static const struct of_device_id ds1307_of_match[] = {
 980         {
 981                 .compatible = "dallas,ds1307",
 982                 .data = (void *)ds_1307
 983         },
 984         {
 985                 .compatible = "dallas,ds1308",
 986                 .data = (void *)ds_1308
 987         },
 988         {
 989                 .compatible = "dallas,ds1337",
 990                 .data = (void *)ds_1337
 991         },
 992         {
 993                 .compatible = "dallas,ds1338",
 994                 .data = (void *)ds_1338
 995         },
 996         {
 997                 .compatible = "dallas,ds1339",
 998                 .data = (void *)ds_1339
 999         },
1000         {
1001                 .compatible = "dallas,ds1388",
1002                 .data = (void *)ds_1388
1003         },
1004         {
1005                 .compatible = "dallas,ds1340",
1006                 .data = (void *)ds_1340
1007         },
1008         {
1009                 .compatible = "dallas,ds1341",
1010                 .data = (void *)ds_1341
1011         },
1012         {
1013                 .compatible = "maxim,ds3231",
1014                 .data = (void *)ds_3231
1015         },
1016         {
1017                 .compatible = "st,m41t0",
1018                 .data = (void *)m41t0
1019         },
1020         {
1021                 .compatible = "st,m41t00",
1022                 .data = (void *)m41t00
1023         },
1024         {
1025                 .compatible = "st,m41t11",
1026                 .data = (void *)m41t11
1027         },
1028         {
1029                 .compatible = "microchip,mcp7940x",
1030                 .data = (void *)mcp794xx
1031         },
1032         {
1033                 .compatible = "microchip,mcp7941x",
1034                 .data = (void *)mcp794xx
1035         },
1036         {
1037                 .compatible = "pericom,pt7c4338",
1038                 .data = (void *)ds_1307
1039         },
1040         {
1041                 .compatible = "epson,rx8025",
1042                 .data = (void *)rx_8025
1043         },
1044         {
1045                 .compatible = "isil,isl12057",
1046                 .data = (void *)ds_1337
1047         },
1048         {
1049                 .compatible = "epson,rx8130",
1050                 .data = (void *)rx_8130
1051         },
1052         { }
1053 };
1054 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1055 #endif
1056
1057 #ifdef CONFIG_ACPI
1058 static const struct acpi_device_id ds1307_acpi_ids[] = {
1059         { .id = "DS1307", .driver_data = ds_1307 },
1060         { .id = "DS1308", .driver_data = ds_1308 },
1061         { .id = "DS1337", .driver_data = ds_1337 },
1062         { .id = "DS1338", .driver_data = ds_1338 },
1063         { .id = "DS1339", .driver_data = ds_1339 },
1064         { .id = "DS1388", .driver_data = ds_1388 },
1065         { .id = "DS1340", .driver_data = ds_1340 },
1066         { .id = "DS1341", .driver_data = ds_1341 },
1067         { .id = "DS3231", .driver_data = ds_3231 },
1068         { .id = "M41T0", .driver_data = m41t0 },
1069         { .id = "M41T00", .driver_data = m41t00 },
1070         { .id = "M41T11", .driver_data = m41t11 },
1071         { .id = "MCP7940X", .driver_data = mcp794xx },
1072         { .id = "MCP7941X", .driver_data = mcp794xx },
1073         { .id = "PT7C4338", .driver_data = ds_1307 },
1074         { .id = "RX8025", .driver_data = rx_8025 },
1075         { .id = "ISL12057", .driver_data = ds_1337 },
1076         { .id = "RX8130", .driver_data = rx_8130 },
1077         { }
1078 };
1079 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1080 #endif
1081
1082 /*
1083  * The ds1337 and ds1339 both have two alarms, but we only use the first
1084  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
1085  * signal; ds1339 chips have only one alarm signal.
1086  */
1087 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1088 {
1089         struct ds1307           *ds1307 = dev_id;
1090         struct mutex            *lock = &ds1307->rtc->ops_lock;
1091         int                     stat, ret;
1092
1093         mutex_lock(lock);
1094         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1095         if (ret)
1096                 goto out;
1097
1098         if (stat & DS1337_BIT_A1I) {
1099                 stat &= ~DS1337_BIT_A1I;
1100                 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1101
1102                 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1103                                          DS1337_BIT_A1IE, 0);
1104                 if (ret)
1105                         goto out;
1106
1107                 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1108         }
1109
1110 out:
1111         mutex_unlock(lock);
1112
1113         return IRQ_HANDLED;
1114 }
1115
1116 /*----------------------------------------------------------------------*/
1117
1118 static const struct rtc_class_ops ds13xx_rtc_ops = {
1119         .read_time      = ds1307_get_time,
1120         .set_time       = ds1307_set_time,
1121         .read_alarm     = ds1337_read_alarm,
1122         .set_alarm      = ds1337_set_alarm,
1123         .alarm_irq_enable = ds1307_alarm_irq_enable,
1124 };
1125
1126 static ssize_t frequency_test_store(struct device *dev,
1127                                     struct device_attribute *attr,
1128                                     const char *buf, size_t count)
1129 {
1130         struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1131         bool freq_test_en;
1132         int ret;
1133
1134         ret = kstrtobool(buf, &freq_test_en);
1135         if (ret) {
1136                 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1137                 return ret;
1138         }
1139
1140         regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1141                            freq_test_en ? M41TXX_BIT_FT : 0);
1142
1143         return count;
1144 }
1145
1146 static ssize_t frequency_test_show(struct device *dev,
1147                                    struct device_attribute *attr,
1148                                    char *buf)
1149 {
1150         struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1151         unsigned int ctrl_reg;
1152
1153         regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1154
1155         return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1156                         "off\n");
1157 }
1158
1159 static DEVICE_ATTR_RW(frequency_test);
1160
1161 static struct attribute *rtc_freq_test_attrs[] = {
1162         &dev_attr_frequency_test.attr,
1163         NULL,
1164 };
1165
1166 static const struct attribute_group rtc_freq_test_attr_group = {
1167         .attrs          = rtc_freq_test_attrs,
1168 };
1169
1170 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1171 {
1172         int err;
1173
1174         switch (ds1307->type) {
1175         case m41t0:
1176         case m41t00:
1177         case m41t11:
1178                 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1179                 if (err)
1180                         return err;
1181                 break;
1182         default:
1183                 break;
1184         }
1185
1186         return 0;
1187 }
1188
1189 /*----------------------------------------------------------------------*/
1190
1191 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1192                              size_t bytes)
1193 {
1194         struct ds1307 *ds1307 = priv;
1195         const struct chip_desc *chip = &chips[ds1307->type];
1196
1197         return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1198                                 val, bytes);
1199 }
1200
1201 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1202                               size_t bytes)
1203 {
1204         struct ds1307 *ds1307 = priv;
1205         const struct chip_desc *chip = &chips[ds1307->type];
1206
1207         return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1208                                  val, bytes);
1209 }
1210
1211 /*----------------------------------------------------------------------*/
1212
1213 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1214                               const struct chip_desc *chip)
1215 {
1216         u32 ohms;
1217         bool diode = true;
1218
1219         if (!chip->do_trickle_setup)
1220                 return 0;
1221
1222         if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1223                                      &ohms))
1224                 return 0;
1225
1226         if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1227                 diode = false;
1228
1229         return chip->do_trickle_setup(ds1307, ohms, diode);
1230 }
1231
1232 /*----------------------------------------------------------------------*/
1233
1234 #if IS_REACHABLE(CONFIG_HWMON)
1235
1236 /*
1237  * Temperature sensor support for ds3231 devices.
1238  */
1239
1240 #define DS3231_REG_TEMPERATURE  0x11
1241
1242 /*
1243  * A user-initiated temperature conversion is not started by this function,
1244  * so the temperature is updated once every 64 seconds.
1245  */
1246 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1247 {
1248         struct ds1307 *ds1307 = dev_get_drvdata(dev);
1249         u8 temp_buf[2];
1250         s16 temp;
1251         int ret;
1252
1253         ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1254                                temp_buf, sizeof(temp_buf));
1255         if (ret)
1256                 return ret;
1257         /*
1258          * Temperature is represented as a 10-bit code with a resolution of
1259          * 0.25 degree celsius and encoded in two's complement format.
1260          */
1261         temp = (temp_buf[0] << 8) | temp_buf[1];
1262         temp >>= 6;
1263         *mC = temp * 250;
1264
1265         return 0;
1266 }
1267
1268 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1269                                       struct device_attribute *attr, char *buf)
1270 {
1271         int ret;
1272         s32 temp;
1273
1274         ret = ds3231_hwmon_read_temp(dev, &temp);
1275         if (ret)
1276                 return ret;
1277
1278         return sprintf(buf, "%d\n", temp);
1279 }
1280 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1281                           NULL, 0);
1282
1283 static struct attribute *ds3231_hwmon_attrs[] = {
1284         &sensor_dev_attr_temp1_input.dev_attr.attr,
1285         NULL,
1286 };
1287 ATTRIBUTE_GROUPS(ds3231_hwmon);
1288
1289 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1290 {
1291         struct device *dev;
1292
1293         if (ds1307->type != ds_3231)
1294                 return;
1295
1296         dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1297                                                      ds1307,
1298                                                      ds3231_hwmon_groups);
1299         if (IS_ERR(dev)) {
1300                 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1301                          PTR_ERR(dev));
1302         }
1303 }
1304
1305 #else
1306
1307 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1308 {
1309 }
1310
1311 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1312
1313 /*----------------------------------------------------------------------*/
1314
1315 /*
1316  * Square-wave output support for DS3231
1317  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1318  */
1319 #ifdef CONFIG_COMMON_CLK
1320
1321 enum {
1322         DS3231_CLK_SQW = 0,
1323         DS3231_CLK_32KHZ,
1324 };
1325
1326 #define clk_sqw_to_ds1307(clk)  \
1327         container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1328 #define clk_32khz_to_ds1307(clk)        \
1329         container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1330
1331 static int ds3231_clk_sqw_rates[] = {
1332         1,
1333         1024,
1334         4096,
1335         8192,
1336 };
1337
1338 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1339 {
1340         struct mutex *lock = &ds1307->rtc->ops_lock;
1341         int ret;
1342
1343         mutex_lock(lock);
1344         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1345                                  mask, value);
1346         mutex_unlock(lock);
1347
1348         return ret;
1349 }
1350
1351 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1352                                                 unsigned long parent_rate)
1353 {
1354         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1355         int control, ret;
1356         int rate_sel = 0;
1357
1358         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1359         if (ret)
1360                 return ret;
1361         if (control & DS1337_BIT_RS1)
1362                 rate_sel += 1;
1363         if (control & DS1337_BIT_RS2)
1364                 rate_sel += 2;
1365
1366         return ds3231_clk_sqw_rates[rate_sel];
1367 }
1368
1369 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1370                                       unsigned long *prate)
1371 {
1372         int i;
1373
1374         for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1375                 if (ds3231_clk_sqw_rates[i] <= rate)
1376                         return ds3231_clk_sqw_rates[i];
1377         }
1378
1379         return 0;
1380 }
1381
1382 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1383                                    unsigned long parent_rate)
1384 {
1385         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1386         int control = 0;
1387         int rate_sel;
1388
1389         for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1390                         rate_sel++) {
1391                 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1392                         break;
1393         }
1394
1395         if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1396                 return -EINVAL;
1397
1398         if (rate_sel & 1)
1399                 control |= DS1337_BIT_RS1;
1400         if (rate_sel & 2)
1401                 control |= DS1337_BIT_RS2;
1402
1403         return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1404                                 control);
1405 }
1406
1407 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1408 {
1409         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1410
1411         return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1412 }
1413
1414 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1415 {
1416         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1417
1418         ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1419 }
1420
1421 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1422 {
1423         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1424         int control, ret;
1425
1426         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1427         if (ret)
1428                 return ret;
1429
1430         return !(control & DS1337_BIT_INTCN);
1431 }
1432
1433 static const struct clk_ops ds3231_clk_sqw_ops = {
1434         .prepare = ds3231_clk_sqw_prepare,
1435         .unprepare = ds3231_clk_sqw_unprepare,
1436         .is_prepared = ds3231_clk_sqw_is_prepared,
1437         .recalc_rate = ds3231_clk_sqw_recalc_rate,
1438         .round_rate = ds3231_clk_sqw_round_rate,
1439         .set_rate = ds3231_clk_sqw_set_rate,
1440 };
1441
1442 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1443                                                   unsigned long parent_rate)
1444 {
1445         return 32768;
1446 }
1447
1448 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1449 {
1450         struct mutex *lock = &ds1307->rtc->ops_lock;
1451         int ret;
1452
1453         mutex_lock(lock);
1454         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1455                                  DS3231_BIT_EN32KHZ,
1456                                  enable ? DS3231_BIT_EN32KHZ : 0);
1457         mutex_unlock(lock);
1458
1459         return ret;
1460 }
1461
1462 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1463 {
1464         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1465
1466         return ds3231_clk_32khz_control(ds1307, true);
1467 }
1468
1469 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1470 {
1471         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1472
1473         ds3231_clk_32khz_control(ds1307, false);
1474 }
1475
1476 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1477 {
1478         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1479         int status, ret;
1480
1481         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1482         if (ret)
1483                 return ret;
1484
1485         return !!(status & DS3231_BIT_EN32KHZ);
1486 }
1487
1488 static const struct clk_ops ds3231_clk_32khz_ops = {
1489         .prepare = ds3231_clk_32khz_prepare,
1490         .unprepare = ds3231_clk_32khz_unprepare,
1491         .is_prepared = ds3231_clk_32khz_is_prepared,
1492         .recalc_rate = ds3231_clk_32khz_recalc_rate,
1493 };
1494
1495 static struct clk_init_data ds3231_clks_init[] = {
1496         [DS3231_CLK_SQW] = {
1497                 .name = "ds3231_clk_sqw",
1498                 .ops = &ds3231_clk_sqw_ops,
1499         },
1500         [DS3231_CLK_32KHZ] = {
1501                 .name = "ds3231_clk_32khz",
1502                 .ops = &ds3231_clk_32khz_ops,
1503         },
1504 };
1505
1506 static int ds3231_clks_register(struct ds1307 *ds1307)
1507 {
1508         struct device_node *node = ds1307->dev->of_node;
1509         struct clk_onecell_data *onecell;
1510         int i;
1511
1512         onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1513         if (!onecell)
1514                 return -ENOMEM;
1515
1516         onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1517         onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1518                                      sizeof(onecell->clks[0]), GFP_KERNEL);
1519         if (!onecell->clks)
1520                 return -ENOMEM;
1521
1522         for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1523                 struct clk_init_data init = ds3231_clks_init[i];
1524
1525                 /*
1526                  * Interrupt signal due to alarm conditions and square-wave
1527                  * output share same pin, so don't initialize both.
1528                  */
1529                 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1530                         continue;
1531
1532                 /* optional override of the clockname */
1533                 of_property_read_string_index(node, "clock-output-names", i,
1534                                               &init.name);
1535                 ds1307->clks[i].init = &init;
1536
1537                 onecell->clks[i] = devm_clk_register(ds1307->dev,
1538                                                      &ds1307->clks[i]);
1539                 if (IS_ERR(onecell->clks[i]))
1540                         return PTR_ERR(onecell->clks[i]);
1541         }
1542
1543         if (!node)
1544                 return 0;
1545
1546         of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1547
1548         return 0;
1549 }
1550
1551 static void ds1307_clks_register(struct ds1307 *ds1307)
1552 {
1553         int ret;
1554
1555         if (ds1307->type != ds_3231)
1556                 return;
1557
1558         ret = ds3231_clks_register(ds1307);
1559         if (ret) {
1560                 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1561                          ret);
1562         }
1563 }
1564
1565 #else
1566
1567 static void ds1307_clks_register(struct ds1307 *ds1307)
1568 {
1569 }
1570
1571 #endif /* CONFIG_COMMON_CLK */
1572
1573 static const struct regmap_config regmap_config = {
1574         .reg_bits = 8,
1575         .val_bits = 8,
1576 };
1577
1578 static int ds1307_probe(struct i2c_client *client,
1579                         const struct i2c_device_id *id)
1580 {
1581         struct ds1307           *ds1307;
1582         int                     err = -ENODEV;
1583         int                     tmp;
1584         const struct chip_desc  *chip;
1585         bool                    want_irq;
1586         bool                    ds1307_can_wakeup_device = false;
1587         unsigned char           regs[8];
1588         struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1589         u8                      trickle_charger_setup = 0;
1590
1591         ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1592         if (!ds1307)
1593                 return -ENOMEM;
1594
1595         dev_set_drvdata(&client->dev, ds1307);
1596         ds1307->dev = &client->dev;
1597         ds1307->name = client->name;
1598
1599         ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1600         if (IS_ERR(ds1307->regmap)) {
1601                 dev_err(ds1307->dev, "regmap allocation failed\n");
1602                 return PTR_ERR(ds1307->regmap);
1603         }
1604
1605         i2c_set_clientdata(client, ds1307);
1606
1607         if (client->dev.of_node) {
1608                 ds1307->type = (enum ds_type)
1609                         of_device_get_match_data(&client->dev);
1610                 chip = &chips[ds1307->type];
1611         } else if (id) {
1612                 chip = &chips[id->driver_data];
1613                 ds1307->type = id->driver_data;
1614         } else {
1615                 const struct acpi_device_id *acpi_id;
1616
1617                 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1618                                             ds1307->dev);
1619                 if (!acpi_id)
1620                         return -ENODEV;
1621                 chip = &chips[acpi_id->driver_data];
1622                 ds1307->type = acpi_id->driver_data;
1623         }
1624
1625         want_irq = client->irq > 0 && chip->alarm;
1626
1627         if (!pdata)
1628                 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1629         else if (pdata->trickle_charger_setup)
1630                 trickle_charger_setup = pdata->trickle_charger_setup;
1631
1632         if (trickle_charger_setup && chip->trickle_charger_reg) {
1633                 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1634                 dev_dbg(ds1307->dev,
1635                         "writing trickle charger info 0x%x to 0x%x\n",
1636                         trickle_charger_setup, chip->trickle_charger_reg);
1637                 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1638                              trickle_charger_setup);
1639         }
1640
1641 #ifdef CONFIG_OF
1642 /*
1643  * For devices with no IRQ directly connected to the SoC, the RTC chip
1644  * can be forced as a wakeup source by stating that explicitly in
1645  * the device's .dts file using the "wakeup-source" boolean property.
1646  * If the "wakeup-source" property is set, don't request an IRQ.
1647  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1648  * if supported by the RTC.
1649  */
1650         if (chip->alarm && of_property_read_bool(client->dev.of_node,
1651                                                  "wakeup-source"))
1652                 ds1307_can_wakeup_device = true;
1653 #endif
1654
1655         switch (ds1307->type) {
1656         case ds_1337:
1657         case ds_1339:
1658         case ds_1341:
1659         case ds_3231:
1660                 /* get registers that the "rtc" read below won't read... */
1661                 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1662                                        regs, 2);
1663                 if (err) {
1664                         dev_dbg(ds1307->dev, "read error %d\n", err);
1665                         goto exit;
1666                 }
1667
1668                 /* oscillator off?  turn it on, so clock can tick. */
1669                 if (regs[0] & DS1337_BIT_nEOSC)
1670                         regs[0] &= ~DS1337_BIT_nEOSC;
1671
1672                 /*
1673                  * Using IRQ or defined as wakeup-source?
1674                  * Disable the square wave and both alarms.
1675                  * For some variants, be sure alarms can trigger when we're
1676                  * running on Vbackup (BBSQI/BBSQW)
1677                  */
1678                 if (want_irq || ds1307_can_wakeup_device) {
1679                         regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1680                         regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1681                 }
1682
1683                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1684                              regs[0]);
1685
1686                 /* oscillator fault?  clear flag, and warn */
1687                 if (regs[1] & DS1337_BIT_OSF) {
1688                         regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1689                                      regs[1] & ~DS1337_BIT_OSF);
1690                         dev_warn(ds1307->dev, "SET TIME!\n");
1691                 }
1692                 break;
1693
1694         case rx_8025:
1695                 err = regmap_bulk_read(ds1307->regmap,
1696                                        RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1697                 if (err) {
1698                         dev_dbg(ds1307->dev, "read error %d\n", err);
1699                         goto exit;
1700                 }
1701
1702                 /* oscillator off?  turn it on, so clock can tick. */
1703                 if (!(regs[1] & RX8025_BIT_XST)) {
1704                         regs[1] |= RX8025_BIT_XST;
1705                         regmap_write(ds1307->regmap,
1706                                      RX8025_REG_CTRL2 << 4 | 0x08,
1707                                      regs[1]);
1708                         dev_warn(ds1307->dev,
1709                                  "oscillator stop detected - SET TIME!\n");
1710                 }
1711
1712                 if (regs[1] & RX8025_BIT_PON) {
1713                         regs[1] &= ~RX8025_BIT_PON;
1714                         regmap_write(ds1307->regmap,
1715                                      RX8025_REG_CTRL2 << 4 | 0x08,
1716                                      regs[1]);
1717                         dev_warn(ds1307->dev, "power-on detected\n");
1718                 }
1719
1720                 if (regs[1] & RX8025_BIT_VDET) {
1721                         regs[1] &= ~RX8025_BIT_VDET;
1722                         regmap_write(ds1307->regmap,
1723                                      RX8025_REG_CTRL2 << 4 | 0x08,
1724                                      regs[1]);
1725                         dev_warn(ds1307->dev, "voltage drop detected\n");
1726                 }
1727
1728                 /* make sure we are running in 24hour mode */
1729                 if (!(regs[0] & RX8025_BIT_2412)) {
1730                         u8 hour;
1731
1732                         /* switch to 24 hour mode */
1733                         regmap_write(ds1307->regmap,
1734                                      RX8025_REG_CTRL1 << 4 | 0x08,
1735                                      regs[0] | RX8025_BIT_2412);
1736
1737                         err = regmap_bulk_read(ds1307->regmap,
1738                                                RX8025_REG_CTRL1 << 4 | 0x08,
1739                                                regs, 2);
1740                         if (err) {
1741                                 dev_dbg(ds1307->dev, "read error %d\n", err);
1742                                 goto exit;
1743                         }
1744
1745                         /* correct hour */
1746                         hour = bcd2bin(regs[DS1307_REG_HOUR]);
1747                         if (hour == 12)
1748                                 hour = 0;
1749                         if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1750                                 hour += 12;
1751
1752                         regmap_write(ds1307->regmap,
1753                                      DS1307_REG_HOUR << 4 | 0x08, hour);
1754                 }
1755                 break;
1756         default:
1757                 break;
1758         }
1759
1760         /* read RTC registers */
1761         err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1762                                sizeof(regs));
1763         if (err) {
1764                 dev_dbg(ds1307->dev, "read error %d\n", err);
1765                 goto exit;
1766         }
1767
1768         if (ds1307->type == mcp794xx &&
1769             !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1770                 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1771                              regs[DS1307_REG_WDAY] |
1772                              MCP794XX_BIT_VBATEN);
1773         }
1774
1775         tmp = regs[DS1307_REG_HOUR];
1776         switch (ds1307->type) {
1777         case ds_1340:
1778         case m41t0:
1779         case m41t00:
1780         case m41t11:
1781                 /*
1782                  * NOTE: ignores century bits; fix before deploying
1783                  * systems that will run through year 2100.
1784                  */
1785                 break;
1786         case rx_8025:
1787                 break;
1788         default:
1789                 if (!(tmp & DS1307_BIT_12HR))
1790                         break;
1791
1792                 /*
1793                  * Be sure we're in 24 hour mode.  Multi-master systems
1794                  * take note...
1795                  */
1796                 tmp = bcd2bin(tmp & 0x1f);
1797                 if (tmp == 12)
1798                         tmp = 0;
1799                 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1800                         tmp += 12;
1801                 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1802                              bin2bcd(tmp));
1803         }
1804
1805         if (want_irq || ds1307_can_wakeup_device) {
1806                 device_set_wakeup_capable(ds1307->dev, true);
1807                 set_bit(HAS_ALARM, &ds1307->flags);
1808         }
1809
1810         ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1811         if (IS_ERR(ds1307->rtc))
1812                 return PTR_ERR(ds1307->rtc);
1813
1814         if (ds1307_can_wakeup_device && !want_irq) {
1815                 dev_info(ds1307->dev,
1816                          "'wakeup-source' is set, request for an IRQ is disabled!\n");
1817                 /* We cannot support UIE mode if we do not have an IRQ line */
1818                 ds1307->rtc->uie_unsupported = 1;
1819         }
1820
1821         if (want_irq) {
1822                 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1823                                                 chip->irq_handler ?: ds1307_irq,
1824                                                 IRQF_SHARED | IRQF_ONESHOT,
1825                                                 ds1307->name, ds1307);
1826                 if (err) {
1827                         client->irq = 0;
1828                         device_set_wakeup_capable(ds1307->dev, false);
1829                         clear_bit(HAS_ALARM, &ds1307->flags);
1830                         dev_err(ds1307->dev, "unable to request IRQ!\n");
1831                 } else {
1832                         dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1833                 }
1834         }
1835
1836         ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1837         err = ds1307_add_frequency_test(ds1307);
1838         if (err)
1839                 return err;
1840
1841         err = rtc_register_device(ds1307->rtc);
1842         if (err)
1843                 return err;
1844
1845         if (chip->nvram_size) {
1846                 struct nvmem_config nvmem_cfg = {
1847                         .name = "ds1307_nvram",
1848                         .word_size = 1,
1849                         .stride = 1,
1850                         .size = chip->nvram_size,
1851                         .reg_read = ds1307_nvram_read,
1852                         .reg_write = ds1307_nvram_write,
1853                         .priv = ds1307,
1854                 };
1855
1856                 ds1307->rtc->nvram_old_abi = true;
1857                 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1858         }
1859
1860         ds1307_hwmon_register(ds1307);
1861         ds1307_clks_register(ds1307);
1862
1863         return 0;
1864
1865 exit:
1866         return err;
1867 }
1868
1869 static struct i2c_driver ds1307_driver = {
1870         .driver = {
1871                 .name   = "rtc-ds1307",
1872                 .of_match_table = of_match_ptr(ds1307_of_match),
1873                 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1874         },
1875         .probe          = ds1307_probe,
1876         .id_table       = ds1307_id,
1877 };
1878
1879 module_i2c_driver(ds1307_driver);
1880
1881 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1882 MODULE_LICENSE("GPL");