1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Pin Function Controller pinmux support.
5 * Copyright (C) 2012 Paul Mundt
8 #define DRV_NAME "sh-pfc"
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/pinctrl/machine.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
26 #include "../pinconf.h"
28 struct sh_pfc_pin_config {
32 struct sh_pfc_pinctrl {
33 struct pinctrl_dev *pctl;
34 struct pinctrl_desc pctl_desc;
38 struct pinctrl_pin_desc *pins;
39 struct sh_pfc_pin_config *configs;
41 const char *func_prop_name;
42 const char *groups_prop_name;
43 const char *pins_prop_name;
46 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
48 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
50 return pmx->pfc->info->nr_groups;
53 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
56 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
58 return pmx->pfc->info->groups[selector].name;
61 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
62 const unsigned **pins, unsigned *num_pins)
64 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
66 *pins = pmx->pfc->info->groups[selector].pins;
67 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
72 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
75 seq_puts(s, DRV_NAME);
79 static int sh_pfc_map_add_config(struct pinctrl_map *map,
80 const char *group_or_pin,
81 enum pinctrl_map_type type,
82 unsigned long *configs,
83 unsigned int num_configs)
87 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
93 map->data.configs.group_or_pin = group_or_pin;
94 map->data.configs.configs = cfgs;
95 map->data.configs.num_configs = num_configs;
100 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
101 struct device_node *np,
102 struct pinctrl_map **map,
103 unsigned int *num_maps, unsigned int *index)
105 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
106 struct device *dev = pmx->pfc->dev;
107 struct pinctrl_map *maps = *map;
108 unsigned int nmaps = *num_maps;
109 unsigned int idx = *index;
110 unsigned int num_configs;
111 const char *function = NULL;
112 unsigned long *configs;
113 struct property *prop;
114 unsigned int num_groups;
115 unsigned int num_pins;
120 /* Support both the old Renesas-specific properties and the new standard
121 * properties. Mixing old and new properties isn't allowed, neither
122 * inside a subnode nor across subnodes.
124 if (!pmx->func_prop_name) {
125 if (of_find_property(np, "groups", NULL) ||
126 of_find_property(np, "pins", NULL)) {
127 pmx->func_prop_name = "function";
128 pmx->groups_prop_name = "groups";
129 pmx->pins_prop_name = "pins";
131 pmx->func_prop_name = "renesas,function";
132 pmx->groups_prop_name = "renesas,groups";
133 pmx->pins_prop_name = "renesas,pins";
137 /* Parse the function and configuration properties. At least a function
138 * or one configuration must be specified.
140 ret = of_property_read_string(np, pmx->func_prop_name, &function);
141 if (ret < 0 && ret != -EINVAL) {
142 dev_err(dev, "Invalid function in DT\n");
146 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
150 if (!function && num_configs == 0) {
152 "DT node must contain at least a function or config\n");
157 /* Count the number of pins and groups and reallocate mappings. */
158 ret = of_property_count_strings(np, pmx->pins_prop_name);
159 if (ret == -EINVAL) {
161 } else if (ret < 0) {
162 dev_err(dev, "Invalid pins list in DT\n");
168 ret = of_property_count_strings(np, pmx->groups_prop_name);
169 if (ret == -EINVAL) {
171 } else if (ret < 0) {
172 dev_err(dev, "Invalid pin groups list in DT\n");
178 if (!num_pins && !num_groups) {
179 dev_err(dev, "No pin or group provided in DT node\n");
187 nmaps += num_pins + num_groups;
189 maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
198 /* Iterate over pins and groups and create the mappings. */
199 of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
201 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
202 maps[idx].data.mux.group = group;
203 maps[idx].data.mux.function = function;
208 ret = sh_pfc_map_add_config(&maps[idx], group,
209 PIN_MAP_TYPE_CONFIGS_GROUP,
210 configs, num_configs);
223 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
224 ret = sh_pfc_map_add_config(&maps[idx], pin,
225 PIN_MAP_TYPE_CONFIGS_PIN,
226 configs, num_configs);
239 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
240 struct pinctrl_map *map, unsigned num_maps)
247 for (i = 0; i < num_maps; ++i) {
248 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
249 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
250 kfree(map[i].data.configs.configs);
256 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
257 struct device_node *np,
258 struct pinctrl_map **map, unsigned *num_maps)
260 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
261 struct device *dev = pmx->pfc->dev;
262 struct device_node *child;
270 for_each_child_of_node(np, child) {
271 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
279 /* If no mapping has been found in child nodes try the config node. */
280 if (*num_maps == 0) {
281 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
290 dev_err(dev, "no mapping found in node %pOF\n", np);
295 sh_pfc_dt_free_map(pctldev, *map, *num_maps);
299 #endif /* CONFIG_OF */
301 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
302 .get_groups_count = sh_pfc_get_groups_count,
303 .get_group_name = sh_pfc_get_group_name,
304 .get_group_pins = sh_pfc_get_group_pins,
305 .pin_dbg_show = sh_pfc_pin_dbg_show,
307 .dt_node_to_map = sh_pfc_dt_node_to_map,
308 .dt_free_map = sh_pfc_dt_free_map,
312 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
314 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
316 return pmx->pfc->info->nr_functions;
319 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
322 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
324 return pmx->pfc->info->functions[selector].name;
327 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
329 const char * const **groups,
330 unsigned * const num_groups)
332 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
334 *groups = pmx->pfc->info->functions[selector].groups;
335 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
340 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
343 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
344 struct sh_pfc *pfc = pmx->pfc;
345 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
350 spin_lock_irqsave(&pfc->lock, flags);
352 for (i = 0; i < grp->nr_pins; ++i) {
353 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
354 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
356 if (cfg->type != PINMUX_TYPE_NONE) {
362 for (i = 0; i < grp->nr_pins; ++i) {
363 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
369 spin_unlock_irqrestore(&pfc->lock, flags);
373 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
374 struct pinctrl_gpio_range *range,
377 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
378 struct sh_pfc *pfc = pmx->pfc;
379 int idx = sh_pfc_get_pin_index(pfc, offset);
380 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
384 spin_lock_irqsave(&pfc->lock, flags);
386 if (cfg->type != PINMUX_TYPE_NONE) {
388 "Pin %u is busy, can't configure it as GPIO.\n",
395 /* If GPIOs are handled externally the pin mux type need to be
398 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
400 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
405 cfg->type = PINMUX_TYPE_GPIO;
410 spin_unlock_irqrestore(&pfc->lock, flags);
415 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
416 struct pinctrl_gpio_range *range,
419 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
420 struct sh_pfc *pfc = pmx->pfc;
421 int idx = sh_pfc_get_pin_index(pfc, offset);
422 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
425 spin_lock_irqsave(&pfc->lock, flags);
426 cfg->type = PINMUX_TYPE_NONE;
427 spin_unlock_irqrestore(&pfc->lock, flags);
430 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
431 struct pinctrl_gpio_range *range,
432 unsigned offset, bool input)
434 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
435 struct sh_pfc *pfc = pmx->pfc;
436 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
437 int idx = sh_pfc_get_pin_index(pfc, offset);
438 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
439 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
444 /* Check if the requested direction is supported by the pin. Not all SoC
445 * provide pin config data, so perform the check conditionally.
448 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
449 if (!(pin->configs & dir))
453 spin_lock_irqsave(&pfc->lock, flags);
455 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
459 cfg->type = new_type;
462 spin_unlock_irqrestore(&pfc->lock, flags);
466 static const struct pinmux_ops sh_pfc_pinmux_ops = {
467 .get_functions_count = sh_pfc_get_functions_count,
468 .get_function_name = sh_pfc_get_function_name,
469 .get_function_groups = sh_pfc_get_function_groups,
470 .set_mux = sh_pfc_func_set_mux,
471 .gpio_request_enable = sh_pfc_gpio_request_enable,
472 .gpio_disable_free = sh_pfc_gpio_disable_free,
473 .gpio_set_direction = sh_pfc_gpio_set_direction,
476 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
477 unsigned int pin, unsigned int *offset, unsigned int *size)
479 const struct pinmux_drive_reg_field *field;
480 const struct pinmux_drive_reg *reg;
483 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
484 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
485 field = ®->fields[i];
487 if (field->size && field->pin == pin) {
488 *offset = field->offset;
499 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
508 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
512 spin_lock_irqsave(&pfc->lock, flags);
513 val = sh_pfc_read(pfc, reg);
514 spin_unlock_irqrestore(&pfc->lock, flags);
516 val = (val >> offset) & GENMASK(size - 1, 0);
518 /* Convert the value to mA based on a full drive strength value of 24mA.
519 * We can make the full value configurable later if needed.
521 return (val + 1) * (size == 2 ? 6 : 3);
524 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
525 unsigned int pin, u16 strength)
534 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
538 step = size == 2 ? 6 : 3;
540 if (strength < step || strength > 24)
543 /* Convert the value from mA based on a full drive strength value of
544 * 24mA. We can make the full value configurable later if needed.
546 strength = strength / step - 1;
548 spin_lock_irqsave(&pfc->lock, flags);
550 val = sh_pfc_read(pfc, reg);
551 val &= ~GENMASK(offset + size - 1, offset);
552 val |= strength << offset;
554 sh_pfc_write(pfc, reg, val);
556 spin_unlock_irqrestore(&pfc->lock, flags);
561 /* Check whether the requested parameter is supported for a pin. */
562 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
563 enum pin_config_param param)
565 int idx = sh_pfc_get_pin_index(pfc, _pin);
566 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
569 case PIN_CONFIG_BIAS_DISABLE:
570 return pin->configs &
571 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
573 case PIN_CONFIG_BIAS_PULL_UP:
574 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
576 case PIN_CONFIG_BIAS_PULL_DOWN:
577 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
579 case PIN_CONFIG_DRIVE_STRENGTH:
580 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
582 case PIN_CONFIG_POWER_SOURCE:
583 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
590 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
591 unsigned long *config)
593 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
594 struct sh_pfc *pfc = pmx->pfc;
595 enum pin_config_param param = pinconf_to_config_param(*config);
599 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
603 case PIN_CONFIG_BIAS_DISABLE:
604 case PIN_CONFIG_BIAS_PULL_UP:
605 case PIN_CONFIG_BIAS_PULL_DOWN: {
608 if (!pfc->info->ops || !pfc->info->ops->get_bias)
611 spin_lock_irqsave(&pfc->lock, flags);
612 bias = pfc->info->ops->get_bias(pfc, _pin);
613 spin_unlock_irqrestore(&pfc->lock, flags);
622 case PIN_CONFIG_DRIVE_STRENGTH: {
625 ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
633 case PIN_CONFIG_POWER_SOURCE: {
637 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
640 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
641 if (WARN(bit < 0, "invalid pin %#x", _pin))
644 spin_lock_irqsave(&pfc->lock, flags);
645 val = sh_pfc_read(pfc, pocctrl);
646 spin_unlock_irqrestore(&pfc->lock, flags);
648 arg = (val & BIT(bit)) ? 3300 : 1800;
656 *config = pinconf_to_config_packed(param, arg);
660 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
661 unsigned long *configs, unsigned num_configs)
663 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
664 struct sh_pfc *pfc = pmx->pfc;
665 enum pin_config_param param;
669 for (i = 0; i < num_configs; i++) {
670 param = pinconf_to_config_param(configs[i]);
672 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
676 case PIN_CONFIG_BIAS_PULL_UP:
677 case PIN_CONFIG_BIAS_PULL_DOWN:
678 case PIN_CONFIG_BIAS_DISABLE:
679 if (!pfc->info->ops || !pfc->info->ops->set_bias)
682 spin_lock_irqsave(&pfc->lock, flags);
683 pfc->info->ops->set_bias(pfc, _pin, param);
684 spin_unlock_irqrestore(&pfc->lock, flags);
688 case PIN_CONFIG_DRIVE_STRENGTH: {
690 pinconf_to_config_argument(configs[i]);
693 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
700 case PIN_CONFIG_POWER_SOURCE: {
701 unsigned int mV = pinconf_to_config_argument(configs[i]);
705 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
708 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
709 if (WARN(bit < 0, "invalid pin %#x", _pin))
712 if (mV != 1800 && mV != 3300)
715 spin_lock_irqsave(&pfc->lock, flags);
716 val = sh_pfc_read(pfc, pocctrl);
721 sh_pfc_write(pfc, pocctrl, val);
722 spin_unlock_irqrestore(&pfc->lock, flags);
730 } /* for each config */
735 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
736 unsigned long *configs,
737 unsigned num_configs)
739 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
740 const unsigned int *pins;
741 unsigned int num_pins;
744 pins = pmx->pfc->info->groups[group].pins;
745 num_pins = pmx->pfc->info->groups[group].nr_pins;
747 for (i = 0; i < num_pins; ++i) {
748 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
756 static const struct pinconf_ops sh_pfc_pinconf_ops = {
758 .pin_config_get = sh_pfc_pinconf_get,
759 .pin_config_set = sh_pfc_pinconf_set,
760 .pin_config_group_set = sh_pfc_pinconf_group_set,
761 .pin_config_config_dbg_show = pinconf_generic_dump_config,
764 /* PFC ranges -> pinctrl pin descs */
765 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
769 /* Allocate and initialize the pins and configs arrays. */
770 pmx->pins = devm_kcalloc(pfc->dev,
771 pfc->info->nr_pins, sizeof(*pmx->pins),
773 if (unlikely(!pmx->pins))
776 pmx->configs = devm_kcalloc(pfc->dev,
777 pfc->info->nr_pins, sizeof(*pmx->configs),
779 if (unlikely(!pmx->configs))
782 for (i = 0; i < pfc->info->nr_pins; ++i) {
783 const struct sh_pfc_pin *info = &pfc->info->pins[i];
784 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
785 struct pinctrl_pin_desc *pin = &pmx->pins[i];
787 /* If the pin number is equal to -1 all pins are considered */
788 pin->number = info->pin != (u16)-1 ? info->pin : i;
789 pin->name = info->name;
790 cfg->type = PINMUX_TYPE_NONE;
796 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
798 struct sh_pfc_pinctrl *pmx;
801 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
807 ret = sh_pfc_map_pins(pfc, pmx);
811 pmx->pctl_desc.name = DRV_NAME;
812 pmx->pctl_desc.owner = THIS_MODULE;
813 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
814 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
815 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
816 pmx->pctl_desc.pins = pmx->pins;
817 pmx->pctl_desc.npins = pfc->info->nr_pins;
819 ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
822 dev_err(pfc->dev, "could not register: %i\n", ret);
827 return pinctrl_enable(pmx->pctl);