drivers/pinctrl/sh-pfc/pfc-r8a7796.c

   1 /*
   2  * R8A7796 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   7  *
   8  * R-Car Gen3 processor support - PFC hardware block.
   9  *
  10  * Copyright (C) 2015  Renesas Electronics Corporation
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; version 2 of the License.
  15  */
  16
  17 #include <linux/kernel.h>
  18
  19 #include "core.h"
  20 #include "sh_pfc.h"
  21
  22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  23                    SH_PFC_PIN_CFG_PULL_UP | \
  24                    SH_PFC_PIN_CFG_PULL_DOWN)
  25
  26 #define CPU_ALL_PORT(fn, sfx)                                           \
  27         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  28         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  31         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  32         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  35         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  36         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  37         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  38         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  39 /*
  40  * F_() : just information
  41  * FM() : macro for FN_xxx / xxx_MARK
  42  */
  43
  44 /* GPSR0 */
  45 #define GPSR0_15        F_(D15,                 IP7_11_8)
  46 #define GPSR0_14        F_(D14,                 IP7_7_4)
  47 #define GPSR0_13        F_(D13,                 IP7_3_0)
  48 #define GPSR0_12        F_(D12,                 IP6_31_28)
  49 #define GPSR0_11        F_(D11,                 IP6_27_24)
  50 #define GPSR0_10        F_(D10,                 IP6_23_20)
  51 #define GPSR0_9         F_(D9,                  IP6_19_16)
  52 #define GPSR0_8         F_(D8,                  IP6_15_12)
  53 #define GPSR0_7         F_(D7,                  IP6_11_8)
  54 #define GPSR0_6         F_(D6,                  IP6_7_4)
  55 #define GPSR0_5         F_(D5,                  IP6_3_0)
  56 #define GPSR0_4         F_(D4,                  IP5_31_28)
  57 #define GPSR0_3         F_(D3,                  IP5_27_24)
  58 #define GPSR0_2         F_(D2,                  IP5_23_20)
  59 #define GPSR0_1         F_(D1,                  IP5_19_16)
  60 #define GPSR0_0         F_(D0,                  IP5_15_12)
  61
  62 /* GPSR1 */
  63 #define GPSR1_28        FM(CLKOUT)
  64 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  65 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  66 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  67 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  68 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  69 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  70 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  71 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  72 #define GPSR1_19        F_(A19,                 IP4_11_8)
  73 #define GPSR1_18        F_(A18,                 IP4_7_4)
  74 #define GPSR1_17        F_(A17,                 IP4_3_0)
  75 #define GPSR1_16        F_(A16,                 IP3_31_28)
  76 #define GPSR1_15        F_(A15,                 IP3_27_24)
  77 #define GPSR1_14        F_(A14,                 IP3_23_20)
  78 #define GPSR1_13        F_(A13,                 IP3_19_16)
  79 #define GPSR1_12        F_(A12,                 IP3_15_12)
  80 #define GPSR1_11        F_(A11,                 IP3_11_8)
  81 #define GPSR1_10        F_(A10,                 IP3_7_4)
  82 #define GPSR1_9         F_(A9,                  IP3_3_0)
  83 #define GPSR1_8         F_(A8,                  IP2_31_28)
  84 #define GPSR1_7         F_(A7,                  IP2_27_24)
  85 #define GPSR1_6         F_(A6,                  IP2_23_20)
  86 #define GPSR1_5         F_(A5,                  IP2_19_16)
  87 #define GPSR1_4         F_(A4,                  IP2_15_12)
  88 #define GPSR1_3         F_(A3,                  IP2_11_8)
  89 #define GPSR1_2         F_(A2,                  IP2_7_4)
  90 #define GPSR1_1         F_(A1,                  IP2_3_0)
  91 #define GPSR1_0         F_(A0,                  IP1_31_28)
  92
  93 /* GPSR2 */
  94 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  95 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  96 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  97 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  98 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
  99 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 100 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 101 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 102 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 103 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 104 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 105 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 106 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 107 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 108 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 109
 110 /* GPSR3 */
 111 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 112 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 113 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 114 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 115 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 116 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 117 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 118 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 119 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 120 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 121 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 122 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 123 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 124 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 125 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 126 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 127
 128 /* GPSR4 */
 129 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 130 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 131 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 132 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 133 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 134 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 135 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 136 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 137 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 138 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 139 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 140 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 141 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 142 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 143 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 144 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 145 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 146 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 147
 148 /* GPSR5 */
 149 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 150 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 151 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 152 #define GPSR5_22        FM(MSIOF0_RXD)
 153 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 154 #define GPSR5_20        FM(MSIOF0_TXD)
 155 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 156 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 157 #define GPSR5_17        FM(MSIOF0_SCK)
 158 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 159 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 160 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 161 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 162 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 163 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 164 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 165 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 166 #define GPSR5_8         F_(RTS1_N_TANS,         IP12_27_24)
 167 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 168 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 169 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 170 #define GPSR5_4         F_(RTS0_N_TANS,         IP12_11_8)
 171 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 172 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 173 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 174 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 175
 176 /* GPSR6 */
 177 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 178 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 179 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 180 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 181 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 182 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 183 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 184 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 185 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 186 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 187 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 188 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 189 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 190 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 191 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 192 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 193 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 194 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 195 #define GPSR6_13        FM(SSI_SDATA5)
 196 #define GPSR6_12        FM(SSI_WS5)
 197 #define GPSR6_11        FM(SSI_SCK5)
 198 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 199 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 200 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 201 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 202 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 203 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 204 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 205 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 206 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 207 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 208 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 209
 210 /* GPSR7 */
 211 #define GPSR7_3         FM(GP7_03)
 212 #define GPSR7_2         FM(HDMI0_CEC)
 213 #define GPSR7_1         FM(AVS2)
 214 #define GPSR7_0         FM(AVS1)
 215
 216
 217 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 218 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_TANS_A)               F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   FM(A25)                 FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    FM(A24)                 FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    FM(A23)                 FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)FM(A22)                 F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        FM(A21)                 FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        FM(A20)                 FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_TANS_B)               F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245
 246 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 247 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N_TANS)                 FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3)             F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276
 277 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 278 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312
 313 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 314 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_11_8       FM(RTS0_N_TANS)         FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_27_24      FM(RTS1_N_TANS)         FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 335 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342
 343 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 344 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 364 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 366 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 367 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 368 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 370 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 371
 372 #define PINMUX_GPSR     \
 373 \
 374                                                                                                 GPSR6_31 \
 375                                                                                                 GPSR6_30 \
 376                                                                                                 GPSR6_29 \
 377                 GPSR1_28                                                                        GPSR6_28 \
 378                 GPSR1_27                                                                        GPSR6_27 \
 379                 GPSR1_26                                                                        GPSR6_26 \
 380                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 381                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 382                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 383                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 384                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 385                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 386                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 387                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 388                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 389                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 390 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 391 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 392 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 393 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 394 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 395 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 396 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 397 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 398 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 399 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 400 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 401 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 402 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 403 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 404 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 405 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 406
 407 #define PINMUX_IPSR                             \
 408 \
 409 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 410 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 411 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 412 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 413 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 414 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 415 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 416 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 417 \
 418 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 419 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 420 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 421 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 422 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 423 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 424 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 425 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 426 \
 427 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 428 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 429 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 430 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 431 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 432 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 433 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 434 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 435 \
 436 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 437 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 438 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 439 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 440 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 441 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 442 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 443 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 444 \
 445 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 446 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 447 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 448 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 449 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 450 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 451 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 452 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 453
 454 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 455 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 456 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 457 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 458 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 459 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 460 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 461 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 462 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 463 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 464 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 465 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 466 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 467 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 468 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 469 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 470 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 471 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 472 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 473
 474 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 475 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 476 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 477 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 478 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 479 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 480 #define MOD_SEL1_20             FM(SEL_SSI_0)           FM(SEL_SSI_1)
 481 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 482 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 483 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 484 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 485 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 486 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 487 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 488 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 489 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 490 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 491 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 492 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 493 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 494 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 495 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 496 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 497
 498 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 499 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 500 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 501 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 502 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 503 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 504 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 505 #define MOD_SEL2_22             FM(SEL_NDF_0)           FM(SEL_NDF_1)
 506 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 507 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 508 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 509 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 510 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 511 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 512
 513 #define PINMUX_MOD_SELS \
 514 \
 515 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 516                                                 MOD_SEL2_30 \
 517                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 518 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 519 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 520                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 521 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 522 MOD_SEL0_22                                     MOD_SEL2_22 \
 523 MOD_SEL0_21                                     MOD_SEL2_21 \
 524 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 525 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 526 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 527                                                 MOD_SEL2_17 \
 528 MOD_SEL0_16             MOD_SEL1_16 \
 529                         MOD_SEL1_15_14 \
 530 MOD_SEL0_14_13 \
 531                         MOD_SEL1_13 \
 532 MOD_SEL0_12             MOD_SEL1_12 \
 533 MOD_SEL0_11             MOD_SEL1_11 \
 534 MOD_SEL0_10             MOD_SEL1_10 \
 535 MOD_SEL0_9_8            MOD_SEL1_9 \
 536 MOD_SEL0_7_6 \
 537                         MOD_SEL1_6 \
 538 MOD_SEL0_5              MOD_SEL1_5 \
 539 MOD_SEL0_4_3            MOD_SEL1_4 \
 540                         MOD_SEL1_3 \
 541                         MOD_SEL1_2 \
 542                         MOD_SEL1_1 \
 543                         MOD_SEL1_0              MOD_SEL2_0
 544
 545 /*
 546  * These pins are not able to be muxed but have other properties
 547  * that can be set, such as drive-strength or pull-up/pull-down enable.
 548  */
 549 #define PINMUX_STATIC \
 550         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 551         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 552         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 553         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 554         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 555         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 556         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 557         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 558         FM(PRESETOUT) \
 559         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 560         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 561
 562 enum {
 563         PINMUX_RESERVED = 0,
 564
 565         PINMUX_DATA_BEGIN,
 566         GP_ALL(DATA),
 567         PINMUX_DATA_END,
 568
 569 #define F_(x, y)
 570 #define FM(x)   FN_##x,
 571         PINMUX_FUNCTION_BEGIN,
 572         GP_ALL(FN),
 573         PINMUX_GPSR
 574         PINMUX_IPSR
 575         PINMUX_MOD_SELS
 576         PINMUX_FUNCTION_END,
 577 #undef F_
 578 #undef FM
 579
 580 #define F_(x, y)
 581 #define FM(x)   x##_MARK,
 582         PINMUX_MARK_BEGIN,
 583         PINMUX_GPSR
 584         PINMUX_IPSR
 585         PINMUX_MOD_SELS
 586         PINMUX_STATIC
 587         PINMUX_MARK_END,
 588 #undef F_
 589 #undef FM
 590 };
 591
 592 static const u16 pinmux_data[] = {
 593         PINMUX_DATA_GP_ALL(),
 594
 595         PINMUX_SINGLE(AVS1),
 596         PINMUX_SINGLE(AVS2),
 597         PINMUX_SINGLE(CLKOUT),
 598         PINMUX_SINGLE(GP7_03),
 599         PINMUX_SINGLE(HDMI0_CEC),
 600         PINMUX_SINGLE(MSIOF0_RXD),
 601         PINMUX_SINGLE(MSIOF0_SCK),
 602         PINMUX_SINGLE(MSIOF0_TXD),
 603         PINMUX_SINGLE(SSI_SCK5),
 604         PINMUX_SINGLE(SSI_SDATA5),
 605         PINMUX_SINGLE(SSI_WS5),
 606
 607         /* IPSR0 */
 608         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 609         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 610
 611         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 612         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 613         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 614
 615         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 616         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 617         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 618
 619         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 620         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 621         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 622
 623         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 624         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 625         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 626
 627         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 628         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 629         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_TANS_A,          SEL_SCIF4_0),
 630
 631         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 632         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 633         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 634         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 635         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 637         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 638
 639         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 640         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 641         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 642         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 643         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 645         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 646
 647         /* IPSR1 */
 648         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 649         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 650         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 651         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 652         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 653         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 654
 655         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 656         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 657         PINMUX_IPSR_GPSR(IP1_7_4,       A25),
 658         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 659         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 660         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 661         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 662
 663         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 664         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 665         PINMUX_IPSR_GPSR(IP1_11_8,      A24),
 666         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 667         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 668         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 669         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 670
 671         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 672         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 673         PINMUX_IPSR_GPSR(IP1_15_12,     A23),
 674         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 675         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 676         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 677         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 678
 679         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 680         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 681         PINMUX_IPSR_GPSR(IP1_19_16,     A22),
 682         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 683         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 684
 685         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 686         PINMUX_IPSR_GPSR(IP1_23_20,     A21),
 687         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 688         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 689         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 690
 691         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 692         PINMUX_IPSR_GPSR(IP1_27_24,     A20),
 693         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 694         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 695
 696         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 697         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 698         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 699         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 700         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 701         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 702
 703         /* IPSR2 */
 704         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 705         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 706         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 707         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 708         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 709         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 710
 711         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 712         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 713         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 714         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 715         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 716         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 717
 718         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 719         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 720         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 721         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 722         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 723         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 724
 725         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 726         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 727         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 728         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 729         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 730         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 731
 732         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 733         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 734         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 735         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 736         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 737         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 738         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 739
 740         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 741         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 742         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 743         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 744         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 745         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 746         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 747
 748         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 749         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 750         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 751         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 752         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 753         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 754         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 755
 756         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 757         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 758         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 759         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 760         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 761         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 762         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 763
 764         /* IPSR3 */
 765         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 766         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 767         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 768         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 769
 770         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 771         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 772         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_TANS_B,          SEL_SCIF4_1),
 773         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 774
 775         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 776         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 777         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 778         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 779         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 780         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 781         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 782         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 783         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 784
 785         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 786         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 787         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 788         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 789         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 790         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 791
 792         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 793         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 794         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 795         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 796         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 797         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 798
 799         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 800         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 801         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 802         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 803         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 804         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 805
 806         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 807         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 808         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 809         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 810         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 811         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 812
 813         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 814         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 815         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 816         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 817
 818         /* IPSR4 */
 819         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 820         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 821         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 822         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 823
 824         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 825         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 826         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 827         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 828
 829         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 830         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 831         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 832         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 833
 834         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 835         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 836
 837         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 838         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 839         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 840
 841         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 842         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 843         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 844         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 845         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 846         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 847         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 848         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 849
 850         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 851         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 852         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 853         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 854         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 855         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 856
 857         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 858         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 859         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 860         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 861         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 862         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 863
 864         /* IPSR5 */
 865         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 866         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 867         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 868         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 869         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 870         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 871         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 872
 873         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 875         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N_TANS),
 876         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 877         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 878         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 879         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 880         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 881
 882         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 883         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 884         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 885         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 886
 887         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 888         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 889         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 890         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 891         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 892
 893         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 894         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 895         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 896         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 897         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 898
 899         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 900         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 901         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 902         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 903
 904         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 905         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 906         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 907         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 908
 909         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 910         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 911         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 912         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 913
 914         /* IPSR6 */
 915         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 916         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 917         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 918         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 919
 920         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 921         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 922         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 923         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 924
 925         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 926         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 927         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 928         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 929
 930         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 931         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 932         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 933         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 934         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 935         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 936
 937         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 938         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 939         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 940         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 941         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 942
 943         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 944         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 945         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 946         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 947         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 948         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 949         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 950
 951         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 952         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 953         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 954         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 955         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 956         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_TANS_C,          SEL_SCIF4_2),
 957         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 958
 959         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 960         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 961         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 962         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 963         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 964         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 965
 966         /* IPSR7 */
 967         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 968         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 969         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 970         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 971         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 972         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 973
 974         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 975         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 976         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 977         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 978         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 979         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 980         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 981
 982         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 983         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 984         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 985         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 986         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 987         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 988         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 989
 990         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 991         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 992         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 993
 994         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 995         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 996         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 997
 998         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 999         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
1000         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
1001         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
1002
1003         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
1004         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1005         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1006         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1007
1008         /* IPSR8 */
1009         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1010         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1011         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1012         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1013
1014         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1015         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1016         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1017         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1018
1019         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1020         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1021         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1022
1023         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1024         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1025         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDF_1),
1026         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1027         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1028
1029         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1030         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1031         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1032         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDF_1),
1033         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1034         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1035
1036         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1037         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1038         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1039         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDF_1),
1040         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1041         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1042
1043         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1044         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1045         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1046         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDF_1),
1047         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1048         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1049
1050         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1051         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1052         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1053         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDF_1),
1054         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1055         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1056
1057         /* IPSR9 */
1058         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1059         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1060
1061         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1062         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1063
1064         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1065         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1066
1067         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1068         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1069
1070         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1071         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1072
1073         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1074         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1075
1076         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1077         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1078
1079         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1080         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1081
1082         /* IPSR10 */
1083         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1084         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1085
1086         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1087         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1088
1089         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1090         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1091
1092         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1093         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1094
1095         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1096         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1097
1098         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1099         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1100         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1101
1102         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1103         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1104         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1105
1106         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1107         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1108         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1109
1110         /* IPSR11 */
1111         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1112         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1113         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1114
1115         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1116         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1117
1118         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1119         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1120         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1121
1122         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1123         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1124
1125         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1126         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1127
1128         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1129         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1130
1131         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1132         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1133         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1137         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1138         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1139         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1141
1142         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1143         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1144         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1145         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1146         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1147
1148         /* IPSR12 */
1149         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1150         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1151         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1152         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1153         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1154
1155         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1156         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1157         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1159         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1160         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1161         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1162         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1163
1164         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N_TANS),
1165         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1166         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1170         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1171         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1172
1173         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1174         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1175         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1176         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1177         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1178
1179         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1180         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1181         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1182         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1183         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1184
1185         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1186         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1187         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1189         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1190         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1191         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1192
1193         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N_TANS),
1194         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1195         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1197         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1198         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1199         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1200
1201         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1202         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1203         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1205         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1206         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1207         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1208
1209         /* IPSR13 */
1210         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1211         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1212         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1214         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1215         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1216
1217         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1218         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1219         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1220         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1221         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1222         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1223
1224         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1225         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1226         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI_1),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1231         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1232
1233         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1234         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1235         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI_1),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1238         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1239
1240         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1241         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1242         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI_1),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1244         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1245         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1246
1247         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1248         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1249         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI_0),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1252         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1253         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1254         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1255
1256         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1257         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1258         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI_0),
1260         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1261         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1262         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1263
1264         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1265         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1266         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1267         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1268
1269         /* IPSR14 */
1270         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1271         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1272         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDF_0),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1274         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI_0),
1275         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1276         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1277         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1278
1279         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1280         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1281         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1283         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI_0),
1284         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1285         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1286         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1287
1288         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1289         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1290         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1291
1292         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1293         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1294         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1295         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1296
1297         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1298         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1299         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1300
1301         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1302         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1303
1304         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1305         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1306
1307         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1308         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1309
1310         /* IPSR15 */
1311         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI_0),
1312
1313         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI_0),
1314         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI_1),
1315
1316         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1317         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1318         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1319
1320         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1321         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1322         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1323         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1324
1325         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1326         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1327         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1331         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1332
1333         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1334         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1335         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1340
1341         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1342         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1343         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1348
1349         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1350         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1351         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1355         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1356
1357         /* IPSR16 */
1358         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1359         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1360
1361         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1362         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1363
1364         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1365         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1366
1367         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1368         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1369         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1370         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1372         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1373         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1374
1375         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1376         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1377         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1378         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1382
1383         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1384         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1385         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1386         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1391
1392         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1393         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1394         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1395         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1399
1400         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI_0),
1401         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1402         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1403         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI_1),
1405         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1406         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1408
1409         /* IPSR17 */
1410         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1411         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1412
1413         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1414         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1415         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1416         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1417         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1418
1419         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1420         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1421         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1422         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1424         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1425         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1426
1427         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1428         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1429         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1430         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1431         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1432         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1433
1434         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1435         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1436         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI_0),
1437         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1441         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1443
1444         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1445         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1446         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI_0),
1447         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1451         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1453
1454         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1455         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1456         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI_1),
1457         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1458         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1460         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1462         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1465
1466         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1467         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1468         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI_1),
1469         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1470         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1471         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1472         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1473         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1474         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1475
1476         /* IPSR18 */
1477         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1478         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1479         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI_1),
1480         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1481         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1483         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1484         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1485         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1486
1487         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1488         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1489         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI_1),
1490         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1491         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1493         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1494         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1495         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1496
1497         /* I2C */
1498         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1499         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1500         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1501
1502 /*
1503  * Static pins can not be muxed between different functions but
1504  * still needs a mark entry in the pinmux list. Add each static
1505  * pin to the list without an associated function. The sh-pfc
1506  * core will do the right thing and skip trying to mux then pin
1507  * while still applying configuration to it
1508  */
1509 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1510         PINMUX_STATIC
1511 #undef FM
1512 };
1513
1514 /*
1515  * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516  * Physical layout rows: A - AW, cols: 1 - 39.
1517  */
1518 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521 #define PIN_NONE U16_MAX
1522
1523 static const struct sh_pfc_pin pinmux_pins[] = {
1524         PINMUX_GPIO_GP_ALL(),
1525
1526         /*
1527          * Pins not associated with a GPIO port.
1528          *
1529          * The pin positions are different between different r8a7796
1530          * packages, all that is needed for the pfc driver is a unique
1531          * number for each pin. To this end use the pin layout from
1532          * R-Car M3SiP to calculate a unique number for each pin.
1533          */
1534         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1535         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1536         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN2, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576 };
1577
1578 /* - AUDIO CLOCK ------------------------------------------------------------ */
1579 static const unsigned int audio_clk_a_a_pins[] = {
1580         /* CLK A */
1581         RCAR_GP_PIN(6, 22),
1582 };
1583 static const unsigned int audio_clk_a_a_mux[] = {
1584         AUDIO_CLKA_A_MARK,
1585 };
1586 static const unsigned int audio_clk_a_b_pins[] = {
1587         /* CLK A */
1588         RCAR_GP_PIN(5, 4),
1589 };
1590 static const unsigned int audio_clk_a_b_mux[] = {
1591         AUDIO_CLKA_B_MARK,
1592 };
1593 static const unsigned int audio_clk_a_c_pins[] = {
1594         /* CLK A */
1595         RCAR_GP_PIN(5, 19),
1596 };
1597 static const unsigned int audio_clk_a_c_mux[] = {
1598         AUDIO_CLKA_C_MARK,
1599 };
1600 static const unsigned int audio_clk_b_a_pins[] = {
1601         /* CLK B */
1602         RCAR_GP_PIN(5, 12),
1603 };
1604 static const unsigned int audio_clk_b_a_mux[] = {
1605         AUDIO_CLKB_A_MARK,
1606 };
1607 static const unsigned int audio_clk_b_b_pins[] = {
1608         /* CLK B */
1609         RCAR_GP_PIN(6, 23),
1610 };
1611 static const unsigned int audio_clk_b_b_mux[] = {
1612         AUDIO_CLKB_B_MARK,
1613 };
1614 static const unsigned int audio_clk_c_a_pins[] = {
1615         /* CLK C */
1616         RCAR_GP_PIN(5, 21),
1617 };
1618 static const unsigned int audio_clk_c_a_mux[] = {
1619         AUDIO_CLKC_A_MARK,
1620 };
1621 static const unsigned int audio_clk_c_b_pins[] = {
1622         /* CLK C */
1623         RCAR_GP_PIN(5, 0),
1624 };
1625 static const unsigned int audio_clk_c_b_mux[] = {
1626         AUDIO_CLKC_B_MARK,
1627 };
1628 static const unsigned int audio_clkout_a_pins[] = {
1629         /* CLKOUT */
1630         RCAR_GP_PIN(5, 18),
1631 };
1632 static const unsigned int audio_clkout_a_mux[] = {
1633         AUDIO_CLKOUT_A_MARK,
1634 };
1635 static const unsigned int audio_clkout_b_pins[] = {
1636         /* CLKOUT */
1637         RCAR_GP_PIN(6, 28),
1638 };
1639 static const unsigned int audio_clkout_b_mux[] = {
1640         AUDIO_CLKOUT_B_MARK,
1641 };
1642 static const unsigned int audio_clkout_c_pins[] = {
1643         /* CLKOUT */
1644         RCAR_GP_PIN(5, 3),
1645 };
1646 static const unsigned int audio_clkout_c_mux[] = {
1647         AUDIO_CLKOUT_C_MARK,
1648 };
1649 static const unsigned int audio_clkout_d_pins[] = {
1650         /* CLKOUT */
1651         RCAR_GP_PIN(5, 21),
1652 };
1653 static const unsigned int audio_clkout_d_mux[] = {
1654         AUDIO_CLKOUT_D_MARK,
1655 };
1656 static const unsigned int audio_clkout1_a_pins[] = {
1657         /* CLKOUT1 */
1658         RCAR_GP_PIN(5, 15),
1659 };
1660 static const unsigned int audio_clkout1_a_mux[] = {
1661         AUDIO_CLKOUT1_A_MARK,
1662 };
1663 static const unsigned int audio_clkout1_b_pins[] = {
1664         /* CLKOUT1 */
1665         RCAR_GP_PIN(6, 29),
1666 };
1667 static const unsigned int audio_clkout1_b_mux[] = {
1668         AUDIO_CLKOUT1_B_MARK,
1669 };
1670 static const unsigned int audio_clkout2_a_pins[] = {
1671         /* CLKOUT2 */
1672         RCAR_GP_PIN(5, 16),
1673 };
1674 static const unsigned int audio_clkout2_a_mux[] = {
1675         AUDIO_CLKOUT2_A_MARK,
1676 };
1677 static const unsigned int audio_clkout2_b_pins[] = {
1678         /* CLKOUT2 */
1679         RCAR_GP_PIN(6, 30),
1680 };
1681 static const unsigned int audio_clkout2_b_mux[] = {
1682         AUDIO_CLKOUT2_B_MARK,
1683 };
1684
1685 static const unsigned int audio_clkout3_a_pins[] = {
1686         /* CLKOUT3 */
1687         RCAR_GP_PIN(5, 19),
1688 };
1689 static const unsigned int audio_clkout3_a_mux[] = {
1690         AUDIO_CLKOUT3_A_MARK,
1691 };
1692 static const unsigned int audio_clkout3_b_pins[] = {
1693         /* CLKOUT3 */
1694         RCAR_GP_PIN(6, 31),
1695 };
1696 static const unsigned int audio_clkout3_b_mux[] = {
1697         AUDIO_CLKOUT3_B_MARK,
1698 };
1699
1700 /* - EtherAVB --------------------------------------------------------------- */
1701 static const unsigned int avb_link_pins[] = {
1702         /* AVB_LINK */
1703         RCAR_GP_PIN(2, 12),
1704 };
1705 static const unsigned int avb_link_mux[] = {
1706         AVB_LINK_MARK,
1707 };
1708 static const unsigned int avb_magic_pins[] = {
1709         /* AVB_MAGIC_ */
1710         RCAR_GP_PIN(2, 10),
1711 };
1712 static const unsigned int avb_magic_mux[] = {
1713         AVB_MAGIC_MARK,
1714 };
1715 static const unsigned int avb_phy_int_pins[] = {
1716         /* AVB_PHY_INT */
1717         RCAR_GP_PIN(2, 11),
1718 };
1719 static const unsigned int avb_phy_int_mux[] = {
1720         AVB_PHY_INT_MARK,
1721 };
1722 static const unsigned int avb_mdc_pins[] = {
1723         /* AVB_MDC, AVB_MDIO */
1724         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1725 };
1726 static const unsigned int avb_mdc_mux[] = {
1727         AVB_MDC_MARK, AVB_MDIO_MARK,
1728 };
1729 static const unsigned int avb_mii_pins[] = {
1730         /*
1731          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732          * AVB_TD1, AVB_TD2, AVB_TD3,
1733          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734          * AVB_RD1, AVB_RD2, AVB_RD3,
1735          * AVB_TXCREFCLK
1736          */
1737         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741         PIN_NUMBER('A', 12),
1742
1743 };
1744 static const unsigned int avb_mii_mux[] = {
1745         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1746         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1747         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1748         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1749         AVB_TXCREFCLK_MARK,
1750 };
1751 static const unsigned int avb_avtp_pps_pins[] = {
1752         /* AVB_AVTP_PPS */
1753         RCAR_GP_PIN(2, 6),
1754 };
1755 static const unsigned int avb_avtp_pps_mux[] = {
1756         AVB_AVTP_PPS_MARK,
1757 };
1758 static const unsigned int avb_avtp_match_a_pins[] = {
1759         /* AVB_AVTP_MATCH_A */
1760         RCAR_GP_PIN(2, 13),
1761 };
1762 static const unsigned int avb_avtp_match_a_mux[] = {
1763         AVB_AVTP_MATCH_A_MARK,
1764 };
1765 static const unsigned int avb_avtp_capture_a_pins[] = {
1766         /* AVB_AVTP_CAPTURE_A */
1767         RCAR_GP_PIN(2, 14),
1768 };
1769 static const unsigned int avb_avtp_capture_a_mux[] = {
1770         AVB_AVTP_CAPTURE_A_MARK,
1771 };
1772 static const unsigned int avb_avtp_match_b_pins[] = {
1773         /*  AVB_AVTP_MATCH_B */
1774         RCAR_GP_PIN(1, 8),
1775 };
1776 static const unsigned int avb_avtp_match_b_mux[] = {
1777         AVB_AVTP_MATCH_B_MARK,
1778 };
1779 static const unsigned int avb_avtp_capture_b_pins[] = {
1780         /* AVB_AVTP_CAPTURE_B */
1781         RCAR_GP_PIN(1, 11),
1782 };
1783 static const unsigned int avb_avtp_capture_b_mux[] = {
1784         AVB_AVTP_CAPTURE_B_MARK,
1785 };
1786
1787 /* - CAN ------------------------------------------------------------------ */
1788 static const unsigned int can0_data_a_pins[] = {
1789         /* TX, RX */
1790         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1791 };
1792 static const unsigned int can0_data_a_mux[] = {
1793         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1794 };
1795 static const unsigned int can0_data_b_pins[] = {
1796         /* TX, RX */
1797         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1798 };
1799 static const unsigned int can0_data_b_mux[] = {
1800         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1801 };
1802 static const unsigned int can1_data_pins[] = {
1803         /* TX, RX */
1804         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1805 };
1806 static const unsigned int can1_data_mux[] = {
1807         CAN1_TX_MARK,           CAN1_RX_MARK,
1808 };
1809
1810 /* - CAN Clock -------------------------------------------------------------- */
1811 static const unsigned int can_clk_pins[] = {
1812         /* CLK */
1813         RCAR_GP_PIN(1, 25),
1814 };
1815 static const unsigned int can_clk_mux[] = {
1816         CAN_CLK_MARK,
1817 };
1818
1819 /* - CAN FD --------------------------------------------------------------- */
1820 static const unsigned int canfd0_data_a_pins[] = {
1821         /* TX, RX */
1822         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1823 };
1824 static const unsigned int canfd0_data_a_mux[] = {
1825         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1826 };
1827 static const unsigned int canfd0_data_b_pins[] = {
1828         /* TX, RX */
1829         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1830 };
1831 static const unsigned int canfd0_data_b_mux[] = {
1832         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1833 };
1834 static const unsigned int canfd1_data_pins[] = {
1835         /* TX, RX */
1836         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1837 };
1838 static const unsigned int canfd1_data_mux[] = {
1839         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1840 };
1841
1842 /* - DRIF0 --------------------------------------------------------------- */
1843 static const unsigned int drif0_ctrl_a_pins[] = {
1844         /* CLK, SYNC */
1845         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1846 };
1847 static const unsigned int drif0_ctrl_a_mux[] = {
1848         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1849 };
1850 static const unsigned int drif0_data0_a_pins[] = {
1851         /* D0 */
1852         RCAR_GP_PIN(6, 10),
1853 };
1854 static const unsigned int drif0_data0_a_mux[] = {
1855         RIF0_D0_A_MARK,
1856 };
1857 static const unsigned int drif0_data1_a_pins[] = {
1858         /* D1 */
1859         RCAR_GP_PIN(6, 7),
1860 };
1861 static const unsigned int drif0_data1_a_mux[] = {
1862         RIF0_D1_A_MARK,
1863 };
1864 static const unsigned int drif0_ctrl_b_pins[] = {
1865         /* CLK, SYNC */
1866         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1867 };
1868 static const unsigned int drif0_ctrl_b_mux[] = {
1869         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1870 };
1871 static const unsigned int drif0_data0_b_pins[] = {
1872         /* D0 */
1873         RCAR_GP_PIN(5, 1),
1874 };
1875 static const unsigned int drif0_data0_b_mux[] = {
1876         RIF0_D0_B_MARK,
1877 };
1878 static const unsigned int drif0_data1_b_pins[] = {
1879         /* D1 */
1880         RCAR_GP_PIN(5, 2),
1881 };
1882 static const unsigned int drif0_data1_b_mux[] = {
1883         RIF0_D1_B_MARK,
1884 };
1885 static const unsigned int drif0_ctrl_c_pins[] = {
1886         /* CLK, SYNC */
1887         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1888 };
1889 static const unsigned int drif0_ctrl_c_mux[] = {
1890         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1891 };
1892 static const unsigned int drif0_data0_c_pins[] = {
1893         /* D0 */
1894         RCAR_GP_PIN(5, 13),
1895 };
1896 static const unsigned int drif0_data0_c_mux[] = {
1897         RIF0_D0_C_MARK,
1898 };
1899 static const unsigned int drif0_data1_c_pins[] = {
1900         /* D1 */
1901         RCAR_GP_PIN(5, 14),
1902 };
1903 static const unsigned int drif0_data1_c_mux[] = {
1904         RIF0_D1_C_MARK,
1905 };
1906 /* - DRIF1 --------------------------------------------------------------- */
1907 static const unsigned int drif1_ctrl_a_pins[] = {
1908         /* CLK, SYNC */
1909         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1910 };
1911 static const unsigned int drif1_ctrl_a_mux[] = {
1912         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1913 };
1914 static const unsigned int drif1_data0_a_pins[] = {
1915         /* D0 */
1916         RCAR_GP_PIN(6, 19),
1917 };
1918 static const unsigned int drif1_data0_a_mux[] = {
1919         RIF1_D0_A_MARK,
1920 };
1921 static const unsigned int drif1_data1_a_pins[] = {
1922         /* D1 */
1923         RCAR_GP_PIN(6, 20),
1924 };
1925 static const unsigned int drif1_data1_a_mux[] = {
1926         RIF1_D1_A_MARK,
1927 };
1928 static const unsigned int drif1_ctrl_b_pins[] = {
1929         /* CLK, SYNC */
1930         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1931 };
1932 static const unsigned int drif1_ctrl_b_mux[] = {
1933         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1934 };
1935 static const unsigned int drif1_data0_b_pins[] = {
1936         /* D0 */
1937         RCAR_GP_PIN(5, 7),
1938 };
1939 static const unsigned int drif1_data0_b_mux[] = {
1940         RIF1_D0_B_MARK,
1941 };
1942 static const unsigned int drif1_data1_b_pins[] = {
1943         /* D1 */
1944         RCAR_GP_PIN(5, 8),
1945 };
1946 static const unsigned int drif1_data1_b_mux[] = {
1947         RIF1_D1_B_MARK,
1948 };
1949 static const unsigned int drif1_ctrl_c_pins[] = {
1950         /* CLK, SYNC */
1951         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1952 };
1953 static const unsigned int drif1_ctrl_c_mux[] = {
1954         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1955 };
1956 static const unsigned int drif1_data0_c_pins[] = {
1957         /* D0 */
1958         RCAR_GP_PIN(5, 6),
1959 };
1960 static const unsigned int drif1_data0_c_mux[] = {
1961         RIF1_D0_C_MARK,
1962 };
1963 static const unsigned int drif1_data1_c_pins[] = {
1964         /* D1 */
1965         RCAR_GP_PIN(5, 10),
1966 };
1967 static const unsigned int drif1_data1_c_mux[] = {
1968         RIF1_D1_C_MARK,
1969 };
1970 /* - DRIF2 --------------------------------------------------------------- */
1971 static const unsigned int drif2_ctrl_a_pins[] = {
1972         /* CLK, SYNC */
1973         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1974 };
1975 static const unsigned int drif2_ctrl_a_mux[] = {
1976         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1977 };
1978 static const unsigned int drif2_data0_a_pins[] = {
1979         /* D0 */
1980         RCAR_GP_PIN(6, 7),
1981 };
1982 static const unsigned int drif2_data0_a_mux[] = {
1983         RIF2_D0_A_MARK,
1984 };
1985 static const unsigned int drif2_data1_a_pins[] = {
1986         /* D1 */
1987         RCAR_GP_PIN(6, 10),
1988 };
1989 static const unsigned int drif2_data1_a_mux[] = {
1990         RIF2_D1_A_MARK,
1991 };
1992 static const unsigned int drif2_ctrl_b_pins[] = {
1993         /* CLK, SYNC */
1994         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1995 };
1996 static const unsigned int drif2_ctrl_b_mux[] = {
1997         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1998 };
1999 static const unsigned int drif2_data0_b_pins[] = {
2000         /* D0 */
2001         RCAR_GP_PIN(6, 30),
2002 };
2003 static const unsigned int drif2_data0_b_mux[] = {
2004         RIF2_D0_B_MARK,
2005 };
2006 static const unsigned int drif2_data1_b_pins[] = {
2007         /* D1 */
2008         RCAR_GP_PIN(6, 31),
2009 };
2010 static const unsigned int drif2_data1_b_mux[] = {
2011         RIF2_D1_B_MARK,
2012 };
2013 /* - DRIF3 --------------------------------------------------------------- */
2014 static const unsigned int drif3_ctrl_a_pins[] = {
2015         /* CLK, SYNC */
2016         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2017 };
2018 static const unsigned int drif3_ctrl_a_mux[] = {
2019         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2020 };
2021 static const unsigned int drif3_data0_a_pins[] = {
2022         /* D0 */
2023         RCAR_GP_PIN(6, 19),
2024 };
2025 static const unsigned int drif3_data0_a_mux[] = {
2026         RIF3_D0_A_MARK,
2027 };
2028 static const unsigned int drif3_data1_a_pins[] = {
2029         /* D1 */
2030         RCAR_GP_PIN(6, 20),
2031 };
2032 static const unsigned int drif3_data1_a_mux[] = {
2033         RIF3_D1_A_MARK,
2034 };
2035 static const unsigned int drif3_ctrl_b_pins[] = {
2036         /* CLK, SYNC */
2037         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2038 };
2039 static const unsigned int drif3_ctrl_b_mux[] = {
2040         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2041 };
2042 static const unsigned int drif3_data0_b_pins[] = {
2043         /* D0 */
2044         RCAR_GP_PIN(6, 28),
2045 };
2046 static const unsigned int drif3_data0_b_mux[] = {
2047         RIF3_D0_B_MARK,
2048 };
2049 static const unsigned int drif3_data1_b_pins[] = {
2050         /* D1 */
2051         RCAR_GP_PIN(6, 29),
2052 };
2053 static const unsigned int drif3_data1_b_mux[] = {
2054         RIF3_D1_B_MARK,
2055 };
2056
2057 /* - DU --------------------------------------------------------------------- */
2058 static const unsigned int du_rgb666_pins[] = {
2059         /* R[7:2], G[7:2], B[7:2] */
2060         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2061         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2062         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2063         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2064         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2065         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2066 };
2067 static const unsigned int du_rgb666_mux[] = {
2068         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2069         DU_DR3_MARK, DU_DR2_MARK,
2070         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2071         DU_DG3_MARK, DU_DG2_MARK,
2072         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2073         DU_DB3_MARK, DU_DB2_MARK,
2074 };
2075 static const unsigned int du_rgb888_pins[] = {
2076         /* R[7:0], G[7:0], B[7:0] */
2077         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2078         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2079         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2080         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2081         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2082         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2083         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2084         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2085         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2086 };
2087 static const unsigned int du_rgb888_mux[] = {
2088         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2089         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2090         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2091         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2092         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2093         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2094 };
2095 static const unsigned int du_clk_out_0_pins[] = {
2096         /* CLKOUT */
2097         RCAR_GP_PIN(1, 27),
2098 };
2099 static const unsigned int du_clk_out_0_mux[] = {
2100         DU_DOTCLKOUT0_MARK
2101 };
2102 static const unsigned int du_clk_out_1_pins[] = {
2103         /* CLKOUT */
2104         RCAR_GP_PIN(2, 3),
2105 };
2106 static const unsigned int du_clk_out_1_mux[] = {
2107         DU_DOTCLKOUT1_MARK
2108 };
2109 static const unsigned int du_sync_pins[] = {
2110         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2111         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2112 };
2113 static const unsigned int du_sync_mux[] = {
2114         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2115 };
2116 static const unsigned int du_oddf_pins[] = {
2117         /* EXDISP/EXODDF/EXCDE */
2118         RCAR_GP_PIN(2, 2),
2119 };
2120 static const unsigned int du_oddf_mux[] = {
2121         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2122 };
2123 static const unsigned int du_cde_pins[] = {
2124         /* CDE */
2125         RCAR_GP_PIN(2, 0),
2126 };
2127 static const unsigned int du_cde_mux[] = {
2128         DU_CDE_MARK,
2129 };
2130 static const unsigned int du_disp_pins[] = {
2131         /* DISP */
2132         RCAR_GP_PIN(2, 1),
2133 };
2134 static const unsigned int du_disp_mux[] = {
2135         DU_DISP_MARK,
2136 };
2137
2138 /* - HSCIF0 ----------------------------------------------------------------- */
2139 static const unsigned int hscif0_data_pins[] = {
2140         /* RX, TX */
2141         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2142 };
2143 static const unsigned int hscif0_data_mux[] = {
2144         HRX0_MARK, HTX0_MARK,
2145 };
2146 static const unsigned int hscif0_clk_pins[] = {
2147         /* SCK */
2148         RCAR_GP_PIN(5, 12),
2149 };
2150 static const unsigned int hscif0_clk_mux[] = {
2151         HSCK0_MARK,
2152 };
2153 static const unsigned int hscif0_ctrl_pins[] = {
2154         /* RTS, CTS */
2155         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2156 };
2157 static const unsigned int hscif0_ctrl_mux[] = {
2158         HRTS0_N_MARK, HCTS0_N_MARK,
2159 };
2160 /* - HSCIF1 ----------------------------------------------------------------- */
2161 static const unsigned int hscif1_data_a_pins[] = {
2162         /* RX, TX */
2163         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2164 };
2165 static const unsigned int hscif1_data_a_mux[] = {
2166         HRX1_A_MARK, HTX1_A_MARK,
2167 };
2168 static const unsigned int hscif1_clk_a_pins[] = {
2169         /* SCK */
2170         RCAR_GP_PIN(6, 21),
2171 };
2172 static const unsigned int hscif1_clk_a_mux[] = {
2173         HSCK1_A_MARK,
2174 };
2175 static const unsigned int hscif1_ctrl_a_pins[] = {
2176         /* RTS, CTS */
2177         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2178 };
2179 static const unsigned int hscif1_ctrl_a_mux[] = {
2180         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2181 };
2182
2183 static const unsigned int hscif1_data_b_pins[] = {
2184         /* RX, TX */
2185         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2186 };
2187 static const unsigned int hscif1_data_b_mux[] = {
2188         HRX1_B_MARK, HTX1_B_MARK,
2189 };
2190 static const unsigned int hscif1_clk_b_pins[] = {
2191         /* SCK */
2192         RCAR_GP_PIN(5, 0),
2193 };
2194 static const unsigned int hscif1_clk_b_mux[] = {
2195         HSCK1_B_MARK,
2196 };
2197 static const unsigned int hscif1_ctrl_b_pins[] = {
2198         /* RTS, CTS */
2199         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2200 };
2201 static const unsigned int hscif1_ctrl_b_mux[] = {
2202         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2203 };
2204 /* - HSCIF2 ----------------------------------------------------------------- */
2205 static const unsigned int hscif2_data_a_pins[] = {
2206         /* RX, TX */
2207         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2208 };
2209 static const unsigned int hscif2_data_a_mux[] = {
2210         HRX2_A_MARK, HTX2_A_MARK,
2211 };
2212 static const unsigned int hscif2_clk_a_pins[] = {
2213         /* SCK */
2214         RCAR_GP_PIN(6, 10),
2215 };
2216 static const unsigned int hscif2_clk_a_mux[] = {
2217         HSCK2_A_MARK,
2218 };
2219 static const unsigned int hscif2_ctrl_a_pins[] = {
2220         /* RTS, CTS */
2221         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2222 };
2223 static const unsigned int hscif2_ctrl_a_mux[] = {
2224         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2225 };
2226
2227 static const unsigned int hscif2_data_b_pins[] = {
2228         /* RX, TX */
2229         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2230 };
2231 static const unsigned int hscif2_data_b_mux[] = {
2232         HRX2_B_MARK, HTX2_B_MARK,
2233 };
2234 static const unsigned int hscif2_clk_b_pins[] = {
2235         /* SCK */
2236         RCAR_GP_PIN(6, 21),
2237 };
2238 static const unsigned int hscif2_clk_b_mux[] = {
2239         HSCK2_B_MARK,
2240 };
2241 static const unsigned int hscif2_ctrl_b_pins[] = {
2242         /* RTS, CTS */
2243         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2244 };
2245 static const unsigned int hscif2_ctrl_b_mux[] = {
2246         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2247 };
2248
2249 static const unsigned int hscif2_data_c_pins[] = {
2250         /* RX, TX */
2251         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2252 };
2253 static const unsigned int hscif2_data_c_mux[] = {
2254         HRX2_C_MARK, HTX2_C_MARK,
2255 };
2256 static const unsigned int hscif2_clk_c_pins[] = {
2257         /* SCK */
2258         RCAR_GP_PIN(6, 24),
2259 };
2260 static const unsigned int hscif2_clk_c_mux[] = {
2261         HSCK2_C_MARK,
2262 };
2263 static const unsigned int hscif2_ctrl_c_pins[] = {
2264         /* RTS, CTS */
2265         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2266 };
2267 static const unsigned int hscif2_ctrl_c_mux[] = {
2268         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2269 };
2270 /* - HSCIF3 ----------------------------------------------------------------- */
2271 static const unsigned int hscif3_data_a_pins[] = {
2272         /* RX, TX */
2273         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2274 };
2275 static const unsigned int hscif3_data_a_mux[] = {
2276         HRX3_A_MARK, HTX3_A_MARK,
2277 };
2278 static const unsigned int hscif3_clk_pins[] = {
2279         /* SCK */
2280         RCAR_GP_PIN(1, 22),
2281 };
2282 static const unsigned int hscif3_clk_mux[] = {
2283         HSCK3_MARK,
2284 };
2285 static const unsigned int hscif3_ctrl_pins[] = {
2286         /* RTS, CTS */
2287         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2288 };
2289 static const unsigned int hscif3_ctrl_mux[] = {
2290         HRTS3_N_MARK, HCTS3_N_MARK,
2291 };
2292
2293 static const unsigned int hscif3_data_b_pins[] = {
2294         /* RX, TX */
2295         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2296 };
2297 static const unsigned int hscif3_data_b_mux[] = {
2298         HRX3_B_MARK, HTX3_B_MARK,
2299 };
2300 static const unsigned int hscif3_data_c_pins[] = {
2301         /* RX, TX */
2302         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2303 };
2304 static const unsigned int hscif3_data_c_mux[] = {
2305         HRX3_C_MARK, HTX3_C_MARK,
2306 };
2307 static const unsigned int hscif3_data_d_pins[] = {
2308         /* RX, TX */
2309         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2310 };
2311 static const unsigned int hscif3_data_d_mux[] = {
2312         HRX3_D_MARK, HTX3_D_MARK,
2313 };
2314 /* - HSCIF4 ----------------------------------------------------------------- */
2315 static const unsigned int hscif4_data_a_pins[] = {
2316         /* RX, TX */
2317         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2318 };
2319 static const unsigned int hscif4_data_a_mux[] = {
2320         HRX4_A_MARK, HTX4_A_MARK,
2321 };
2322 static const unsigned int hscif4_clk_pins[] = {
2323         /* SCK */
2324         RCAR_GP_PIN(1, 11),
2325 };
2326 static const unsigned int hscif4_clk_mux[] = {
2327         HSCK4_MARK,
2328 };
2329 static const unsigned int hscif4_ctrl_pins[] = {
2330         /* RTS, CTS */
2331         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2332 };
2333 static const unsigned int hscif4_ctrl_mux[] = {
2334         HRTS4_N_MARK, HCTS4_N_MARK,
2335 };
2336
2337 static const unsigned int hscif4_data_b_pins[] = {
2338         /* RX, TX */
2339         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2340 };
2341 static const unsigned int hscif4_data_b_mux[] = {
2342         HRX4_B_MARK, HTX4_B_MARK,
2343 };
2344
2345 /* - I2C -------------------------------------------------------------------- */
2346 static const unsigned int i2c1_a_pins[] = {
2347         /* SDA, SCL */
2348         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2349 };
2350 static const unsigned int i2c1_a_mux[] = {
2351         SDA1_A_MARK, SCL1_A_MARK,
2352 };
2353 static const unsigned int i2c1_b_pins[] = {
2354         /* SDA, SCL */
2355         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2356 };
2357 static const unsigned int i2c1_b_mux[] = {
2358         SDA1_B_MARK, SCL1_B_MARK,
2359 };
2360 static const unsigned int i2c2_a_pins[] = {
2361         /* SDA, SCL */
2362         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2363 };
2364 static const unsigned int i2c2_a_mux[] = {
2365         SDA2_A_MARK, SCL2_A_MARK,
2366 };
2367 static const unsigned int i2c2_b_pins[] = {
2368         /* SDA, SCL */
2369         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2370 };
2371 static const unsigned int i2c2_b_mux[] = {
2372         SDA2_B_MARK, SCL2_B_MARK,
2373 };
2374 static const unsigned int i2c6_a_pins[] = {
2375         /* SDA, SCL */
2376         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2377 };
2378 static const unsigned int i2c6_a_mux[] = {
2379         SDA6_A_MARK, SCL6_A_MARK,
2380 };
2381 static const unsigned int i2c6_b_pins[] = {
2382         /* SDA, SCL */
2383         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2384 };
2385 static const unsigned int i2c6_b_mux[] = {
2386         SDA6_B_MARK, SCL6_B_MARK,
2387 };
2388 static const unsigned int i2c6_c_pins[] = {
2389         /* SDA, SCL */
2390         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2391 };
2392 static const unsigned int i2c6_c_mux[] = {
2393         SDA6_C_MARK, SCL6_C_MARK,
2394 };
2395
2396 /* - INTC-EX ---------------------------------------------------------------- */
2397 static const unsigned int intc_ex_irq0_pins[] = {
2398         /* IRQ0 */
2399         RCAR_GP_PIN(2, 0),
2400 };
2401 static const unsigned int intc_ex_irq0_mux[] = {
2402         IRQ0_MARK,
2403 };
2404 static const unsigned int intc_ex_irq1_pins[] = {
2405         /* IRQ1 */
2406         RCAR_GP_PIN(2, 1),
2407 };
2408 static const unsigned int intc_ex_irq1_mux[] = {
2409         IRQ1_MARK,
2410 };
2411 static const unsigned int intc_ex_irq2_pins[] = {
2412         /* IRQ2 */
2413         RCAR_GP_PIN(2, 2),
2414 };
2415 static const unsigned int intc_ex_irq2_mux[] = {
2416         IRQ2_MARK,
2417 };
2418 static const unsigned int intc_ex_irq3_pins[] = {
2419         /* IRQ3 */
2420         RCAR_GP_PIN(2, 3),
2421 };
2422 static const unsigned int intc_ex_irq3_mux[] = {
2423         IRQ3_MARK,
2424 };
2425 static const unsigned int intc_ex_irq4_pins[] = {
2426         /* IRQ4 */
2427         RCAR_GP_PIN(2, 4),
2428 };
2429 static const unsigned int intc_ex_irq4_mux[] = {
2430         IRQ4_MARK,
2431 };
2432 static const unsigned int intc_ex_irq5_pins[] = {
2433         /* IRQ5 */
2434         RCAR_GP_PIN(2, 5),
2435 };
2436 static const unsigned int intc_ex_irq5_mux[] = {
2437         IRQ5_MARK,
2438 };
2439
2440 /* - MSIOF0 ----------------------------------------------------------------- */
2441 static const unsigned int msiof0_clk_pins[] = {
2442         /* SCK */
2443         RCAR_GP_PIN(5, 17),
2444 };
2445 static const unsigned int msiof0_clk_mux[] = {
2446         MSIOF0_SCK_MARK,
2447 };
2448 static const unsigned int msiof0_sync_pins[] = {
2449         /* SYNC */
2450         RCAR_GP_PIN(5, 18),
2451 };
2452 static const unsigned int msiof0_sync_mux[] = {
2453         MSIOF0_SYNC_MARK,
2454 };
2455 static const unsigned int msiof0_ss1_pins[] = {
2456         /* SS1 */
2457         RCAR_GP_PIN(5, 19),
2458 };
2459 static const unsigned int msiof0_ss1_mux[] = {
2460         MSIOF0_SS1_MARK,
2461 };
2462 static const unsigned int msiof0_ss2_pins[] = {
2463         /* SS2 */
2464         RCAR_GP_PIN(5, 21),
2465 };
2466 static const unsigned int msiof0_ss2_mux[] = {
2467         MSIOF0_SS2_MARK,
2468 };
2469 static const unsigned int msiof0_txd_pins[] = {
2470         /* TXD */
2471         RCAR_GP_PIN(5, 20),
2472 };
2473 static const unsigned int msiof0_txd_mux[] = {
2474         MSIOF0_TXD_MARK,
2475 };
2476 static const unsigned int msiof0_rxd_pins[] = {
2477         /* RXD */
2478         RCAR_GP_PIN(5, 22),
2479 };
2480 static const unsigned int msiof0_rxd_mux[] = {
2481         MSIOF0_RXD_MARK,
2482 };
2483 /* - MSIOF1 ----------------------------------------------------------------- */
2484 static const unsigned int msiof1_clk_a_pins[] = {
2485         /* SCK */
2486         RCAR_GP_PIN(6, 8),
2487 };
2488 static const unsigned int msiof1_clk_a_mux[] = {
2489         MSIOF1_SCK_A_MARK,
2490 };
2491 static const unsigned int msiof1_sync_a_pins[] = {
2492         /* SYNC */
2493         RCAR_GP_PIN(6, 9),
2494 };
2495 static const unsigned int msiof1_sync_a_mux[] = {
2496         MSIOF1_SYNC_A_MARK,
2497 };
2498 static const unsigned int msiof1_ss1_a_pins[] = {
2499         /* SS1 */
2500         RCAR_GP_PIN(6, 5),
2501 };
2502 static const unsigned int msiof1_ss1_a_mux[] = {
2503         MSIOF1_SS1_A_MARK,
2504 };
2505 static const unsigned int msiof1_ss2_a_pins[] = {
2506         /* SS2 */
2507         RCAR_GP_PIN(6, 6),
2508 };
2509 static const unsigned int msiof1_ss2_a_mux[] = {
2510         MSIOF1_SS2_A_MARK,
2511 };
2512 static const unsigned int msiof1_txd_a_pins[] = {
2513         /* TXD */
2514         RCAR_GP_PIN(6, 7),
2515 };
2516 static const unsigned int msiof1_txd_a_mux[] = {
2517         MSIOF1_TXD_A_MARK,
2518 };
2519 static const unsigned int msiof1_rxd_a_pins[] = {
2520         /* RXD */
2521         RCAR_GP_PIN(6, 10),
2522 };
2523 static const unsigned int msiof1_rxd_a_mux[] = {
2524         MSIOF1_RXD_A_MARK,
2525 };
2526 static const unsigned int msiof1_clk_b_pins[] = {
2527         /* SCK */
2528         RCAR_GP_PIN(5, 9),
2529 };
2530 static const unsigned int msiof1_clk_b_mux[] = {
2531         MSIOF1_SCK_B_MARK,
2532 };
2533 static const unsigned int msiof1_sync_b_pins[] = {
2534         /* SYNC */
2535         RCAR_GP_PIN(5, 3),
2536 };
2537 static const unsigned int msiof1_sync_b_mux[] = {
2538         MSIOF1_SYNC_B_MARK,
2539 };
2540 static const unsigned int msiof1_ss1_b_pins[] = {
2541         /* SS1 */
2542         RCAR_GP_PIN(5, 4),
2543 };
2544 static const unsigned int msiof1_ss1_b_mux[] = {
2545         MSIOF1_SS1_B_MARK,
2546 };
2547 static const unsigned int msiof1_ss2_b_pins[] = {
2548         /* SS2 */
2549         RCAR_GP_PIN(5, 0),
2550 };
2551 static const unsigned int msiof1_ss2_b_mux[] = {
2552         MSIOF1_SS2_B_MARK,
2553 };
2554 static const unsigned int msiof1_txd_b_pins[] = {
2555         /* TXD */
2556         RCAR_GP_PIN(5, 8),
2557 };
2558 static const unsigned int msiof1_txd_b_mux[] = {
2559         MSIOF1_TXD_B_MARK,
2560 };
2561 static const unsigned int msiof1_rxd_b_pins[] = {
2562         /* RXD */
2563         RCAR_GP_PIN(5, 7),
2564 };
2565 static const unsigned int msiof1_rxd_b_mux[] = {
2566         MSIOF1_RXD_B_MARK,
2567 };
2568 static const unsigned int msiof1_clk_c_pins[] = {
2569         /* SCK */
2570         RCAR_GP_PIN(6, 17),
2571 };
2572 static const unsigned int msiof1_clk_c_mux[] = {
2573         MSIOF1_SCK_C_MARK,
2574 };
2575 static const unsigned int msiof1_sync_c_pins[] = {
2576         /* SYNC */
2577         RCAR_GP_PIN(6, 18),
2578 };
2579 static const unsigned int msiof1_sync_c_mux[] = {
2580         MSIOF1_SYNC_C_MARK,
2581 };
2582 static const unsigned int msiof1_ss1_c_pins[] = {
2583         /* SS1 */
2584         RCAR_GP_PIN(6, 21),
2585 };
2586 static const unsigned int msiof1_ss1_c_mux[] = {
2587         MSIOF1_SS1_C_MARK,
2588 };
2589 static const unsigned int msiof1_ss2_c_pins[] = {
2590         /* SS2 */
2591         RCAR_GP_PIN(6, 27),
2592 };
2593 static const unsigned int msiof1_ss2_c_mux[] = {
2594         MSIOF1_SS2_C_MARK,
2595 };
2596 static const unsigned int msiof1_txd_c_pins[] = {
2597         /* TXD */
2598         RCAR_GP_PIN(6, 20),
2599 };
2600 static const unsigned int msiof1_txd_c_mux[] = {
2601         MSIOF1_TXD_C_MARK,
2602 };
2603 static const unsigned int msiof1_rxd_c_pins[] = {
2604         /* RXD */
2605         RCAR_GP_PIN(6, 19),
2606 };
2607 static const unsigned int msiof1_rxd_c_mux[] = {
2608         MSIOF1_RXD_C_MARK,
2609 };
2610 static const unsigned int msiof1_clk_d_pins[] = {
2611         /* SCK */
2612         RCAR_GP_PIN(5, 12),
2613 };
2614 static const unsigned int msiof1_clk_d_mux[] = {
2615         MSIOF1_SCK_D_MARK,
2616 };
2617 static const unsigned int msiof1_sync_d_pins[] = {
2618         /* SYNC */
2619         RCAR_GP_PIN(5, 15),
2620 };
2621 static const unsigned int msiof1_sync_d_mux[] = {
2622         MSIOF1_SYNC_D_MARK,
2623 };
2624 static const unsigned int msiof1_ss1_d_pins[] = {
2625         /* SS1 */
2626         RCAR_GP_PIN(5, 16),
2627 };
2628 static const unsigned int msiof1_ss1_d_mux[] = {
2629         MSIOF1_SS1_D_MARK,
2630 };
2631 static const unsigned int msiof1_ss2_d_pins[] = {
2632         /* SS2 */
2633         RCAR_GP_PIN(5, 21),
2634 };
2635 static const unsigned int msiof1_ss2_d_mux[] = {
2636         MSIOF1_SS2_D_MARK,
2637 };
2638 static const unsigned int msiof1_txd_d_pins[] = {
2639         /* TXD */
2640         RCAR_GP_PIN(5, 14),
2641 };
2642 static const unsigned int msiof1_txd_d_mux[] = {
2643         MSIOF1_TXD_D_MARK,
2644 };
2645 static const unsigned int msiof1_rxd_d_pins[] = {
2646         /* RXD */
2647         RCAR_GP_PIN(5, 13),
2648 };
2649 static const unsigned int msiof1_rxd_d_mux[] = {
2650         MSIOF1_RXD_D_MARK,
2651 };
2652 static const unsigned int msiof1_clk_e_pins[] = {
2653         /* SCK */
2654         RCAR_GP_PIN(3, 0),
2655 };
2656 static const unsigned int msiof1_clk_e_mux[] = {
2657         MSIOF1_SCK_E_MARK,
2658 };
2659 static const unsigned int msiof1_sync_e_pins[] = {
2660         /* SYNC */
2661         RCAR_GP_PIN(3, 1),
2662 };
2663 static const unsigned int msiof1_sync_e_mux[] = {
2664         MSIOF1_SYNC_E_MARK,
2665 };
2666 static const unsigned int msiof1_ss1_e_pins[] = {
2667         /* SS1 */
2668         RCAR_GP_PIN(3, 4),
2669 };
2670 static const unsigned int msiof1_ss1_e_mux[] = {
2671         MSIOF1_SS1_E_MARK,
2672 };
2673 static const unsigned int msiof1_ss2_e_pins[] = {
2674         /* SS2 */
2675         RCAR_GP_PIN(3, 5),
2676 };
2677 static const unsigned int msiof1_ss2_e_mux[] = {
2678         MSIOF1_SS2_E_MARK,
2679 };
2680 static const unsigned int msiof1_txd_e_pins[] = {
2681         /* TXD */
2682         RCAR_GP_PIN(3, 3),
2683 };
2684 static const unsigned int msiof1_txd_e_mux[] = {
2685         MSIOF1_TXD_E_MARK,
2686 };
2687 static const unsigned int msiof1_rxd_e_pins[] = {
2688         /* RXD */
2689         RCAR_GP_PIN(3, 2),
2690 };
2691 static const unsigned int msiof1_rxd_e_mux[] = {
2692         MSIOF1_RXD_E_MARK,
2693 };
2694 static const unsigned int msiof1_clk_f_pins[] = {
2695         /* SCK */
2696         RCAR_GP_PIN(5, 23),
2697 };
2698 static const unsigned int msiof1_clk_f_mux[] = {
2699         MSIOF1_SCK_F_MARK,
2700 };
2701 static const unsigned int msiof1_sync_f_pins[] = {
2702         /* SYNC */
2703         RCAR_GP_PIN(5, 24),
2704 };
2705 static const unsigned int msiof1_sync_f_mux[] = {
2706         MSIOF1_SYNC_F_MARK,
2707 };
2708 static const unsigned int msiof1_ss1_f_pins[] = {
2709         /* SS1 */
2710         RCAR_GP_PIN(6, 1),
2711 };
2712 static const unsigned int msiof1_ss1_f_mux[] = {
2713         MSIOF1_SS1_F_MARK,
2714 };
2715 static const unsigned int msiof1_ss2_f_pins[] = {
2716         /* SS2 */
2717         RCAR_GP_PIN(6, 2),
2718 };
2719 static const unsigned int msiof1_ss2_f_mux[] = {
2720         MSIOF1_SS2_F_MARK,
2721 };
2722 static const unsigned int msiof1_txd_f_pins[] = {
2723         /* TXD */
2724         RCAR_GP_PIN(6, 0),
2725 };
2726 static const unsigned int msiof1_txd_f_mux[] = {
2727         MSIOF1_TXD_F_MARK,
2728 };
2729 static const unsigned int msiof1_rxd_f_pins[] = {
2730         /* RXD */
2731         RCAR_GP_PIN(5, 25),
2732 };
2733 static const unsigned int msiof1_rxd_f_mux[] = {
2734         MSIOF1_RXD_F_MARK,
2735 };
2736 static const unsigned int msiof1_clk_g_pins[] = {
2737         /* SCK */
2738         RCAR_GP_PIN(3, 6),
2739 };
2740 static const unsigned int msiof1_clk_g_mux[] = {
2741         MSIOF1_SCK_G_MARK,
2742 };
2743 static const unsigned int msiof1_sync_g_pins[] = {
2744         /* SYNC */
2745         RCAR_GP_PIN(3, 7),
2746 };
2747 static const unsigned int msiof1_sync_g_mux[] = {
2748         MSIOF1_SYNC_G_MARK,
2749 };
2750 static const unsigned int msiof1_ss1_g_pins[] = {
2751         /* SS1 */
2752         RCAR_GP_PIN(3, 10),
2753 };
2754 static const unsigned int msiof1_ss1_g_mux[] = {
2755         MSIOF1_SS1_G_MARK,
2756 };
2757 static const unsigned int msiof1_ss2_g_pins[] = {
2758         /* SS2 */
2759         RCAR_GP_PIN(3, 11),
2760 };
2761 static const unsigned int msiof1_ss2_g_mux[] = {
2762         MSIOF1_SS2_G_MARK,
2763 };
2764 static const unsigned int msiof1_txd_g_pins[] = {
2765         /* TXD */
2766         RCAR_GP_PIN(3, 9),
2767 };
2768 static const unsigned int msiof1_txd_g_mux[] = {
2769         MSIOF1_TXD_G_MARK,
2770 };
2771 static const unsigned int msiof1_rxd_g_pins[] = {
2772         /* RXD */
2773         RCAR_GP_PIN(3, 8),
2774 };
2775 static const unsigned int msiof1_rxd_g_mux[] = {
2776         MSIOF1_RXD_G_MARK,
2777 };
2778 /* - MSIOF2 ----------------------------------------------------------------- */
2779 static const unsigned int msiof2_clk_a_pins[] = {
2780         /* SCK */
2781         RCAR_GP_PIN(1, 9),
2782 };
2783 static const unsigned int msiof2_clk_a_mux[] = {
2784         MSIOF2_SCK_A_MARK,
2785 };
2786 static const unsigned int msiof2_sync_a_pins[] = {
2787         /* SYNC */
2788         RCAR_GP_PIN(1, 8),
2789 };
2790 static const unsigned int msiof2_sync_a_mux[] = {
2791         MSIOF2_SYNC_A_MARK,
2792 };
2793 static const unsigned int msiof2_ss1_a_pins[] = {
2794         /* SS1 */
2795         RCAR_GP_PIN(1, 6),
2796 };
2797 static const unsigned int msiof2_ss1_a_mux[] = {
2798         MSIOF2_SS1_A_MARK,
2799 };
2800 static const unsigned int msiof2_ss2_a_pins[] = {
2801         /* SS2 */
2802         RCAR_GP_PIN(1, 7),
2803 };
2804 static const unsigned int msiof2_ss2_a_mux[] = {
2805         MSIOF2_SS2_A_MARK,
2806 };
2807 static const unsigned int msiof2_txd_a_pins[] = {
2808         /* TXD */
2809         RCAR_GP_PIN(1, 11),
2810 };
2811 static const unsigned int msiof2_txd_a_mux[] = {
2812         MSIOF2_TXD_A_MARK,
2813 };
2814 static const unsigned int msiof2_rxd_a_pins[] = {
2815         /* RXD */
2816         RCAR_GP_PIN(1, 10),
2817 };
2818 static const unsigned int msiof2_rxd_a_mux[] = {
2819         MSIOF2_RXD_A_MARK,
2820 };
2821 static const unsigned int msiof2_clk_b_pins[] = {
2822         /* SCK */
2823         RCAR_GP_PIN(0, 4),
2824 };
2825 static const unsigned int msiof2_clk_b_mux[] = {
2826         MSIOF2_SCK_B_MARK,
2827 };
2828 static const unsigned int msiof2_sync_b_pins[] = {
2829         /* SYNC */
2830         RCAR_GP_PIN(0, 5),
2831 };
2832 static const unsigned int msiof2_sync_b_mux[] = {
2833         MSIOF2_SYNC_B_MARK,
2834 };
2835 static const unsigned int msiof2_ss1_b_pins[] = {
2836         /* SS1 */
2837         RCAR_GP_PIN(0, 0),
2838 };
2839 static const unsigned int msiof2_ss1_b_mux[] = {
2840         MSIOF2_SS1_B_MARK,
2841 };
2842 static const unsigned int msiof2_ss2_b_pins[] = {
2843         /* SS2 */
2844         RCAR_GP_PIN(0, 1),
2845 };
2846 static const unsigned int msiof2_ss2_b_mux[] = {
2847         MSIOF2_SS2_B_MARK,
2848 };
2849 static const unsigned int msiof2_txd_b_pins[] = {
2850         /* TXD */
2851         RCAR_GP_PIN(0, 7),
2852 };
2853 static const unsigned int msiof2_txd_b_mux[] = {
2854         MSIOF2_TXD_B_MARK,
2855 };
2856 static const unsigned int msiof2_rxd_b_pins[] = {
2857         /* RXD */
2858         RCAR_GP_PIN(0, 6),
2859 };
2860 static const unsigned int msiof2_rxd_b_mux[] = {
2861         MSIOF2_RXD_B_MARK,
2862 };
2863 static const unsigned int msiof2_clk_c_pins[] = {
2864         /* SCK */
2865         RCAR_GP_PIN(2, 12),
2866 };
2867 static const unsigned int msiof2_clk_c_mux[] = {
2868         MSIOF2_SCK_C_MARK,
2869 };
2870 static const unsigned int msiof2_sync_c_pins[] = {
2871         /* SYNC */
2872         RCAR_GP_PIN(2, 11),
2873 };
2874 static const unsigned int msiof2_sync_c_mux[] = {
2875         MSIOF2_SYNC_C_MARK,
2876 };
2877 static const unsigned int msiof2_ss1_c_pins[] = {
2878         /* SS1 */
2879         RCAR_GP_PIN(2, 10),
2880 };
2881 static const unsigned int msiof2_ss1_c_mux[] = {
2882         MSIOF2_SS1_C_MARK,
2883 };
2884 static const unsigned int msiof2_ss2_c_pins[] = {
2885         /* SS2 */
2886         RCAR_GP_PIN(2, 9),
2887 };
2888 static const unsigned int msiof2_ss2_c_mux[] = {
2889         MSIOF2_SS2_C_MARK,
2890 };
2891 static const unsigned int msiof2_txd_c_pins[] = {
2892         /* TXD */
2893         RCAR_GP_PIN(2, 14),
2894 };
2895 static const unsigned int msiof2_txd_c_mux[] = {
2896         MSIOF2_TXD_C_MARK,
2897 };
2898 static const unsigned int msiof2_rxd_c_pins[] = {
2899         /* RXD */
2900         RCAR_GP_PIN(2, 13),
2901 };
2902 static const unsigned int msiof2_rxd_c_mux[] = {
2903         MSIOF2_RXD_C_MARK,
2904 };
2905 static const unsigned int msiof2_clk_d_pins[] = {
2906         /* SCK */
2907         RCAR_GP_PIN(0, 8),
2908 };
2909 static const unsigned int msiof2_clk_d_mux[] = {
2910         MSIOF2_SCK_D_MARK,
2911 };
2912 static const unsigned int msiof2_sync_d_pins[] = {
2913         /* SYNC */
2914         RCAR_GP_PIN(0, 9),
2915 };
2916 static const unsigned int msiof2_sync_d_mux[] = {
2917         MSIOF2_SYNC_D_MARK,
2918 };
2919 static const unsigned int msiof2_ss1_d_pins[] = {
2920         /* SS1 */
2921         RCAR_GP_PIN(0, 12),
2922 };
2923 static const unsigned int msiof2_ss1_d_mux[] = {
2924         MSIOF2_SS1_D_MARK,
2925 };
2926 static const unsigned int msiof2_ss2_d_pins[] = {
2927         /* SS2 */
2928         RCAR_GP_PIN(0, 13),
2929 };
2930 static const unsigned int msiof2_ss2_d_mux[] = {
2931         MSIOF2_SS2_D_MARK,
2932 };
2933 static const unsigned int msiof2_txd_d_pins[] = {
2934         /* TXD */
2935         RCAR_GP_PIN(0, 11),
2936 };
2937 static const unsigned int msiof2_txd_d_mux[] = {
2938         MSIOF2_TXD_D_MARK,
2939 };
2940 static const unsigned int msiof2_rxd_d_pins[] = {
2941         /* RXD */
2942         RCAR_GP_PIN(0, 10),
2943 };
2944 static const unsigned int msiof2_rxd_d_mux[] = {
2945         MSIOF2_RXD_D_MARK,
2946 };
2947 /* - MSIOF3 ----------------------------------------------------------------- */
2948 static const unsigned int msiof3_clk_a_pins[] = {
2949         /* SCK */
2950         RCAR_GP_PIN(0, 0),
2951 };
2952 static const unsigned int msiof3_clk_a_mux[] = {
2953         MSIOF3_SCK_A_MARK,
2954 };
2955 static const unsigned int msiof3_sync_a_pins[] = {
2956         /* SYNC */
2957         RCAR_GP_PIN(0, 1),
2958 };
2959 static const unsigned int msiof3_sync_a_mux[] = {
2960         MSIOF3_SYNC_A_MARK,
2961 };
2962 static const unsigned int msiof3_ss1_a_pins[] = {
2963         /* SS1 */
2964         RCAR_GP_PIN(0, 14),
2965 };
2966 static const unsigned int msiof3_ss1_a_mux[] = {
2967         MSIOF3_SS1_A_MARK,
2968 };
2969 static const unsigned int msiof3_ss2_a_pins[] = {
2970         /* SS2 */
2971         RCAR_GP_PIN(0, 15),
2972 };
2973 static const unsigned int msiof3_ss2_a_mux[] = {
2974         MSIOF3_SS2_A_MARK,
2975 };
2976 static const unsigned int msiof3_txd_a_pins[] = {
2977         /* TXD */
2978         RCAR_GP_PIN(0, 3),
2979 };
2980 static const unsigned int msiof3_txd_a_mux[] = {
2981         MSIOF3_TXD_A_MARK,
2982 };
2983 static const unsigned int msiof3_rxd_a_pins[] = {
2984         /* RXD */
2985         RCAR_GP_PIN(0, 2),
2986 };
2987 static const unsigned int msiof3_rxd_a_mux[] = {
2988         MSIOF3_RXD_A_MARK,
2989 };
2990 static const unsigned int msiof3_clk_b_pins[] = {
2991         /* SCK */
2992         RCAR_GP_PIN(1, 2),
2993 };
2994 static const unsigned int msiof3_clk_b_mux[] = {
2995         MSIOF3_SCK_B_MARK,
2996 };
2997 static const unsigned int msiof3_sync_b_pins[] = {
2998         /* SYNC */
2999         RCAR_GP_PIN(1, 0),
3000 };
3001 static const unsigned int msiof3_sync_b_mux[] = {
3002         MSIOF3_SYNC_B_MARK,
3003 };
3004 static const unsigned int msiof3_ss1_b_pins[] = {
3005         /* SS1 */
3006         RCAR_GP_PIN(1, 4),
3007 };
3008 static const unsigned int msiof3_ss1_b_mux[] = {
3009         MSIOF3_SS1_B_MARK,
3010 };
3011 static const unsigned int msiof3_ss2_b_pins[] = {
3012         /* SS2 */
3013         RCAR_GP_PIN(1, 5),
3014 };
3015 static const unsigned int msiof3_ss2_b_mux[] = {
3016         MSIOF3_SS2_B_MARK,
3017 };
3018 static const unsigned int msiof3_txd_b_pins[] = {
3019         /* TXD */
3020         RCAR_GP_PIN(1, 1),
3021 };
3022 static const unsigned int msiof3_txd_b_mux[] = {
3023         MSIOF3_TXD_B_MARK,
3024 };
3025 static const unsigned int msiof3_rxd_b_pins[] = {
3026         /* RXD */
3027         RCAR_GP_PIN(1, 3),
3028 };
3029 static const unsigned int msiof3_rxd_b_mux[] = {
3030         MSIOF3_RXD_B_MARK,
3031 };
3032 static const unsigned int msiof3_clk_c_pins[] = {
3033         /* SCK */
3034         RCAR_GP_PIN(1, 12),
3035 };
3036 static const unsigned int msiof3_clk_c_mux[] = {
3037         MSIOF3_SCK_C_MARK,
3038 };
3039 static const unsigned int msiof3_sync_c_pins[] = {
3040         /* SYNC */
3041         RCAR_GP_PIN(1, 13),
3042 };
3043 static const unsigned int msiof3_sync_c_mux[] = {
3044         MSIOF3_SYNC_C_MARK,
3045 };
3046 static const unsigned int msiof3_txd_c_pins[] = {
3047         /* TXD */
3048         RCAR_GP_PIN(1, 15),
3049 };
3050 static const unsigned int msiof3_txd_c_mux[] = {
3051         MSIOF3_TXD_C_MARK,
3052 };
3053 static const unsigned int msiof3_rxd_c_pins[] = {
3054         /* RXD */
3055         RCAR_GP_PIN(1, 14),
3056 };
3057 static const unsigned int msiof3_rxd_c_mux[] = {
3058         MSIOF3_RXD_C_MARK,
3059 };
3060 static const unsigned int msiof3_clk_d_pins[] = {
3061         /* SCK */
3062         RCAR_GP_PIN(1, 22),
3063 };
3064 static const unsigned int msiof3_clk_d_mux[] = {
3065         MSIOF3_SCK_D_MARK,
3066 };
3067 static const unsigned int msiof3_sync_d_pins[] = {
3068         /* SYNC */
3069         RCAR_GP_PIN(1, 23),
3070 };
3071 static const unsigned int msiof3_sync_d_mux[] = {
3072         MSIOF3_SYNC_D_MARK,
3073 };
3074 static const unsigned int msiof3_ss1_d_pins[] = {
3075         /* SS1 */
3076         RCAR_GP_PIN(1, 26),
3077 };
3078 static const unsigned int msiof3_ss1_d_mux[] = {
3079         MSIOF3_SS1_D_MARK,
3080 };
3081 static const unsigned int msiof3_txd_d_pins[] = {
3082         /* TXD */
3083         RCAR_GP_PIN(1, 25),
3084 };
3085 static const unsigned int msiof3_txd_d_mux[] = {
3086         MSIOF3_TXD_D_MARK,
3087 };
3088 static const unsigned int msiof3_rxd_d_pins[] = {
3089         /* RXD */
3090         RCAR_GP_PIN(1, 24),
3091 };
3092 static const unsigned int msiof3_rxd_d_mux[] = {
3093         MSIOF3_RXD_D_MARK,
3094 };
3095
3096 static const unsigned int msiof3_clk_e_pins[] = {
3097         /* SCK */
3098         RCAR_GP_PIN(2, 3),
3099 };
3100 static const unsigned int msiof3_clk_e_mux[] = {
3101         MSIOF3_SCK_E_MARK,
3102 };
3103 static const unsigned int msiof3_sync_e_pins[] = {
3104         /* SYNC */
3105         RCAR_GP_PIN(2, 2),
3106 };
3107 static const unsigned int msiof3_sync_e_mux[] = {
3108         MSIOF3_SYNC_E_MARK,
3109 };
3110 static const unsigned int msiof3_ss1_e_pins[] = {
3111         /* SS1 */
3112         RCAR_GP_PIN(2, 1),
3113 };
3114 static const unsigned int msiof3_ss1_e_mux[] = {
3115         MSIOF3_SS1_E_MARK,
3116 };
3117 static const unsigned int msiof3_ss2_e_pins[] = {
3118         /* SS1 */
3119         RCAR_GP_PIN(2, 0),
3120 };
3121 static const unsigned int msiof3_ss2_e_mux[] = {
3122         MSIOF3_SS2_E_MARK,
3123 };
3124 static const unsigned int msiof3_txd_e_pins[] = {
3125         /* TXD */
3126         RCAR_GP_PIN(2, 5),
3127 };
3128 static const unsigned int msiof3_txd_e_mux[] = {
3129         MSIOF3_TXD_E_MARK,
3130 };
3131 static const unsigned int msiof3_rxd_e_pins[] = {
3132         /* RXD */
3133         RCAR_GP_PIN(2, 4),
3134 };
3135 static const unsigned int msiof3_rxd_e_mux[] = {
3136         MSIOF3_RXD_E_MARK,
3137 };
3138
3139 /* - PWM0 --------------------------------------------------------------------*/
3140 static const unsigned int pwm0_pins[] = {
3141         /* PWM */
3142         RCAR_GP_PIN(2, 6),
3143 };
3144 static const unsigned int pwm0_mux[] = {
3145         PWM0_MARK,
3146 };
3147 /* - PWM1 --------------------------------------------------------------------*/
3148 static const unsigned int pwm1_a_pins[] = {
3149         /* PWM */
3150         RCAR_GP_PIN(2, 7),
3151 };
3152 static const unsigned int pwm1_a_mux[] = {
3153         PWM1_A_MARK,
3154 };
3155 static const unsigned int pwm1_b_pins[] = {
3156         /* PWM */
3157         RCAR_GP_PIN(1, 8),
3158 };
3159 static const unsigned int pwm1_b_mux[] = {
3160         PWM1_B_MARK,
3161 };
3162 /* - PWM2 --------------------------------------------------------------------*/
3163 static const unsigned int pwm2_a_pins[] = {
3164         /* PWM */
3165         RCAR_GP_PIN(2, 8),
3166 };
3167 static const unsigned int pwm2_a_mux[] = {
3168         PWM2_A_MARK,
3169 };
3170 static const unsigned int pwm2_b_pins[] = {
3171         /* PWM */
3172         RCAR_GP_PIN(1, 11),
3173 };
3174 static const unsigned int pwm2_b_mux[] = {
3175         PWM2_B_MARK,
3176 };
3177 /* - PWM3 --------------------------------------------------------------------*/
3178 static const unsigned int pwm3_a_pins[] = {
3179         /* PWM */
3180         RCAR_GP_PIN(1, 0),
3181 };
3182 static const unsigned int pwm3_a_mux[] = {
3183         PWM3_A_MARK,
3184 };
3185 static const unsigned int pwm3_b_pins[] = {
3186         /* PWM */
3187         RCAR_GP_PIN(2, 2),
3188 };
3189 static const unsigned int pwm3_b_mux[] = {
3190         PWM3_B_MARK,
3191 };
3192 /* - PWM4 --------------------------------------------------------------------*/
3193 static const unsigned int pwm4_a_pins[] = {
3194         /* PWM */
3195         RCAR_GP_PIN(1, 1),
3196 };
3197 static const unsigned int pwm4_a_mux[] = {
3198         PWM4_A_MARK,
3199 };
3200 static const unsigned int pwm4_b_pins[] = {
3201         /* PWM */
3202         RCAR_GP_PIN(2, 3),
3203 };
3204 static const unsigned int pwm4_b_mux[] = {
3205         PWM4_B_MARK,
3206 };
3207 /* - PWM5 --------------------------------------------------------------------*/
3208 static const unsigned int pwm5_a_pins[] = {
3209         /* PWM */
3210         RCAR_GP_PIN(1, 2),
3211 };
3212 static const unsigned int pwm5_a_mux[] = {
3213         PWM5_A_MARK,
3214 };
3215 static const unsigned int pwm5_b_pins[] = {
3216         /* PWM */
3217         RCAR_GP_PIN(2, 4),
3218 };
3219 static const unsigned int pwm5_b_mux[] = {
3220         PWM5_B_MARK,
3221 };
3222 /* - PWM6 --------------------------------------------------------------------*/
3223 static const unsigned int pwm6_a_pins[] = {
3224         /* PWM */
3225         RCAR_GP_PIN(1, 3),
3226 };
3227 static const unsigned int pwm6_a_mux[] = {
3228         PWM6_A_MARK,
3229 };
3230 static const unsigned int pwm6_b_pins[] = {
3231         /* PWM */
3232         RCAR_GP_PIN(2, 5),
3233 };
3234 static const unsigned int pwm6_b_mux[] = {
3235         PWM6_B_MARK,
3236 };
3237
3238 /* - SCIF0 ------------------------------------------------------------------ */
3239 static const unsigned int scif0_data_pins[] = {
3240         /* RX, TX */
3241         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3242 };
3243 static const unsigned int scif0_data_mux[] = {
3244         RX0_MARK, TX0_MARK,
3245 };
3246 static const unsigned int scif0_clk_pins[] = {
3247         /* SCK */
3248         RCAR_GP_PIN(5, 0),
3249 };
3250 static const unsigned int scif0_clk_mux[] = {
3251         SCK0_MARK,
3252 };
3253 static const unsigned int scif0_ctrl_pins[] = {
3254         /* RTS, CTS */
3255         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3256 };
3257 static const unsigned int scif0_ctrl_mux[] = {
3258         RTS0_N_TANS_MARK, CTS0_N_MARK,
3259 };
3260 /* - SCIF1 ------------------------------------------------------------------ */
3261 static const unsigned int scif1_data_a_pins[] = {
3262         /* RX, TX */
3263         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3264 };
3265 static const unsigned int scif1_data_a_mux[] = {
3266         RX1_A_MARK, TX1_A_MARK,
3267 };
3268 static const unsigned int scif1_clk_pins[] = {
3269         /* SCK */
3270         RCAR_GP_PIN(6, 21),
3271 };
3272 static const unsigned int scif1_clk_mux[] = {
3273         SCK1_MARK,
3274 };
3275 static const unsigned int scif1_ctrl_pins[] = {
3276         /* RTS, CTS */
3277         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3278 };
3279 static const unsigned int scif1_ctrl_mux[] = {
3280         RTS1_N_TANS_MARK, CTS1_N_MARK,
3281 };
3282
3283 static const unsigned int scif1_data_b_pins[] = {
3284         /* RX, TX */
3285         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3286 };
3287 static const unsigned int scif1_data_b_mux[] = {
3288         RX1_B_MARK, TX1_B_MARK,
3289 };
3290 /* - SCIF2 ------------------------------------------------------------------ */
3291 static const unsigned int scif2_data_a_pins[] = {
3292         /* RX, TX */
3293         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3294 };
3295 static const unsigned int scif2_data_a_mux[] = {
3296         RX2_A_MARK, TX2_A_MARK,
3297 };
3298 static const unsigned int scif2_clk_pins[] = {
3299         /* SCK */
3300         RCAR_GP_PIN(5, 9),
3301 };
3302 static const unsigned int scif2_clk_mux[] = {
3303         SCK2_MARK,
3304 };
3305 static const unsigned int scif2_data_b_pins[] = {
3306         /* RX, TX */
3307         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3308 };
3309 static const unsigned int scif2_data_b_mux[] = {
3310         RX2_B_MARK, TX2_B_MARK,
3311 };
3312 /* - SCIF3 ------------------------------------------------------------------ */
3313 static const unsigned int scif3_data_a_pins[] = {
3314         /* RX, TX */
3315         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3316 };
3317 static const unsigned int scif3_data_a_mux[] = {
3318         RX3_A_MARK, TX3_A_MARK,
3319 };
3320 static const unsigned int scif3_clk_pins[] = {
3321         /* SCK */
3322         RCAR_GP_PIN(1, 22),
3323 };
3324 static const unsigned int scif3_clk_mux[] = {
3325         SCK3_MARK,
3326 };
3327 static const unsigned int scif3_ctrl_pins[] = {
3328         /* RTS, CTS */
3329         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3330 };
3331 static const unsigned int scif3_ctrl_mux[] = {
3332         RTS3_N_TANS_MARK, CTS3_N_MARK,
3333 };
3334 static const unsigned int scif3_data_b_pins[] = {
3335         /* RX, TX */
3336         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3337 };
3338 static const unsigned int scif3_data_b_mux[] = {
3339         RX3_B_MARK, TX3_B_MARK,
3340 };
3341 /* - SCIF4 ------------------------------------------------------------------ */
3342 static const unsigned int scif4_data_a_pins[] = {
3343         /* RX, TX */
3344         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3345 };
3346 static const unsigned int scif4_data_a_mux[] = {
3347         RX4_A_MARK, TX4_A_MARK,
3348 };
3349 static const unsigned int scif4_clk_a_pins[] = {
3350         /* SCK */
3351         RCAR_GP_PIN(2, 10),
3352 };
3353 static const unsigned int scif4_clk_a_mux[] = {
3354         SCK4_A_MARK,
3355 };
3356 static const unsigned int scif4_ctrl_a_pins[] = {
3357         /* RTS, CTS */
3358         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3359 };
3360 static const unsigned int scif4_ctrl_a_mux[] = {
3361         RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3362 };
3363 static const unsigned int scif4_data_b_pins[] = {
3364         /* RX, TX */
3365         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3366 };
3367 static const unsigned int scif4_data_b_mux[] = {
3368         RX4_B_MARK, TX4_B_MARK,
3369 };
3370 static const unsigned int scif4_clk_b_pins[] = {
3371         /* SCK */
3372         RCAR_GP_PIN(1, 5),
3373 };
3374 static const unsigned int scif4_clk_b_mux[] = {
3375         SCK4_B_MARK,
3376 };
3377 static const unsigned int scif4_ctrl_b_pins[] = {
3378         /* RTS, CTS */
3379         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3380 };
3381 static const unsigned int scif4_ctrl_b_mux[] = {
3382         RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3383 };
3384 static const unsigned int scif4_data_c_pins[] = {
3385         /* RX, TX */
3386         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3387 };
3388 static const unsigned int scif4_data_c_mux[] = {
3389         RX4_C_MARK, TX4_C_MARK,
3390 };
3391 static const unsigned int scif4_clk_c_pins[] = {
3392         /* SCK */
3393         RCAR_GP_PIN(0, 8),
3394 };
3395 static const unsigned int scif4_clk_c_mux[] = {
3396         SCK4_C_MARK,
3397 };
3398 static const unsigned int scif4_ctrl_c_pins[] = {
3399         /* RTS, CTS */
3400         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3401 };
3402 static const unsigned int scif4_ctrl_c_mux[] = {
3403         RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3404 };
3405 /* - SCIF5 ------------------------------------------------------------------ */
3406 static const unsigned int scif5_data_a_pins[] = {
3407         /* RX, TX */
3408         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3409 };
3410 static const unsigned int scif5_data_a_mux[] = {
3411         RX5_A_MARK, TX5_A_MARK,
3412 };
3413 static const unsigned int scif5_clk_a_pins[] = {
3414         /* SCK */
3415         RCAR_GP_PIN(6, 21),
3416 };
3417 static const unsigned int scif5_clk_a_mux[] = {
3418         SCK5_A_MARK,
3419 };
3420
3421 static const unsigned int scif5_data_b_pins[] = {
3422         /* RX, TX */
3423         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3424 };
3425 static const unsigned int scif5_data_b_mux[] = {
3426         RX5_B_MARK, TX5_B_MARK,
3427 };
3428 static const unsigned int scif5_clk_b_pins[] = {
3429         /* SCK */
3430         RCAR_GP_PIN(5, 0),
3431 };
3432 static const unsigned int scif5_clk_b_mux[] = {
3433         SCK5_B_MARK,
3434 };
3435
3436 /* - SCIF Clock ------------------------------------------------------------- */
3437 static const unsigned int scif_clk_a_pins[] = {
3438         /* SCIF_CLK */
3439         RCAR_GP_PIN(6, 23),
3440 };
3441 static const unsigned int scif_clk_a_mux[] = {
3442         SCIF_CLK_A_MARK,
3443 };
3444 static const unsigned int scif_clk_b_pins[] = {
3445         /* SCIF_CLK */
3446         RCAR_GP_PIN(5, 9),
3447 };
3448 static const unsigned int scif_clk_b_mux[] = {
3449         SCIF_CLK_B_MARK,
3450 };
3451
3452 /* - SDHI0 ------------------------------------------------------------------ */
3453 static const unsigned int sdhi0_data1_pins[] = {
3454         /* D0 */
3455         RCAR_GP_PIN(3, 2),
3456 };
3457 static const unsigned int sdhi0_data1_mux[] = {
3458         SD0_DAT0_MARK,
3459 };
3460 static const unsigned int sdhi0_data4_pins[] = {
3461         /* D[0:3] */
3462         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3463         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3464 };
3465 static const unsigned int sdhi0_data4_mux[] = {
3466         SD0_DAT0_MARK, SD0_DAT1_MARK,
3467         SD0_DAT2_MARK, SD0_DAT3_MARK,
3468 };
3469 static const unsigned int sdhi0_ctrl_pins[] = {
3470         /* CLK, CMD */
3471         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3472 };
3473 static const unsigned int sdhi0_ctrl_mux[] = {
3474         SD0_CLK_MARK, SD0_CMD_MARK,
3475 };
3476 static const unsigned int sdhi0_cd_pins[] = {
3477         /* CD */
3478         RCAR_GP_PIN(3, 12),
3479 };
3480 static const unsigned int sdhi0_cd_mux[] = {
3481         SD0_CD_MARK,
3482 };
3483 static const unsigned int sdhi0_wp_pins[] = {
3484         /* WP */
3485         RCAR_GP_PIN(3, 13),
3486 };
3487 static const unsigned int sdhi0_wp_mux[] = {
3488         SD0_WP_MARK,
3489 };
3490 /* - SDHI1 ------------------------------------------------------------------ */
3491 static const unsigned int sdhi1_data1_pins[] = {
3492         /* D0 */
3493         RCAR_GP_PIN(3, 8),
3494 };
3495 static const unsigned int sdhi1_data1_mux[] = {
3496         SD1_DAT0_MARK,
3497 };
3498 static const unsigned int sdhi1_data4_pins[] = {
3499         /* D[0:3] */
3500         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3501         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3502 };
3503 static const unsigned int sdhi1_data4_mux[] = {
3504         SD1_DAT0_MARK, SD1_DAT1_MARK,
3505         SD1_DAT2_MARK, SD1_DAT3_MARK,
3506 };
3507 static const unsigned int sdhi1_ctrl_pins[] = {
3508         /* CLK, CMD */
3509         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3510 };
3511 static const unsigned int sdhi1_ctrl_mux[] = {
3512         SD1_CLK_MARK, SD1_CMD_MARK,
3513 };
3514 static const unsigned int sdhi1_cd_pins[] = {
3515         /* CD */
3516         RCAR_GP_PIN(3, 14),
3517 };
3518 static const unsigned int sdhi1_cd_mux[] = {
3519         SD1_CD_MARK,
3520 };
3521 static const unsigned int sdhi1_wp_pins[] = {
3522         /* WP */
3523         RCAR_GP_PIN(3, 15),
3524 };
3525 static const unsigned int sdhi1_wp_mux[] = {
3526         SD1_WP_MARK,
3527 };
3528 /* - SDHI2 ------------------------------------------------------------------ */
3529 static const unsigned int sdhi2_data1_pins[] = {
3530         /* D0 */
3531         RCAR_GP_PIN(4, 2),
3532 };
3533 static const unsigned int sdhi2_data1_mux[] = {
3534         SD2_DAT0_MARK,
3535 };
3536 static const unsigned int sdhi2_data4_pins[] = {
3537         /* D[0:3] */
3538         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3539         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3540 };
3541 static const unsigned int sdhi2_data4_mux[] = {
3542         SD2_DAT0_MARK, SD2_DAT1_MARK,
3543         SD2_DAT2_MARK, SD2_DAT3_MARK,
3544 };
3545 static const unsigned int sdhi2_data8_pins[] = {
3546         /* D[0:7] */
3547         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3548         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3549         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3550         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3551 };
3552 static const unsigned int sdhi2_data8_mux[] = {
3553         SD2_DAT0_MARK, SD2_DAT1_MARK,
3554         SD2_DAT2_MARK, SD2_DAT3_MARK,
3555         SD2_DAT4_MARK, SD2_DAT5_MARK,
3556         SD2_DAT6_MARK, SD2_DAT7_MARK,
3557 };
3558 static const unsigned int sdhi2_ctrl_pins[] = {
3559         /* CLK, CMD */
3560         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3561 };
3562 static const unsigned int sdhi2_ctrl_mux[] = {
3563         SD2_CLK_MARK, SD2_CMD_MARK,
3564 };
3565 static const unsigned int sdhi2_cd_a_pins[] = {
3566         /* CD */
3567         RCAR_GP_PIN(4, 13),
3568 };
3569 static const unsigned int sdhi2_cd_a_mux[] = {
3570         SD2_CD_A_MARK,
3571 };
3572 static const unsigned int sdhi2_cd_b_pins[] = {
3573         /* CD */
3574         RCAR_GP_PIN(5, 10),
3575 };
3576 static const unsigned int sdhi2_cd_b_mux[] = {
3577         SD2_CD_B_MARK,
3578 };
3579 static const unsigned int sdhi2_wp_a_pins[] = {
3580         /* WP */
3581         RCAR_GP_PIN(4, 14),
3582 };
3583 static const unsigned int sdhi2_wp_a_mux[] = {
3584         SD2_WP_A_MARK,
3585 };
3586 static const unsigned int sdhi2_wp_b_pins[] = {
3587         /* WP */
3588         RCAR_GP_PIN(5, 11),
3589 };
3590 static const unsigned int sdhi2_wp_b_mux[] = {
3591         SD2_WP_B_MARK,
3592 };
3593 static const unsigned int sdhi2_ds_pins[] = {
3594         /* DS */
3595         RCAR_GP_PIN(4, 6),
3596 };
3597 static const unsigned int sdhi2_ds_mux[] = {
3598         SD2_DS_MARK,
3599 };
3600 /* - SDHI3 ------------------------------------------------------------------ */
3601 static const unsigned int sdhi3_data1_pins[] = {
3602         /* D0 */
3603         RCAR_GP_PIN(4, 9),
3604 };
3605 static const unsigned int sdhi3_data1_mux[] = {
3606         SD3_DAT0_MARK,
3607 };
3608 static const unsigned int sdhi3_data4_pins[] = {
3609         /* D[0:3] */
3610         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3611         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3612 };
3613 static const unsigned int sdhi3_data4_mux[] = {
3614         SD3_DAT0_MARK, SD3_DAT1_MARK,
3615         SD3_DAT2_MARK, SD3_DAT3_MARK,
3616 };
3617 static const unsigned int sdhi3_data8_pins[] = {
3618         /* D[0:7] */
3619         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3620         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3621         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3622         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3623 };
3624 static const unsigned int sdhi3_data8_mux[] = {
3625         SD3_DAT0_MARK, SD3_DAT1_MARK,
3626         SD3_DAT2_MARK, SD3_DAT3_MARK,
3627         SD3_DAT4_MARK, SD3_DAT5_MARK,
3628         SD3_DAT6_MARK, SD3_DAT7_MARK,
3629 };
3630 static const unsigned int sdhi3_ctrl_pins[] = {
3631         /* CLK, CMD */
3632         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3633 };
3634 static const unsigned int sdhi3_ctrl_mux[] = {
3635         SD3_CLK_MARK, SD3_CMD_MARK,
3636 };
3637 static const unsigned int sdhi3_cd_pins[] = {
3638         /* CD */
3639         RCAR_GP_PIN(4, 15),
3640 };
3641 static const unsigned int sdhi3_cd_mux[] = {
3642         SD3_CD_MARK,
3643 };
3644 static const unsigned int sdhi3_wp_pins[] = {
3645         /* WP */
3646         RCAR_GP_PIN(4, 16),
3647 };
3648 static const unsigned int sdhi3_wp_mux[] = {
3649         SD3_WP_MARK,
3650 };
3651 static const unsigned int sdhi3_ds_pins[] = {
3652         /* DS */
3653         RCAR_GP_PIN(4, 17),
3654 };
3655 static const unsigned int sdhi3_ds_mux[] = {
3656         SD3_DS_MARK,
3657 };
3658
3659 /* - SSI -------------------------------------------------------------------- */
3660 static const unsigned int ssi0_data_pins[] = {
3661         /* SDATA */
3662         RCAR_GP_PIN(6, 2),
3663 };
3664 static const unsigned int ssi0_data_mux[] = {
3665         SSI_SDATA0_MARK,
3666 };
3667 static const unsigned int ssi01239_ctrl_pins[] = {
3668         /* SCK, WS */
3669         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3670 };
3671 static const unsigned int ssi01239_ctrl_mux[] = {
3672         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3673 };
3674 static const unsigned int ssi1_data_a_pins[] = {
3675         /* SDATA */
3676         RCAR_GP_PIN(6, 3),
3677 };
3678 static const unsigned int ssi1_data_a_mux[] = {
3679         SSI_SDATA1_A_MARK,
3680 };
3681 static const unsigned int ssi1_data_b_pins[] = {
3682         /* SDATA */
3683         RCAR_GP_PIN(5, 12),
3684 };
3685 static const unsigned int ssi1_data_b_mux[] = {
3686         SSI_SDATA1_B_MARK,
3687 };
3688 static const unsigned int ssi1_ctrl_a_pins[] = {
3689         /* SCK, WS */
3690         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3691 };
3692 static const unsigned int ssi1_ctrl_a_mux[] = {
3693         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3694 };
3695 static const unsigned int ssi1_ctrl_b_pins[] = {
3696         /* SCK, WS */
3697         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3698 };
3699 static const unsigned int ssi1_ctrl_b_mux[] = {
3700         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3701 };
3702 static const unsigned int ssi2_data_a_pins[] = {
3703         /* SDATA */
3704         RCAR_GP_PIN(6, 4),
3705 };
3706 static const unsigned int ssi2_data_a_mux[] = {
3707         SSI_SDATA2_A_MARK,
3708 };
3709 static const unsigned int ssi2_data_b_pins[] = {
3710         /* SDATA */
3711         RCAR_GP_PIN(5, 13),
3712 };
3713 static const unsigned int ssi2_data_b_mux[] = {
3714         SSI_SDATA2_B_MARK,
3715 };
3716 static const unsigned int ssi2_ctrl_a_pins[] = {
3717         /* SCK, WS */
3718         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3719 };
3720 static const unsigned int ssi2_ctrl_a_mux[] = {
3721         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3722 };
3723 static const unsigned int ssi2_ctrl_b_pins[] = {
3724         /* SCK, WS */
3725         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3726 };
3727 static const unsigned int ssi2_ctrl_b_mux[] = {
3728         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3729 };
3730 static const unsigned int ssi3_data_pins[] = {
3731         /* SDATA */
3732         RCAR_GP_PIN(6, 7),
3733 };
3734 static const unsigned int ssi3_data_mux[] = {
3735         SSI_SDATA3_MARK,
3736 };
3737 static const unsigned int ssi349_ctrl_pins[] = {
3738         /* SCK, WS */
3739         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3740 };
3741 static const unsigned int ssi349_ctrl_mux[] = {
3742         SSI_SCK349_MARK, SSI_WS349_MARK,
3743 };
3744 static const unsigned int ssi4_data_pins[] = {
3745         /* SDATA */
3746         RCAR_GP_PIN(6, 10),
3747 };
3748 static const unsigned int ssi4_data_mux[] = {
3749         SSI_SDATA4_MARK,
3750 };
3751 static const unsigned int ssi4_ctrl_pins[] = {
3752         /* SCK, WS */
3753         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3754 };
3755 static const unsigned int ssi4_ctrl_mux[] = {
3756         SSI_SCK4_MARK, SSI_WS4_MARK,
3757 };
3758 static const unsigned int ssi5_data_pins[] = {
3759         /* SDATA */
3760         RCAR_GP_PIN(6, 13),
3761 };
3762 static const unsigned int ssi5_data_mux[] = {
3763         SSI_SDATA5_MARK,
3764 };
3765 static const unsigned int ssi5_ctrl_pins[] = {
3766         /* SCK, WS */
3767         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3768 };
3769 static const unsigned int ssi5_ctrl_mux[] = {
3770         SSI_SCK5_MARK, SSI_WS5_MARK,
3771 };
3772 static const unsigned int ssi6_data_pins[] = {
3773         /* SDATA */
3774         RCAR_GP_PIN(6, 16),
3775 };
3776 static const unsigned int ssi6_data_mux[] = {
3777         SSI_SDATA6_MARK,
3778 };
3779 static const unsigned int ssi6_ctrl_pins[] = {
3780         /* SCK, WS */
3781         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3782 };
3783 static const unsigned int ssi6_ctrl_mux[] = {
3784         SSI_SCK6_MARK, SSI_WS6_MARK,
3785 };
3786 static const unsigned int ssi7_data_pins[] = {
3787         /* SDATA */
3788         RCAR_GP_PIN(6, 19),
3789 };
3790 static const unsigned int ssi7_data_mux[] = {
3791         SSI_SDATA7_MARK,
3792 };
3793 static const unsigned int ssi78_ctrl_pins[] = {
3794         /* SCK, WS */
3795         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3796 };
3797 static const unsigned int ssi78_ctrl_mux[] = {
3798         SSI_SCK78_MARK, SSI_WS78_MARK,
3799 };
3800 static const unsigned int ssi8_data_pins[] = {
3801         /* SDATA */
3802         RCAR_GP_PIN(6, 20),
3803 };
3804 static const unsigned int ssi8_data_mux[] = {
3805         SSI_SDATA8_MARK,
3806 };
3807 static const unsigned int ssi9_data_a_pins[] = {
3808         /* SDATA */
3809         RCAR_GP_PIN(6, 21),
3810 };
3811 static const unsigned int ssi9_data_a_mux[] = {
3812         SSI_SDATA9_A_MARK,
3813 };
3814 static const unsigned int ssi9_data_b_pins[] = {
3815         /* SDATA */
3816         RCAR_GP_PIN(5, 14),
3817 };
3818 static const unsigned int ssi9_data_b_mux[] = {
3819         SSI_SDATA9_B_MARK,
3820 };
3821 static const unsigned int ssi9_ctrl_a_pins[] = {
3822         /* SCK, WS */
3823         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3824 };
3825 static const unsigned int ssi9_ctrl_a_mux[] = {
3826         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3827 };
3828 static const unsigned int ssi9_ctrl_b_pins[] = {
3829         /* SCK, WS */
3830         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3831 };
3832 static const unsigned int ssi9_ctrl_b_mux[] = {
3833         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3834 };
3835
3836 /* - USB0 ------------------------------------------------------------------- */
3837 static const unsigned int usb0_pins[] = {
3838         /* PWEN, OVC */
3839         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3840 };
3841 static const unsigned int usb0_mux[] = {
3842         USB0_PWEN_MARK, USB0_OVC_MARK,
3843 };
3844 /* - USB1 ------------------------------------------------------------------- */
3845 static const unsigned int usb1_pins[] = {
3846         /* PWEN, OVC */
3847         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3848 };
3849 static const unsigned int usb1_mux[] = {
3850         USB1_PWEN_MARK, USB1_OVC_MARK,
3851 };
3852
3853 /* - USB30 ------------------------------------------------------------------ */
3854 static const unsigned int usb30_pins[] = {
3855         /* PWEN, OVC */
3856         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3857 };
3858 static const unsigned int usb30_mux[] = {
3859         USB30_PWEN_MARK, USB30_OVC_MARK,
3860 };
3861
3862 static const struct sh_pfc_pin_group pinmux_groups[] = {
3863         SH_PFC_PIN_GROUP(audio_clk_a_a),
3864         SH_PFC_PIN_GROUP(audio_clk_a_b),
3865         SH_PFC_PIN_GROUP(audio_clk_a_c),
3866         SH_PFC_PIN_GROUP(audio_clk_b_a),
3867         SH_PFC_PIN_GROUP(audio_clk_b_b),
3868         SH_PFC_PIN_GROUP(audio_clk_c_a),
3869         SH_PFC_PIN_GROUP(audio_clk_c_b),
3870         SH_PFC_PIN_GROUP(audio_clkout_a),
3871         SH_PFC_PIN_GROUP(audio_clkout_b),
3872         SH_PFC_PIN_GROUP(audio_clkout_c),
3873         SH_PFC_PIN_GROUP(audio_clkout_d),
3874         SH_PFC_PIN_GROUP(audio_clkout1_a),
3875         SH_PFC_PIN_GROUP(audio_clkout1_b),
3876         SH_PFC_PIN_GROUP(audio_clkout2_a),
3877         SH_PFC_PIN_GROUP(audio_clkout2_b),
3878         SH_PFC_PIN_GROUP(audio_clkout3_a),
3879         SH_PFC_PIN_GROUP(audio_clkout3_b),
3880         SH_PFC_PIN_GROUP(avb_link),
3881         SH_PFC_PIN_GROUP(avb_magic),
3882         SH_PFC_PIN_GROUP(avb_phy_int),
3883         SH_PFC_PIN_GROUP(avb_mdc),
3884         SH_PFC_PIN_GROUP(avb_mii),
3885         SH_PFC_PIN_GROUP(avb_avtp_pps),
3886         SH_PFC_PIN_GROUP(avb_avtp_match_a),
3887         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3888         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3889         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3890         SH_PFC_PIN_GROUP(can0_data_a),
3891         SH_PFC_PIN_GROUP(can0_data_b),
3892         SH_PFC_PIN_GROUP(can1_data),
3893         SH_PFC_PIN_GROUP(can_clk),
3894         SH_PFC_PIN_GROUP(canfd0_data_a),
3895         SH_PFC_PIN_GROUP(canfd0_data_b),
3896         SH_PFC_PIN_GROUP(canfd1_data),
3897         SH_PFC_PIN_GROUP(drif0_ctrl_a),
3898         SH_PFC_PIN_GROUP(drif0_data0_a),
3899         SH_PFC_PIN_GROUP(drif0_data1_a),
3900         SH_PFC_PIN_GROUP(drif0_ctrl_b),
3901         SH_PFC_PIN_GROUP(drif0_data0_b),
3902         SH_PFC_PIN_GROUP(drif0_data1_b),
3903         SH_PFC_PIN_GROUP(drif0_ctrl_c),
3904         SH_PFC_PIN_GROUP(drif0_data0_c),
3905         SH_PFC_PIN_GROUP(drif0_data1_c),
3906         SH_PFC_PIN_GROUP(drif1_ctrl_a),
3907         SH_PFC_PIN_GROUP(drif1_data0_a),
3908         SH_PFC_PIN_GROUP(drif1_data1_a),
3909         SH_PFC_PIN_GROUP(drif1_ctrl_b),
3910         SH_PFC_PIN_GROUP(drif1_data0_b),
3911         SH_PFC_PIN_GROUP(drif1_data1_b),
3912         SH_PFC_PIN_GROUP(drif1_ctrl_c),
3913         SH_PFC_PIN_GROUP(drif1_data0_c),
3914         SH_PFC_PIN_GROUP(drif1_data1_c),
3915         SH_PFC_PIN_GROUP(drif2_ctrl_a),
3916         SH_PFC_PIN_GROUP(drif2_data0_a),
3917         SH_PFC_PIN_GROUP(drif2_data1_a),
3918         SH_PFC_PIN_GROUP(drif2_ctrl_b),
3919         SH_PFC_PIN_GROUP(drif2_data0_b),
3920         SH_PFC_PIN_GROUP(drif2_data1_b),
3921         SH_PFC_PIN_GROUP(drif3_ctrl_a),
3922         SH_PFC_PIN_GROUP(drif3_data0_a),
3923         SH_PFC_PIN_GROUP(drif3_data1_a),
3924         SH_PFC_PIN_GROUP(drif3_ctrl_b),
3925         SH_PFC_PIN_GROUP(drif3_data0_b),
3926         SH_PFC_PIN_GROUP(drif3_data1_b),
3927         SH_PFC_PIN_GROUP(du_rgb666),
3928         SH_PFC_PIN_GROUP(du_rgb888),
3929         SH_PFC_PIN_GROUP(du_clk_out_0),
3930         SH_PFC_PIN_GROUP(du_clk_out_1),
3931         SH_PFC_PIN_GROUP(du_sync),
3932         SH_PFC_PIN_GROUP(du_oddf),
3933         SH_PFC_PIN_GROUP(du_cde),
3934         SH_PFC_PIN_GROUP(du_disp),
3935         SH_PFC_PIN_GROUP(hscif0_data),
3936         SH_PFC_PIN_GROUP(hscif0_clk),
3937         SH_PFC_PIN_GROUP(hscif0_ctrl),
3938         SH_PFC_PIN_GROUP(hscif1_data_a),
3939         SH_PFC_PIN_GROUP(hscif1_clk_a),
3940         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3941         SH_PFC_PIN_GROUP(hscif1_data_b),
3942         SH_PFC_PIN_GROUP(hscif1_clk_b),
3943         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3944         SH_PFC_PIN_GROUP(hscif2_data_a),
3945         SH_PFC_PIN_GROUP(hscif2_clk_a),
3946         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3947         SH_PFC_PIN_GROUP(hscif2_data_b),
3948         SH_PFC_PIN_GROUP(hscif2_clk_b),
3949         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3950         SH_PFC_PIN_GROUP(hscif2_data_c),
3951         SH_PFC_PIN_GROUP(hscif2_clk_c),
3952         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3953         SH_PFC_PIN_GROUP(hscif3_data_a),
3954         SH_PFC_PIN_GROUP(hscif3_clk),
3955         SH_PFC_PIN_GROUP(hscif3_ctrl),
3956         SH_PFC_PIN_GROUP(hscif3_data_b),
3957         SH_PFC_PIN_GROUP(hscif3_data_c),
3958         SH_PFC_PIN_GROUP(hscif3_data_d),
3959         SH_PFC_PIN_GROUP(hscif4_data_a),
3960         SH_PFC_PIN_GROUP(hscif4_clk),
3961         SH_PFC_PIN_GROUP(hscif4_ctrl),
3962         SH_PFC_PIN_GROUP(hscif4_data_b),
3963         SH_PFC_PIN_GROUP(i2c1_a),
3964         SH_PFC_PIN_GROUP(i2c1_b),
3965         SH_PFC_PIN_GROUP(i2c2_a),
3966         SH_PFC_PIN_GROUP(i2c2_b),
3967         SH_PFC_PIN_GROUP(i2c6_a),
3968         SH_PFC_PIN_GROUP(i2c6_b),
3969         SH_PFC_PIN_GROUP(i2c6_c),
3970         SH_PFC_PIN_GROUP(intc_ex_irq0),
3971         SH_PFC_PIN_GROUP(intc_ex_irq1),
3972         SH_PFC_PIN_GROUP(intc_ex_irq2),
3973         SH_PFC_PIN_GROUP(intc_ex_irq3),
3974         SH_PFC_PIN_GROUP(intc_ex_irq4),
3975         SH_PFC_PIN_GROUP(intc_ex_irq5),
3976         SH_PFC_PIN_GROUP(msiof0_clk),
3977         SH_PFC_PIN_GROUP(msiof0_sync),
3978         SH_PFC_PIN_GROUP(msiof0_ss1),
3979         SH_PFC_PIN_GROUP(msiof0_ss2),
3980         SH_PFC_PIN_GROUP(msiof0_txd),
3981         SH_PFC_PIN_GROUP(msiof0_rxd),
3982         SH_PFC_PIN_GROUP(msiof1_clk_a),
3983         SH_PFC_PIN_GROUP(msiof1_sync_a),
3984         SH_PFC_PIN_GROUP(msiof1_ss1_a),
3985         SH_PFC_PIN_GROUP(msiof1_ss2_a),
3986         SH_PFC_PIN_GROUP(msiof1_txd_a),
3987         SH_PFC_PIN_GROUP(msiof1_rxd_a),
3988         SH_PFC_PIN_GROUP(msiof1_clk_b),
3989         SH_PFC_PIN_GROUP(msiof1_sync_b),
3990         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3991         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3992         SH_PFC_PIN_GROUP(msiof1_txd_b),
3993         SH_PFC_PIN_GROUP(msiof1_rxd_b),
3994         SH_PFC_PIN_GROUP(msiof1_clk_c),
3995         SH_PFC_PIN_GROUP(msiof1_sync_c),
3996         SH_PFC_PIN_GROUP(msiof1_ss1_c),
3997         SH_PFC_PIN_GROUP(msiof1_ss2_c),
3998         SH_PFC_PIN_GROUP(msiof1_txd_c),
3999         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4000         SH_PFC_PIN_GROUP(msiof1_clk_d),
4001         SH_PFC_PIN_GROUP(msiof1_sync_d),
4002         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4003         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4004         SH_PFC_PIN_GROUP(msiof1_txd_d),
4005         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4006         SH_PFC_PIN_GROUP(msiof1_clk_e),
4007         SH_PFC_PIN_GROUP(msiof1_sync_e),
4008         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4009         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4010         SH_PFC_PIN_GROUP(msiof1_txd_e),
4011         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4012         SH_PFC_PIN_GROUP(msiof1_clk_f),
4013         SH_PFC_PIN_GROUP(msiof1_sync_f),
4014         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4015         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4016         SH_PFC_PIN_GROUP(msiof1_txd_f),
4017         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4018         SH_PFC_PIN_GROUP(msiof1_clk_g),
4019         SH_PFC_PIN_GROUP(msiof1_sync_g),
4020         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4021         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4022         SH_PFC_PIN_GROUP(msiof1_txd_g),
4023         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4024         SH_PFC_PIN_GROUP(msiof2_clk_a),
4025         SH_PFC_PIN_GROUP(msiof2_sync_a),
4026         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4027         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4028         SH_PFC_PIN_GROUP(msiof2_txd_a),
4029         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4030         SH_PFC_PIN_GROUP(msiof2_clk_b),
4031         SH_PFC_PIN_GROUP(msiof2_sync_b),
4032         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4033         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4034         SH_PFC_PIN_GROUP(msiof2_txd_b),
4035         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4036         SH_PFC_PIN_GROUP(msiof2_clk_c),
4037         SH_PFC_PIN_GROUP(msiof2_sync_c),
4038         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4039         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4040         SH_PFC_PIN_GROUP(msiof2_txd_c),
4041         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4042         SH_PFC_PIN_GROUP(msiof2_clk_d),
4043         SH_PFC_PIN_GROUP(msiof2_sync_d),
4044         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4045         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4046         SH_PFC_PIN_GROUP(msiof2_txd_d),
4047         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4048         SH_PFC_PIN_GROUP(msiof3_clk_a),
4049         SH_PFC_PIN_GROUP(msiof3_sync_a),
4050         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4051         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4052         SH_PFC_PIN_GROUP(msiof3_txd_a),
4053         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4054         SH_PFC_PIN_GROUP(msiof3_clk_b),
4055         SH_PFC_PIN_GROUP(msiof3_sync_b),
4056         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4057         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4058         SH_PFC_PIN_GROUP(msiof3_txd_b),
4059         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4060         SH_PFC_PIN_GROUP(msiof3_clk_c),
4061         SH_PFC_PIN_GROUP(msiof3_sync_c),
4062         SH_PFC_PIN_GROUP(msiof3_txd_c),
4063         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4064         SH_PFC_PIN_GROUP(msiof3_clk_d),
4065         SH_PFC_PIN_GROUP(msiof3_sync_d),
4066         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4067         SH_PFC_PIN_GROUP(msiof3_txd_d),
4068         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4069         SH_PFC_PIN_GROUP(msiof3_clk_e),
4070         SH_PFC_PIN_GROUP(msiof3_sync_e),
4071         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4072         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4073         SH_PFC_PIN_GROUP(msiof3_txd_e),
4074         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4075         SH_PFC_PIN_GROUP(pwm0),
4076         SH_PFC_PIN_GROUP(pwm1_a),
4077         SH_PFC_PIN_GROUP(pwm1_b),
4078         SH_PFC_PIN_GROUP(pwm2_a),
4079         SH_PFC_PIN_GROUP(pwm2_b),
4080         SH_PFC_PIN_GROUP(pwm3_a),
4081         SH_PFC_PIN_GROUP(pwm3_b),
4082         SH_PFC_PIN_GROUP(pwm4_a),
4083         SH_PFC_PIN_GROUP(pwm4_b),
4084         SH_PFC_PIN_GROUP(pwm5_a),
4085         SH_PFC_PIN_GROUP(pwm5_b),
4086         SH_PFC_PIN_GROUP(pwm6_a),
4087         SH_PFC_PIN_GROUP(pwm6_b),
4088         SH_PFC_PIN_GROUP(scif0_data),
4089         SH_PFC_PIN_GROUP(scif0_clk),
4090         SH_PFC_PIN_GROUP(scif0_ctrl),
4091         SH_PFC_PIN_GROUP(scif1_data_a),
4092         SH_PFC_PIN_GROUP(scif1_clk),
4093         SH_PFC_PIN_GROUP(scif1_ctrl),
4094         SH_PFC_PIN_GROUP(scif1_data_b),
4095         SH_PFC_PIN_GROUP(scif2_data_a),
4096         SH_PFC_PIN_GROUP(scif2_clk),
4097         SH_PFC_PIN_GROUP(scif2_data_b),
4098         SH_PFC_PIN_GROUP(scif3_data_a),
4099         SH_PFC_PIN_GROUP(scif3_clk),
4100         SH_PFC_PIN_GROUP(scif3_ctrl),
4101         SH_PFC_PIN_GROUP(scif3_data_b),
4102         SH_PFC_PIN_GROUP(scif4_data_a),
4103         SH_PFC_PIN_GROUP(scif4_clk_a),
4104         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4105         SH_PFC_PIN_GROUP(scif4_data_b),
4106         SH_PFC_PIN_GROUP(scif4_clk_b),
4107         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4108         SH_PFC_PIN_GROUP(scif4_data_c),
4109         SH_PFC_PIN_GROUP(scif4_clk_c),
4110         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4111         SH_PFC_PIN_GROUP(scif5_data_a),
4112         SH_PFC_PIN_GROUP(scif5_clk_a),
4113         SH_PFC_PIN_GROUP(scif5_data_b),
4114         SH_PFC_PIN_GROUP(scif5_clk_b),
4115         SH_PFC_PIN_GROUP(scif_clk_a),
4116         SH_PFC_PIN_GROUP(scif_clk_b),
4117         SH_PFC_PIN_GROUP(sdhi0_data1),
4118         SH_PFC_PIN_GROUP(sdhi0_data4),
4119         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4120         SH_PFC_PIN_GROUP(sdhi0_cd),
4121         SH_PFC_PIN_GROUP(sdhi0_wp),
4122         SH_PFC_PIN_GROUP(sdhi1_data1),
4123         SH_PFC_PIN_GROUP(sdhi1_data4),
4124         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4125         SH_PFC_PIN_GROUP(sdhi1_cd),
4126         SH_PFC_PIN_GROUP(sdhi1_wp),
4127         SH_PFC_PIN_GROUP(sdhi2_data1),
4128         SH_PFC_PIN_GROUP(sdhi2_data4),
4129         SH_PFC_PIN_GROUP(sdhi2_data8),
4130         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4131         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4132         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4133         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4134         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4135         SH_PFC_PIN_GROUP(sdhi2_ds),
4136         SH_PFC_PIN_GROUP(sdhi3_data1),
4137         SH_PFC_PIN_GROUP(sdhi3_data4),
4138         SH_PFC_PIN_GROUP(sdhi3_data8),
4139         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4140         SH_PFC_PIN_GROUP(sdhi3_cd),
4141         SH_PFC_PIN_GROUP(sdhi3_wp),
4142         SH_PFC_PIN_GROUP(sdhi3_ds),
4143         SH_PFC_PIN_GROUP(ssi0_data),
4144         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4145         SH_PFC_PIN_GROUP(ssi1_data_a),
4146         SH_PFC_PIN_GROUP(ssi1_data_b),
4147         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4148         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4149         SH_PFC_PIN_GROUP(ssi2_data_a),
4150         SH_PFC_PIN_GROUP(ssi2_data_b),
4151         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4152         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4153         SH_PFC_PIN_GROUP(ssi3_data),
4154         SH_PFC_PIN_GROUP(ssi349_ctrl),
4155         SH_PFC_PIN_GROUP(ssi4_data),
4156         SH_PFC_PIN_GROUP(ssi4_ctrl),
4157         SH_PFC_PIN_GROUP(ssi5_data),
4158         SH_PFC_PIN_GROUP(ssi5_ctrl),
4159         SH_PFC_PIN_GROUP(ssi6_data),
4160         SH_PFC_PIN_GROUP(ssi6_ctrl),
4161         SH_PFC_PIN_GROUP(ssi7_data),
4162         SH_PFC_PIN_GROUP(ssi78_ctrl),
4163         SH_PFC_PIN_GROUP(ssi8_data),
4164         SH_PFC_PIN_GROUP(ssi9_data_a),
4165         SH_PFC_PIN_GROUP(ssi9_data_b),
4166         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4167         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4168         SH_PFC_PIN_GROUP(usb0),
4169         SH_PFC_PIN_GROUP(usb1),
4170         SH_PFC_PIN_GROUP(usb30),
4171 };
4172
4173 static const char * const audio_clk_groups[] = {
4174         "audio_clk_a_a",
4175         "audio_clk_a_b",
4176         "audio_clk_a_c",
4177         "audio_clk_b_a",
4178         "audio_clk_b_b",
4179         "audio_clk_c_a",
4180         "audio_clk_c_b",
4181         "audio_clkout_a",
4182         "audio_clkout_b",
4183         "audio_clkout_c",
4184         "audio_clkout_d",
4185         "audio_clkout1_a",
4186         "audio_clkout1_b",
4187         "audio_clkout2_a",
4188         "audio_clkout2_b",
4189         "audio_clkout3_a",
4190         "audio_clkout3_b",
4191 };
4192
4193 static const char * const avb_groups[] = {
4194         "avb_link",
4195         "avb_magic",
4196         "avb_phy_int",
4197         "avb_mdc",
4198         "avb_mii",
4199         "avb_avtp_pps",
4200         "avb_avtp_match_a",
4201         "avb_avtp_capture_a",
4202         "avb_avtp_match_b",
4203         "avb_avtp_capture_b",
4204 };
4205
4206 static const char * const can0_groups[] = {
4207         "can0_data_a",
4208         "can0_data_b",
4209 };
4210
4211 static const char * const can1_groups[] = {
4212         "can1_data",
4213 };
4214
4215 static const char * const can_clk_groups[] = {
4216         "can_clk",
4217 };
4218
4219 static const char * const canfd0_groups[] = {
4220         "canfd0_data_a",
4221         "canfd0_data_b",
4222 };
4223
4224 static const char * const canfd1_groups[] = {
4225         "canfd1_data",
4226 };
4227
4228 static const char * const drif0_groups[] = {
4229         "drif0_ctrl_a",
4230         "drif0_data0_a",
4231         "drif0_data1_a",
4232         "drif0_ctrl_b",
4233         "drif0_data0_b",
4234         "drif0_data1_b",
4235         "drif0_ctrl_c",
4236         "drif0_data0_c",
4237         "drif0_data1_c",
4238 };
4239
4240 static const char * const drif1_groups[] = {
4241         "drif1_ctrl_a",
4242         "drif1_data0_a",
4243         "drif1_data1_a",
4244         "drif1_ctrl_b",
4245         "drif1_data0_b",
4246         "drif1_data1_b",
4247         "drif1_ctrl_c",
4248         "drif1_data0_c",
4249         "drif1_data1_c",
4250 };
4251
4252 static const char * const drif2_groups[] = {
4253         "drif2_ctrl_a",
4254         "drif2_data0_a",
4255         "drif2_data1_a",
4256         "drif2_ctrl_b",
4257         "drif2_data0_b",
4258         "drif2_data1_b",
4259 };
4260
4261 static const char * const drif3_groups[] = {
4262         "drif3_ctrl_a",
4263         "drif3_data0_a",
4264         "drif3_data1_a",
4265         "drif3_ctrl_b",
4266         "drif3_data0_b",
4267         "drif3_data1_b",
4268 };
4269
4270 static const char * const du_groups[] = {
4271         "du_rgb666",
4272         "du_rgb888",
4273         "du_clk_out_0",
4274         "du_clk_out_1",
4275         "du_sync",
4276         "du_oddf",
4277         "du_cde",
4278         "du_disp",
4279 };
4280
4281 static const char * const hscif0_groups[] = {
4282         "hscif0_data",
4283         "hscif0_clk",
4284         "hscif0_ctrl",
4285 };
4286
4287 static const char * const hscif1_groups[] = {
4288         "hscif1_data_a",
4289         "hscif1_clk_a",
4290         "hscif1_ctrl_a",
4291         "hscif1_data_b",
4292         "hscif1_clk_b",
4293         "hscif1_ctrl_b",
4294 };
4295
4296 static const char * const hscif2_groups[] = {
4297         "hscif2_data_a",
4298         "hscif2_clk_a",
4299         "hscif2_ctrl_a",
4300         "hscif2_data_b",
4301         "hscif2_clk_b",
4302         "hscif2_ctrl_b",
4303         "hscif2_data_c",
4304         "hscif2_clk_c",
4305         "hscif2_ctrl_c",
4306 };
4307
4308 static const char * const hscif3_groups[] = {
4309         "hscif3_data_a",
4310         "hscif3_clk",
4311         "hscif3_ctrl",
4312         "hscif3_data_b",
4313         "hscif3_data_c",
4314         "hscif3_data_d",
4315 };
4316
4317 static const char * const hscif4_groups[] = {
4318         "hscif4_data_a",
4319         "hscif4_clk",
4320         "hscif4_ctrl",
4321         "hscif4_data_b",
4322 };
4323
4324 static const char * const i2c1_groups[] = {
4325         "i2c1_a",
4326         "i2c1_b",
4327 };
4328
4329 static const char * const i2c2_groups[] = {
4330         "i2c2_a",
4331         "i2c2_b",
4332 };
4333
4334 static const char * const i2c6_groups[] = {
4335         "i2c6_a",
4336         "i2c6_b",
4337         "i2c6_c",
4338 };
4339
4340 static const char * const intc_ex_groups[] = {
4341         "intc_ex_irq0",
4342         "intc_ex_irq1",
4343         "intc_ex_irq2",
4344         "intc_ex_irq3",
4345         "intc_ex_irq4",
4346         "intc_ex_irq5",
4347 };
4348
4349 static const char * const msiof0_groups[] = {
4350         "msiof0_clk",
4351         "msiof0_sync",
4352         "msiof0_ss1",
4353         "msiof0_ss2",
4354         "msiof0_txd",
4355         "msiof0_rxd",
4356 };
4357
4358 static const char * const msiof1_groups[] = {
4359         "msiof1_clk_a",
4360         "msiof1_sync_a",
4361         "msiof1_ss1_a",
4362         "msiof1_ss2_a",
4363         "msiof1_txd_a",
4364         "msiof1_rxd_a",
4365         "msiof1_clk_b",
4366         "msiof1_sync_b",
4367         "msiof1_ss1_b",
4368         "msiof1_ss2_b",
4369         "msiof1_txd_b",
4370         "msiof1_rxd_b",
4371         "msiof1_clk_c",
4372         "msiof1_sync_c",
4373         "msiof1_ss1_c",
4374         "msiof1_ss2_c",
4375         "msiof1_txd_c",
4376         "msiof1_rxd_c",
4377         "msiof1_clk_d",
4378         "msiof1_sync_d",
4379         "msiof1_ss1_d",
4380         "msiof1_ss2_d",
4381         "msiof1_txd_d",
4382         "msiof1_rxd_d",
4383         "msiof1_clk_e",
4384         "msiof1_sync_e",
4385         "msiof1_ss1_e",
4386         "msiof1_ss2_e",
4387         "msiof1_txd_e",
4388         "msiof1_rxd_e",
4389         "msiof1_clk_f",
4390         "msiof1_sync_f",
4391         "msiof1_ss1_f",
4392         "msiof1_ss2_f",
4393         "msiof1_txd_f",
4394         "msiof1_rxd_f",
4395         "msiof1_clk_g",
4396         "msiof1_sync_g",
4397         "msiof1_ss1_g",
4398         "msiof1_ss2_g",
4399         "msiof1_txd_g",
4400         "msiof1_rxd_g",
4401 };
4402
4403 static const char * const msiof2_groups[] = {
4404         "msiof2_clk_a",
4405         "msiof2_sync_a",
4406         "msiof2_ss1_a",
4407         "msiof2_ss2_a",
4408         "msiof2_txd_a",
4409         "msiof2_rxd_a",
4410         "msiof2_clk_b",
4411         "msiof2_sync_b",
4412         "msiof2_ss1_b",
4413         "msiof2_ss2_b",
4414         "msiof2_txd_b",
4415         "msiof2_rxd_b",
4416         "msiof2_clk_c",
4417         "msiof2_sync_c",
4418         "msiof2_ss1_c",
4419         "msiof2_ss2_c",
4420         "msiof2_txd_c",
4421         "msiof2_rxd_c",
4422         "msiof2_clk_d",
4423         "msiof2_sync_d",
4424         "msiof2_ss1_d",
4425         "msiof2_ss2_d",
4426         "msiof2_txd_d",
4427         "msiof2_rxd_d",
4428 };
4429
4430 static const char * const msiof3_groups[] = {
4431         "msiof3_clk_a",
4432         "msiof3_sync_a",
4433         "msiof3_ss1_a",
4434         "msiof3_ss2_a",
4435         "msiof3_txd_a",
4436         "msiof3_rxd_a",
4437         "msiof3_clk_b",
4438         "msiof3_sync_b",
4439         "msiof3_ss1_b",
4440         "msiof3_ss2_b",
4441         "msiof3_txd_b",
4442         "msiof3_rxd_b",
4443         "msiof3_clk_c",
4444         "msiof3_sync_c",
4445         "msiof3_txd_c",
4446         "msiof3_rxd_c",
4447         "msiof3_clk_d",
4448         "msiof3_sync_d",
4449         "msiof3_ss1_d",
4450         "msiof3_txd_d",
4451         "msiof3_rxd_d",
4452         "msiof3_clk_e",
4453         "msiof3_sync_e",
4454         "msiof3_ss1_e",
4455         "msiof3_ss2_e",
4456         "msiof3_txd_e",
4457         "msiof3_rxd_e",
4458 };
4459
4460 static const char * const pwm0_groups[] = {
4461         "pwm0",
4462 };
4463
4464 static const char * const pwm1_groups[] = {
4465         "pwm1_a",
4466         "pwm1_b",
4467 };
4468
4469 static const char * const pwm2_groups[] = {
4470         "pwm2_a",
4471         "pwm2_b",
4472 };
4473
4474 static const char * const pwm3_groups[] = {
4475         "pwm3_a",
4476         "pwm3_b",
4477 };
4478
4479 static const char * const pwm4_groups[] = {
4480         "pwm4_a",
4481         "pwm4_b",
4482 };
4483
4484 static const char * const pwm5_groups[] = {
4485         "pwm5_a",
4486         "pwm5_b",
4487 };
4488
4489 static const char * const pwm6_groups[] = {
4490         "pwm6_a",
4491         "pwm6_b",
4492 };
4493
4494 static const char * const scif0_groups[] = {
4495         "scif0_data",
4496         "scif0_clk",
4497         "scif0_ctrl",
4498 };
4499
4500 static const char * const scif1_groups[] = {
4501         "scif1_data_a",
4502         "scif1_clk",
4503         "scif1_ctrl",
4504         "scif1_data_b",
4505 };
4506
4507 static const char * const scif2_groups[] = {
4508         "scif2_data_a",
4509         "scif2_clk",
4510         "scif2_data_b",
4511 };
4512
4513 static const char * const scif3_groups[] = {
4514         "scif3_data_a",
4515         "scif3_clk",
4516         "scif3_ctrl",
4517         "scif3_data_b",
4518 };
4519
4520 static const char * const scif4_groups[] = {
4521         "scif4_data_a",
4522         "scif4_clk_a",
4523         "scif4_ctrl_a",
4524         "scif4_data_b",
4525         "scif4_clk_b",
4526         "scif4_ctrl_b",
4527         "scif4_data_c",
4528         "scif4_clk_c",
4529         "scif4_ctrl_c",
4530 };
4531
4532 static const char * const scif5_groups[] = {
4533         "scif5_data_a",
4534         "scif5_clk_a",
4535         "scif5_data_b",
4536         "scif5_clk_b",
4537 };
4538
4539 static const char * const scif_clk_groups[] = {
4540         "scif_clk_a",
4541         "scif_clk_b",
4542 };
4543
4544 static const char * const sdhi0_groups[] = {
4545         "sdhi0_data1",
4546         "sdhi0_data4",
4547         "sdhi0_ctrl",
4548         "sdhi0_cd",
4549         "sdhi0_wp",
4550 };
4551
4552 static const char * const sdhi1_groups[] = {
4553         "sdhi1_data1",
4554         "sdhi1_data4",
4555         "sdhi1_ctrl",
4556         "sdhi1_cd",
4557         "sdhi1_wp",
4558 };
4559
4560 static const char * const sdhi2_groups[] = {
4561         "sdhi2_data1",
4562         "sdhi2_data4",
4563         "sdhi2_data8",
4564         "sdhi2_ctrl",
4565         "sdhi2_cd_a",
4566         "sdhi2_wp_a",
4567         "sdhi2_cd_b",
4568         "sdhi2_wp_b",
4569         "sdhi2_ds",
4570 };
4571
4572 static const char * const sdhi3_groups[] = {
4573         "sdhi3_data1",
4574         "sdhi3_data4",
4575         "sdhi3_data8",
4576         "sdhi3_ctrl",
4577         "sdhi3_cd",
4578         "sdhi3_wp",
4579         "sdhi3_ds",
4580 };
4581
4582 static const char * const ssi_groups[] = {
4583         "ssi0_data",
4584         "ssi01239_ctrl",
4585         "ssi1_data_a",
4586         "ssi1_data_b",
4587         "ssi1_ctrl_a",
4588         "ssi1_ctrl_b",
4589         "ssi2_data_a",
4590         "ssi2_data_b",
4591         "ssi2_ctrl_a",
4592         "ssi2_ctrl_b",
4593         "ssi3_data",
4594         "ssi349_ctrl",
4595         "ssi4_data",
4596         "ssi4_ctrl",
4597         "ssi5_data",
4598         "ssi5_ctrl",
4599         "ssi6_data",
4600         "ssi6_ctrl",
4601         "ssi7_data",
4602         "ssi78_ctrl",
4603         "ssi8_data",
4604         "ssi9_data_a",
4605         "ssi9_data_b",
4606         "ssi9_ctrl_a",
4607         "ssi9_ctrl_b",
4608 };
4609
4610 static const char * const usb0_groups[] = {
4611         "usb0",
4612 };
4613
4614 static const char * const usb1_groups[] = {
4615         "usb1",
4616 };
4617
4618 static const char * const usb30_groups[] = {
4619         "usb30",
4620 };
4621
4622 static const struct sh_pfc_function pinmux_functions[] = {
4623         SH_PFC_FUNCTION(audio_clk),
4624         SH_PFC_FUNCTION(avb),
4625         SH_PFC_FUNCTION(can0),
4626         SH_PFC_FUNCTION(can1),
4627         SH_PFC_FUNCTION(can_clk),
4628         SH_PFC_FUNCTION(canfd0),
4629         SH_PFC_FUNCTION(canfd1),
4630         SH_PFC_FUNCTION(drif0),
4631         SH_PFC_FUNCTION(drif1),
4632         SH_PFC_FUNCTION(drif2),
4633         SH_PFC_FUNCTION(drif3),
4634         SH_PFC_FUNCTION(du),
4635         SH_PFC_FUNCTION(hscif0),
4636         SH_PFC_FUNCTION(hscif1),
4637         SH_PFC_FUNCTION(hscif2),
4638         SH_PFC_FUNCTION(hscif3),
4639         SH_PFC_FUNCTION(hscif4),
4640         SH_PFC_FUNCTION(i2c1),
4641         SH_PFC_FUNCTION(i2c2),
4642         SH_PFC_FUNCTION(i2c6),
4643         SH_PFC_FUNCTION(intc_ex),
4644         SH_PFC_FUNCTION(msiof0),
4645         SH_PFC_FUNCTION(msiof1),
4646         SH_PFC_FUNCTION(msiof2),
4647         SH_PFC_FUNCTION(msiof3),
4648         SH_PFC_FUNCTION(pwm0),
4649         SH_PFC_FUNCTION(pwm1),
4650         SH_PFC_FUNCTION(pwm2),
4651         SH_PFC_FUNCTION(pwm3),
4652         SH_PFC_FUNCTION(pwm4),
4653         SH_PFC_FUNCTION(pwm5),
4654         SH_PFC_FUNCTION(pwm6),
4655         SH_PFC_FUNCTION(scif0),
4656         SH_PFC_FUNCTION(scif1),
4657         SH_PFC_FUNCTION(scif2),
4658         SH_PFC_FUNCTION(scif3),
4659         SH_PFC_FUNCTION(scif4),
4660         SH_PFC_FUNCTION(scif5),
4661         SH_PFC_FUNCTION(scif_clk),
4662         SH_PFC_FUNCTION(sdhi0),
4663         SH_PFC_FUNCTION(sdhi1),
4664         SH_PFC_FUNCTION(sdhi2),
4665         SH_PFC_FUNCTION(sdhi3),
4666         SH_PFC_FUNCTION(ssi),
4667         SH_PFC_FUNCTION(usb0),
4668         SH_PFC_FUNCTION(usb1),
4669         SH_PFC_FUNCTION(usb30),
4670 };
4671
4672 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4673 #define F_(x, y)        FN_##y
4674 #define FM(x)           FN_##x
4675         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4676                 0, 0,
4677                 0, 0,
4678                 0, 0,
4679                 0, 0,
4680                 0, 0,
4681                 0, 0,
4682                 0, 0,
4683                 0, 0,
4684                 0, 0,
4685                 0, 0,
4686                 0, 0,
4687                 0, 0,
4688                 0, 0,
4689                 0, 0,
4690                 0, 0,
4691                 0, 0,
4692                 GP_0_15_FN,     GPSR0_15,
4693                 GP_0_14_FN,     GPSR0_14,
4694                 GP_0_13_FN,     GPSR0_13,
4695                 GP_0_12_FN,     GPSR0_12,
4696                 GP_0_11_FN,     GPSR0_11,
4697                 GP_0_10_FN,     GPSR0_10,
4698                 GP_0_9_FN,      GPSR0_9,
4699                 GP_0_8_FN,      GPSR0_8,
4700                 GP_0_7_FN,      GPSR0_7,
4701                 GP_0_6_FN,      GPSR0_6,
4702                 GP_0_5_FN,      GPSR0_5,
4703                 GP_0_4_FN,      GPSR0_4,
4704                 GP_0_3_FN,      GPSR0_3,
4705                 GP_0_2_FN,      GPSR0_2,
4706                 GP_0_1_FN,      GPSR0_1,
4707                 GP_0_0_FN,      GPSR0_0, }
4708         },
4709         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4710                 0, 0,
4711                 0, 0,
4712                 0, 0,
4713                 GP_1_28_FN,     GPSR1_28,
4714                 GP_1_27_FN,     GPSR1_27,
4715                 GP_1_26_FN,     GPSR1_26,
4716                 GP_1_25_FN,     GPSR1_25,
4717                 GP_1_24_FN,     GPSR1_24,
4718                 GP_1_23_FN,     GPSR1_23,
4719                 GP_1_22_FN,     GPSR1_22,
4720                 GP_1_21_FN,     GPSR1_21,
4721                 GP_1_20_FN,     GPSR1_20,
4722                 GP_1_19_FN,     GPSR1_19,
4723                 GP_1_18_FN,     GPSR1_18,
4724                 GP_1_17_FN,     GPSR1_17,
4725                 GP_1_16_FN,     GPSR1_16,
4726                 GP_1_15_FN,     GPSR1_15,
4727                 GP_1_14_FN,     GPSR1_14,
4728                 GP_1_13_FN,     GPSR1_13,
4729                 GP_1_12_FN,     GPSR1_12,
4730                 GP_1_11_FN,     GPSR1_11,
4731                 GP_1_10_FN,     GPSR1_10,
4732                 GP_1_9_FN,      GPSR1_9,
4733                 GP_1_8_FN,      GPSR1_8,
4734                 GP_1_7_FN,      GPSR1_7,
4735                 GP_1_6_FN,      GPSR1_6,
4736                 GP_1_5_FN,      GPSR1_5,
4737                 GP_1_4_FN,      GPSR1_4,
4738                 GP_1_3_FN,      GPSR1_3,
4739                 GP_1_2_FN,      GPSR1_2,
4740                 GP_1_1_FN,      GPSR1_1,
4741                 GP_1_0_FN,      GPSR1_0, }
4742         },
4743         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4744                 0, 0,
4745                 0, 0,
4746                 0, 0,
4747                 0, 0,
4748                 0, 0,
4749                 0, 0,
4750                 0, 0,
4751                 0, 0,
4752                 0, 0,
4753                 0, 0,
4754                 0, 0,
4755                 0, 0,
4756                 0, 0,
4757                 0, 0,
4758                 0, 0,
4759                 0, 0,
4760                 0, 0,
4761                 GP_2_14_FN,     GPSR2_14,
4762                 GP_2_13_FN,     GPSR2_13,
4763                 GP_2_12_FN,     GPSR2_12,
4764                 GP_2_11_FN,     GPSR2_11,
4765                 GP_2_10_FN,     GPSR2_10,
4766                 GP_2_9_FN,      GPSR2_9,
4767                 GP_2_8_FN,      GPSR2_8,
4768                 GP_2_7_FN,      GPSR2_7,
4769                 GP_2_6_FN,      GPSR2_6,
4770                 GP_2_5_FN,      GPSR2_5,
4771                 GP_2_4_FN,      GPSR2_4,
4772                 GP_2_3_FN,      GPSR2_3,
4773                 GP_2_2_FN,      GPSR2_2,
4774                 GP_2_1_FN,      GPSR2_1,
4775                 GP_2_0_FN,      GPSR2_0, }
4776         },
4777         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4778                 0, 0,
4779                 0, 0,
4780                 0, 0,
4781                 0, 0,
4782                 0, 0,
4783                 0, 0,
4784                 0, 0,
4785                 0, 0,
4786                 0, 0,
4787                 0, 0,
4788                 0, 0,
4789                 0, 0,
4790                 0, 0,
4791                 0, 0,
4792                 0, 0,
4793                 0, 0,
4794                 GP_3_15_FN,     GPSR3_15,
4795                 GP_3_14_FN,     GPSR3_14,
4796                 GP_3_13_FN,     GPSR3_13,
4797                 GP_3_12_FN,     GPSR3_12,
4798                 GP_3_11_FN,     GPSR3_11,
4799                 GP_3_10_FN,     GPSR3_10,
4800                 GP_3_9_FN,      GPSR3_9,
4801                 GP_3_8_FN,      GPSR3_8,
4802                 GP_3_7_FN,      GPSR3_7,
4803                 GP_3_6_FN,      GPSR3_6,
4804                 GP_3_5_FN,      GPSR3_5,
4805                 GP_3_4_FN,      GPSR3_4,
4806                 GP_3_3_FN,      GPSR3_3,
4807                 GP_3_2_FN,      GPSR3_2,
4808                 GP_3_1_FN,      GPSR3_1,
4809                 GP_3_0_FN,      GPSR3_0, }
4810         },
4811         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4812                 0, 0,
4813                 0, 0,
4814                 0, 0,
4815                 0, 0,
4816                 0, 0,
4817                 0, 0,
4818                 0, 0,
4819                 0, 0,
4820                 0, 0,
4821                 0, 0,
4822                 0, 0,
4823                 0, 0,
4824                 0, 0,
4825                 0, 0,
4826                 GP_4_17_FN,     GPSR4_17,
4827                 GP_4_16_FN,     GPSR4_16,
4828                 GP_4_15_FN,     GPSR4_15,
4829                 GP_4_14_FN,     GPSR4_14,
4830                 GP_4_13_FN,     GPSR4_13,
4831                 GP_4_12_FN,     GPSR4_12,
4832                 GP_4_11_FN,     GPSR4_11,
4833                 GP_4_10_FN,     GPSR4_10,
4834                 GP_4_9_FN,      GPSR4_9,
4835                 GP_4_8_FN,      GPSR4_8,
4836                 GP_4_7_FN,      GPSR4_7,
4837                 GP_4_6_FN,      GPSR4_6,
4838                 GP_4_5_FN,      GPSR4_5,
4839                 GP_4_4_FN,      GPSR4_4,
4840                 GP_4_3_FN,      GPSR4_3,
4841                 GP_4_2_FN,      GPSR4_2,
4842                 GP_4_1_FN,      GPSR4_1,
4843                 GP_4_0_FN,      GPSR4_0, }
4844         },
4845         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4846                 0, 0,
4847                 0, 0,
4848                 0, 0,
4849                 0, 0,
4850                 0, 0,
4851                 0, 0,
4852                 GP_5_25_FN,     GPSR5_25,
4853                 GP_5_24_FN,     GPSR5_24,
4854                 GP_5_23_FN,     GPSR5_23,
4855                 GP_5_22_FN,     GPSR5_22,
4856                 GP_5_21_FN,     GPSR5_21,
4857                 GP_5_20_FN,     GPSR5_20,
4858                 GP_5_19_FN,     GPSR5_19,
4859                 GP_5_18_FN,     GPSR5_18,
4860                 GP_5_17_FN,     GPSR5_17,
4861                 GP_5_16_FN,     GPSR5_16,
4862                 GP_5_15_FN,     GPSR5_15,
4863                 GP_5_14_FN,     GPSR5_14,
4864                 GP_5_13_FN,     GPSR5_13,
4865                 GP_5_12_FN,     GPSR5_12,
4866                 GP_5_11_FN,     GPSR5_11,
4867                 GP_5_10_FN,     GPSR5_10,
4868                 GP_5_9_FN,      GPSR5_9,
4869                 GP_5_8_FN,      GPSR5_8,
4870                 GP_5_7_FN,      GPSR5_7,
4871                 GP_5_6_FN,      GPSR5_6,
4872                 GP_5_5_FN,      GPSR5_5,
4873                 GP_5_4_FN,      GPSR5_4,
4874                 GP_5_3_FN,      GPSR5_3,
4875                 GP_5_2_FN,      GPSR5_2,
4876                 GP_5_1_FN,      GPSR5_1,
4877                 GP_5_0_FN,      GPSR5_0, }
4878         },
4879         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4880                 GP_6_31_FN,     GPSR6_31,
4881                 GP_6_30_FN,     GPSR6_30,
4882                 GP_6_29_FN,     GPSR6_29,
4883                 GP_6_28_FN,     GPSR6_28,
4884                 GP_6_27_FN,     GPSR6_27,
4885                 GP_6_26_FN,     GPSR6_26,
4886                 GP_6_25_FN,     GPSR6_25,
4887                 GP_6_24_FN,     GPSR6_24,
4888                 GP_6_23_FN,     GPSR6_23,
4889                 GP_6_22_FN,     GPSR6_22,
4890                 GP_6_21_FN,     GPSR6_21,
4891                 GP_6_20_FN,     GPSR6_20,
4892                 GP_6_19_FN,     GPSR6_19,
4893                 GP_6_18_FN,     GPSR6_18,
4894                 GP_6_17_FN,     GPSR6_17,
4895                 GP_6_16_FN,     GPSR6_16,
4896                 GP_6_15_FN,     GPSR6_15,
4897                 GP_6_14_FN,     GPSR6_14,
4898                 GP_6_13_FN,     GPSR6_13,
4899                 GP_6_12_FN,     GPSR6_12,
4900                 GP_6_11_FN,     GPSR6_11,
4901                 GP_6_10_FN,     GPSR6_10,
4902                 GP_6_9_FN,      GPSR6_9,
4903                 GP_6_8_FN,      GPSR6_8,
4904                 GP_6_7_FN,      GPSR6_7,
4905                 GP_6_6_FN,      GPSR6_6,
4906                 GP_6_5_FN,      GPSR6_5,
4907                 GP_6_4_FN,      GPSR6_4,
4908                 GP_6_3_FN,      GPSR6_3,
4909                 GP_6_2_FN,      GPSR6_2,
4910                 GP_6_1_FN,      GPSR6_1,
4911                 GP_6_0_FN,      GPSR6_0, }
4912         },
4913         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4914                 0, 0,
4915                 0, 0,
4916                 0, 0,
4917                 0, 0,
4918                 0, 0,
4919                 0, 0,
4920                 0, 0,
4921                 0, 0,
4922                 0, 0,
4923                 0, 0,
4924                 0, 0,
4925                 0, 0,
4926                 0, 0,
4927                 0, 0,
4928                 0, 0,
4929                 0, 0,
4930                 0, 0,
4931                 0, 0,
4932                 0, 0,
4933                 0, 0,
4934                 0, 0,
4935                 0, 0,
4936                 0, 0,
4937                 0, 0,
4938                 0, 0,
4939                 0, 0,
4940                 0, 0,
4941                 0, 0,
4942                 GP_7_3_FN, GPSR7_3,
4943                 GP_7_2_FN, GPSR7_2,
4944                 GP_7_1_FN, GPSR7_1,
4945                 GP_7_0_FN, GPSR7_0, }
4946         },
4947 #undef F_
4948 #undef FM
4949
4950 #define F_(x, y)        x,
4951 #define FM(x)           FN_##x,
4952         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4953                 IP0_31_28
4954                 IP0_27_24
4955                 IP0_23_20
4956                 IP0_19_16
4957                 IP0_15_12
4958                 IP0_11_8
4959                 IP0_7_4
4960                 IP0_3_0 }
4961         },
4962         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4963                 IP1_31_28
4964                 IP1_27_24
4965                 IP1_23_20
4966                 IP1_19_16
4967                 IP1_15_12
4968                 IP1_11_8
4969                 IP1_7_4
4970                 IP1_3_0 }
4971         },
4972         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4973                 IP2_31_28
4974                 IP2_27_24
4975                 IP2_23_20
4976                 IP2_19_16
4977                 IP2_15_12
4978                 IP2_11_8
4979                 IP2_7_4
4980                 IP2_3_0 }
4981         },
4982         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4983                 IP3_31_28
4984                 IP3_27_24
4985                 IP3_23_20
4986                 IP3_19_16
4987                 IP3_15_12
4988                 IP3_11_8
4989                 IP3_7_4
4990                 IP3_3_0 }
4991         },
4992         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4993                 IP4_31_28
4994                 IP4_27_24
4995                 IP4_23_20
4996                 IP4_19_16
4997                 IP4_15_12
4998                 IP4_11_8
4999                 IP4_7_4
5000                 IP4_3_0 }
5001         },
5002         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5003                 IP5_31_28
5004                 IP5_27_24
5005                 IP5_23_20
5006                 IP5_19_16
5007                 IP5_15_12
5008                 IP5_11_8
5009                 IP5_7_4
5010                 IP5_3_0 }
5011         },
5012         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5013                 IP6_31_28
5014                 IP6_27_24
5015                 IP6_23_20
5016                 IP6_19_16
5017                 IP6_15_12
5018                 IP6_11_8
5019                 IP6_7_4
5020                 IP6_3_0 }
5021         },
5022         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5023                 IP7_31_28
5024                 IP7_27_24
5025                 IP7_23_20
5026                 IP7_19_16
5027                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5028                 IP7_11_8
5029                 IP7_7_4
5030                 IP7_3_0 }
5031         },
5032         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5033                 IP8_31_28
5034                 IP8_27_24
5035                 IP8_23_20
5036                 IP8_19_16
5037                 IP8_15_12
5038                 IP8_11_8
5039                 IP8_7_4
5040                 IP8_3_0 }
5041         },
5042         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5043                 IP9_31_28
5044                 IP9_27_24
5045                 IP9_23_20
5046                 IP9_19_16
5047                 IP9_15_12
5048                 IP9_11_8
5049                 IP9_7_4
5050                 IP9_3_0 }
5051         },
5052         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5053                 IP10_31_28
5054                 IP10_27_24
5055                 IP10_23_20
5056                 IP10_19_16
5057                 IP10_15_12
5058                 IP10_11_8
5059                 IP10_7_4
5060                 IP10_3_0 }
5061         },
5062         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5063                 IP11_31_28
5064                 IP11_27_24
5065                 IP11_23_20
5066                 IP11_19_16
5067                 IP11_15_12
5068                 IP11_11_8
5069                 IP11_7_4
5070                 IP11_3_0 }
5071         },
5072         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5073                 IP12_31_28
5074                 IP12_27_24
5075                 IP12_23_20
5076                 IP12_19_16
5077                 IP12_15_12
5078                 IP12_11_8
5079                 IP12_7_4
5080                 IP12_3_0 }
5081         },
5082         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5083                 IP13_31_28
5084                 IP13_27_24
5085                 IP13_23_20
5086                 IP13_19_16
5087                 IP13_15_12
5088                 IP13_11_8
5089                 IP13_7_4
5090                 IP13_3_0 }
5091         },
5092         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5093                 IP14_31_28
5094                 IP14_27_24
5095                 IP14_23_20
5096                 IP14_19_16
5097                 IP14_15_12
5098                 IP14_11_8
5099                 IP14_7_4
5100                 IP14_3_0 }
5101         },
5102         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5103                 IP15_31_28
5104                 IP15_27_24
5105                 IP15_23_20
5106                 IP15_19_16
5107                 IP15_15_12
5108                 IP15_11_8
5109                 IP15_7_4
5110                 IP15_3_0 }
5111         },
5112         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5113                 IP16_31_28
5114                 IP16_27_24
5115                 IP16_23_20
5116                 IP16_19_16
5117                 IP16_15_12
5118                 IP16_11_8
5119                 IP16_7_4
5120                 IP16_3_0 }
5121         },
5122         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5123                 IP17_31_28
5124                 IP17_27_24
5125                 IP17_23_20
5126                 IP17_19_16
5127                 IP17_15_12
5128                 IP17_11_8
5129                 IP17_7_4
5130                 IP17_3_0 }
5131         },
5132         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5133                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5134                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5135                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5136                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5137                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5138                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5139                 IP18_7_4
5140                 IP18_3_0 }
5141         },
5142 #undef F_
5143 #undef FM
5144
5145 #define F_(x, y)        x,
5146 #define FM(x)           FN_##x,
5147         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5148                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5149                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5150                 MOD_SEL0_31_30_29
5151                 MOD_SEL0_28_27
5152                 MOD_SEL0_26_25_24
5153                 MOD_SEL0_23
5154                 MOD_SEL0_22
5155                 MOD_SEL0_21
5156                 MOD_SEL0_20
5157                 MOD_SEL0_19
5158                 MOD_SEL0_18_17
5159                 MOD_SEL0_16
5160                 0, 0, /* RESERVED 15 */
5161                 MOD_SEL0_14_13
5162                 MOD_SEL0_12
5163                 MOD_SEL0_11
5164                 MOD_SEL0_10
5165                 MOD_SEL0_9_8
5166                 MOD_SEL0_7_6
5167                 MOD_SEL0_5
5168                 MOD_SEL0_4_3
5169                 /* RESERVED 2, 1, 0 */
5170                 0, 0, 0, 0, 0, 0, 0, 0 }
5171         },
5172         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5173                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5174                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5175                 MOD_SEL1_31_30
5176                 MOD_SEL1_29_28_27
5177                 MOD_SEL1_26
5178                 MOD_SEL1_25_24
5179                 MOD_SEL1_23_22_21
5180                 MOD_SEL1_20
5181                 MOD_SEL1_19
5182                 MOD_SEL1_18_17
5183                 MOD_SEL1_16
5184                 MOD_SEL1_15_14
5185                 MOD_SEL1_13
5186                 MOD_SEL1_12
5187                 MOD_SEL1_11
5188                 MOD_SEL1_10
5189                 MOD_SEL1_9
5190                 0, 0, 0, 0, /* RESERVED 8, 7 */
5191                 MOD_SEL1_6
5192                 MOD_SEL1_5
5193                 MOD_SEL1_4
5194                 MOD_SEL1_3
5195                 MOD_SEL1_2
5196                 MOD_SEL1_1
5197                 MOD_SEL1_0 }
5198         },
5199         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5200                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5201                              4, 4, 4, 3, 1) {
5202                 MOD_SEL2_31
5203                 MOD_SEL2_30
5204                 MOD_SEL2_29
5205                 MOD_SEL2_28_27
5206                 MOD_SEL2_26
5207                 MOD_SEL2_25_24_23
5208                 MOD_SEL2_22
5209                 MOD_SEL2_21
5210                 MOD_SEL2_20
5211                 MOD_SEL2_19
5212                 MOD_SEL2_18
5213                 MOD_SEL2_17
5214                 /* RESERVED 16 */
5215                 0, 0,
5216                 /* RESERVED 15, 14, 13, 12 */
5217                 0, 0, 0, 0, 0, 0, 0, 0,
5218                 0, 0, 0, 0, 0, 0, 0, 0,
5219                 /* RESERVED 11, 10, 9, 8 */
5220                 0, 0, 0, 0, 0, 0, 0, 0,
5221                 0, 0, 0, 0, 0, 0, 0, 0,
5222                 /* RESERVED 7, 6, 5, 4 */
5223                 0, 0, 0, 0, 0, 0, 0, 0,
5224                 0, 0, 0, 0, 0, 0, 0, 0,
5225                 /* RESERVED 3, 2, 1 */
5226                 0, 0, 0, 0, 0, 0, 0, 0,
5227                 MOD_SEL2_0 }
5228         },
5229         { },
5230 };
5231
5232 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5233         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5234                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5235                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5236                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5237                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5238                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5239                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5240                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5241                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5242         } },
5243         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5244                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5245                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5246                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5247                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5248                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5249                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5250                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5251                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5252         } },
5253         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5254                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5255                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5256                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5257                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5258                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5259                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5260                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5261                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5262         } },
5263         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5264                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5265                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5266                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5267                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5268                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5269                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5270                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5271                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5272         } },
5273         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5274                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5275                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5276                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5277                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5278                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5279                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5280                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5281                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5282         } },
5283         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5284                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5285                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5286                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5287                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5288                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5289                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5290                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5291                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5292         } },
5293         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5294                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5295                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5296                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5297                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5298                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5299                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5300                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5301                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5302         } },
5303         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5304                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5305                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5306                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5307                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5308                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5309                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5310                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5311                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5312         } },
5313         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5314                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5315                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5316                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5317                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5318                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5319                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5320                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5321                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5322         } },
5323         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5324                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5325                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5326                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5327                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5328                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5329                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5330                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5331                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5332         } },
5333         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5334                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5335                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5336                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5337                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5338                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5339                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5340                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5341                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5342         } },
5343         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5344                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5345                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5346                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5347                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5348                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5349                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5350                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5351                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5352         } },
5353         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5354                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN2 */
5355                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5356                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5357         } },
5358         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5359                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5360                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5361                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5362                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5363                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5364                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5365                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5366                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5367         } },
5368         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5369                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5370                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5371                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5372                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5373                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5374                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5375                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5376                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5377         } },
5378         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5379                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5380                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5381                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5382                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5383                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5384                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5385                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5386                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5387         } },
5388         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5389                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5390                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5391                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5392                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5393                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5394                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5395                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5396                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5397         } },
5398         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5399                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5400                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5401                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5402                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5403                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5404                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5405                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5406                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5407         } },
5408         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5409                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0_TANS */
5410                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5411                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5412                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5413                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1_TANS */
5414                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5415                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5416                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5417         } },
5418         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5419                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5420                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5421                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5422                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5423                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5424                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5425                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5426                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5427         } },
5428         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5429                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5430                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5431                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5432                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5433                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5434                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5435                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5436                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5437         } },
5438         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5439                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5440                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5441                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5442                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5443                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5444                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5445                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5446                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5447         } },
5448         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5449                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5450                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5451                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5452                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5453                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5454                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5455                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5456                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5457         } },
5458         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5459                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5460                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5461                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5462                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5463                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5464                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5465                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5466                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5467         } },
5468         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5469                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5470                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5471                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5472                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5473                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5474                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5475                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5476         } },
5477         { },
5478 };
5479
5480 enum ioctrl_regs {
5481         POCCTRL,
5482 };
5483
5484 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5485         [POCCTRL] = { 0xe6060380, },
5486         { /* sentinel */ },
5487 };
5488
5489 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5490 {
5491         int bit = -EINVAL;
5492
5493         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5494
5495         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5496                 bit = pin & 0x1f;
5497
5498         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5499                 bit = (pin & 0x1f) + 12;
5500
5501         return bit;
5502 }
5503
5504 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5505         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5506                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
5507                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
5508                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
5509                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
5510                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
5511                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
5512                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
5513                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
5514                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
5515                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
5516                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
5517                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
5518                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
5519                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
5520                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
5521                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
5522                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
5523                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
5524                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
5525                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
5526                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
5527                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
5528                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
5529                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
5530                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
5531                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
5532                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
5533                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
5534                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
5535                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
5536                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
5537                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
5538         } },
5539         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5540                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
5541                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
5542                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
5543                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
5544                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
5545                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
5546                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
5547                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
5548                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
5549                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
5550                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
5551                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
5552                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
5553                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
5554                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
5555                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
5556                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
5557                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
5558                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
5559                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
5560                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
5561                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
5562                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
5563                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
5564                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
5565                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
5566                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
5567                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
5568                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
5569                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
5570                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
5571                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
5572         } },
5573         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5574                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
5575                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
5576                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
5577                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
5578                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
5579                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
5580                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
5581                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
5582                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
5583                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
5584                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
5585                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
5586                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
5587                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
5588                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
5589                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
5590                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
5591                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
5592                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
5593                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
5594                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
5595                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
5596                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
5597                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5598                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
5599                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
5600                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
5601                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
5602                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
5603                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
5604                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
5605                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
5606         } },
5607         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5608                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN2 */
5609                 [ 1] = PIN_NONE,
5610                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
5611                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
5612                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
5613                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
5614                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
5615                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
5616                 [ 8] = PIN_NONE,
5617                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
5618                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5619                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5620                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5621                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5622                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5623                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5624                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5625                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5626                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5627                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5628                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5629                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5630                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
5631                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
5632                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
5633                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
5634                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
5635                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
5636                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
5637                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
5638                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
5639                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
5640         } },
5641         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5642                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
5643                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
5644                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
5645                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
5646                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
5647                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
5648                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
5649                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
5650                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5651                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5652                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5653                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5654                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
5655                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
5656                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
5657                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
5658                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N_TANS */
5659                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
5660                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
5661                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
5662                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N_TANS */
5663                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
5664                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
5665                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
5666                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
5667                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
5668                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
5669                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
5670                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
5671                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
5672                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
5673                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
5674         } },
5675         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5676                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
5677                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
5678                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
5679                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
5680                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
5681                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
5682                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
5683                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5684                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5685                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5686                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
5687                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
5688                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5689                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5690                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5691                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
5692                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
5693                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5694                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5695                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5696                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5697                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5698                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5699                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5700                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
5701                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
5702                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
5703                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
5704                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
5705                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
5706                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
5707                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
5708         } },
5709         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5710                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
5711                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
5712                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
5713                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
5714                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
5715                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
5716                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
5717                 [ 7] = PIN_NONE,
5718                 [ 8] = PIN_NONE,
5719                 [ 9] = PIN_NONE,
5720                 [10] = PIN_NONE,
5721                 [11] = PIN_NONE,
5722                 [12] = PIN_NONE,
5723                 [13] = PIN_NONE,
5724                 [14] = PIN_NONE,
5725                 [15] = PIN_NONE,
5726                 [16] = PIN_NONE,
5727                 [17] = PIN_NONE,
5728                 [18] = PIN_NONE,
5729                 [19] = PIN_NONE,
5730                 [20] = PIN_NONE,
5731                 [21] = PIN_NONE,
5732                 [22] = PIN_NONE,
5733                 [23] = PIN_NONE,
5734                 [24] = PIN_NONE,
5735                 [25] = PIN_NONE,
5736                 [26] = PIN_NONE,
5737                 [27] = PIN_NONE,
5738                 [28] = PIN_NONE,
5739                 [29] = PIN_NONE,
5740                 [30] = PIN_NONE,
5741                 [31] = PIN_NONE,
5742         } },
5743         { /* sentinel */ },
5744 };
5745
5746 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5747                                             unsigned int pin)
5748 {
5749         const struct pinmux_bias_reg *reg;
5750         unsigned int bit;
5751
5752         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5753         if (!reg)
5754                 return PIN_CONFIG_BIAS_DISABLE;
5755
5756         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5757                 return PIN_CONFIG_BIAS_DISABLE;
5758         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5759                 return PIN_CONFIG_BIAS_PULL_UP;
5760         else
5761                 return PIN_CONFIG_BIAS_PULL_DOWN;
5762 }
5763
5764 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5765                                    unsigned int bias)
5766 {
5767         const struct pinmux_bias_reg *reg;
5768         u32 enable, updown;
5769         unsigned int bit;
5770
5771         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5772         if (!reg)
5773                 return;
5774
5775         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5776         if (bias != PIN_CONFIG_BIAS_DISABLE)
5777                 enable |= BIT(bit);
5778
5779         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5780         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5781                 updown |= BIT(bit);
5782
5783         sh_pfc_write(pfc, reg->pud, updown);
5784         sh_pfc_write(pfc, reg->puen, enable);
5785 }
5786
5787 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
5788         .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
5789         .get_bias = r8a7796_pinmux_get_bias,
5790         .set_bias = r8a7796_pinmux_set_bias,
5791 };
5792
5793 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5794         .name = "r8a77960_pfc",
5795         .ops = &r8a7796_pinmux_ops,
5796         .unlock_reg = 0xe6060000, /* PMMR */
5797
5798         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5799
5800         .pins = pinmux_pins,
5801         .nr_pins = ARRAY_SIZE(pinmux_pins),
5802         .groups = pinmux_groups,
5803         .nr_groups = ARRAY_SIZE(pinmux_groups),
5804         .functions = pinmux_functions,
5805         .nr_functions = ARRAY_SIZE(pinmux_functions),
5806
5807         .cfg_regs = pinmux_config_regs,
5808         .drive_regs = pinmux_drive_regs,
5809         .bias_regs = pinmux_bias_regs,
5810         .ioctrl_regs = pinmux_ioctrl_regs,
5811
5812         .pinmux_data = pinmux_data,
5813         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5814 };