drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7791/r8a7743 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2013 Renesas Electronics Corporation
   6  * Copyright (C) 2014-2017 Cogent Embedded, Inc.
   7  */
   8
   9 #include <linux/kernel.h>
  10
  11 #include "sh_pfc.h"
  12
  13 /*
  14  * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
  15  * which case they support both 3.3V and 1.8V signalling.
  16  */
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_32(0, fn, sfx),                                         \
  19         PORT_GP_26(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_32(3, fn, sfx),                                         \
  22         PORT_GP_32(4, fn, sfx),                                         \
  23         PORT_GP_32(5, fn, sfx),                                         \
  24         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  25         PORT_GP_1(6, 24, fn, sfx),                                      \
  26         PORT_GP_1(6, 25, fn, sfx),                                      \
  27         PORT_GP_1(6, 26, fn, sfx),                                      \
  28         PORT_GP_1(6, 27, fn, sfx),                                      \
  29         PORT_GP_1(6, 28, fn, sfx),                                      \
  30         PORT_GP_1(6, 29, fn, sfx),                                      \
  31         PORT_GP_1(6, 30, fn, sfx),                                      \
  32         PORT_GP_1(6, 31, fn, sfx),                                      \
  33         PORT_GP_26(7, fn, sfx)
  34
  35 enum {
  36         PINMUX_RESERVED = 0,
  37
  38         PINMUX_DATA_BEGIN,
  39         GP_ALL(DATA),
  40         PINMUX_DATA_END,
  41
  42         PINMUX_FUNCTION_BEGIN,
  43         GP_ALL(FN),
  44
  45         /* GPSR0 */
  46         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  47         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  48         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  49         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  50         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  51         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  52
  53         /* GPSR1 */
  54         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  55         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  56         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  57         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  58         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  59         FN_IP3_21_20,
  60
  61         /* GPSR2 */
  62         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  63         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  64         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  65         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  66         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  67         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  68         FN_IP6_5_3, FN_IP6_7_6,
  69
  70         /* GPSR3 */
  71         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  72         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  73         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  74         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  75         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  76         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  77         FN_IP9_18_17,
  78
  79         /* GPSR4 */
  80         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  81         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  82         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  83         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  84         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  85         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  86         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  87         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  88
  89         /* GPSR5 */
  90         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  91         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  92         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  93         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  94         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  95         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  96         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
  97
  98         /* GPSR6 */
  99         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
 100         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
 101         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
 102         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
 103         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
 104         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
 105         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
 106         FN_USB1_OVC, FN_DU0_DOTCLKIN,
 107
 108         /* GPSR7 */
 109         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 110         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 111         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 112         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 113         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 114         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 115
 116         /* IPSR0 */
 117         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 118         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 119         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
 120         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 121         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 122         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 123
 124         /* IPSR1 */
 125         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
 126         FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
 127         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 128         FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
 129         FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
 130         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 131         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 132         FN_A15, FN_BPFCLK_C,
 133         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 134         FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
 135         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 136
 137         /* IPSR2 */
 138         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 139         FN_A20, FN_SPCLK,
 140         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 141         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 142         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 143         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 144         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 145         FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
 146         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
 147         FN_EX_CS1_N, FN_MSIOF2_SCK,
 148         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 149         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 150
 151         /* IPSR3 */
 152         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 153         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 154         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 155         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 156         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 157         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 158         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 159         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 160         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 161         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 162         FN_DACK0, FN_DRACK0, FN_REMOCON,
 163         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 164         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 165         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 166         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 167
 168         /* IPSR4 */
 169         FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
 170         FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
 171         FN_GLO_I0_D,
 172         FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 173         FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
 174         FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 175         FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
 176         FN_GLO_Q1_D, FN_HCTS1_N_E,
 177         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 178         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 179         FN_SSI_SCK4, FN_GLO_SS_D,
 180         FN_SSI_WS4, FN_GLO_RFON_D,
 181         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 182         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 183         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 184
 185         /* IPSR5 */
 186         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 187         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 188         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 189         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 190         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 191         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 192         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 193         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 194         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 195         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 196         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 197         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 198         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 199         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 200         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 201
 202         /* IPSR6 */
 203         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 204         FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
 205         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 206         FN_SCIFA2_RXD, FN_FMIN_E,
 207         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 208         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 209         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 210         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 211         FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 212         FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 213         FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
 214         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
 215         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 216         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 217
 218         /* IPSR7 */
 219         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 220         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 221         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 222         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 223         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 224         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 225         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 226         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 227         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 228         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 229         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 230         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 231         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 232         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 233         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 234         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 235         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 236         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 237
 238         /* IPSR8 */
 239         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 240         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 241         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 242         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 243         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 244         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 245         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 246         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 247         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 248         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 249         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 250         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 251         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 252         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 253         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 254         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 255         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 256
 257         /* IPSR9 */
 258         FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
 259         FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 260         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 261         FN_DU1_DOTCLKOUT0, FN_QCLK,
 262         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 263         FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
 264         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 265         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 266         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 267         FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
 268         FN_DU1_DISP, FN_QPOLA,
 269         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 270         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 271         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 272         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 273         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 274         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 275         FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
 276         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 277
 278         /* IPSR10 */
 279         FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
 280         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 281         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
 282         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 283         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
 284         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 285         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 286         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 287         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 288         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 289         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 290         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 291         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 292         FN_TS_SDATA0_C, FN_ATACS11_N,
 293         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 294         FN_TS_SCK0_C, FN_ATAG1_N,
 295         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 296         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 297         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
 298
 299         /* IPSR11 */
 300         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
 301         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
 302         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 303         FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 304         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 305         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 306         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 307         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 308         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 309         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 310         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 311         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 312         FN_VI1_DATA7, FN_AVB_MDC,
 313         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
 314         FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
 315
 316         /* IPSR12 */
 317         FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
 318         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
 319         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 320         FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
 321         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
 322         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 323         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 324         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 325         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 326         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 327         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 328         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 329         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 330         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 331         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 332         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 333         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 334
 335         /* IPSR13 */
 336         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 337         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 338         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 339         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 340         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 341         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 342         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 343         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 344         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 345         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 346         FN_SCIFA5_TXD_B, FN_TX3_C,
 347         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 348         FN_SCIFA5_RXD_B, FN_RX3_C,
 349         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 350         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 351         FN_SD1_DATA3, FN_IERX_B,
 352         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
 353
 354         /* IPSR14 */
 355         FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
 356         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 357         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 358         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 359         FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 360         FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 361         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 362         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 363         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 364         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 365         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 366         FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
 367         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 368         FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
 369
 370         /* IPSR15 */
 371         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 372         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 373         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 374         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 375         FN_PWM5_B, FN_SCIFA3_TXD_C,
 376         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 377         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 378         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 379         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 380         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 381         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 382         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 383         FN_TCLK2, FN_VI1_DATA3_C,
 384         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 385         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 386
 387         /* IPSR16 */
 388         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 389         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 390         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
 391         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 392         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 393
 394         /* MOD_SEL */
 395         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 396         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 397         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 398         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 399         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 400         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 401         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 402         FN_SEL_QSP_0, FN_SEL_QSP_1,
 403         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 404         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 405         FN_SEL_HSCIF1_4,
 406         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 407         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 408         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 409         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 410         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 411
 412         /* MOD_SEL2 */
 413         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 414         FN_SEL_SCIF0_4,
 415         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 416         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 417         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 418         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 419         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 420         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 421         FN_SEL_ADG_0, FN_SEL_ADG_1,
 422         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 423         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 424         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 425         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 426         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 427         FN_SEL_SIM_0, FN_SEL_SIM_1,
 428         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 429
 430         /* MOD_SEL3 */
 431         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 432         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 433         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 434         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 435         FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
 436         FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
 437         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 438         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 439         FN_SEL_MMC_0, FN_SEL_MMC_1,
 440         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 441         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 442         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 443         FN_SEL_I2C1_4,
 444         FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
 445
 446         /* MOD_SEL4 */
 447         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 448         FN_SEL_SOF1_4,
 449         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 450         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 451         FN_SEL_RAD_0, FN_SEL_RAD_1,
 452         FN_SEL_RCN_0, FN_SEL_RCN_1,
 453         FN_SEL_RSP_0, FN_SEL_RSP_1,
 454         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 455         FN_SEL_SCIF2_4,
 456         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 457         FN_SEL_SOF2_4,
 458         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 459         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 460         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 461         PINMUX_FUNCTION_END,
 462
 463         PINMUX_MARK_BEGIN,
 464
 465         EX_CS0_N_MARK, RD_N_MARK,
 466
 467         AUDIO_CLKA_MARK,
 468
 469         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 470         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 471         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 472
 473         SD1_CLK_MARK,
 474
 475         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 476         DU0_DOTCLKIN_MARK,
 477
 478         /* IPSR0 */
 479         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 480         D6_MARK, D7_MARK, D8_MARK,
 481         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 482         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
 483         PWM2_B_MARK,
 484         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 485         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 486         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 487
 488         /* IPSR1 */
 489         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
 490         A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
 491         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 492         A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
 493         A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
 494         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 495         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 496         A15_MARK, BPFCLK_C_MARK,
 497         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 498         A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
 499         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 500
 501         /* IPSR2 */
 502         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 503         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 504         A20_MARK, SPCLK_MARK,
 505         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 506         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 507         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 508         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 509         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 510         RX1_MARK, SCIFA1_RXD_MARK,
 511         CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
 512         CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
 513         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 514         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 515         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 516         ATAG0_N_MARK, EX_WAIT1_MARK,
 517
 518         /* IPSR3 */
 519         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 520         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 521         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 522         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 523         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 524         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 525         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 526         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 527         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 528         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 529         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 530         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 531         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 532         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 533         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 534         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 535         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 536         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 537
 538         /* IPSR4 */
 539         SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
 540         SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
 541         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 542         SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
 543         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 544         SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
 545         SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
 546         HSCK1_E_MARK,
 547         SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 548         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 549         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 550         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 551         SSI_SCK4_MARK, GLO_SS_D_MARK,
 552         SSI_WS4_MARK, GLO_RFON_D_MARK,
 553         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 554         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 555         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 556
 557         /* IPSR5 */
 558         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 559         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 560         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 561         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 562         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 563         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 564         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 565         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 566         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 567         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 568         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 569         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 570         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 571         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 572         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 573
 574         /* IPSR6 */
 575         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 576         SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
 577         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 578         SCIFA2_RXD_MARK, FMIN_E_MARK,
 579         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 580         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 581         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 582         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 583         IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 584         IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
 585         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 586         IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
 587         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 588         I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
 589         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 590         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 591         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 592         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 593
 594         /* IPSR7 */
 595         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 596         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 597         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 598         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 599         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 600         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 601         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 602         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 603         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 604         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 605         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 606         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 607         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 608         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 609         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 610         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 611         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 612         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 613
 614         /* IPSR8 */
 615         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 616         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 617         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 618         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 619         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 620         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 621         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 622         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 623         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 624         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 625         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 626         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 627         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 628         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 629         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 630         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 631         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 632         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 633
 634         /* IPSR9 */
 635         DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 636         DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
 637         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 638         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 639         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 640         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 641         TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
 642         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 643         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 644         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 645         CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
 646         DU1_DISP_MARK, QPOLA_MARK,
 647         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 648         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 649         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 650         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 651         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 652         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 653         VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
 654         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 655
 656         /* IPSR10 */
 657         VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
 658         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 659         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
 660         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 661         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
 662         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 663         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 664         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 665         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 666         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 667         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 668         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 669         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 670         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 671         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 672         TS_SCK0_C_MARK, ATAG1_N_MARK,
 673         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 674         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 675         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
 676         I2C1_SCL_D_MARK,
 677
 678         /* IPSR11 */
 679         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
 680         I2C1_SDA_D_MARK,
 681         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
 682         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 683         I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 684         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 685         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 686         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 687         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 688         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 689         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 690         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 691         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 692         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 693         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 694         VI1_DATA7_MARK, AVB_MDC_MARK,
 695         ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
 696         ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
 697
 698         /* IPSR12 */
 699         ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
 700         ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
 701         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 702         I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
 703         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 704         I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
 705         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 706         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 707         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 708         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 709         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 710         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 711         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 712         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 713         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 714         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 715         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 716         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 717
 718         /* IPSR13 */
 719         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 720         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 721         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 722         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 723         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 724         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 725         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 726         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 727         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 728         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 729         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 730         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 731         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 732         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 733         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 734         SD1_DATA3_MARK, IERX_B_MARK,
 735         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
 736
 737         /* IPSR14 */
 738         SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
 739         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 740         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 741         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 742         SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
 743         SCIFA5_TXD_C_MARK,
 744         SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
 745         SCIFA5_RXD_C_MARK,
 746         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 747         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 748         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 749         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 750         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 751         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 752         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 753         VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
 754         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 755         VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
 756
 757         /* IPSR15 */
 758         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 759         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 760         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 761         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 762         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 763         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 764         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 765         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 766         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 767         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 768         TCLK1_MARK, VI1_DATA1_C_MARK,
 769         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 770         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 771         TCLK2_MARK, VI1_DATA3_C_MARK,
 772         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 773         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 774         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 775         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 776
 777         /* IPSR16 */
 778         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 779         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 780         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 781         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 782         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
 783         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 784         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 785         PINMUX_MARK_END,
 786 };
 787
 788 static const u16 pinmux_data[] = {
 789         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 790
 791         PINMUX_SINGLE(EX_CS0_N),
 792         PINMUX_SINGLE(RD_N),
 793         PINMUX_SINGLE(AUDIO_CLKA),
 794         PINMUX_SINGLE(VI0_CLK),
 795         PINMUX_SINGLE(VI0_DATA0_VI0_B0),
 796         PINMUX_SINGLE(VI0_DATA1_VI0_B1),
 797         PINMUX_SINGLE(VI0_DATA2_VI0_B2),
 798         PINMUX_SINGLE(VI0_DATA4_VI0_B4),
 799         PINMUX_SINGLE(VI0_DATA5_VI0_B5),
 800         PINMUX_SINGLE(VI0_DATA6_VI0_B6),
 801         PINMUX_SINGLE(VI0_DATA7_VI0_B7),
 802         PINMUX_SINGLE(USB0_PWEN),
 803         PINMUX_SINGLE(USB0_OVC),
 804         PINMUX_SINGLE(USB1_PWEN),
 805         PINMUX_SINGLE(USB1_OVC),
 806         PINMUX_SINGLE(DU0_DOTCLKIN),
 807         PINMUX_SINGLE(SD1_CLK),
 808
 809         /* IPSR0 */
 810         PINMUX_IPSR_GPSR(IP0_0, D0),
 811         PINMUX_IPSR_GPSR(IP0_1, D1),
 812         PINMUX_IPSR_GPSR(IP0_2, D2),
 813         PINMUX_IPSR_GPSR(IP0_3, D3),
 814         PINMUX_IPSR_GPSR(IP0_4, D4),
 815         PINMUX_IPSR_GPSR(IP0_5, D5),
 816         PINMUX_IPSR_GPSR(IP0_6, D6),
 817         PINMUX_IPSR_GPSR(IP0_7, D7),
 818         PINMUX_IPSR_GPSR(IP0_8, D8),
 819         PINMUX_IPSR_GPSR(IP0_9, D9),
 820         PINMUX_IPSR_GPSR(IP0_10, D10),
 821         PINMUX_IPSR_GPSR(IP0_11, D11),
 822         PINMUX_IPSR_GPSR(IP0_12, D12),
 823         PINMUX_IPSR_GPSR(IP0_13, D13),
 824         PINMUX_IPSR_GPSR(IP0_14, D14),
 825         PINMUX_IPSR_GPSR(IP0_15, D15),
 826         PINMUX_IPSR_GPSR(IP0_18_16, A0),
 827         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 828         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 829         PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
 830         PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
 831         PINMUX_IPSR_GPSR(IP0_20_19, A1),
 832         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 833         PINMUX_IPSR_GPSR(IP0_22_21, A2),
 834         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 835         PINMUX_IPSR_GPSR(IP0_24_23, A3),
 836         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 837         PINMUX_IPSR_GPSR(IP0_26_25, A4),
 838         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 839         PINMUX_IPSR_GPSR(IP0_28_27, A5),
 840         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 841         PINMUX_IPSR_GPSR(IP0_30_29, A6),
 842         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 843
 844         /* IPSR1 */
 845         PINMUX_IPSR_GPSR(IP1_1_0, A7),
 846         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 847         PINMUX_IPSR_GPSR(IP1_3_2, A8),
 848         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 849         PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
 850         PINMUX_IPSR_GPSR(IP1_5_4, A9),
 851         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 852         PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
 853         PINMUX_IPSR_GPSR(IP1_7_6, A10),
 854         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 855         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 856         PINMUX_IPSR_GPSR(IP1_10_8, A11),
 857         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 858         PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
 859         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 860         PINMUX_IPSR_GPSR(IP1_13_11, A12),
 861         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
 862         PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
 863         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 864         PINMUX_IPSR_GPSR(IP1_16_14, A13),
 865         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 866         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
 867         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 868         PINMUX_IPSR_GPSR(IP1_19_17, A14),
 869         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 870         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
 871         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
 872         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 873         PINMUX_IPSR_GPSR(IP1_22_20, A15),
 874         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
 875         PINMUX_IPSR_GPSR(IP1_25_23, A16),
 876         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
 877         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
 878         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 879         PINMUX_IPSR_GPSR(IP1_28_26, A17),
 880         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
 881         PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
 882         PINMUX_IPSR_GPSR(IP1_31_29, A18),
 883         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
 884         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 885         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 886
 887         /* IPSR2 */
 888         PINMUX_IPSR_GPSR(IP2_2_0, A19),
 889         PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
 890         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 891         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 892         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
 893         PINMUX_IPSR_GPSR(IP2_2_0, A20),
 894         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
 895         PINMUX_IPSR_GPSR(IP2_6_5, A21),
 896         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 897         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 898         PINMUX_IPSR_GPSR(IP2_9_7, A22),
 899         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
 900         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
 901         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
 902         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 903         PINMUX_IPSR_GPSR(IP2_12_10, A23),
 904         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
 905         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
 906         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
 907         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 908         PINMUX_IPSR_GPSR(IP2_15_13, A24),
 909         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
 910         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
 911         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
 912         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 913         PINMUX_IPSR_GPSR(IP2_18_16, A25),
 914         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
 915         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
 916         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
 917         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
 918         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 919         PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
 920         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 921         PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
 922         PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
 923         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 924         PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
 925         PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
 926         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 927         PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
 928         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 929         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 930         PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
 931         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 932         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 933         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
 934         PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
 935
 936         /* IPSR3 */
 937         PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
 938         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
 939         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 940         PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
 941         PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
 942         PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
 943         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 944         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 945         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 946         PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
 947         PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
 948         PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
 949         PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
 950         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 951         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 952         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 953         PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
 954         PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
 955         PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
 956         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 957         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
 958         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 959         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
 960         PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
 961         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 962         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 963         PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
 964         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 965         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 966         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 967         PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
 968         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 969         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 970         PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
 971         PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
 972         PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
 973         PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
 974         PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
 975         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
 976         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
 977         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 978         PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 979         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 980         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 981         PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
 982         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 983         PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 984         PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 985         PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 986         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 987         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 988         PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 989         PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 990         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 991         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 992         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 993
 994         /* IPSR4 */
 995         PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 996         PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
 997         PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
 998         PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 999         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1000         PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1001         PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1002         PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1003         PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1004         PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1005         PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1006         PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1007         PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1008         PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1009         PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1010         PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1011         PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1012         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1013         PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1014         PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1015         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1016         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1017         PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1018         PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1019         PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1020         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1021         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1022         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1023         PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1024         PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1025         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1026         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1027         PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1028         PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1029         PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1030         PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1031         PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1032         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1033         PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1034         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1035         PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1036         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1037         PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1038         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1039         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1040         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1041         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1042         PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1043
1044         /* IPSR5 */
1045         PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1046         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1047         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1048         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1049         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1050         PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1051         PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1052         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1053         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1054         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1055         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1056         PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1057         PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1058         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1059         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1060         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1061         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1062         PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1063         PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1064         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1065         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1066         PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1067         PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1068         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1069         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1070         PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1071         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1072         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1073         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1074         PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1075         PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1076         PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1077         PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1078         PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1079         PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1080         PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1081         PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1082         PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1083         PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1084         PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1085         PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1086         PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1087         PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1088         PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1089         PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1090         PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1091         PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1092         PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1093         PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1094
1095         /* IPSR6 */
1096         PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1097         PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1098         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1099         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1100         PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1101         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1102         PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1103         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1104         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1105         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1106         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1107         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1108         PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1109         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1110         PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1111         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1112         PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1113         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1114         PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1115         PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1116         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1117         PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1118         PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1119         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1120         PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1121         PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1122         PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1123         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1124         PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1125         PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1126         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1127         PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1128         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1129         PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1130         PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1131         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1132         PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1133         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1134         PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1135         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1136         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1137         PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1138         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1139         PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1140         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1141         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1142         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1143         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1144         PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1145         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1146         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1147         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1148         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1149
1150         /* IPSR7 */
1151         PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1152         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1153         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1154         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1155         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1156         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1157         PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1158         PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1159         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1160         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1161         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1162         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1163         PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1164         PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1165         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1166         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1167         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1168         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1169         PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1170         PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1171         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1172         PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1173         PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1174         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1175         PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1176         PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1177         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1178         PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1179         PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1180         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1181         PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1182         PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1183         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1184         PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1185         PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1186         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1187         PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1188         PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1189         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1190         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1191         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1192         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1193         PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1194         PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1195         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1196         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1197         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1198         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1199         PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1200         PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1201         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1202         PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1203         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1204         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1205
1206         /* IPSR8 */
1207         PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1208         PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1209         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1210         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1211         PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1212         PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1213         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1214         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1215         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1216         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1217         PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1218         PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1219         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1220         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1221         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1222         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1223         PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1224         PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1225         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1226         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1227         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1228         PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1229         PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1230         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1231         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1232         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1233         PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1234         PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1235         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1236         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1237         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1238         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1239         PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1240         PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1241         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1242         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1243         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1244         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1245         PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1246         PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1247         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1248         PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1249         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1250         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1251         PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1252         PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1253         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1254         PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1255         PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1256         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1257         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1258         PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1259         PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1260         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1261         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1262         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1263
1264         /* IPSR9 */
1265         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1266         PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1267         PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1268         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1269         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1270         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1271         PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1272         PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1273         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1274         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1275         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1276         PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1277         PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1278         PINMUX_IPSR_GPSR(IP9_7, QCLK),
1279         PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1280         PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1281         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1282         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1283         PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1284         PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1285         PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1286         PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1287         PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1288         PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1289         PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1290         PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1291         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1292         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1293         PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1294         PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1295         PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1296         PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1297         PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1298         PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1299         PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1300         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1301         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1302         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1303         PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1304         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1305         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1306         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1307         PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1308         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1309         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1310         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1311         PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1312         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1313         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1314         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1315         PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1316         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1317         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1318         PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1319         PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1320         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1321         PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1322         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1323         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1324         PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1325
1326         /* IPSR10 */
1327         PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1328         PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1329         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1330         PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1331         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1332         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1333         PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1334         PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1335         PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1336         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1337         PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1338         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1339         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1340         PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1341         PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1342         PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1343         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1344         PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1345         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1346         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1347         PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1348         PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1349         PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1350         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1351         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1352         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1353         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1354         PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1355         PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1356         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1357         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1358         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1359         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1360         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1361         PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1362         PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1363         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1364         PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1365         PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1366         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1367         PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1368         PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1369         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1370         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1371         PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1372         PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1373         PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1374         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1375         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1376         PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1377         PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1378         PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1379         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1380         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1381         PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1382         PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1383         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1384         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1385         PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1386         PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1387         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1388         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1389         PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1390
1391         /* IPSR11 */
1392         PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1393         PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1394         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1395         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1396         PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1397         PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1398         PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1399         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1400         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1401         PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1402         PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1403         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1404         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1405         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1406         PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1407         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1408         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1409         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1410         PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1411         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1412         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1413         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1414         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1415         PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1416         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1417         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1418         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1419         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1420         PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1421         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1422         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1423         PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1424         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1425         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1426         PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1427         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1428         PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1429         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1430         PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1431         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1432         PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1433         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1434         PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1435         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1436         PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1437         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1438         PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1439         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1440         PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1441         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1442         PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1443         PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1444         PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1445         PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1446         PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1447         PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1448         PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1449
1450         /* IPSR12 */
1451         PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1452         PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1453         PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1454         PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1455         PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1456         PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1457         PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1458         PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1459         PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1460         PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1461         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1462         PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1463         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1464         PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1465         PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1466         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1467         PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1468         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1469         PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1470         PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1471         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1472         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1473         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1474         PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1475         PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1476         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1477         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1478         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1479         PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1480         PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1481         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1482         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1483         PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1484         PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1485         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1486         PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1487         PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1488         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1489         PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1490         PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1491         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1492         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1493         PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1494         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1495         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1496         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1497         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1498         PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1499         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1500         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1501         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1502
1503         /* IPSR13 */
1504         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1505         PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1506         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1507         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1508         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1509         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1510         PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1511         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1512         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1513         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1514         PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1515         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1516         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1517         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1518         PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1519         PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1520         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1521         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1522         PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1523         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1524         PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1525         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1526         PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1527         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1528         PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1529         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1530         PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1531         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1532         PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1533         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1534         PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1535         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1536         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1537         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1538         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1539         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1540         PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1541         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1542         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1543         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1544         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1545         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1546         PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1547         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1548         PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1549         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1550         PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1551         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1552         PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1553         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1554         PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1555         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1556         PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1557         PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1558         PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1559         PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1560
1561         /* IPSR14 */
1562         PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1563         PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1564         PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1565         PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1566         PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1567         PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1568         PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1569         PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1570         PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1571         PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1572         PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1573         PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1574         PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1575         PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1576         PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1577         PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1578         PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1579         PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1580         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1581         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1582         PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1583         PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1584         PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1585         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1586         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1587         PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1588         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1589         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1590         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1591         PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1592         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1593         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1594         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1595         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1596         PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1597         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1598         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1599         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1600         PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1601         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1602         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1603         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1604         PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1605         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1606         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1607         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1608         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1609         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1610         PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1611         PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1612         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1613         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1614         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1615         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1616         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1617         PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1618         PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1619
1620         /* IPSR15 */
1621         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1622         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1623         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1624         PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1625         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1626         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1627         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1628         PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1629         PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1630         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1631         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1632         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1633         PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1634         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1635         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1636         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1637         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1638         PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1639         PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1640         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1641         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1642         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1643         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1644         PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1645         PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1646         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1647         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1648         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1649         PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1650         PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1651         PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1652         PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1653         PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1654         PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1655         PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1656         PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1657         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1658         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1659         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1660         PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1661         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1662         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1663         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1664         PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1665         PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1666         PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1667         PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1668         PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1669         PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1670         PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1671         PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1672
1673         /* IPSR16 */
1674         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1675         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1676         PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1677         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1678         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1679         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1680         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1681         PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1682         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1683         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1684         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1685         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1686         PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1687         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1688         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1689         PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1690         PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1691         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1692         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1693         PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1694         PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1695         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1696 };
1697
1698 static const struct sh_pfc_pin pinmux_pins[] = {
1699         PINMUX_GPIO_GP_ALL(),
1700 };
1701
1702 /* - ADI -------------------------------------------------------------------- */
1703 static const unsigned int adi_common_pins[] = {
1704         /* ADIDATA, ADICS/SAMP, ADICLK */
1705         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1706 };
1707 static const unsigned int adi_common_mux[] = {
1708         /* ADIDATA, ADICS/SAMP, ADICLK */
1709         ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1710 };
1711 static const unsigned int adi_chsel0_pins[] = {
1712         /* ADICHS 0 */
1713         RCAR_GP_PIN(6, 27),
1714 };
1715 static const unsigned int adi_chsel0_mux[] = {
1716         /* ADICHS 0 */
1717         ADICHS0_MARK,
1718 };
1719 static const unsigned int adi_chsel1_pins[] = {
1720         /* ADICHS 1 */
1721         RCAR_GP_PIN(6, 28),
1722 };
1723 static const unsigned int adi_chsel1_mux[] = {
1724         /* ADICHS 1 */
1725         ADICHS1_MARK,
1726 };
1727 static const unsigned int adi_chsel2_pins[] = {
1728         /* ADICHS 2 */
1729         RCAR_GP_PIN(6, 29),
1730 };
1731 static const unsigned int adi_chsel2_mux[] = {
1732         /* ADICHS 2 */
1733         ADICHS2_MARK,
1734 };
1735 static const unsigned int adi_common_b_pins[] = {
1736         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1737         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1738 };
1739 static const unsigned int adi_common_b_mux[] = {
1740         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1741         ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1742 };
1743 static const unsigned int adi_chsel0_b_pins[] = {
1744         /* ADICHS B 0 */
1745         RCAR_GP_PIN(5, 28),
1746 };
1747 static const unsigned int adi_chsel0_b_mux[] = {
1748         /* ADICHS B 0 */
1749         ADICHS0_B_MARK,
1750 };
1751 static const unsigned int adi_chsel1_b_pins[] = {
1752         /* ADICHS B 1 */
1753         RCAR_GP_PIN(5, 29),
1754 };
1755 static const unsigned int adi_chsel1_b_mux[] = {
1756         /* ADICHS B 1 */
1757         ADICHS1_B_MARK,
1758 };
1759 static const unsigned int adi_chsel2_b_pins[] = {
1760         /* ADICHS B 2 */
1761         RCAR_GP_PIN(5, 30),
1762 };
1763 static const unsigned int adi_chsel2_b_mux[] = {
1764         /* ADICHS B 2 */
1765         ADICHS2_B_MARK,
1766 };
1767
1768 /* - Audio Clock ------------------------------------------------------------ */
1769 static const unsigned int audio_clk_a_pins[] = {
1770         /* CLK */
1771         RCAR_GP_PIN(2, 28),
1772 };
1773
1774 static const unsigned int audio_clk_a_mux[] = {
1775         AUDIO_CLKA_MARK,
1776 };
1777
1778 static const unsigned int audio_clk_b_pins[] = {
1779         /* CLK */
1780         RCAR_GP_PIN(2, 29),
1781 };
1782
1783 static const unsigned int audio_clk_b_mux[] = {
1784         AUDIO_CLKB_MARK,
1785 };
1786
1787 static const unsigned int audio_clk_b_b_pins[] = {
1788         /* CLK */
1789         RCAR_GP_PIN(7, 20),
1790 };
1791
1792 static const unsigned int audio_clk_b_b_mux[] = {
1793         AUDIO_CLKB_B_MARK,
1794 };
1795
1796 static const unsigned int audio_clk_c_pins[] = {
1797         /* CLK */
1798         RCAR_GP_PIN(2, 30),
1799 };
1800
1801 static const unsigned int audio_clk_c_mux[] = {
1802         AUDIO_CLKC_MARK,
1803 };
1804
1805 static const unsigned int audio_clkout_pins[] = {
1806         /* CLK */
1807         RCAR_GP_PIN(2, 31),
1808 };
1809
1810 static const unsigned int audio_clkout_mux[] = {
1811         AUDIO_CLKOUT_MARK,
1812 };
1813
1814 /* - AVB -------------------------------------------------------------------- */
1815 static const unsigned int avb_link_pins[] = {
1816         RCAR_GP_PIN(5, 14),
1817 };
1818 static const unsigned int avb_link_mux[] = {
1819         AVB_LINK_MARK,
1820 };
1821 static const unsigned int avb_magic_pins[] = {
1822         RCAR_GP_PIN(5, 11),
1823 };
1824 static const unsigned int avb_magic_mux[] = {
1825         AVB_MAGIC_MARK,
1826 };
1827 static const unsigned int avb_phy_int_pins[] = {
1828         RCAR_GP_PIN(5, 16),
1829 };
1830 static const unsigned int avb_phy_int_mux[] = {
1831         AVB_PHY_INT_MARK,
1832 };
1833 static const unsigned int avb_mdio_pins[] = {
1834         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1835 };
1836 static const unsigned int avb_mdio_mux[] = {
1837         AVB_MDC_MARK, AVB_MDIO_MARK,
1838 };
1839 static const unsigned int avb_mii_pins[] = {
1840         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1841         RCAR_GP_PIN(5, 21),
1842
1843         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1844         RCAR_GP_PIN(5, 3),
1845
1846         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1847         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1848         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1849 };
1850 static const unsigned int avb_mii_mux[] = {
1851         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1852         AVB_TXD3_MARK,
1853
1854         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1855         AVB_RXD3_MARK,
1856
1857         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1858         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1859         AVB_TX_CLK_MARK, AVB_COL_MARK,
1860 };
1861 static const unsigned int avb_gmii_pins[] = {
1862         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1863         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1864         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1865
1866         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1867         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1868         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1869
1870         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1871         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1872         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1873         RCAR_GP_PIN(5, 29),
1874 };
1875 static const unsigned int avb_gmii_mux[] = {
1876         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1877         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1878         AVB_TXD6_MARK, AVB_TXD7_MARK,
1879
1880         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1881         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1882         AVB_RXD6_MARK, AVB_RXD7_MARK,
1883
1884         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1885         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1886         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1887         AVB_COL_MARK,
1888 };
1889
1890 /* - CAN -------------------------------------------------------------------- */
1891
1892 static const unsigned int can0_data_pins[] = {
1893         /* TX, RX */
1894         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1895 };
1896
1897 static const unsigned int can0_data_mux[] = {
1898         CAN0_TX_MARK, CAN0_RX_MARK,
1899 };
1900
1901 static const unsigned int can0_data_b_pins[] = {
1902         /* TX, RX */
1903         RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1904 };
1905
1906 static const unsigned int can0_data_b_mux[] = {
1907         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1908 };
1909
1910 static const unsigned int can0_data_c_pins[] = {
1911         /* TX, RX */
1912         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1913 };
1914
1915 static const unsigned int can0_data_c_mux[] = {
1916         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1917 };
1918
1919 static const unsigned int can0_data_d_pins[] = {
1920         /* TX, RX */
1921         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1922 };
1923
1924 static const unsigned int can0_data_d_mux[] = {
1925         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1926 };
1927
1928 static const unsigned int can0_data_e_pins[] = {
1929         /* TX, RX */
1930         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1931 };
1932
1933 static const unsigned int can0_data_e_mux[] = {
1934         CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1935 };
1936
1937 static const unsigned int can0_data_f_pins[] = {
1938         /* TX, RX */
1939         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1940 };
1941
1942 static const unsigned int can0_data_f_mux[] = {
1943         CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1944 };
1945
1946 static const unsigned int can1_data_pins[] = {
1947         /* TX, RX */
1948          RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1949 };
1950
1951 static const unsigned int can1_data_mux[] = {
1952         CAN1_TX_MARK, CAN1_RX_MARK,
1953 };
1954
1955 static const unsigned int can1_data_b_pins[] = {
1956         /* TX, RX */
1957         RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1958 };
1959
1960 static const unsigned int can1_data_b_mux[] = {
1961         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1962 };
1963
1964 static const unsigned int can1_data_c_pins[] = {
1965         /* TX, RX */
1966         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1967 };
1968
1969 static const unsigned int can1_data_c_mux[] = {
1970         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1971 };
1972
1973 static const unsigned int can1_data_d_pins[] = {
1974         /* TX, RX */
1975          RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1976 };
1977
1978 static const unsigned int can1_data_d_mux[] = {
1979         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1980 };
1981
1982 static const unsigned int can_clk_pins[] = {
1983         /* CLK */
1984         RCAR_GP_PIN(7, 2),
1985 };
1986
1987 static const unsigned int can_clk_mux[] = {
1988         CAN_CLK_MARK,
1989 };
1990
1991 static const unsigned int can_clk_b_pins[] = {
1992         /* CLK */
1993         RCAR_GP_PIN(5, 21),
1994 };
1995
1996 static const unsigned int can_clk_b_mux[] = {
1997         CAN_CLK_B_MARK,
1998 };
1999
2000 static const unsigned int can_clk_c_pins[] = {
2001         /* CLK */
2002         RCAR_GP_PIN(4, 30),
2003 };
2004
2005 static const unsigned int can_clk_c_mux[] = {
2006         CAN_CLK_C_MARK,
2007 };
2008
2009 static const unsigned int can_clk_d_pins[] = {
2010         /* CLK */
2011         RCAR_GP_PIN(7, 19),
2012 };
2013
2014 static const unsigned int can_clk_d_mux[] = {
2015         CAN_CLK_D_MARK,
2016 };
2017
2018 /* - DU --------------------------------------------------------------------- */
2019 static const unsigned int du_rgb666_pins[] = {
2020         /* R[7:2], G[7:2], B[7:2] */
2021         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2022         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2023         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2024         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2025         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2026         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2027 };
2028 static const unsigned int du_rgb666_mux[] = {
2029         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2030         DU1_DR3_MARK, DU1_DR2_MARK,
2031         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2032         DU1_DG3_MARK, DU1_DG2_MARK,
2033         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2034         DU1_DB3_MARK, DU1_DB2_MARK,
2035 };
2036 static const unsigned int du_rgb888_pins[] = {
2037         /* R[7:0], G[7:0], B[7:0] */
2038         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2039         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2040         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
2041         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2042         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2043         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
2044         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2045         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2046         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2047 };
2048 static const unsigned int du_rgb888_mux[] = {
2049         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2050         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2051         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2052         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2053         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2054         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2055 };
2056 static const unsigned int du_clk_out_0_pins[] = {
2057         /* CLKOUT */
2058         RCAR_GP_PIN(3, 25),
2059 };
2060 static const unsigned int du_clk_out_0_mux[] = {
2061         DU1_DOTCLKOUT0_MARK
2062 };
2063 static const unsigned int du_clk_out_1_pins[] = {
2064         /* CLKOUT */
2065         RCAR_GP_PIN(3, 26),
2066 };
2067 static const unsigned int du_clk_out_1_mux[] = {
2068         DU1_DOTCLKOUT1_MARK
2069 };
2070 static const unsigned int du_sync_pins[] = {
2071         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2072         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2073 };
2074 static const unsigned int du_sync_mux[] = {
2075         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2076 };
2077 static const unsigned int du_oddf_pins[] = {
2078         /* EXDISP/EXODDF/EXCDE */
2079         RCAR_GP_PIN(3, 29),
2080 };
2081 static const unsigned int du_oddf_mux[] = {
2082         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2083 };
2084 static const unsigned int du_cde_pins[] = {
2085         /* CDE */
2086         RCAR_GP_PIN(3, 31),
2087 };
2088 static const unsigned int du_cde_mux[] = {
2089         DU1_CDE_MARK,
2090 };
2091 static const unsigned int du_disp_pins[] = {
2092         /* DISP */
2093         RCAR_GP_PIN(3, 30),
2094 };
2095 static const unsigned int du_disp_mux[] = {
2096         DU1_DISP_MARK,
2097 };
2098 static const unsigned int du0_clk_in_pins[] = {
2099         /* CLKIN */
2100         RCAR_GP_PIN(6, 31),
2101 };
2102 static const unsigned int du0_clk_in_mux[] = {
2103         DU0_DOTCLKIN_MARK
2104 };
2105 static const unsigned int du1_clk_in_pins[] = {
2106         /* CLKIN */
2107         RCAR_GP_PIN(3, 24),
2108 };
2109 static const unsigned int du1_clk_in_mux[] = {
2110         DU1_DOTCLKIN_MARK
2111 };
2112 static const unsigned int du1_clk_in_b_pins[] = {
2113         /* CLKIN */
2114         RCAR_GP_PIN(7, 19),
2115 };
2116 static const unsigned int du1_clk_in_b_mux[] = {
2117         DU1_DOTCLKIN_B_MARK,
2118 };
2119 static const unsigned int du1_clk_in_c_pins[] = {
2120         /* CLKIN */
2121         RCAR_GP_PIN(7, 20),
2122 };
2123 static const unsigned int du1_clk_in_c_mux[] = {
2124         DU1_DOTCLKIN_C_MARK,
2125 };
2126 /* - ETH -------------------------------------------------------------------- */
2127 static const unsigned int eth_link_pins[] = {
2128         /* LINK */
2129         RCAR_GP_PIN(5, 18),
2130 };
2131 static const unsigned int eth_link_mux[] = {
2132         ETH_LINK_MARK,
2133 };
2134 static const unsigned int eth_magic_pins[] = {
2135         /* MAGIC */
2136         RCAR_GP_PIN(5, 22),
2137 };
2138 static const unsigned int eth_magic_mux[] = {
2139         ETH_MAGIC_MARK,
2140 };
2141 static const unsigned int eth_mdio_pins[] = {
2142         /* MDC, MDIO */
2143         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2144 };
2145 static const unsigned int eth_mdio_mux[] = {
2146         ETH_MDC_MARK, ETH_MDIO_MARK,
2147 };
2148 static const unsigned int eth_rmii_pins[] = {
2149         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2150         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2151         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2152         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2153 };
2154 static const unsigned int eth_rmii_mux[] = {
2155         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2156         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2157 };
2158
2159 /* - HSCIF0 ----------------------------------------------------------------- */
2160 static const unsigned int hscif0_data_pins[] = {
2161         /* RX, TX */
2162         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2163 };
2164 static const unsigned int hscif0_data_mux[] = {
2165         HRX0_MARK, HTX0_MARK,
2166 };
2167 static const unsigned int hscif0_clk_pins[] = {
2168         /* SCK */
2169         RCAR_GP_PIN(7, 2),
2170 };
2171 static const unsigned int hscif0_clk_mux[] = {
2172         HSCK0_MARK,
2173 };
2174 static const unsigned int hscif0_ctrl_pins[] = {
2175         /* RTS, CTS */
2176         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2177 };
2178 static const unsigned int hscif0_ctrl_mux[] = {
2179         HRTS0_N_MARK, HCTS0_N_MARK,
2180 };
2181 static const unsigned int hscif0_data_b_pins[] = {
2182         /* RX, TX */
2183         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2184 };
2185 static const unsigned int hscif0_data_b_mux[] = {
2186         HRX0_B_MARK, HTX0_B_MARK,
2187 };
2188 static const unsigned int hscif0_ctrl_b_pins[] = {
2189         /* RTS, CTS */
2190         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2191 };
2192 static const unsigned int hscif0_ctrl_b_mux[] = {
2193         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2194 };
2195 static const unsigned int hscif0_data_c_pins[] = {
2196         /* RX, TX */
2197         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2198 };
2199 static const unsigned int hscif0_data_c_mux[] = {
2200         HRX0_C_MARK, HTX0_C_MARK,
2201 };
2202 static const unsigned int hscif0_clk_c_pins[] = {
2203         /* SCK */
2204         RCAR_GP_PIN(5, 31),
2205 };
2206 static const unsigned int hscif0_clk_c_mux[] = {
2207         HSCK0_C_MARK,
2208 };
2209 /* - HSCIF1 ----------------------------------------------------------------- */
2210 static const unsigned int hscif1_data_pins[] = {
2211         /* RX, TX */
2212         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2213 };
2214 static const unsigned int hscif1_data_mux[] = {
2215         HRX1_MARK, HTX1_MARK,
2216 };
2217 static const unsigned int hscif1_clk_pins[] = {
2218         /* SCK */
2219         RCAR_GP_PIN(7, 7),
2220 };
2221 static const unsigned int hscif1_clk_mux[] = {
2222         HSCK1_MARK,
2223 };
2224 static const unsigned int hscif1_ctrl_pins[] = {
2225         /* RTS, CTS */
2226         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2227 };
2228 static const unsigned int hscif1_ctrl_mux[] = {
2229         HRTS1_N_MARK, HCTS1_N_MARK,
2230 };
2231 static const unsigned int hscif1_data_b_pins[] = {
2232         /* RX, TX */
2233         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2234 };
2235 static const unsigned int hscif1_data_b_mux[] = {
2236         HRX1_B_MARK, HTX1_B_MARK,
2237 };
2238 static const unsigned int hscif1_data_c_pins[] = {
2239         /* RX, TX */
2240         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2241 };
2242 static const unsigned int hscif1_data_c_mux[] = {
2243         HRX1_C_MARK, HTX1_C_MARK,
2244 };
2245 static const unsigned int hscif1_clk_c_pins[] = {
2246         /* SCK */
2247         RCAR_GP_PIN(7, 16),
2248 };
2249 static const unsigned int hscif1_clk_c_mux[] = {
2250         HSCK1_C_MARK,
2251 };
2252 static const unsigned int hscif1_ctrl_c_pins[] = {
2253         /* RTS, CTS */
2254         RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2255 };
2256 static const unsigned int hscif1_ctrl_c_mux[] = {
2257         HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2258 };
2259 static const unsigned int hscif1_data_d_pins[] = {
2260         /* RX, TX */
2261         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2262 };
2263 static const unsigned int hscif1_data_d_mux[] = {
2264         HRX1_D_MARK, HTX1_D_MARK,
2265 };
2266 static const unsigned int hscif1_data_e_pins[] = {
2267         /* RX, TX */
2268         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2269 };
2270 static const unsigned int hscif1_data_e_mux[] = {
2271         HRX1_C_MARK, HTX1_C_MARK,
2272 };
2273 static const unsigned int hscif1_clk_e_pins[] = {
2274         /* SCK */
2275         RCAR_GP_PIN(2, 6),
2276 };
2277 static const unsigned int hscif1_clk_e_mux[] = {
2278         HSCK1_E_MARK,
2279 };
2280 static const unsigned int hscif1_ctrl_e_pins[] = {
2281         /* RTS, CTS */
2282         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2283 };
2284 static const unsigned int hscif1_ctrl_e_mux[] = {
2285         HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2286 };
2287 /* - HSCIF2 ----------------------------------------------------------------- */
2288 static const unsigned int hscif2_data_pins[] = {
2289         /* RX, TX */
2290         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2291 };
2292 static const unsigned int hscif2_data_mux[] = {
2293         HRX2_MARK, HTX2_MARK,
2294 };
2295 static const unsigned int hscif2_clk_pins[] = {
2296         /* SCK */
2297         RCAR_GP_PIN(4, 15),
2298 };
2299 static const unsigned int hscif2_clk_mux[] = {
2300         HSCK2_MARK,
2301 };
2302 static const unsigned int hscif2_ctrl_pins[] = {
2303         /* RTS, CTS */
2304         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2305 };
2306 static const unsigned int hscif2_ctrl_mux[] = {
2307         HRTS2_N_MARK, HCTS2_N_MARK,
2308 };
2309 static const unsigned int hscif2_data_b_pins[] = {
2310         /* RX, TX */
2311         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2312 };
2313 static const unsigned int hscif2_data_b_mux[] = {
2314         HRX2_B_MARK, HTX2_B_MARK,
2315 };
2316 static const unsigned int hscif2_ctrl_b_pins[] = {
2317         /* RTS, CTS */
2318         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2319 };
2320 static const unsigned int hscif2_ctrl_b_mux[] = {
2321         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2322 };
2323 static const unsigned int hscif2_data_c_pins[] = {
2324         /* RX, TX */
2325         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2326 };
2327 static const unsigned int hscif2_data_c_mux[] = {
2328         HRX2_C_MARK, HTX2_C_MARK,
2329 };
2330 static const unsigned int hscif2_clk_c_pins[] = {
2331         /* SCK */
2332         RCAR_GP_PIN(5, 31),
2333 };
2334 static const unsigned int hscif2_clk_c_mux[] = {
2335         HSCK2_C_MARK,
2336 };
2337 static const unsigned int hscif2_data_d_pins[] = {
2338         /* RX, TX */
2339         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2340 };
2341 static const unsigned int hscif2_data_d_mux[] = {
2342         HRX2_B_MARK, HTX2_D_MARK,
2343 };
2344 /* - I2C0 ------------------------------------------------------------------- */
2345 static const unsigned int i2c0_pins[] = {
2346         /* SCL, SDA */
2347         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2348 };
2349 static const unsigned int i2c0_mux[] = {
2350         I2C0_SCL_MARK, I2C0_SDA_MARK,
2351 };
2352 static const unsigned int i2c0_b_pins[] = {
2353         /* SCL, SDA */
2354         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2355 };
2356 static const unsigned int i2c0_b_mux[] = {
2357         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2358 };
2359 static const unsigned int i2c0_c_pins[] = {
2360         /* SCL, SDA */
2361         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2362 };
2363 static const unsigned int i2c0_c_mux[] = {
2364         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2365 };
2366 /* - I2C1 ------------------------------------------------------------------- */
2367 static const unsigned int i2c1_pins[] = {
2368         /* SCL, SDA */
2369         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2370 };
2371 static const unsigned int i2c1_mux[] = {
2372         I2C1_SCL_MARK, I2C1_SDA_MARK,
2373 };
2374 static const unsigned int i2c1_b_pins[] = {
2375         /* SCL, SDA */
2376         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2377 };
2378 static const unsigned int i2c1_b_mux[] = {
2379         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2380 };
2381 static const unsigned int i2c1_c_pins[] = {
2382         /* SCL, SDA */
2383         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2384 };
2385 static const unsigned int i2c1_c_mux[] = {
2386         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2387 };
2388 static const unsigned int i2c1_d_pins[] = {
2389         /* SCL, SDA */
2390         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2391 };
2392 static const unsigned int i2c1_d_mux[] = {
2393         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2394 };
2395 static const unsigned int i2c1_e_pins[] = {
2396         /* SCL, SDA */
2397         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2398 };
2399 static const unsigned int i2c1_e_mux[] = {
2400         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2401 };
2402 /* - I2C2 ------------------------------------------------------------------- */
2403 static const unsigned int i2c2_pins[] = {
2404         /* SCL, SDA */
2405         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2406 };
2407 static const unsigned int i2c2_mux[] = {
2408         I2C2_SCL_MARK, I2C2_SDA_MARK,
2409 };
2410 static const unsigned int i2c2_b_pins[] = {
2411         /* SCL, SDA */
2412         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2413 };
2414 static const unsigned int i2c2_b_mux[] = {
2415         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2416 };
2417 static const unsigned int i2c2_c_pins[] = {
2418         /* SCL, SDA */
2419         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2420 };
2421 static const unsigned int i2c2_c_mux[] = {
2422         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2423 };
2424 static const unsigned int i2c2_d_pins[] = {
2425         /* SCL, SDA */
2426         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2427 };
2428 static const unsigned int i2c2_d_mux[] = {
2429         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2430 };
2431 /* - I2C3 ------------------------------------------------------------------- */
2432 static const unsigned int i2c3_pins[] = {
2433         /* SCL, SDA */
2434         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2435 };
2436 static const unsigned int i2c3_mux[] = {
2437         I2C3_SCL_MARK, I2C3_SDA_MARK,
2438 };
2439 static const unsigned int i2c3_b_pins[] = {
2440         /* SCL, SDA */
2441         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2442 };
2443 static const unsigned int i2c3_b_mux[] = {
2444         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2445 };
2446 static const unsigned int i2c3_c_pins[] = {
2447         /* SCL, SDA */
2448         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2449 };
2450 static const unsigned int i2c3_c_mux[] = {
2451         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2452 };
2453 static const unsigned int i2c3_d_pins[] = {
2454         /* SCL, SDA */
2455         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2456 };
2457 static const unsigned int i2c3_d_mux[] = {
2458         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2459 };
2460 /* - I2C4 ------------------------------------------------------------------- */
2461 static const unsigned int i2c4_pins[] = {
2462         /* SCL, SDA */
2463         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2464 };
2465 static const unsigned int i2c4_mux[] = {
2466         I2C4_SCL_MARK, I2C4_SDA_MARK,
2467 };
2468 static const unsigned int i2c4_b_pins[] = {
2469         /* SCL, SDA */
2470         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2471 };
2472 static const unsigned int i2c4_b_mux[] = {
2473         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2474 };
2475 static const unsigned int i2c4_c_pins[] = {
2476         /* SCL, SDA */
2477         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2478 };
2479 static const unsigned int i2c4_c_mux[] = {
2480         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2481 };
2482 /* - I2C7 ------------------------------------------------------------------- */
2483 static const unsigned int i2c7_pins[] = {
2484         /* SCL, SDA */
2485         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2486 };
2487 static const unsigned int i2c7_mux[] = {
2488         IIC0_SCL_MARK, IIC0_SDA_MARK,
2489 };
2490 static const unsigned int i2c7_b_pins[] = {
2491         /* SCL, SDA */
2492         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2493 };
2494 static const unsigned int i2c7_b_mux[] = {
2495         IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2496 };
2497 static const unsigned int i2c7_c_pins[] = {
2498         /* SCL, SDA */
2499         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2500 };
2501 static const unsigned int i2c7_c_mux[] = {
2502         IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2503 };
2504 /* - I2C8 ------------------------------------------------------------------- */
2505 static const unsigned int i2c8_pins[] = {
2506         /* SCL, SDA */
2507         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2508 };
2509 static const unsigned int i2c8_mux[] = {
2510         IIC1_SCL_MARK, IIC1_SDA_MARK,
2511 };
2512 static const unsigned int i2c8_b_pins[] = {
2513         /* SCL, SDA */
2514         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2515 };
2516 static const unsigned int i2c8_b_mux[] = {
2517         IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2518 };
2519 static const unsigned int i2c8_c_pins[] = {
2520         /* SCL, SDA */
2521         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2522 };
2523 static const unsigned int i2c8_c_mux[] = {
2524         IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2525 };
2526 /* - INTC ------------------------------------------------------------------- */
2527 static const unsigned int intc_irq0_pins[] = {
2528         /* IRQ */
2529         RCAR_GP_PIN(7, 10),
2530 };
2531 static const unsigned int intc_irq0_mux[] = {
2532         IRQ0_MARK,
2533 };
2534 static const unsigned int intc_irq1_pins[] = {
2535         /* IRQ */
2536         RCAR_GP_PIN(7, 11),
2537 };
2538 static const unsigned int intc_irq1_mux[] = {
2539         IRQ1_MARK,
2540 };
2541 static const unsigned int intc_irq2_pins[] = {
2542         /* IRQ */
2543         RCAR_GP_PIN(7, 12),
2544 };
2545 static const unsigned int intc_irq2_mux[] = {
2546         IRQ2_MARK,
2547 };
2548 static const unsigned int intc_irq3_pins[] = {
2549         /* IRQ */
2550         RCAR_GP_PIN(7, 13),
2551 };
2552 static const unsigned int intc_irq3_mux[] = {
2553         IRQ3_MARK,
2554 };
2555 /* - MLB+ ------------------------------------------------------------------- */
2556 static const unsigned int mlb_3pin_pins[] = {
2557         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2558 };
2559 static const unsigned int mlb_3pin_mux[] = {
2560         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2561 };
2562 /* - MMCIF ------------------------------------------------------------------ */
2563 static const unsigned int mmc_data1_pins[] = {
2564         /* D[0] */
2565         RCAR_GP_PIN(6, 18),
2566 };
2567 static const unsigned int mmc_data1_mux[] = {
2568         MMC_D0_MARK,
2569 };
2570 static const unsigned int mmc_data4_pins[] = {
2571         /* D[0:3] */
2572         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2573         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2574 };
2575 static const unsigned int mmc_data4_mux[] = {
2576         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2577 };
2578 static const unsigned int mmc_data8_pins[] = {
2579         /* D[0:7] */
2580         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2581         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2582         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2583         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2584 };
2585 static const unsigned int mmc_data8_mux[] = {
2586         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2587         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2588 };
2589 static const unsigned int mmc_data8_b_pins[] = {
2590         /* D[0:7] */
2591         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2592         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2593         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2594         RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2595 };
2596 static const unsigned int mmc_data8_b_mux[] = {
2597         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2598         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2599 };
2600 static const unsigned int mmc_ctrl_pins[] = {
2601         /* CLK, CMD */
2602         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2603 };
2604 static const unsigned int mmc_ctrl_mux[] = {
2605         MMC_CLK_MARK, MMC_CMD_MARK,
2606 };
2607 /* - MSIOF0 ----------------------------------------------------------------- */
2608 static const unsigned int msiof0_clk_pins[] = {
2609         /* SCK */
2610         RCAR_GP_PIN(6, 24),
2611 };
2612 static const unsigned int msiof0_clk_mux[] = {
2613         MSIOF0_SCK_MARK,
2614 };
2615 static const unsigned int msiof0_sync_pins[] = {
2616         /* SYNC */
2617         RCAR_GP_PIN(6, 25),
2618 };
2619 static const unsigned int msiof0_sync_mux[] = {
2620         MSIOF0_SYNC_MARK,
2621 };
2622 static const unsigned int msiof0_ss1_pins[] = {
2623         /* SS1 */
2624         RCAR_GP_PIN(6, 28),
2625 };
2626 static const unsigned int msiof0_ss1_mux[] = {
2627         MSIOF0_SS1_MARK,
2628 };
2629 static const unsigned int msiof0_ss2_pins[] = {
2630         /* SS2 */
2631         RCAR_GP_PIN(6, 29),
2632 };
2633 static const unsigned int msiof0_ss2_mux[] = {
2634         MSIOF0_SS2_MARK,
2635 };
2636 static const unsigned int msiof0_rx_pins[] = {
2637         /* RXD */
2638         RCAR_GP_PIN(6, 27),
2639 };
2640 static const unsigned int msiof0_rx_mux[] = {
2641         MSIOF0_RXD_MARK,
2642 };
2643 static const unsigned int msiof0_tx_pins[] = {
2644         /* TXD */
2645         RCAR_GP_PIN(6, 26),
2646 };
2647 static const unsigned int msiof0_tx_mux[] = {
2648         MSIOF0_TXD_MARK,
2649 };
2650
2651 static const unsigned int msiof0_clk_b_pins[] = {
2652         /* SCK */
2653         RCAR_GP_PIN(0, 16),
2654 };
2655 static const unsigned int msiof0_clk_b_mux[] = {
2656         MSIOF0_SCK_B_MARK,
2657 };
2658 static const unsigned int msiof0_sync_b_pins[] = {
2659         /* SYNC */
2660         RCAR_GP_PIN(0, 17),
2661 };
2662 static const unsigned int msiof0_sync_b_mux[] = {
2663         MSIOF0_SYNC_B_MARK,
2664 };
2665 static const unsigned int msiof0_ss1_b_pins[] = {
2666         /* SS1 */
2667         RCAR_GP_PIN(0, 18),
2668 };
2669 static const unsigned int msiof0_ss1_b_mux[] = {
2670         MSIOF0_SS1_B_MARK,
2671 };
2672 static const unsigned int msiof0_ss2_b_pins[] = {
2673         /* SS2 */
2674         RCAR_GP_PIN(0, 19),
2675 };
2676 static const unsigned int msiof0_ss2_b_mux[] = {
2677         MSIOF0_SS2_B_MARK,
2678 };
2679 static const unsigned int msiof0_rx_b_pins[] = {
2680         /* RXD */
2681         RCAR_GP_PIN(0, 21),
2682 };
2683 static const unsigned int msiof0_rx_b_mux[] = {
2684         MSIOF0_RXD_B_MARK,
2685 };
2686 static const unsigned int msiof0_tx_b_pins[] = {
2687         /* TXD */
2688         RCAR_GP_PIN(0, 20),
2689 };
2690 static const unsigned int msiof0_tx_b_mux[] = {
2691         MSIOF0_TXD_B_MARK,
2692 };
2693
2694 static const unsigned int msiof0_clk_c_pins[] = {
2695         /* SCK */
2696         RCAR_GP_PIN(5, 26),
2697 };
2698 static const unsigned int msiof0_clk_c_mux[] = {
2699         MSIOF0_SCK_C_MARK,
2700 };
2701 static const unsigned int msiof0_sync_c_pins[] = {
2702         /* SYNC */
2703         RCAR_GP_PIN(5, 25),
2704 };
2705 static const unsigned int msiof0_sync_c_mux[] = {
2706         MSIOF0_SYNC_C_MARK,
2707 };
2708 static const unsigned int msiof0_ss1_c_pins[] = {
2709         /* SS1 */
2710         RCAR_GP_PIN(5, 27),
2711 };
2712 static const unsigned int msiof0_ss1_c_mux[] = {
2713         MSIOF0_SS1_C_MARK,
2714 };
2715 static const unsigned int msiof0_ss2_c_pins[] = {
2716         /* SS2 */
2717         RCAR_GP_PIN(5, 28),
2718 };
2719 static const unsigned int msiof0_ss2_c_mux[] = {
2720         MSIOF0_SS2_C_MARK,
2721 };
2722 static const unsigned int msiof0_rx_c_pins[] = {
2723         /* RXD */
2724         RCAR_GP_PIN(5, 29),
2725 };
2726 static const unsigned int msiof0_rx_c_mux[] = {
2727         MSIOF0_RXD_C_MARK,
2728 };
2729 static const unsigned int msiof0_tx_c_pins[] = {
2730         /* TXD */
2731         RCAR_GP_PIN(5, 30),
2732 };
2733 static const unsigned int msiof0_tx_c_mux[] = {
2734         MSIOF0_TXD_C_MARK,
2735 };
2736 /* - MSIOF1 ----------------------------------------------------------------- */
2737 static const unsigned int msiof1_clk_pins[] = {
2738         /* SCK */
2739         RCAR_GP_PIN(0, 22),
2740 };
2741 static const unsigned int msiof1_clk_mux[] = {
2742         MSIOF1_SCK_MARK,
2743 };
2744 static const unsigned int msiof1_sync_pins[] = {
2745         /* SYNC */
2746         RCAR_GP_PIN(0, 23),
2747 };
2748 static const unsigned int msiof1_sync_mux[] = {
2749         MSIOF1_SYNC_MARK,
2750 };
2751 static const unsigned int msiof1_ss1_pins[] = {
2752         /* SS1 */
2753         RCAR_GP_PIN(0, 24),
2754 };
2755 static const unsigned int msiof1_ss1_mux[] = {
2756         MSIOF1_SS1_MARK,
2757 };
2758 static const unsigned int msiof1_ss2_pins[] = {
2759         /* SS2 */
2760         RCAR_GP_PIN(0, 25),
2761 };
2762 static const unsigned int msiof1_ss2_mux[] = {
2763         MSIOF1_SS2_MARK,
2764 };
2765 static const unsigned int msiof1_rx_pins[] = {
2766         /* RXD */
2767         RCAR_GP_PIN(0, 27),
2768 };
2769 static const unsigned int msiof1_rx_mux[] = {
2770         MSIOF1_RXD_MARK,
2771 };
2772 static const unsigned int msiof1_tx_pins[] = {
2773         /* TXD */
2774         RCAR_GP_PIN(0, 26),
2775 };
2776 static const unsigned int msiof1_tx_mux[] = {
2777         MSIOF1_TXD_MARK,
2778 };
2779
2780 static const unsigned int msiof1_clk_b_pins[] = {
2781         /* SCK */
2782         RCAR_GP_PIN(2, 29),
2783 };
2784 static const unsigned int msiof1_clk_b_mux[] = {
2785         MSIOF1_SCK_B_MARK,
2786 };
2787 static const unsigned int msiof1_sync_b_pins[] = {
2788         /* SYNC */
2789         RCAR_GP_PIN(2, 30),
2790 };
2791 static const unsigned int msiof1_sync_b_mux[] = {
2792         MSIOF1_SYNC_B_MARK,
2793 };
2794 static const unsigned int msiof1_ss1_b_pins[] = {
2795         /* SS1 */
2796         RCAR_GP_PIN(2, 31),
2797 };
2798 static const unsigned int msiof1_ss1_b_mux[] = {
2799         MSIOF1_SS1_B_MARK,
2800 };
2801 static const unsigned int msiof1_ss2_b_pins[] = {
2802         /* SS2 */
2803         RCAR_GP_PIN(7, 16),
2804 };
2805 static const unsigned int msiof1_ss2_b_mux[] = {
2806         MSIOF1_SS2_B_MARK,
2807 };
2808 static const unsigned int msiof1_rx_b_pins[] = {
2809         /* RXD */
2810         RCAR_GP_PIN(7, 18),
2811 };
2812 static const unsigned int msiof1_rx_b_mux[] = {
2813         MSIOF1_RXD_B_MARK,
2814 };
2815 static const unsigned int msiof1_tx_b_pins[] = {
2816         /* TXD */
2817         RCAR_GP_PIN(7, 17),
2818 };
2819 static const unsigned int msiof1_tx_b_mux[] = {
2820         MSIOF1_TXD_B_MARK,
2821 };
2822
2823 static const unsigned int msiof1_clk_c_pins[] = {
2824         /* SCK */
2825         RCAR_GP_PIN(2, 15),
2826 };
2827 static const unsigned int msiof1_clk_c_mux[] = {
2828         MSIOF1_SCK_C_MARK,
2829 };
2830 static const unsigned int msiof1_sync_c_pins[] = {
2831         /* SYNC */
2832         RCAR_GP_PIN(2, 16),
2833 };
2834 static const unsigned int msiof1_sync_c_mux[] = {
2835         MSIOF1_SYNC_C_MARK,
2836 };
2837 static const unsigned int msiof1_rx_c_pins[] = {
2838         /* RXD */
2839         RCAR_GP_PIN(2, 18),
2840 };
2841 static const unsigned int msiof1_rx_c_mux[] = {
2842         MSIOF1_RXD_C_MARK,
2843 };
2844 static const unsigned int msiof1_tx_c_pins[] = {
2845         /* TXD */
2846         RCAR_GP_PIN(2, 17),
2847 };
2848 static const unsigned int msiof1_tx_c_mux[] = {
2849         MSIOF1_TXD_C_MARK,
2850 };
2851
2852 static const unsigned int msiof1_clk_d_pins[] = {
2853         /* SCK */
2854         RCAR_GP_PIN(0, 28),
2855 };
2856 static const unsigned int msiof1_clk_d_mux[] = {
2857         MSIOF1_SCK_D_MARK,
2858 };
2859 static const unsigned int msiof1_sync_d_pins[] = {
2860         /* SYNC */
2861         RCAR_GP_PIN(0, 30),
2862 };
2863 static const unsigned int msiof1_sync_d_mux[] = {
2864         MSIOF1_SYNC_D_MARK,
2865 };
2866 static const unsigned int msiof1_ss1_d_pins[] = {
2867         /* SS1 */
2868         RCAR_GP_PIN(0, 29),
2869 };
2870 static const unsigned int msiof1_ss1_d_mux[] = {
2871         MSIOF1_SS1_D_MARK,
2872 };
2873 static const unsigned int msiof1_rx_d_pins[] = {
2874         /* RXD */
2875         RCAR_GP_PIN(0, 27),
2876 };
2877 static const unsigned int msiof1_rx_d_mux[] = {
2878         MSIOF1_RXD_D_MARK,
2879 };
2880 static const unsigned int msiof1_tx_d_pins[] = {
2881         /* TXD */
2882         RCAR_GP_PIN(0, 26),
2883 };
2884 static const unsigned int msiof1_tx_d_mux[] = {
2885         MSIOF1_TXD_D_MARK,
2886 };
2887
2888 static const unsigned int msiof1_clk_e_pins[] = {
2889         /* SCK */
2890         RCAR_GP_PIN(5, 18),
2891 };
2892 static const unsigned int msiof1_clk_e_mux[] = {
2893         MSIOF1_SCK_E_MARK,
2894 };
2895 static const unsigned int msiof1_sync_e_pins[] = {
2896         /* SYNC */
2897         RCAR_GP_PIN(5, 19),
2898 };
2899 static const unsigned int msiof1_sync_e_mux[] = {
2900         MSIOF1_SYNC_E_MARK,
2901 };
2902 static const unsigned int msiof1_rx_e_pins[] = {
2903         /* RXD */
2904         RCAR_GP_PIN(5, 17),
2905 };
2906 static const unsigned int msiof1_rx_e_mux[] = {
2907         MSIOF1_RXD_E_MARK,
2908 };
2909 static const unsigned int msiof1_tx_e_pins[] = {
2910         /* TXD */
2911         RCAR_GP_PIN(5, 20),
2912 };
2913 static const unsigned int msiof1_tx_e_mux[] = {
2914         MSIOF1_TXD_E_MARK,
2915 };
2916 /* - MSIOF2 ----------------------------------------------------------------- */
2917 static const unsigned int msiof2_clk_pins[] = {
2918         /* SCK */
2919         RCAR_GP_PIN(1, 13),
2920 };
2921 static const unsigned int msiof2_clk_mux[] = {
2922         MSIOF2_SCK_MARK,
2923 };
2924 static const unsigned int msiof2_sync_pins[] = {
2925         /* SYNC */
2926         RCAR_GP_PIN(1, 14),
2927 };
2928 static const unsigned int msiof2_sync_mux[] = {
2929         MSIOF2_SYNC_MARK,
2930 };
2931 static const unsigned int msiof2_ss1_pins[] = {
2932         /* SS1 */
2933         RCAR_GP_PIN(1, 17),
2934 };
2935 static const unsigned int msiof2_ss1_mux[] = {
2936         MSIOF2_SS1_MARK,
2937 };
2938 static const unsigned int msiof2_ss2_pins[] = {
2939         /* SS2 */
2940         RCAR_GP_PIN(1, 18),
2941 };
2942 static const unsigned int msiof2_ss2_mux[] = {
2943         MSIOF2_SS2_MARK,
2944 };
2945 static const unsigned int msiof2_rx_pins[] = {
2946         /* RXD */
2947         RCAR_GP_PIN(1, 16),
2948 };
2949 static const unsigned int msiof2_rx_mux[] = {
2950         MSIOF2_RXD_MARK,
2951 };
2952 static const unsigned int msiof2_tx_pins[] = {
2953         /* TXD */
2954         RCAR_GP_PIN(1, 15),
2955 };
2956 static const unsigned int msiof2_tx_mux[] = {
2957         MSIOF2_TXD_MARK,
2958 };
2959
2960 static const unsigned int msiof2_clk_b_pins[] = {
2961         /* SCK */
2962         RCAR_GP_PIN(3, 0),
2963 };
2964 static const unsigned int msiof2_clk_b_mux[] = {
2965         MSIOF2_SCK_B_MARK,
2966 };
2967 static const unsigned int msiof2_sync_b_pins[] = {
2968         /* SYNC */
2969         RCAR_GP_PIN(3, 1),
2970 };
2971 static const unsigned int msiof2_sync_b_mux[] = {
2972         MSIOF2_SYNC_B_MARK,
2973 };
2974 static const unsigned int msiof2_ss1_b_pins[] = {
2975         /* SS1 */
2976         RCAR_GP_PIN(3, 8),
2977 };
2978 static const unsigned int msiof2_ss1_b_mux[] = {
2979         MSIOF2_SS1_B_MARK,
2980 };
2981 static const unsigned int msiof2_ss2_b_pins[] = {
2982         /* SS2 */
2983         RCAR_GP_PIN(3, 9),
2984 };
2985 static const unsigned int msiof2_ss2_b_mux[] = {
2986         MSIOF2_SS2_B_MARK,
2987 };
2988 static const unsigned int msiof2_rx_b_pins[] = {
2989         /* RXD */
2990         RCAR_GP_PIN(3, 17),
2991 };
2992 static const unsigned int msiof2_rx_b_mux[] = {
2993         MSIOF2_RXD_B_MARK,
2994 };
2995 static const unsigned int msiof2_tx_b_pins[] = {
2996         /* TXD */
2997         RCAR_GP_PIN(3, 16),
2998 };
2999 static const unsigned int msiof2_tx_b_mux[] = {
3000         MSIOF2_TXD_B_MARK,
3001 };
3002
3003 static const unsigned int msiof2_clk_c_pins[] = {
3004         /* SCK */
3005         RCAR_GP_PIN(2, 2),
3006 };
3007 static const unsigned int msiof2_clk_c_mux[] = {
3008         MSIOF2_SCK_C_MARK,
3009 };
3010 static const unsigned int msiof2_sync_c_pins[] = {
3011         /* SYNC */
3012         RCAR_GP_PIN(2, 3),
3013 };
3014 static const unsigned int msiof2_sync_c_mux[] = {
3015         MSIOF2_SYNC_C_MARK,
3016 };
3017 static const unsigned int msiof2_rx_c_pins[] = {
3018         /* RXD */
3019         RCAR_GP_PIN(2, 5),
3020 };
3021 static const unsigned int msiof2_rx_c_mux[] = {
3022         MSIOF2_RXD_C_MARK,
3023 };
3024 static const unsigned int msiof2_tx_c_pins[] = {
3025         /* TXD */
3026         RCAR_GP_PIN(2, 4),
3027 };
3028 static const unsigned int msiof2_tx_c_mux[] = {
3029         MSIOF2_TXD_C_MARK,
3030 };
3031
3032 static const unsigned int msiof2_clk_d_pins[] = {
3033         /* SCK */
3034         RCAR_GP_PIN(2, 14),
3035 };
3036 static const unsigned int msiof2_clk_d_mux[] = {
3037         MSIOF2_SCK_D_MARK,
3038 };
3039 static const unsigned int msiof2_sync_d_pins[] = {
3040         /* SYNC */
3041         RCAR_GP_PIN(2, 15),
3042 };
3043 static const unsigned int msiof2_sync_d_mux[] = {
3044         MSIOF2_SYNC_D_MARK,
3045 };
3046 static const unsigned int msiof2_ss1_d_pins[] = {
3047         /* SS1 */
3048         RCAR_GP_PIN(2, 17),
3049 };
3050 static const unsigned int msiof2_ss1_d_mux[] = {
3051         MSIOF2_SS1_D_MARK,
3052 };
3053 static const unsigned int msiof2_ss2_d_pins[] = {
3054         /* SS2 */
3055         RCAR_GP_PIN(2, 19),
3056 };
3057 static const unsigned int msiof2_ss2_d_mux[] = {
3058         MSIOF2_SS2_D_MARK,
3059 };
3060 static const unsigned int msiof2_rx_d_pins[] = {
3061         /* RXD */
3062         RCAR_GP_PIN(2, 18),
3063 };
3064 static const unsigned int msiof2_rx_d_mux[] = {
3065         MSIOF2_RXD_D_MARK,
3066 };
3067 static const unsigned int msiof2_tx_d_pins[] = {
3068         /* TXD */
3069         RCAR_GP_PIN(2, 16),
3070 };
3071 static const unsigned int msiof2_tx_d_mux[] = {
3072         MSIOF2_TXD_D_MARK,
3073 };
3074
3075 static const unsigned int msiof2_clk_e_pins[] = {
3076         /* SCK */
3077         RCAR_GP_PIN(7, 15),
3078 };
3079 static const unsigned int msiof2_clk_e_mux[] = {
3080         MSIOF2_SCK_E_MARK,
3081 };
3082 static const unsigned int msiof2_sync_e_pins[] = {
3083         /* SYNC */
3084         RCAR_GP_PIN(7, 16),
3085 };
3086 static const unsigned int msiof2_sync_e_mux[] = {
3087         MSIOF2_SYNC_E_MARK,
3088 };
3089 static const unsigned int msiof2_rx_e_pins[] = {
3090         /* RXD */
3091         RCAR_GP_PIN(7, 14),
3092 };
3093 static const unsigned int msiof2_rx_e_mux[] = {
3094         MSIOF2_RXD_E_MARK,
3095 };
3096 static const unsigned int msiof2_tx_e_pins[] = {
3097         /* TXD */
3098         RCAR_GP_PIN(7, 13),
3099 };
3100 static const unsigned int msiof2_tx_e_mux[] = {
3101         MSIOF2_TXD_E_MARK,
3102 };
3103 /* - PWM -------------------------------------------------------------------- */
3104 static const unsigned int pwm0_pins[] = {
3105         RCAR_GP_PIN(6, 14),
3106 };
3107 static const unsigned int pwm0_mux[] = {
3108         PWM0_MARK,
3109 };
3110 static const unsigned int pwm0_b_pins[] = {
3111         RCAR_GP_PIN(5, 30),
3112 };
3113 static const unsigned int pwm0_b_mux[] = {
3114         PWM0_B_MARK,
3115 };
3116 static const unsigned int pwm1_pins[] = {
3117         RCAR_GP_PIN(1, 17),
3118 };
3119 static const unsigned int pwm1_mux[] = {
3120         PWM1_MARK,
3121 };
3122 static const unsigned int pwm1_b_pins[] = {
3123         RCAR_GP_PIN(6, 15),
3124 };
3125 static const unsigned int pwm1_b_mux[] = {
3126         PWM1_B_MARK,
3127 };
3128 static const unsigned int pwm2_pins[] = {
3129         RCAR_GP_PIN(1, 18),
3130 };
3131 static const unsigned int pwm2_mux[] = {
3132         PWM2_MARK,
3133 };
3134 static const unsigned int pwm2_b_pins[] = {
3135         RCAR_GP_PIN(0, 16),
3136 };
3137 static const unsigned int pwm2_b_mux[] = {
3138         PWM2_B_MARK,
3139 };
3140 static const unsigned int pwm3_pins[] = {
3141         RCAR_GP_PIN(1, 24),
3142 };
3143 static const unsigned int pwm3_mux[] = {
3144         PWM3_MARK,
3145 };
3146 static const unsigned int pwm4_pins[] = {
3147         RCAR_GP_PIN(3, 26),
3148 };
3149 static const unsigned int pwm4_mux[] = {
3150         PWM4_MARK,
3151 };
3152 static const unsigned int pwm4_b_pins[] = {
3153         RCAR_GP_PIN(3, 31),
3154 };
3155 static const unsigned int pwm4_b_mux[] = {
3156         PWM4_B_MARK,
3157 };
3158 static const unsigned int pwm5_pins[] = {
3159         RCAR_GP_PIN(7, 21),
3160 };
3161 static const unsigned int pwm5_mux[] = {
3162         PWM5_MARK,
3163 };
3164 static const unsigned int pwm5_b_pins[] = {
3165         RCAR_GP_PIN(7, 20),
3166 };
3167 static const unsigned int pwm5_b_mux[] = {
3168         PWM5_B_MARK,
3169 };
3170 static const unsigned int pwm6_pins[] = {
3171         RCAR_GP_PIN(7, 22),
3172 };
3173 static const unsigned int pwm6_mux[] = {
3174         PWM6_MARK,
3175 };
3176 /* - QSPI ------------------------------------------------------------------- */
3177 static const unsigned int qspi_ctrl_pins[] = {
3178         /* SPCLK, SSL */
3179         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3180 };
3181 static const unsigned int qspi_ctrl_mux[] = {
3182         SPCLK_MARK, SSL_MARK,
3183 };
3184 static const unsigned int qspi_data2_pins[] = {
3185         /* MOSI_IO0, MISO_IO1 */
3186         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3187 };
3188 static const unsigned int qspi_data2_mux[] = {
3189         MOSI_IO0_MARK, MISO_IO1_MARK,
3190 };
3191 static const unsigned int qspi_data4_pins[] = {
3192         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3193         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3194         RCAR_GP_PIN(1, 8),
3195 };
3196 static const unsigned int qspi_data4_mux[] = {
3197         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3198 };
3199
3200 static const unsigned int qspi_ctrl_b_pins[] = {
3201         /* SPCLK, SSL */
3202         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3203 };
3204 static const unsigned int qspi_ctrl_b_mux[] = {
3205         SPCLK_B_MARK, SSL_B_MARK,
3206 };
3207 static const unsigned int qspi_data2_b_pins[] = {
3208         /* MOSI_IO0, MISO_IO1 */
3209         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3210 };
3211 static const unsigned int qspi_data2_b_mux[] = {
3212         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3213 };
3214 static const unsigned int qspi_data4_b_pins[] = {
3215         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3216         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3217         RCAR_GP_PIN(6, 4),
3218 };
3219 static const unsigned int qspi_data4_b_mux[] = {
3220         MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
3221 };
3222 /* - SCIF0 ------------------------------------------------------------------ */
3223 static const unsigned int scif0_data_pins[] = {
3224         /* RX, TX */
3225         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3226 };
3227 static const unsigned int scif0_data_mux[] = {
3228         RX0_MARK, TX0_MARK,
3229 };
3230 static const unsigned int scif0_data_b_pins[] = {
3231         /* RX, TX */
3232         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3233 };
3234 static const unsigned int scif0_data_b_mux[] = {
3235         RX0_B_MARK, TX0_B_MARK,
3236 };
3237 static const unsigned int scif0_data_c_pins[] = {
3238         /* RX, TX */
3239         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3240 };
3241 static const unsigned int scif0_data_c_mux[] = {
3242         RX0_C_MARK, TX0_C_MARK,
3243 };
3244 static const unsigned int scif0_data_d_pins[] = {
3245         /* RX, TX */
3246         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3247 };
3248 static const unsigned int scif0_data_d_mux[] = {
3249         RX0_D_MARK, TX0_D_MARK,
3250 };
3251 static const unsigned int scif0_data_e_pins[] = {
3252         /* RX, TX */
3253         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3254 };
3255 static const unsigned int scif0_data_e_mux[] = {
3256         RX0_E_MARK, TX0_E_MARK,
3257 };
3258 /* - SCIF1 ------------------------------------------------------------------ */
3259 static const unsigned int scif1_data_pins[] = {
3260         /* RX, TX */
3261         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3262 };
3263 static const unsigned int scif1_data_mux[] = {
3264         RX1_MARK, TX1_MARK,
3265 };
3266 static const unsigned int scif1_data_b_pins[] = {
3267         /* RX, TX */
3268         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3269 };
3270 static const unsigned int scif1_data_b_mux[] = {
3271         RX1_B_MARK, TX1_B_MARK,
3272 };
3273 static const unsigned int scif1_clk_b_pins[] = {
3274         /* SCK */
3275         RCAR_GP_PIN(3, 10),
3276 };
3277 static const unsigned int scif1_clk_b_mux[] = {
3278         SCIF1_SCK_B_MARK,
3279 };
3280 static const unsigned int scif1_data_c_pins[] = {
3281         /* RX, TX */
3282         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3283 };
3284 static const unsigned int scif1_data_c_mux[] = {
3285         RX1_C_MARK, TX1_C_MARK,
3286 };
3287 static const unsigned int scif1_data_d_pins[] = {
3288         /* RX, TX */
3289         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3290 };
3291 static const unsigned int scif1_data_d_mux[] = {
3292         RX1_D_MARK, TX1_D_MARK,
3293 };
3294 /* - SCIF2 ------------------------------------------------------------------ */
3295 static const unsigned int scif2_data_pins[] = {
3296         /* RX, TX */
3297         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3298 };
3299 static const unsigned int scif2_data_mux[] = {
3300         RX2_MARK, TX2_MARK,
3301 };
3302 static const unsigned int scif2_data_b_pins[] = {
3303         /* RX, TX */
3304         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3305 };
3306 static const unsigned int scif2_data_b_mux[] = {
3307         RX2_B_MARK, TX2_B_MARK,
3308 };
3309 static const unsigned int scif2_clk_b_pins[] = {
3310         /* SCK */
3311         RCAR_GP_PIN(3, 18),
3312 };
3313 static const unsigned int scif2_clk_b_mux[] = {
3314         SCIF2_SCK_B_MARK,
3315 };
3316 static const unsigned int scif2_data_c_pins[] = {
3317         /* RX, TX */
3318         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3319 };
3320 static const unsigned int scif2_data_c_mux[] = {
3321         RX2_C_MARK, TX2_C_MARK,
3322 };
3323 static const unsigned int scif2_data_e_pins[] = {
3324         /* RX, TX */
3325         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3326 };
3327 static const unsigned int scif2_data_e_mux[] = {
3328         RX2_E_MARK, TX2_E_MARK,
3329 };
3330 /* - SCIF3 ------------------------------------------------------------------ */
3331 static const unsigned int scif3_data_pins[] = {
3332         /* RX, TX */
3333         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3334 };
3335 static const unsigned int scif3_data_mux[] = {
3336         RX3_MARK, TX3_MARK,
3337 };
3338 static const unsigned int scif3_clk_pins[] = {
3339         /* SCK */
3340         RCAR_GP_PIN(3, 23),
3341 };
3342 static const unsigned int scif3_clk_mux[] = {
3343         SCIF3_SCK_MARK,
3344 };
3345 static const unsigned int scif3_data_b_pins[] = {
3346         /* RX, TX */
3347         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3348 };
3349 static const unsigned int scif3_data_b_mux[] = {
3350         RX3_B_MARK, TX3_B_MARK,
3351 };
3352 static const unsigned int scif3_clk_b_pins[] = {
3353         /* SCK */
3354         RCAR_GP_PIN(4, 8),
3355 };
3356 static const unsigned int scif3_clk_b_mux[] = {
3357         SCIF3_SCK_B_MARK,
3358 };
3359 static const unsigned int scif3_data_c_pins[] = {
3360         /* RX, TX */
3361         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3362 };
3363 static const unsigned int scif3_data_c_mux[] = {
3364         RX3_C_MARK, TX3_C_MARK,
3365 };
3366 static const unsigned int scif3_data_d_pins[] = {
3367         /* RX, TX */
3368         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3369 };
3370 static const unsigned int scif3_data_d_mux[] = {
3371         RX3_D_MARK, TX3_D_MARK,
3372 };
3373 /* - SCIF4 ------------------------------------------------------------------ */
3374 static const unsigned int scif4_data_pins[] = {
3375         /* RX, TX */
3376         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3377 };
3378 static const unsigned int scif4_data_mux[] = {
3379         RX4_MARK, TX4_MARK,
3380 };
3381 static const unsigned int scif4_data_b_pins[] = {
3382         /* RX, TX */
3383         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3384 };
3385 static const unsigned int scif4_data_b_mux[] = {
3386         RX4_B_MARK, TX4_B_MARK,
3387 };
3388 static const unsigned int scif4_data_c_pins[] = {
3389         /* RX, TX */
3390         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3391 };
3392 static const unsigned int scif4_data_c_mux[] = {
3393         RX4_C_MARK, TX4_C_MARK,
3394 };
3395 /* - SCIF5 ------------------------------------------------------------------ */
3396 static const unsigned int scif5_data_pins[] = {
3397         /* RX, TX */
3398         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3399 };
3400 static const unsigned int scif5_data_mux[] = {
3401         RX5_MARK, TX5_MARK,
3402 };
3403 static const unsigned int scif5_data_b_pins[] = {
3404         /* RX, TX */
3405         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3406 };
3407 static const unsigned int scif5_data_b_mux[] = {
3408         RX5_B_MARK, TX5_B_MARK,
3409 };
3410 /* - SCIFA0 ----------------------------------------------------------------- */
3411 static const unsigned int scifa0_data_pins[] = {
3412         /* RXD, TXD */
3413         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3414 };
3415 static const unsigned int scifa0_data_mux[] = {
3416         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3417 };
3418 static const unsigned int scifa0_data_b_pins[] = {
3419         /* RXD, TXD */
3420         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3421 };
3422 static const unsigned int scifa0_data_b_mux[] = {
3423         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3424 };
3425 /* - SCIFA1 ----------------------------------------------------------------- */
3426 static const unsigned int scifa1_data_pins[] = {
3427         /* RXD, TXD */
3428         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3429 };
3430 static const unsigned int scifa1_data_mux[] = {
3431         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3432 };
3433 static const unsigned int scifa1_clk_pins[] = {
3434         /* SCK */
3435         RCAR_GP_PIN(3, 10),
3436 };
3437 static const unsigned int scifa1_clk_mux[] = {
3438         SCIFA1_SCK_MARK,
3439 };
3440 static const unsigned int scifa1_data_b_pins[] = {
3441         /* RXD, TXD */
3442         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3443 };
3444 static const unsigned int scifa1_data_b_mux[] = {
3445         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3446 };
3447 static const unsigned int scifa1_clk_b_pins[] = {
3448         /* SCK */
3449         RCAR_GP_PIN(1, 0),
3450 };
3451 static const unsigned int scifa1_clk_b_mux[] = {
3452         SCIFA1_SCK_B_MARK,
3453 };
3454 static const unsigned int scifa1_data_c_pins[] = {
3455         /* RXD, TXD */
3456         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3457 };
3458 static const unsigned int scifa1_data_c_mux[] = {
3459         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3460 };
3461 /* - SCIFA2 ----------------------------------------------------------------- */
3462 static const unsigned int scifa2_data_pins[] = {
3463         /* RXD, TXD */
3464         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3465 };
3466 static const unsigned int scifa2_data_mux[] = {
3467         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3468 };
3469 static const unsigned int scifa2_clk_pins[] = {
3470         /* SCK */
3471         RCAR_GP_PIN(3, 18),
3472 };
3473 static const unsigned int scifa2_clk_mux[] = {
3474         SCIFA2_SCK_MARK,
3475 };
3476 static const unsigned int scifa2_data_b_pins[] = {
3477         /* RXD, TXD */
3478         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3479 };
3480 static const unsigned int scifa2_data_b_mux[] = {
3481         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3482 };
3483 /* - SCIFA3 ----------------------------------------------------------------- */
3484 static const unsigned int scifa3_data_pins[] = {
3485         /* RXD, TXD */
3486         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3487 };
3488 static const unsigned int scifa3_data_mux[] = {
3489         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3490 };
3491 static const unsigned int scifa3_clk_pins[] = {
3492         /* SCK */
3493         RCAR_GP_PIN(3, 23),
3494 };
3495 static const unsigned int scifa3_clk_mux[] = {
3496         SCIFA3_SCK_MARK,
3497 };
3498 static const unsigned int scifa3_data_b_pins[] = {
3499         /* RXD, TXD */
3500         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3501 };
3502 static const unsigned int scifa3_data_b_mux[] = {
3503         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3504 };
3505 static const unsigned int scifa3_clk_b_pins[] = {
3506         /* SCK */
3507         RCAR_GP_PIN(4, 8),
3508 };
3509 static const unsigned int scifa3_clk_b_mux[] = {
3510         SCIFA3_SCK_B_MARK,
3511 };
3512 static const unsigned int scifa3_data_c_pins[] = {
3513         /* RXD, TXD */
3514         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3515 };
3516 static const unsigned int scifa3_data_c_mux[] = {
3517         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3518 };
3519 static const unsigned int scifa3_clk_c_pins[] = {
3520         /* SCK */
3521         RCAR_GP_PIN(7, 22),
3522 };
3523 static const unsigned int scifa3_clk_c_mux[] = {
3524         SCIFA3_SCK_C_MARK,
3525 };
3526 /* - SCIFA4 ----------------------------------------------------------------- */
3527 static const unsigned int scifa4_data_pins[] = {
3528         /* RXD, TXD */
3529         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3530 };
3531 static const unsigned int scifa4_data_mux[] = {
3532         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3533 };
3534 static const unsigned int scifa4_data_b_pins[] = {
3535         /* RXD, TXD */
3536         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3537 };
3538 static const unsigned int scifa4_data_b_mux[] = {
3539         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3540 };
3541 static const unsigned int scifa4_data_c_pins[] = {
3542         /* RXD, TXD */
3543         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3544 };
3545 static const unsigned int scifa4_data_c_mux[] = {
3546         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3547 };
3548 /* - SCIFA5 ----------------------------------------------------------------- */
3549 static const unsigned int scifa5_data_pins[] = {
3550         /* RXD, TXD */
3551         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3552 };
3553 static const unsigned int scifa5_data_mux[] = {
3554         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3555 };
3556 static const unsigned int scifa5_data_b_pins[] = {
3557         /* RXD, TXD */
3558         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3559 };
3560 static const unsigned int scifa5_data_b_mux[] = {
3561         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3562 };
3563 static const unsigned int scifa5_data_c_pins[] = {
3564         /* RXD, TXD */
3565         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3566 };
3567 static const unsigned int scifa5_data_c_mux[] = {
3568         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3569 };
3570 /* - SCIFB0 ----------------------------------------------------------------- */
3571 static const unsigned int scifb0_data_pins[] = {
3572         /* RXD, TXD */
3573         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3574 };
3575 static const unsigned int scifb0_data_mux[] = {
3576         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3577 };
3578 static const unsigned int scifb0_clk_pins[] = {
3579         /* SCK */
3580         RCAR_GP_PIN(7, 2),
3581 };
3582 static const unsigned int scifb0_clk_mux[] = {
3583         SCIFB0_SCK_MARK,
3584 };
3585 static const unsigned int scifb0_ctrl_pins[] = {
3586         /* RTS, CTS */
3587         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3588 };
3589 static const unsigned int scifb0_ctrl_mux[] = {
3590         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3591 };
3592 static const unsigned int scifb0_data_b_pins[] = {
3593         /* RXD, TXD */
3594         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3595 };
3596 static const unsigned int scifb0_data_b_mux[] = {
3597         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3598 };
3599 static const unsigned int scifb0_clk_b_pins[] = {
3600         /* SCK */
3601         RCAR_GP_PIN(5, 31),
3602 };
3603 static const unsigned int scifb0_clk_b_mux[] = {
3604         SCIFB0_SCK_B_MARK,
3605 };
3606 static const unsigned int scifb0_ctrl_b_pins[] = {
3607         /* RTS, CTS */
3608         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3609 };
3610 static const unsigned int scifb0_ctrl_b_mux[] = {
3611         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3612 };
3613 static const unsigned int scifb0_data_c_pins[] = {
3614         /* RXD, TXD */
3615         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3616 };
3617 static const unsigned int scifb0_data_c_mux[] = {
3618         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3619 };
3620 static const unsigned int scifb0_clk_c_pins[] = {
3621         /* SCK */
3622         RCAR_GP_PIN(2, 30),
3623 };
3624 static const unsigned int scifb0_clk_c_mux[] = {
3625         SCIFB0_SCK_C_MARK,
3626 };
3627 static const unsigned int scifb0_data_d_pins[] = {
3628         /* RXD, TXD */
3629         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3630 };
3631 static const unsigned int scifb0_data_d_mux[] = {
3632         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3633 };
3634 static const unsigned int scifb0_clk_d_pins[] = {
3635         /* SCK */
3636         RCAR_GP_PIN(4, 17),
3637 };
3638 static const unsigned int scifb0_clk_d_mux[] = {
3639         SCIFB0_SCK_D_MARK,
3640 };
3641 /* - SCIFB1 ----------------------------------------------------------------- */
3642 static const unsigned int scifb1_data_pins[] = {
3643         /* RXD, TXD */
3644         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3645 };
3646 static const unsigned int scifb1_data_mux[] = {
3647         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3648 };
3649 static const unsigned int scifb1_clk_pins[] = {
3650         /* SCK */
3651         RCAR_GP_PIN(7, 7),
3652 };
3653 static const unsigned int scifb1_clk_mux[] = {
3654         SCIFB1_SCK_MARK,
3655 };
3656 static const unsigned int scifb1_ctrl_pins[] = {
3657         /* RTS, CTS */
3658         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3659 };
3660 static const unsigned int scifb1_ctrl_mux[] = {
3661         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3662 };
3663 static const unsigned int scifb1_data_b_pins[] = {
3664         /* RXD, TXD */
3665         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3666 };
3667 static const unsigned int scifb1_data_b_mux[] = {
3668         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3669 };
3670 static const unsigned int scifb1_clk_b_pins[] = {
3671         /* SCK */
3672         RCAR_GP_PIN(1, 3),
3673 };
3674 static const unsigned int scifb1_clk_b_mux[] = {
3675         SCIFB1_SCK_B_MARK,
3676 };
3677 static const unsigned int scifb1_data_c_pins[] = {
3678         /* RXD, TXD */
3679         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3680 };
3681 static const unsigned int scifb1_data_c_mux[] = {
3682         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3683 };
3684 static const unsigned int scifb1_clk_c_pins[] = {
3685         /* SCK */
3686         RCAR_GP_PIN(7, 11),
3687 };
3688 static const unsigned int scifb1_clk_c_mux[] = {
3689         SCIFB1_SCK_C_MARK,
3690 };
3691 static const unsigned int scifb1_data_d_pins[] = {
3692         /* RXD, TXD */
3693         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3694 };
3695 static const unsigned int scifb1_data_d_mux[] = {
3696         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3697 };
3698 /* - SCIFB2 ----------------------------------------------------------------- */
3699 static const unsigned int scifb2_data_pins[] = {
3700         /* RXD, TXD */
3701         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3702 };
3703 static const unsigned int scifb2_data_mux[] = {
3704         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3705 };
3706 static const unsigned int scifb2_clk_pins[] = {
3707         /* SCK */
3708         RCAR_GP_PIN(4, 15),
3709 };
3710 static const unsigned int scifb2_clk_mux[] = {
3711         SCIFB2_SCK_MARK,
3712 };
3713 static const unsigned int scifb2_ctrl_pins[] = {
3714         /* RTS, CTS */
3715         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3716 };
3717 static const unsigned int scifb2_ctrl_mux[] = {
3718         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3719 };
3720 static const unsigned int scifb2_data_b_pins[] = {
3721         /* RXD, TXD */
3722         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3723 };
3724 static const unsigned int scifb2_data_b_mux[] = {
3725         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3726 };
3727 static const unsigned int scifb2_clk_b_pins[] = {
3728         /* SCK */
3729         RCAR_GP_PIN(5, 31),
3730 };
3731 static const unsigned int scifb2_clk_b_mux[] = {
3732         SCIFB2_SCK_B_MARK,
3733 };
3734 static const unsigned int scifb2_ctrl_b_pins[] = {
3735         /* RTS, CTS */
3736         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3737 };
3738 static const unsigned int scifb2_ctrl_b_mux[] = {
3739         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3740 };
3741 static const unsigned int scifb2_data_c_pins[] = {
3742         /* RXD, TXD */
3743         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3744 };
3745 static const unsigned int scifb2_data_c_mux[] = {
3746         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3747 };
3748 static const unsigned int scifb2_clk_c_pins[] = {
3749         /* SCK */
3750         RCAR_GP_PIN(5, 27),
3751 };
3752 static const unsigned int scifb2_clk_c_mux[] = {
3753         SCIFB2_SCK_C_MARK,
3754 };
3755 static const unsigned int scifb2_data_d_pins[] = {
3756         /* RXD, TXD */
3757         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3758 };
3759 static const unsigned int scifb2_data_d_mux[] = {
3760         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3761 };
3762
3763 /* - SCIF Clock ------------------------------------------------------------- */
3764 static const unsigned int scif_clk_pins[] = {
3765         /* SCIF_CLK */
3766         RCAR_GP_PIN(2, 29),
3767 };
3768 static const unsigned int scif_clk_mux[] = {
3769         SCIF_CLK_MARK,
3770 };
3771 static const unsigned int scif_clk_b_pins[] = {
3772         /* SCIF_CLK */
3773         RCAR_GP_PIN(7, 19),
3774 };
3775 static const unsigned int scif_clk_b_mux[] = {
3776         SCIF_CLK_B_MARK,
3777 };
3778
3779 /* - SDHI0 ------------------------------------------------------------------ */
3780 static const unsigned int sdhi0_data1_pins[] = {
3781         /* D0 */
3782         RCAR_GP_PIN(6, 2),
3783 };
3784 static const unsigned int sdhi0_data1_mux[] = {
3785         SD0_DATA0_MARK,
3786 };
3787 static const unsigned int sdhi0_data4_pins[] = {
3788         /* D[0:3] */
3789         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3790         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3791 };
3792 static const unsigned int sdhi0_data4_mux[] = {
3793         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3794 };
3795 static const unsigned int sdhi0_ctrl_pins[] = {
3796         /* CLK, CMD */
3797         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3798 };
3799 static const unsigned int sdhi0_ctrl_mux[] = {
3800         SD0_CLK_MARK, SD0_CMD_MARK,
3801 };
3802 static const unsigned int sdhi0_cd_pins[] = {
3803         /* CD */
3804         RCAR_GP_PIN(6, 6),
3805 };
3806 static const unsigned int sdhi0_cd_mux[] = {
3807         SD0_CD_MARK,
3808 };
3809 static const unsigned int sdhi0_wp_pins[] = {
3810         /* WP */
3811         RCAR_GP_PIN(6, 7),
3812 };
3813 static const unsigned int sdhi0_wp_mux[] = {
3814         SD0_WP_MARK,
3815 };
3816 /* - SDHI1 ------------------------------------------------------------------ */
3817 static const unsigned int sdhi1_data1_pins[] = {
3818         /* D0 */
3819         RCAR_GP_PIN(6, 10),
3820 };
3821 static const unsigned int sdhi1_data1_mux[] = {
3822         SD1_DATA0_MARK,
3823 };
3824 static const unsigned int sdhi1_data4_pins[] = {
3825         /* D[0:3] */
3826         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3827         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3828 };
3829 static const unsigned int sdhi1_data4_mux[] = {
3830         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3831 };
3832 static const unsigned int sdhi1_ctrl_pins[] = {
3833         /* CLK, CMD */
3834         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3835 };
3836 static const unsigned int sdhi1_ctrl_mux[] = {
3837         SD1_CLK_MARK, SD1_CMD_MARK,
3838 };
3839 static const unsigned int sdhi1_cd_pins[] = {
3840         /* CD */
3841         RCAR_GP_PIN(6, 14),
3842 };
3843 static const unsigned int sdhi1_cd_mux[] = {
3844         SD1_CD_MARK,
3845 };
3846 static const unsigned int sdhi1_wp_pins[] = {
3847         /* WP */
3848         RCAR_GP_PIN(6, 15),
3849 };
3850 static const unsigned int sdhi1_wp_mux[] = {
3851         SD1_WP_MARK,
3852 };
3853 /* - SDHI2 ------------------------------------------------------------------ */
3854 static const unsigned int sdhi2_data1_pins[] = {
3855         /* D0 */
3856         RCAR_GP_PIN(6, 18),
3857 };
3858 static const unsigned int sdhi2_data1_mux[] = {
3859         SD2_DATA0_MARK,
3860 };
3861 static const unsigned int sdhi2_data4_pins[] = {
3862         /* D[0:3] */
3863         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3864         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3865 };
3866 static const unsigned int sdhi2_data4_mux[] = {
3867         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3868 };
3869 static const unsigned int sdhi2_ctrl_pins[] = {
3870         /* CLK, CMD */
3871         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3872 };
3873 static const unsigned int sdhi2_ctrl_mux[] = {
3874         SD2_CLK_MARK, SD2_CMD_MARK,
3875 };
3876 static const unsigned int sdhi2_cd_pins[] = {
3877         /* CD */
3878         RCAR_GP_PIN(6, 22),
3879 };
3880 static const unsigned int sdhi2_cd_mux[] = {
3881         SD2_CD_MARK,
3882 };
3883 static const unsigned int sdhi2_wp_pins[] = {
3884         /* WP */
3885         RCAR_GP_PIN(6, 23),
3886 };
3887 static const unsigned int sdhi2_wp_mux[] = {
3888         SD2_WP_MARK,
3889 };
3890
3891 /* - SSI -------------------------------------------------------------------- */
3892 static const unsigned int ssi0_data_pins[] = {
3893         /* SDATA */
3894         RCAR_GP_PIN(2, 2),
3895 };
3896
3897 static const unsigned int ssi0_data_mux[] = {
3898         SSI_SDATA0_MARK,
3899 };
3900
3901 static const unsigned int ssi0_data_b_pins[] = {
3902         /* SDATA */
3903         RCAR_GP_PIN(3, 4),
3904 };
3905
3906 static const unsigned int ssi0_data_b_mux[] = {
3907         SSI_SDATA0_B_MARK,
3908 };
3909
3910 static const unsigned int ssi0129_ctrl_pins[] = {
3911         /* SCK, WS */
3912         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3913 };
3914
3915 static const unsigned int ssi0129_ctrl_mux[] = {
3916         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3917 };
3918
3919 static const unsigned int ssi0129_ctrl_b_pins[] = {
3920         /* SCK, WS */
3921         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3922 };
3923
3924 static const unsigned int ssi0129_ctrl_b_mux[] = {
3925         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3926 };
3927
3928 static const unsigned int ssi1_data_pins[] = {
3929         /* SDATA */
3930         RCAR_GP_PIN(2, 5),
3931 };
3932
3933 static const unsigned int ssi1_data_mux[] = {
3934         SSI_SDATA1_MARK,
3935 };
3936
3937 static const unsigned int ssi1_data_b_pins[] = {
3938         /* SDATA */
3939         RCAR_GP_PIN(3, 7),
3940 };
3941
3942 static const unsigned int ssi1_data_b_mux[] = {
3943         SSI_SDATA1_B_MARK,
3944 };
3945
3946 static const unsigned int ssi1_ctrl_pins[] = {
3947         /* SCK, WS */
3948         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3949 };
3950
3951 static const unsigned int ssi1_ctrl_mux[] = {
3952         SSI_SCK1_MARK, SSI_WS1_MARK,
3953 };
3954
3955 static const unsigned int ssi1_ctrl_b_pins[] = {
3956         /* SCK, WS */
3957         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3958 };
3959
3960 static const unsigned int ssi1_ctrl_b_mux[] = {
3961         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3962 };
3963
3964 static const unsigned int ssi2_data_pins[] = {
3965         /* SDATA */
3966         RCAR_GP_PIN(2, 8),
3967 };
3968
3969 static const unsigned int ssi2_data_mux[] = {
3970         SSI_SDATA2_MARK,
3971 };
3972
3973 static const unsigned int ssi2_ctrl_pins[] = {
3974         /* SCK, WS */
3975         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3976 };
3977
3978 static const unsigned int ssi2_ctrl_mux[] = {
3979         SSI_SCK2_MARK, SSI_WS2_MARK,
3980 };
3981
3982 static const unsigned int ssi3_data_pins[] = {
3983         /* SDATA */
3984         RCAR_GP_PIN(2, 11),
3985 };
3986
3987 static const unsigned int ssi3_data_mux[] = {
3988         SSI_SDATA3_MARK,
3989 };
3990
3991 static const unsigned int ssi34_ctrl_pins[] = {
3992         /* SCK, WS */
3993         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3994 };
3995
3996 static const unsigned int ssi34_ctrl_mux[] = {
3997         SSI_SCK34_MARK, SSI_WS34_MARK,
3998 };
3999
4000 static const unsigned int ssi4_data_pins[] = {
4001         /* SDATA */
4002         RCAR_GP_PIN(2, 14),
4003 };
4004
4005 static const unsigned int ssi4_data_mux[] = {
4006         SSI_SDATA4_MARK,
4007 };
4008
4009 static const unsigned int ssi4_ctrl_pins[] = {
4010         /* SCK, WS */
4011         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4012 };
4013
4014 static const unsigned int ssi4_ctrl_mux[] = {
4015         SSI_SCK4_MARK, SSI_WS4_MARK,
4016 };
4017
4018 static const unsigned int ssi5_data_pins[] = {
4019         /* SDATA */
4020         RCAR_GP_PIN(2, 17),
4021 };
4022
4023 static const unsigned int ssi5_data_mux[] = {
4024         SSI_SDATA5_MARK,
4025 };
4026
4027 static const unsigned int ssi5_ctrl_pins[] = {
4028         /* SCK, WS */
4029         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4030 };
4031
4032 static const unsigned int ssi5_ctrl_mux[] = {
4033         SSI_SCK5_MARK, SSI_WS5_MARK,
4034 };
4035
4036 static const unsigned int ssi6_data_pins[] = {
4037         /* SDATA */
4038         RCAR_GP_PIN(2, 20),
4039 };
4040
4041 static const unsigned int ssi6_data_mux[] = {
4042         SSI_SDATA6_MARK,
4043 };
4044
4045 static const unsigned int ssi6_ctrl_pins[] = {
4046         /* SCK, WS */
4047         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4048 };
4049
4050 static const unsigned int ssi6_ctrl_mux[] = {
4051         SSI_SCK6_MARK, SSI_WS6_MARK,
4052 };
4053
4054 static const unsigned int ssi7_data_pins[] = {
4055         /* SDATA */
4056         RCAR_GP_PIN(2, 23),
4057 };
4058
4059 static const unsigned int ssi7_data_mux[] = {
4060         SSI_SDATA7_MARK,
4061 };
4062
4063 static const unsigned int ssi7_data_b_pins[] = {
4064         /* SDATA */
4065         RCAR_GP_PIN(3, 12),
4066 };
4067
4068 static const unsigned int ssi7_data_b_mux[] = {
4069         SSI_SDATA7_B_MARK,
4070 };
4071
4072 static const unsigned int ssi78_ctrl_pins[] = {
4073         /* SCK, WS */
4074         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4075 };
4076
4077 static const unsigned int ssi78_ctrl_mux[] = {
4078         SSI_SCK78_MARK, SSI_WS78_MARK,
4079 };
4080
4081 static const unsigned int ssi78_ctrl_b_pins[] = {
4082         /* SCK, WS */
4083         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4084 };
4085
4086 static const unsigned int ssi78_ctrl_b_mux[] = {
4087         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4088 };
4089
4090 static const unsigned int ssi8_data_pins[] = {
4091         /* SDATA */
4092         RCAR_GP_PIN(2, 24),
4093 };
4094
4095 static const unsigned int ssi8_data_mux[] = {
4096         SSI_SDATA8_MARK,
4097 };
4098
4099 static const unsigned int ssi8_data_b_pins[] = {
4100         /* SDATA */
4101         RCAR_GP_PIN(3, 13),
4102 };
4103
4104 static const unsigned int ssi8_data_b_mux[] = {
4105         SSI_SDATA8_B_MARK,
4106 };
4107
4108 static const unsigned int ssi9_data_pins[] = {
4109         /* SDATA */
4110         RCAR_GP_PIN(2, 27),
4111 };
4112
4113 static const unsigned int ssi9_data_mux[] = {
4114         SSI_SDATA9_MARK,
4115 };
4116
4117 static const unsigned int ssi9_data_b_pins[] = {
4118         /* SDATA */
4119         RCAR_GP_PIN(3, 18),
4120 };
4121
4122 static const unsigned int ssi9_data_b_mux[] = {
4123         SSI_SDATA9_B_MARK,
4124 };
4125
4126 static const unsigned int ssi9_ctrl_pins[] = {
4127         /* SCK, WS */
4128         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4129 };
4130
4131 static const unsigned int ssi9_ctrl_mux[] = {
4132         SSI_SCK9_MARK, SSI_WS9_MARK,
4133 };
4134
4135 static const unsigned int ssi9_ctrl_b_pins[] = {
4136         /* SCK, WS */
4137         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4138 };
4139
4140 static const unsigned int ssi9_ctrl_b_mux[] = {
4141         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4142 };
4143
4144 /* - TPU -------------------------------------------------------------------- */
4145 static const unsigned int tpu_to0_pins[] = {
4146         RCAR_GP_PIN(6, 14),
4147 };
4148 static const unsigned int tpu_to0_mux[] = {
4149         TPU_TO0_MARK,
4150 };
4151 static const unsigned int tpu_to1_pins[] = {
4152         RCAR_GP_PIN(1, 17),
4153 };
4154 static const unsigned int tpu_to1_mux[] = {
4155         TPU_TO1_MARK,
4156 };
4157 static const unsigned int tpu_to2_pins[] = {
4158         RCAR_GP_PIN(1, 18),
4159 };
4160 static const unsigned int tpu_to2_mux[] = {
4161         TPU_TO2_MARK,
4162 };
4163 static const unsigned int tpu_to3_pins[] = {
4164         RCAR_GP_PIN(1, 24),
4165 };
4166 static const unsigned int tpu_to3_mux[] = {
4167         TPU_TO3_MARK,
4168 };
4169
4170 /* - USB0 ------------------------------------------------------------------- */
4171 static const unsigned int usb0_pins[] = {
4172         RCAR_GP_PIN(7, 23), /* PWEN */
4173         RCAR_GP_PIN(7, 24), /* OVC */
4174 };
4175 static const unsigned int usb0_mux[] = {
4176         USB0_PWEN_MARK,
4177         USB0_OVC_MARK,
4178 };
4179 /* - USB1 ------------------------------------------------------------------- */
4180 static const unsigned int usb1_pins[] = {
4181         RCAR_GP_PIN(7, 25), /* PWEN */
4182         RCAR_GP_PIN(6, 30), /* OVC */
4183 };
4184 static const unsigned int usb1_mux[] = {
4185         USB1_PWEN_MARK,
4186         USB1_OVC_MARK,
4187 };
4188 /* - VIN0 ------------------------------------------------------------------- */
4189 static const union vin_data vin0_data_pins = {
4190         .data24 = {
4191                 /* B */
4192                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4193                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4194                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4195                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4196                 /* G */
4197                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4198                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4199                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4200                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4201                 /* R */
4202                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4203                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4204                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4205                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4206         },
4207 };
4208 static const union vin_data vin0_data_mux = {
4209         .data24 = {
4210                 /* B */
4211                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4212                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4213                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4214                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4215                 /* G */
4216                 VI0_G0_MARK, VI0_G1_MARK,
4217                 VI0_G2_MARK, VI0_G3_MARK,
4218                 VI0_G4_MARK, VI0_G5_MARK,
4219                 VI0_G6_MARK, VI0_G7_MARK,
4220                 /* R */
4221                 VI0_R0_MARK, VI0_R1_MARK,
4222                 VI0_R2_MARK, VI0_R3_MARK,
4223                 VI0_R4_MARK, VI0_R5_MARK,
4224                 VI0_R6_MARK, VI0_R7_MARK,
4225         },
4226 };
4227 static const unsigned int vin0_data18_pins[] = {
4228         /* B */
4229         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4230         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4231         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4232         /* G */
4233         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4234         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4235         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4236         /* R */
4237         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4238         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4239         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4240 };
4241 static const unsigned int vin0_data18_mux[] = {
4242         /* B */
4243         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4244         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4245         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4246         /* G */
4247         VI0_G2_MARK, VI0_G3_MARK,
4248         VI0_G4_MARK, VI0_G5_MARK,
4249         VI0_G6_MARK, VI0_G7_MARK,
4250         /* R */
4251         VI0_R2_MARK, VI0_R3_MARK,
4252         VI0_R4_MARK, VI0_R5_MARK,
4253         VI0_R6_MARK, VI0_R7_MARK,
4254 };
4255 static const unsigned int vin0_sync_pins[] = {
4256         RCAR_GP_PIN(4, 3), /* HSYNC */
4257         RCAR_GP_PIN(4, 4), /* VSYNC */
4258 };
4259 static const unsigned int vin0_sync_mux[] = {
4260         VI0_HSYNC_N_MARK,
4261         VI0_VSYNC_N_MARK,
4262 };
4263 static const unsigned int vin0_field_pins[] = {
4264         RCAR_GP_PIN(4, 2),
4265 };
4266 static const unsigned int vin0_field_mux[] = {
4267         VI0_FIELD_MARK,
4268 };
4269 static const unsigned int vin0_clkenb_pins[] = {
4270         RCAR_GP_PIN(4, 1),
4271 };
4272 static const unsigned int vin0_clkenb_mux[] = {
4273         VI0_CLKENB_MARK,
4274 };
4275 static const unsigned int vin0_clk_pins[] = {
4276         RCAR_GP_PIN(4, 0),
4277 };
4278 static const unsigned int vin0_clk_mux[] = {
4279         VI0_CLK_MARK,
4280 };
4281 /* - VIN1 ----------------------------------------------------------------- */
4282 static const unsigned int vin1_data8_pins[] = {
4283         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4284         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4285         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4286         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4287 };
4288 static const unsigned int vin1_data8_mux[] = {
4289         VI1_DATA0_MARK, VI1_DATA1_MARK,
4290         VI1_DATA2_MARK, VI1_DATA3_MARK,
4291         VI1_DATA4_MARK, VI1_DATA5_MARK,
4292         VI1_DATA6_MARK, VI1_DATA7_MARK,
4293 };
4294 static const unsigned int vin1_sync_pins[] = {
4295         RCAR_GP_PIN(5, 0), /* HSYNC */
4296         RCAR_GP_PIN(5, 1), /* VSYNC */
4297 };
4298 static const unsigned int vin1_sync_mux[] = {
4299         VI1_HSYNC_N_MARK,
4300         VI1_VSYNC_N_MARK,
4301 };
4302 static const unsigned int vin1_field_pins[] = {
4303         RCAR_GP_PIN(5, 3),
4304 };
4305 static const unsigned int vin1_field_mux[] = {
4306         VI1_FIELD_MARK,
4307 };
4308 static const unsigned int vin1_clkenb_pins[] = {
4309         RCAR_GP_PIN(5, 2),
4310 };
4311 static const unsigned int vin1_clkenb_mux[] = {
4312         VI1_CLKENB_MARK,
4313 };
4314 static const unsigned int vin1_clk_pins[] = {
4315         RCAR_GP_PIN(5, 4),
4316 };
4317 static const unsigned int vin1_clk_mux[] = {
4318         VI1_CLK_MARK,
4319 };
4320 static const union vin_data vin1_data_b_pins = {
4321         .data24 = {
4322                 /* B */
4323                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4324                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4325                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4326                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4327                 /* G */
4328                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4329                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4330                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4331                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4332                 /* R */
4333                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4334                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4335                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4336                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4337         },
4338 };
4339 static const union vin_data vin1_data_b_mux = {
4340         .data24 = {
4341                 /* B */
4342                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4343                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4344                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4345                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4346                 /* G */
4347                 VI1_G0_B_MARK, VI1_G1_B_MARK,
4348                 VI1_G2_B_MARK, VI1_G3_B_MARK,
4349                 VI1_G4_B_MARK, VI1_G5_B_MARK,
4350                 VI1_G6_B_MARK, VI1_G7_B_MARK,
4351                 /* R */
4352                 VI1_R0_B_MARK, VI1_R1_B_MARK,
4353                 VI1_R2_B_MARK, VI1_R3_B_MARK,
4354                 VI1_R4_B_MARK, VI1_R5_B_MARK,
4355                 VI1_R6_B_MARK, VI1_R7_B_MARK,
4356         },
4357 };
4358 static const unsigned int vin1_data18_b_pins[] = {
4359         /* B */
4360         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4361         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4362         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4363         /* G */
4364         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4365         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4366         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4367         /* R */
4368         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4369         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4370         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4371 };
4372 static const unsigned int vin1_data18_b_mux[] = {
4373         /* B */
4374         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4375         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4376         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4377         /* G */
4378         VI1_G2_B_MARK, VI1_G3_B_MARK,
4379         VI1_G4_B_MARK, VI1_G5_B_MARK,
4380         VI1_G6_B_MARK, VI1_G7_B_MARK,
4381         /* R */
4382         VI1_R2_B_MARK, VI1_R3_B_MARK,
4383         VI1_R4_B_MARK, VI1_R5_B_MARK,
4384         VI1_R6_B_MARK, VI1_R7_B_MARK,
4385 };
4386 static const unsigned int vin1_sync_b_pins[] = {
4387         RCAR_GP_PIN(3, 17), /* HSYNC */
4388         RCAR_GP_PIN(3, 18), /* VSYNC */
4389 };
4390 static const unsigned int vin1_sync_b_mux[] = {
4391         VI1_HSYNC_N_B_MARK,
4392         VI1_VSYNC_N_B_MARK,
4393 };
4394 static const unsigned int vin1_field_b_pins[] = {
4395         RCAR_GP_PIN(3, 20),
4396 };
4397 static const unsigned int vin1_field_b_mux[] = {
4398         VI1_FIELD_B_MARK,
4399 };
4400 static const unsigned int vin1_clkenb_b_pins[] = {
4401         RCAR_GP_PIN(3, 19),
4402 };
4403 static const unsigned int vin1_clkenb_b_mux[] = {
4404         VI1_CLKENB_B_MARK,
4405 };
4406 static const unsigned int vin1_clk_b_pins[] = {
4407         RCAR_GP_PIN(3, 16),
4408 };
4409 static const unsigned int vin1_clk_b_mux[] = {
4410         VI1_CLK_B_MARK,
4411 };
4412 /* - VIN2 ----------------------------------------------------------------- */
4413 static const unsigned int vin2_data8_pins[] = {
4414         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4415         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4416         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4417         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4418 };
4419 static const unsigned int vin2_data8_mux[] = {
4420         VI2_DATA0_MARK, VI2_DATA1_MARK,
4421         VI2_DATA2_MARK, VI2_DATA3_MARK,
4422         VI2_DATA4_MARK, VI2_DATA5_MARK,
4423         VI2_DATA6_MARK, VI2_DATA7_MARK,
4424 };
4425 static const unsigned int vin2_sync_pins[] = {
4426         RCAR_GP_PIN(4, 15), /* HSYNC */
4427         RCAR_GP_PIN(4, 16), /* VSYNC */
4428 };
4429 static const unsigned int vin2_sync_mux[] = {
4430         VI2_HSYNC_N_MARK,
4431         VI2_VSYNC_N_MARK,
4432 };
4433 static const unsigned int vin2_field_pins[] = {
4434         RCAR_GP_PIN(4, 18),
4435 };
4436 static const unsigned int vin2_field_mux[] = {
4437         VI2_FIELD_MARK,
4438 };
4439 static const unsigned int vin2_clkenb_pins[] = {
4440         RCAR_GP_PIN(4, 17),
4441 };
4442 static const unsigned int vin2_clkenb_mux[] = {
4443         VI2_CLKENB_MARK,
4444 };
4445 static const unsigned int vin2_clk_pins[] = {
4446         RCAR_GP_PIN(4, 19),
4447 };
4448 static const unsigned int vin2_clk_mux[] = {
4449         VI2_CLK_MARK,
4450 };
4451
4452 static const struct {
4453         struct sh_pfc_pin_group common[346];
4454         struct sh_pfc_pin_group automotive[9];
4455 } pinmux_groups = {
4456         .common = {
4457                 SH_PFC_PIN_GROUP(audio_clk_a),
4458                 SH_PFC_PIN_GROUP(audio_clk_b),
4459                 SH_PFC_PIN_GROUP(audio_clk_b_b),
4460                 SH_PFC_PIN_GROUP(audio_clk_c),
4461                 SH_PFC_PIN_GROUP(audio_clkout),
4462                 SH_PFC_PIN_GROUP(avb_link),
4463                 SH_PFC_PIN_GROUP(avb_magic),
4464                 SH_PFC_PIN_GROUP(avb_phy_int),
4465                 SH_PFC_PIN_GROUP(avb_mdio),
4466                 SH_PFC_PIN_GROUP(avb_mii),
4467                 SH_PFC_PIN_GROUP(avb_gmii),
4468                 SH_PFC_PIN_GROUP(can0_data),
4469                 SH_PFC_PIN_GROUP(can0_data_b),
4470                 SH_PFC_PIN_GROUP(can0_data_c),
4471                 SH_PFC_PIN_GROUP(can0_data_d),
4472                 SH_PFC_PIN_GROUP(can0_data_e),
4473                 SH_PFC_PIN_GROUP(can0_data_f),
4474                 SH_PFC_PIN_GROUP(can1_data),
4475                 SH_PFC_PIN_GROUP(can1_data_b),
4476                 SH_PFC_PIN_GROUP(can1_data_c),
4477                 SH_PFC_PIN_GROUP(can1_data_d),
4478                 SH_PFC_PIN_GROUP(can_clk),
4479                 SH_PFC_PIN_GROUP(can_clk_b),
4480                 SH_PFC_PIN_GROUP(can_clk_c),
4481                 SH_PFC_PIN_GROUP(can_clk_d),
4482                 SH_PFC_PIN_GROUP(du_rgb666),
4483                 SH_PFC_PIN_GROUP(du_rgb888),
4484                 SH_PFC_PIN_GROUP(du_clk_out_0),
4485                 SH_PFC_PIN_GROUP(du_clk_out_1),
4486                 SH_PFC_PIN_GROUP(du_sync),
4487                 SH_PFC_PIN_GROUP(du_oddf),
4488                 SH_PFC_PIN_GROUP(du_cde),
4489                 SH_PFC_PIN_GROUP(du_disp),
4490                 SH_PFC_PIN_GROUP(du0_clk_in),
4491                 SH_PFC_PIN_GROUP(du1_clk_in),
4492                 SH_PFC_PIN_GROUP(du1_clk_in_b),
4493                 SH_PFC_PIN_GROUP(du1_clk_in_c),
4494                 SH_PFC_PIN_GROUP(eth_link),
4495                 SH_PFC_PIN_GROUP(eth_magic),
4496                 SH_PFC_PIN_GROUP(eth_mdio),
4497                 SH_PFC_PIN_GROUP(eth_rmii),
4498                 SH_PFC_PIN_GROUP(hscif0_data),
4499                 SH_PFC_PIN_GROUP(hscif0_clk),
4500                 SH_PFC_PIN_GROUP(hscif0_ctrl),
4501                 SH_PFC_PIN_GROUP(hscif0_data_b),
4502                 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4503                 SH_PFC_PIN_GROUP(hscif0_data_c),
4504                 SH_PFC_PIN_GROUP(hscif0_clk_c),
4505                 SH_PFC_PIN_GROUP(hscif1_data),
4506                 SH_PFC_PIN_GROUP(hscif1_clk),
4507                 SH_PFC_PIN_GROUP(hscif1_ctrl),
4508                 SH_PFC_PIN_GROUP(hscif1_data_b),
4509                 SH_PFC_PIN_GROUP(hscif1_data_c),
4510                 SH_PFC_PIN_GROUP(hscif1_clk_c),
4511                 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4512                 SH_PFC_PIN_GROUP(hscif1_data_d),
4513                 SH_PFC_PIN_GROUP(hscif1_data_e),
4514                 SH_PFC_PIN_GROUP(hscif1_clk_e),
4515                 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4516                 SH_PFC_PIN_GROUP(hscif2_data),
4517                 SH_PFC_PIN_GROUP(hscif2_clk),
4518                 SH_PFC_PIN_GROUP(hscif2_ctrl),
4519                 SH_PFC_PIN_GROUP(hscif2_data_b),
4520                 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4521                 SH_PFC_PIN_GROUP(hscif2_data_c),
4522                 SH_PFC_PIN_GROUP(hscif2_clk_c),
4523                 SH_PFC_PIN_GROUP(hscif2_data_d),
4524                 SH_PFC_PIN_GROUP(i2c0),
4525                 SH_PFC_PIN_GROUP(i2c0_b),
4526                 SH_PFC_PIN_GROUP(i2c0_c),
4527                 SH_PFC_PIN_GROUP(i2c1),
4528                 SH_PFC_PIN_GROUP(i2c1_b),
4529                 SH_PFC_PIN_GROUP(i2c1_c),
4530                 SH_PFC_PIN_GROUP(i2c1_d),
4531                 SH_PFC_PIN_GROUP(i2c1_e),
4532                 SH_PFC_PIN_GROUP(i2c2),
4533                 SH_PFC_PIN_GROUP(i2c2_b),
4534                 SH_PFC_PIN_GROUP(i2c2_c),
4535                 SH_PFC_PIN_GROUP(i2c2_d),
4536                 SH_PFC_PIN_GROUP(i2c3),
4537                 SH_PFC_PIN_GROUP(i2c3_b),
4538                 SH_PFC_PIN_GROUP(i2c3_c),
4539                 SH_PFC_PIN_GROUP(i2c3_d),
4540                 SH_PFC_PIN_GROUP(i2c4),
4541                 SH_PFC_PIN_GROUP(i2c4_b),
4542                 SH_PFC_PIN_GROUP(i2c4_c),
4543                 SH_PFC_PIN_GROUP(i2c7),
4544                 SH_PFC_PIN_GROUP(i2c7_b),
4545                 SH_PFC_PIN_GROUP(i2c7_c),
4546                 SH_PFC_PIN_GROUP(i2c8),
4547                 SH_PFC_PIN_GROUP(i2c8_b),
4548                 SH_PFC_PIN_GROUP(i2c8_c),
4549                 SH_PFC_PIN_GROUP(intc_irq0),
4550                 SH_PFC_PIN_GROUP(intc_irq1),
4551                 SH_PFC_PIN_GROUP(intc_irq2),
4552                 SH_PFC_PIN_GROUP(intc_irq3),
4553                 SH_PFC_PIN_GROUP(mmc_data1),
4554                 SH_PFC_PIN_GROUP(mmc_data4),
4555                 SH_PFC_PIN_GROUP(mmc_data8),
4556                 SH_PFC_PIN_GROUP(mmc_data8_b),
4557                 SH_PFC_PIN_GROUP(mmc_ctrl),
4558                 SH_PFC_PIN_GROUP(msiof0_clk),
4559                 SH_PFC_PIN_GROUP(msiof0_sync),
4560                 SH_PFC_PIN_GROUP(msiof0_ss1),
4561                 SH_PFC_PIN_GROUP(msiof0_ss2),
4562                 SH_PFC_PIN_GROUP(msiof0_rx),
4563                 SH_PFC_PIN_GROUP(msiof0_tx),
4564                 SH_PFC_PIN_GROUP(msiof0_clk_b),
4565                 SH_PFC_PIN_GROUP(msiof0_sync_b),
4566                 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4567                 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4568                 SH_PFC_PIN_GROUP(msiof0_rx_b),
4569                 SH_PFC_PIN_GROUP(msiof0_tx_b),
4570                 SH_PFC_PIN_GROUP(msiof0_clk_c),
4571                 SH_PFC_PIN_GROUP(msiof0_sync_c),
4572                 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4573                 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4574                 SH_PFC_PIN_GROUP(msiof0_rx_c),
4575                 SH_PFC_PIN_GROUP(msiof0_tx_c),
4576                 SH_PFC_PIN_GROUP(msiof1_clk),
4577                 SH_PFC_PIN_GROUP(msiof1_sync),
4578                 SH_PFC_PIN_GROUP(msiof1_ss1),
4579                 SH_PFC_PIN_GROUP(msiof1_ss2),
4580                 SH_PFC_PIN_GROUP(msiof1_rx),
4581                 SH_PFC_PIN_GROUP(msiof1_tx),
4582                 SH_PFC_PIN_GROUP(msiof1_clk_b),
4583                 SH_PFC_PIN_GROUP(msiof1_sync_b),
4584                 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4585                 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4586                 SH_PFC_PIN_GROUP(msiof1_rx_b),
4587                 SH_PFC_PIN_GROUP(msiof1_tx_b),
4588                 SH_PFC_PIN_GROUP(msiof1_clk_c),
4589                 SH_PFC_PIN_GROUP(msiof1_sync_c),
4590                 SH_PFC_PIN_GROUP(msiof1_rx_c),
4591                 SH_PFC_PIN_GROUP(msiof1_tx_c),
4592                 SH_PFC_PIN_GROUP(msiof1_clk_d),
4593                 SH_PFC_PIN_GROUP(msiof1_sync_d),
4594                 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4595                 SH_PFC_PIN_GROUP(msiof1_rx_d),
4596                 SH_PFC_PIN_GROUP(msiof1_tx_d),
4597                 SH_PFC_PIN_GROUP(msiof1_clk_e),
4598                 SH_PFC_PIN_GROUP(msiof1_sync_e),
4599                 SH_PFC_PIN_GROUP(msiof1_rx_e),
4600                 SH_PFC_PIN_GROUP(msiof1_tx_e),
4601                 SH_PFC_PIN_GROUP(msiof2_clk),
4602                 SH_PFC_PIN_GROUP(msiof2_sync),
4603                 SH_PFC_PIN_GROUP(msiof2_ss1),
4604                 SH_PFC_PIN_GROUP(msiof2_ss2),
4605                 SH_PFC_PIN_GROUP(msiof2_rx),
4606                 SH_PFC_PIN_GROUP(msiof2_tx),
4607                 SH_PFC_PIN_GROUP(msiof2_clk_b),
4608                 SH_PFC_PIN_GROUP(msiof2_sync_b),
4609                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4610                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4611                 SH_PFC_PIN_GROUP(msiof2_rx_b),
4612                 SH_PFC_PIN_GROUP(msiof2_tx_b),
4613                 SH_PFC_PIN_GROUP(msiof2_clk_c),
4614                 SH_PFC_PIN_GROUP(msiof2_sync_c),
4615                 SH_PFC_PIN_GROUP(msiof2_rx_c),
4616                 SH_PFC_PIN_GROUP(msiof2_tx_c),
4617                 SH_PFC_PIN_GROUP(msiof2_clk_d),
4618                 SH_PFC_PIN_GROUP(msiof2_sync_d),
4619                 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4620                 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4621                 SH_PFC_PIN_GROUP(msiof2_rx_d),
4622                 SH_PFC_PIN_GROUP(msiof2_tx_d),
4623                 SH_PFC_PIN_GROUP(msiof2_clk_e),
4624                 SH_PFC_PIN_GROUP(msiof2_sync_e),
4625                 SH_PFC_PIN_GROUP(msiof2_rx_e),
4626                 SH_PFC_PIN_GROUP(msiof2_tx_e),
4627                 SH_PFC_PIN_GROUP(pwm0),
4628                 SH_PFC_PIN_GROUP(pwm0_b),
4629                 SH_PFC_PIN_GROUP(pwm1),
4630                 SH_PFC_PIN_GROUP(pwm1_b),
4631                 SH_PFC_PIN_GROUP(pwm2),
4632                 SH_PFC_PIN_GROUP(pwm2_b),
4633                 SH_PFC_PIN_GROUP(pwm3),
4634                 SH_PFC_PIN_GROUP(pwm4),
4635                 SH_PFC_PIN_GROUP(pwm4_b),
4636                 SH_PFC_PIN_GROUP(pwm5),
4637                 SH_PFC_PIN_GROUP(pwm5_b),
4638                 SH_PFC_PIN_GROUP(pwm6),
4639                 SH_PFC_PIN_GROUP(qspi_ctrl),
4640                 SH_PFC_PIN_GROUP(qspi_data2),
4641                 SH_PFC_PIN_GROUP(qspi_data4),
4642                 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4643                 SH_PFC_PIN_GROUP(qspi_data2_b),
4644                 SH_PFC_PIN_GROUP(qspi_data4_b),
4645                 SH_PFC_PIN_GROUP(scif0_data),
4646                 SH_PFC_PIN_GROUP(scif0_data_b),
4647                 SH_PFC_PIN_GROUP(scif0_data_c),
4648                 SH_PFC_PIN_GROUP(scif0_data_d),
4649                 SH_PFC_PIN_GROUP(scif0_data_e),
4650                 SH_PFC_PIN_GROUP(scif1_data),
4651                 SH_PFC_PIN_GROUP(scif1_data_b),
4652                 SH_PFC_PIN_GROUP(scif1_clk_b),
4653                 SH_PFC_PIN_GROUP(scif1_data_c),
4654                 SH_PFC_PIN_GROUP(scif1_data_d),
4655                 SH_PFC_PIN_GROUP(scif2_data),
4656                 SH_PFC_PIN_GROUP(scif2_data_b),
4657                 SH_PFC_PIN_GROUP(scif2_clk_b),
4658                 SH_PFC_PIN_GROUP(scif2_data_c),
4659                 SH_PFC_PIN_GROUP(scif2_data_e),
4660                 SH_PFC_PIN_GROUP(scif3_data),
4661                 SH_PFC_PIN_GROUP(scif3_clk),
4662                 SH_PFC_PIN_GROUP(scif3_data_b),
4663                 SH_PFC_PIN_GROUP(scif3_clk_b),
4664                 SH_PFC_PIN_GROUP(scif3_data_c),
4665                 SH_PFC_PIN_GROUP(scif3_data_d),
4666                 SH_PFC_PIN_GROUP(scif4_data),
4667                 SH_PFC_PIN_GROUP(scif4_data_b),
4668                 SH_PFC_PIN_GROUP(scif4_data_c),
4669                 SH_PFC_PIN_GROUP(scif5_data),
4670                 SH_PFC_PIN_GROUP(scif5_data_b),
4671                 SH_PFC_PIN_GROUP(scifa0_data),
4672                 SH_PFC_PIN_GROUP(scifa0_data_b),
4673                 SH_PFC_PIN_GROUP(scifa1_data),
4674                 SH_PFC_PIN_GROUP(scifa1_clk),
4675                 SH_PFC_PIN_GROUP(scifa1_data_b),
4676                 SH_PFC_PIN_GROUP(scifa1_clk_b),
4677                 SH_PFC_PIN_GROUP(scifa1_data_c),
4678                 SH_PFC_PIN_GROUP(scifa2_data),
4679                 SH_PFC_PIN_GROUP(scifa2_clk),
4680                 SH_PFC_PIN_GROUP(scifa2_data_b),
4681                 SH_PFC_PIN_GROUP(scifa3_data),
4682                 SH_PFC_PIN_GROUP(scifa3_clk),
4683                 SH_PFC_PIN_GROUP(scifa3_data_b),
4684                 SH_PFC_PIN_GROUP(scifa3_clk_b),
4685                 SH_PFC_PIN_GROUP(scifa3_data_c),
4686                 SH_PFC_PIN_GROUP(scifa3_clk_c),
4687                 SH_PFC_PIN_GROUP(scifa4_data),
4688                 SH_PFC_PIN_GROUP(scifa4_data_b),
4689                 SH_PFC_PIN_GROUP(scifa4_data_c),
4690                 SH_PFC_PIN_GROUP(scifa5_data),
4691                 SH_PFC_PIN_GROUP(scifa5_data_b),
4692                 SH_PFC_PIN_GROUP(scifa5_data_c),
4693                 SH_PFC_PIN_GROUP(scifb0_data),
4694                 SH_PFC_PIN_GROUP(scifb0_clk),
4695                 SH_PFC_PIN_GROUP(scifb0_ctrl),
4696                 SH_PFC_PIN_GROUP(scifb0_data_b),
4697                 SH_PFC_PIN_GROUP(scifb0_clk_b),
4698                 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4699                 SH_PFC_PIN_GROUP(scifb0_data_c),
4700                 SH_PFC_PIN_GROUP(scifb0_clk_c),
4701                 SH_PFC_PIN_GROUP(scifb0_data_d),
4702                 SH_PFC_PIN_GROUP(scifb0_clk_d),
4703                 SH_PFC_PIN_GROUP(scifb1_data),
4704                 SH_PFC_PIN_GROUP(scifb1_clk),
4705                 SH_PFC_PIN_GROUP(scifb1_ctrl),
4706                 SH_PFC_PIN_GROUP(scifb1_data_b),
4707                 SH_PFC_PIN_GROUP(scifb1_clk_b),
4708                 SH_PFC_PIN_GROUP(scifb1_data_c),
4709                 SH_PFC_PIN_GROUP(scifb1_clk_c),
4710                 SH_PFC_PIN_GROUP(scifb1_data_d),
4711                 SH_PFC_PIN_GROUP(scifb2_data),
4712                 SH_PFC_PIN_GROUP(scifb2_clk),
4713                 SH_PFC_PIN_GROUP(scifb2_ctrl),
4714                 SH_PFC_PIN_GROUP(scifb2_data_b),
4715                 SH_PFC_PIN_GROUP(scifb2_clk_b),
4716                 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4717                 SH_PFC_PIN_GROUP(scifb2_data_c),
4718                 SH_PFC_PIN_GROUP(scifb2_clk_c),
4719                 SH_PFC_PIN_GROUP(scifb2_data_d),
4720                 SH_PFC_PIN_GROUP(scif_clk),
4721                 SH_PFC_PIN_GROUP(scif_clk_b),
4722                 SH_PFC_PIN_GROUP(sdhi0_data1),
4723                 SH_PFC_PIN_GROUP(sdhi0_data4),
4724                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4725                 SH_PFC_PIN_GROUP(sdhi0_cd),
4726                 SH_PFC_PIN_GROUP(sdhi0_wp),
4727                 SH_PFC_PIN_GROUP(sdhi1_data1),
4728                 SH_PFC_PIN_GROUP(sdhi1_data4),
4729                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4730                 SH_PFC_PIN_GROUP(sdhi1_cd),
4731                 SH_PFC_PIN_GROUP(sdhi1_wp),
4732                 SH_PFC_PIN_GROUP(sdhi2_data1),
4733                 SH_PFC_PIN_GROUP(sdhi2_data4),
4734                 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4735                 SH_PFC_PIN_GROUP(sdhi2_cd),
4736                 SH_PFC_PIN_GROUP(sdhi2_wp),
4737                 SH_PFC_PIN_GROUP(ssi0_data),
4738                 SH_PFC_PIN_GROUP(ssi0_data_b),
4739                 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4740                 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4741                 SH_PFC_PIN_GROUP(ssi1_data),
4742                 SH_PFC_PIN_GROUP(ssi1_data_b),
4743                 SH_PFC_PIN_GROUP(ssi1_ctrl),
4744                 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4745                 SH_PFC_PIN_GROUP(ssi2_data),
4746                 SH_PFC_PIN_GROUP(ssi2_ctrl),
4747                 SH_PFC_PIN_GROUP(ssi3_data),
4748                 SH_PFC_PIN_GROUP(ssi34_ctrl),
4749                 SH_PFC_PIN_GROUP(ssi4_data),
4750                 SH_PFC_PIN_GROUP(ssi4_ctrl),
4751                 SH_PFC_PIN_GROUP(ssi5_data),
4752                 SH_PFC_PIN_GROUP(ssi5_ctrl),
4753                 SH_PFC_PIN_GROUP(ssi6_data),
4754                 SH_PFC_PIN_GROUP(ssi6_ctrl),
4755                 SH_PFC_PIN_GROUP(ssi7_data),
4756                 SH_PFC_PIN_GROUP(ssi7_data_b),
4757                 SH_PFC_PIN_GROUP(ssi78_ctrl),
4758                 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4759                 SH_PFC_PIN_GROUP(ssi8_data),
4760                 SH_PFC_PIN_GROUP(ssi8_data_b),
4761                 SH_PFC_PIN_GROUP(ssi9_data),
4762                 SH_PFC_PIN_GROUP(ssi9_data_b),
4763                 SH_PFC_PIN_GROUP(ssi9_ctrl),
4764                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4765                 SH_PFC_PIN_GROUP(tpu_to0),
4766                 SH_PFC_PIN_GROUP(tpu_to1),
4767                 SH_PFC_PIN_GROUP(tpu_to2),
4768                 SH_PFC_PIN_GROUP(tpu_to3),
4769                 SH_PFC_PIN_GROUP(usb0),
4770                 SH_PFC_PIN_GROUP(usb1),
4771                 VIN_DATA_PIN_GROUP(vin0_data, 24),
4772                 VIN_DATA_PIN_GROUP(vin0_data, 20),
4773                 SH_PFC_PIN_GROUP(vin0_data18),
4774                 VIN_DATA_PIN_GROUP(vin0_data, 16),
4775                 VIN_DATA_PIN_GROUP(vin0_data, 12),
4776                 VIN_DATA_PIN_GROUP(vin0_data, 10),
4777                 VIN_DATA_PIN_GROUP(vin0_data, 8),
4778                 SH_PFC_PIN_GROUP(vin0_sync),
4779                 SH_PFC_PIN_GROUP(vin0_field),
4780                 SH_PFC_PIN_GROUP(vin0_clkenb),
4781                 SH_PFC_PIN_GROUP(vin0_clk),
4782                 SH_PFC_PIN_GROUP(vin1_data8),
4783                 SH_PFC_PIN_GROUP(vin1_sync),
4784                 SH_PFC_PIN_GROUP(vin1_field),
4785                 SH_PFC_PIN_GROUP(vin1_clkenb),
4786                 SH_PFC_PIN_GROUP(vin1_clk),
4787                 VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4788                 VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4789                 SH_PFC_PIN_GROUP(vin1_data18_b),
4790                 VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4791                 VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4792                 VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4793                 VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4794                 SH_PFC_PIN_GROUP(vin1_sync_b),
4795                 SH_PFC_PIN_GROUP(vin1_field_b),
4796                 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4797                 SH_PFC_PIN_GROUP(vin1_clk_b),
4798                 SH_PFC_PIN_GROUP(vin2_data8),
4799                 SH_PFC_PIN_GROUP(vin2_sync),
4800                 SH_PFC_PIN_GROUP(vin2_field),
4801                 SH_PFC_PIN_GROUP(vin2_clkenb),
4802                 SH_PFC_PIN_GROUP(vin2_clk),
4803         },
4804         .automotive = {
4805                 SH_PFC_PIN_GROUP(adi_common),
4806                 SH_PFC_PIN_GROUP(adi_chsel0),
4807                 SH_PFC_PIN_GROUP(adi_chsel1),
4808                 SH_PFC_PIN_GROUP(adi_chsel2),
4809                 SH_PFC_PIN_GROUP(adi_common_b),
4810                 SH_PFC_PIN_GROUP(adi_chsel0_b),
4811                 SH_PFC_PIN_GROUP(adi_chsel1_b),
4812                 SH_PFC_PIN_GROUP(adi_chsel2_b),
4813                 SH_PFC_PIN_GROUP(mlb_3pin),
4814         }
4815 };
4816
4817 static const char * const adi_groups[] = {
4818         "adi_common",
4819         "adi_chsel0",
4820         "adi_chsel1",
4821         "adi_chsel2",
4822         "adi_common_b",
4823         "adi_chsel0_b",
4824         "adi_chsel1_b",
4825         "adi_chsel2_b",
4826 };
4827
4828 static const char * const audio_clk_groups[] = {
4829         "audio_clk_a",
4830         "audio_clk_b",
4831         "audio_clk_b_b",
4832         "audio_clk_c",
4833         "audio_clkout",
4834 };
4835
4836 static const char * const avb_groups[] = {
4837         "avb_link",
4838         "avb_magic",
4839         "avb_phy_int",
4840         "avb_mdio",
4841         "avb_mii",
4842         "avb_gmii",
4843 };
4844
4845 static const char * const can0_groups[] = {
4846         "can0_data",
4847         "can0_data_b",
4848         "can0_data_c",
4849         "can0_data_d",
4850         "can0_data_e",
4851         "can0_data_f",
4852         /*
4853          * Retained for backwards compatibility, use can_clk_groups in new
4854          * designs.
4855          */
4856         "can_clk",
4857         "can_clk_b",
4858         "can_clk_c",
4859         "can_clk_d",
4860 };
4861
4862 static const char * const can1_groups[] = {
4863         "can1_data",
4864         "can1_data_b",
4865         "can1_data_c",
4866         "can1_data_d",
4867         /*
4868          * Retained for backwards compatibility, use can_clk_groups in new
4869          * designs.
4870          */
4871         "can_clk",
4872         "can_clk_b",
4873         "can_clk_c",
4874         "can_clk_d",
4875 };
4876
4877 /*
4878  * can_clk_groups allows for independent configuration, use can_clk function
4879  * in new designs.
4880  */
4881 static const char * const can_clk_groups[] = {
4882         "can_clk",
4883         "can_clk_b",
4884         "can_clk_c",
4885         "can_clk_d",
4886 };
4887
4888 static const char * const du_groups[] = {
4889         "du_rgb666",
4890         "du_rgb888",
4891         "du_clk_out_0",
4892         "du_clk_out_1",
4893         "du_sync",
4894         "du_oddf",
4895         "du_cde",
4896         "du_disp",
4897 };
4898
4899 static const char * const du0_groups[] = {
4900         "du0_clk_in",
4901 };
4902
4903 static const char * const du1_groups[] = {
4904         "du1_clk_in",
4905         "du1_clk_in_b",
4906         "du1_clk_in_c",
4907 };
4908
4909 static const char * const eth_groups[] = {
4910         "eth_link",
4911         "eth_magic",
4912         "eth_mdio",
4913         "eth_rmii",
4914 };
4915
4916 static const char * const hscif0_groups[] = {
4917         "hscif0_data",
4918         "hscif0_clk",
4919         "hscif0_ctrl",
4920         "hscif0_data_b",
4921         "hscif0_ctrl_b",
4922         "hscif0_data_c",
4923         "hscif0_clk_c",
4924 };
4925
4926 static const char * const hscif1_groups[] = {
4927         "hscif1_data",
4928         "hscif1_clk",
4929         "hscif1_ctrl",
4930         "hscif1_data_b",
4931         "hscif1_data_c",
4932         "hscif1_clk_c",
4933         "hscif1_ctrl_c",
4934         "hscif1_data_d",
4935         "hscif1_data_e",
4936         "hscif1_clk_e",
4937         "hscif1_ctrl_e",
4938 };
4939
4940 static const char * const hscif2_groups[] = {
4941         "hscif2_data",
4942         "hscif2_clk",
4943         "hscif2_ctrl",
4944         "hscif2_data_b",
4945         "hscif2_ctrl_b",
4946         "hscif2_data_c",
4947         "hscif2_clk_c",
4948         "hscif2_data_d",
4949 };
4950
4951 static const char * const i2c0_groups[] = {
4952         "i2c0",
4953         "i2c0_b",
4954         "i2c0_c",
4955 };
4956
4957 static const char * const i2c1_groups[] = {
4958         "i2c1",
4959         "i2c1_b",
4960         "i2c1_c",
4961         "i2c1_d",
4962         "i2c1_e",
4963 };
4964
4965 static const char * const i2c2_groups[] = {
4966         "i2c2",
4967         "i2c2_b",
4968         "i2c2_c",
4969         "i2c2_d",
4970 };
4971
4972 static const char * const i2c3_groups[] = {
4973         "i2c3",
4974         "i2c3_b",
4975         "i2c3_c",
4976         "i2c3_d",
4977 };
4978
4979 static const char * const i2c4_groups[] = {
4980         "i2c4",
4981         "i2c4_b",
4982         "i2c4_c",
4983 };
4984
4985 static const char * const i2c7_groups[] = {
4986         "i2c7",
4987         "i2c7_b",
4988         "i2c7_c",
4989 };
4990
4991 static const char * const i2c8_groups[] = {
4992         "i2c8",
4993         "i2c8_b",
4994         "i2c8_c",
4995 };
4996
4997 static const char * const intc_groups[] = {
4998         "intc_irq0",
4999         "intc_irq1",
5000         "intc_irq2",
5001         "intc_irq3",
5002 };
5003
5004 static const char * const mlb_groups[] = {
5005         "mlb_3pin",
5006 };
5007
5008 static const char * const mmc_groups[] = {
5009         "mmc_data1",
5010         "mmc_data4",
5011         "mmc_data8",
5012         "mmc_data8_b",
5013         "mmc_ctrl",
5014 };
5015
5016 static const char * const msiof0_groups[] = {
5017         "msiof0_clk",
5018         "msiof0_sync",
5019         "msiof0_ss1",
5020         "msiof0_ss2",
5021         "msiof0_rx",
5022         "msiof0_tx",
5023         "msiof0_clk_b",
5024         "msiof0_sync_b",
5025         "msiof0_ss1_b",
5026         "msiof0_ss2_b",
5027         "msiof0_rx_b",
5028         "msiof0_tx_b",
5029         "msiof0_clk_c",
5030         "msiof0_sync_c",
5031         "msiof0_ss1_c",
5032         "msiof0_ss2_c",
5033         "msiof0_rx_c",
5034         "msiof0_tx_c",
5035 };
5036
5037 static const char * const msiof1_groups[] = {
5038         "msiof1_clk",
5039         "msiof1_sync",
5040         "msiof1_ss1",
5041         "msiof1_ss2",
5042         "msiof1_rx",
5043         "msiof1_tx",
5044         "msiof1_clk_b",
5045         "msiof1_sync_b",
5046         "msiof1_ss1_b",
5047         "msiof1_ss2_b",
5048         "msiof1_rx_b",
5049         "msiof1_tx_b",
5050         "msiof1_clk_c",
5051         "msiof1_sync_c",
5052         "msiof1_rx_c",
5053         "msiof1_tx_c",
5054         "msiof1_clk_d",
5055         "msiof1_sync_d",
5056         "msiof1_ss1_d",
5057         "msiof1_rx_d",
5058         "msiof1_tx_d",
5059         "msiof1_clk_e",
5060         "msiof1_sync_e",
5061         "msiof1_rx_e",
5062         "msiof1_tx_e",
5063 };
5064
5065 static const char * const msiof2_groups[] = {
5066         "msiof2_clk",
5067         "msiof2_sync",
5068         "msiof2_ss1",
5069         "msiof2_ss2",
5070         "msiof2_rx",
5071         "msiof2_tx",
5072         "msiof2_clk_b",
5073         "msiof2_sync_b",
5074         "msiof2_ss1_b",
5075         "msiof2_ss2_b",
5076         "msiof2_rx_b",
5077         "msiof2_tx_b",
5078         "msiof2_clk_c",
5079         "msiof2_sync_c",
5080         "msiof2_rx_c",
5081         "msiof2_tx_c",
5082         "msiof2_clk_d",
5083         "msiof2_sync_d",
5084         "msiof2_ss1_d",
5085         "msiof2_ss2_d",
5086         "msiof2_rx_d",
5087         "msiof2_tx_d",
5088         "msiof2_clk_e",
5089         "msiof2_sync_e",
5090         "msiof2_rx_e",
5091         "msiof2_tx_e",
5092 };
5093
5094 static const char * const pwm0_groups[] = {
5095         "pwm0",
5096         "pwm0_b",
5097 };
5098
5099 static const char * const pwm1_groups[] = {
5100         "pwm1",
5101         "pwm1_b",
5102 };
5103
5104 static const char * const pwm2_groups[] = {
5105         "pwm2",
5106         "pwm2_b",
5107 };
5108
5109 static const char * const pwm3_groups[] = {
5110         "pwm3",
5111 };
5112
5113 static const char * const pwm4_groups[] = {
5114         "pwm4",
5115         "pwm4_b",
5116 };
5117
5118 static const char * const pwm5_groups[] = {
5119         "pwm5",
5120         "pwm5_b",
5121 };
5122
5123 static const char * const pwm6_groups[] = {
5124         "pwm6",
5125 };
5126
5127 static const char * const qspi_groups[] = {
5128         "qspi_ctrl",
5129         "qspi_data2",
5130         "qspi_data4",
5131         "qspi_ctrl_b",
5132         "qspi_data2_b",
5133         "qspi_data4_b",
5134 };
5135
5136 static const char * const scif0_groups[] = {
5137         "scif0_data",
5138         "scif0_data_b",
5139         "scif0_data_c",
5140         "scif0_data_d",
5141         "scif0_data_e",
5142 };
5143
5144 static const char * const scif1_groups[] = {
5145         "scif1_data",
5146         "scif1_data_b",
5147         "scif1_clk_b",
5148         "scif1_data_c",
5149         "scif1_data_d",
5150 };
5151
5152 static const char * const scif2_groups[] = {
5153         "scif2_data",
5154         "scif2_data_b",
5155         "scif2_clk_b",
5156         "scif2_data_c",
5157         "scif2_data_e",
5158 };
5159 static const char * const scif3_groups[] = {
5160         "scif3_data",
5161         "scif3_clk",
5162         "scif3_data_b",
5163         "scif3_clk_b",
5164         "scif3_data_c",
5165         "scif3_data_d",
5166 };
5167 static const char * const scif4_groups[] = {
5168         "scif4_data",
5169         "scif4_data_b",
5170         "scif4_data_c",
5171 };
5172 static const char * const scif5_groups[] = {
5173         "scif5_data",
5174         "scif5_data_b",
5175 };
5176 static const char * const scifa0_groups[] = {
5177         "scifa0_data",
5178         "scifa0_data_b",
5179 };
5180 static const char * const scifa1_groups[] = {
5181         "scifa1_data",
5182         "scifa1_clk",
5183         "scifa1_data_b",
5184         "scifa1_clk_b",
5185         "scifa1_data_c",
5186 };
5187 static const char * const scifa2_groups[] = {
5188         "scifa2_data",
5189         "scifa2_clk",
5190         "scifa2_data_b",
5191 };
5192 static const char * const scifa3_groups[] = {
5193         "scifa3_data",
5194         "scifa3_clk",
5195         "scifa3_data_b",
5196         "scifa3_clk_b",
5197         "scifa3_data_c",
5198         "scifa3_clk_c",
5199 };
5200 static const char * const scifa4_groups[] = {
5201         "scifa4_data",
5202         "scifa4_data_b",
5203         "scifa4_data_c",
5204 };
5205 static const char * const scifa5_groups[] = {
5206         "scifa5_data",
5207         "scifa5_data_b",
5208         "scifa5_data_c",
5209 };
5210 static const char * const scifb0_groups[] = {
5211         "scifb0_data",
5212         "scifb0_clk",
5213         "scifb0_ctrl",
5214         "scifb0_data_b",
5215         "scifb0_clk_b",
5216         "scifb0_ctrl_b",
5217         "scifb0_data_c",
5218         "scifb0_clk_c",
5219         "scifb0_data_d",
5220         "scifb0_clk_d",
5221 };
5222 static const char * const scifb1_groups[] = {
5223         "scifb1_data",
5224         "scifb1_clk",
5225         "scifb1_ctrl",
5226         "scifb1_data_b",
5227         "scifb1_clk_b",
5228         "scifb1_data_c",
5229         "scifb1_clk_c",
5230         "scifb1_data_d",
5231 };
5232 static const char * const scifb2_groups[] = {
5233         "scifb2_data",
5234         "scifb2_clk",
5235         "scifb2_ctrl",
5236         "scifb2_data_b",
5237         "scifb2_clk_b",
5238         "scifb2_ctrl_b",
5239         "scifb2_data_c",
5240         "scifb2_clk_c",
5241         "scifb2_data_d",
5242 };
5243
5244 static const char * const scif_clk_groups[] = {
5245         "scif_clk",
5246         "scif_clk_b",
5247 };
5248
5249 static const char * const sdhi0_groups[] = {
5250         "sdhi0_data1",
5251         "sdhi0_data4",
5252         "sdhi0_ctrl",
5253         "sdhi0_cd",
5254         "sdhi0_wp",
5255 };
5256
5257 static const char * const sdhi1_groups[] = {
5258         "sdhi1_data1",
5259         "sdhi1_data4",
5260         "sdhi1_ctrl",
5261         "sdhi1_cd",
5262         "sdhi1_wp",
5263 };
5264
5265 static const char * const sdhi2_groups[] = {
5266         "sdhi2_data1",
5267         "sdhi2_data4",
5268         "sdhi2_ctrl",
5269         "sdhi2_cd",
5270         "sdhi2_wp",
5271 };
5272
5273 static const char * const ssi_groups[] = {
5274         "ssi0_data",
5275         "ssi0_data_b",
5276         "ssi0129_ctrl",
5277         "ssi0129_ctrl_b",
5278         "ssi1_data",
5279         "ssi1_data_b",
5280         "ssi1_ctrl",
5281         "ssi1_ctrl_b",
5282         "ssi2_data",
5283         "ssi2_ctrl",
5284         "ssi3_data",
5285         "ssi34_ctrl",
5286         "ssi4_data",
5287         "ssi4_ctrl",
5288         "ssi5_data",
5289         "ssi5_ctrl",
5290         "ssi6_data",
5291         "ssi6_ctrl",
5292         "ssi7_data",
5293         "ssi7_data_b",
5294         "ssi78_ctrl",
5295         "ssi78_ctrl_b",
5296         "ssi8_data",
5297         "ssi8_data_b",
5298         "ssi9_data",
5299         "ssi9_data_b",
5300         "ssi9_ctrl",
5301         "ssi9_ctrl_b",
5302 };
5303
5304 static const char * const tpu_groups[] = {
5305         "tpu_to0",
5306         "tpu_to1",
5307         "tpu_to2",
5308         "tpu_to3",
5309 };
5310
5311 static const char * const usb0_groups[] = {
5312         "usb0",
5313 };
5314 static const char * const usb1_groups[] = {
5315         "usb1",
5316 };
5317
5318 static const char * const vin0_groups[] = {
5319         "vin0_data24",
5320         "vin0_data20",
5321         "vin0_data18",
5322         "vin0_data16",
5323         "vin0_data12",
5324         "vin0_data10",
5325         "vin0_data8",
5326         "vin0_sync",
5327         "vin0_field",
5328         "vin0_clkenb",
5329         "vin0_clk",
5330 };
5331
5332 static const char * const vin1_groups[] = {
5333         "vin1_data8",
5334         "vin1_sync",
5335         "vin1_field",
5336         "vin1_clkenb",
5337         "vin1_clk",
5338         "vin1_data24_b",
5339         "vin1_data20_b",
5340         "vin1_data18_b",
5341         "vin1_data16_b",
5342         "vin1_data12_b",
5343         "vin1_data10_b",
5344         "vin1_data8_b",
5345         "vin1_sync_b",
5346         "vin1_field_b",
5347         "vin1_clkenb_b",
5348         "vin1_clk_b",
5349 };
5350
5351 static const char * const vin2_groups[] = {
5352         "vin2_data8",
5353         "vin2_sync",
5354         "vin2_field",
5355         "vin2_clkenb",
5356         "vin2_clk",
5357 };
5358
5359 static const struct {
5360         struct sh_pfc_function common[58];
5361         struct sh_pfc_function automotive[2];
5362 } pinmux_functions = {
5363         .common = {
5364                 SH_PFC_FUNCTION(audio_clk),
5365                 SH_PFC_FUNCTION(avb),
5366                 SH_PFC_FUNCTION(can0),
5367                 SH_PFC_FUNCTION(can1),
5368                 SH_PFC_FUNCTION(can_clk),
5369                 SH_PFC_FUNCTION(du),
5370                 SH_PFC_FUNCTION(du0),
5371                 SH_PFC_FUNCTION(du1),
5372                 SH_PFC_FUNCTION(eth),
5373                 SH_PFC_FUNCTION(hscif0),
5374                 SH_PFC_FUNCTION(hscif1),
5375                 SH_PFC_FUNCTION(hscif2),
5376                 SH_PFC_FUNCTION(i2c0),
5377                 SH_PFC_FUNCTION(i2c1),
5378                 SH_PFC_FUNCTION(i2c2),
5379                 SH_PFC_FUNCTION(i2c3),
5380                 SH_PFC_FUNCTION(i2c4),
5381                 SH_PFC_FUNCTION(i2c7),
5382                 SH_PFC_FUNCTION(i2c8),
5383                 SH_PFC_FUNCTION(intc),
5384                 SH_PFC_FUNCTION(mmc),
5385                 SH_PFC_FUNCTION(msiof0),
5386                 SH_PFC_FUNCTION(msiof1),
5387                 SH_PFC_FUNCTION(msiof2),
5388                 SH_PFC_FUNCTION(pwm0),
5389                 SH_PFC_FUNCTION(pwm1),
5390                 SH_PFC_FUNCTION(pwm2),
5391                 SH_PFC_FUNCTION(pwm3),
5392                 SH_PFC_FUNCTION(pwm4),
5393                 SH_PFC_FUNCTION(pwm5),
5394                 SH_PFC_FUNCTION(pwm6),
5395                 SH_PFC_FUNCTION(qspi),
5396                 SH_PFC_FUNCTION(scif0),
5397                 SH_PFC_FUNCTION(scif1),
5398                 SH_PFC_FUNCTION(scif2),
5399                 SH_PFC_FUNCTION(scif3),
5400                 SH_PFC_FUNCTION(scif4),
5401                 SH_PFC_FUNCTION(scif5),
5402                 SH_PFC_FUNCTION(scifa0),
5403                 SH_PFC_FUNCTION(scifa1),
5404                 SH_PFC_FUNCTION(scifa2),
5405                 SH_PFC_FUNCTION(scifa3),
5406                 SH_PFC_FUNCTION(scifa4),
5407                 SH_PFC_FUNCTION(scifa5),
5408                 SH_PFC_FUNCTION(scifb0),
5409                 SH_PFC_FUNCTION(scifb1),
5410                 SH_PFC_FUNCTION(scifb2),
5411                 SH_PFC_FUNCTION(scif_clk),
5412                 SH_PFC_FUNCTION(sdhi0),
5413                 SH_PFC_FUNCTION(sdhi1),
5414                 SH_PFC_FUNCTION(sdhi2),
5415                 SH_PFC_FUNCTION(ssi),
5416                 SH_PFC_FUNCTION(tpu),
5417                 SH_PFC_FUNCTION(usb0),
5418                 SH_PFC_FUNCTION(usb1),
5419                 SH_PFC_FUNCTION(vin0),
5420                 SH_PFC_FUNCTION(vin1),
5421                 SH_PFC_FUNCTION(vin2),
5422         },
5423         .automotive = {
5424                 SH_PFC_FUNCTION(adi),
5425                 SH_PFC_FUNCTION(mlb),
5426         }
5427 };
5428
5429 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5430         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5431                 GP_0_31_FN, FN_IP1_22_20,
5432                 GP_0_30_FN, FN_IP1_19_17,
5433                 GP_0_29_FN, FN_IP1_16_14,
5434                 GP_0_28_FN, FN_IP1_13_11,
5435                 GP_0_27_FN, FN_IP1_10_8,
5436                 GP_0_26_FN, FN_IP1_7_6,
5437                 GP_0_25_FN, FN_IP1_5_4,
5438                 GP_0_24_FN, FN_IP1_3_2,
5439                 GP_0_23_FN, FN_IP1_1_0,
5440                 GP_0_22_FN, FN_IP0_30_29,
5441                 GP_0_21_FN, FN_IP0_28_27,
5442                 GP_0_20_FN, FN_IP0_26_25,
5443                 GP_0_19_FN, FN_IP0_24_23,
5444                 GP_0_18_FN, FN_IP0_22_21,
5445                 GP_0_17_FN, FN_IP0_20_19,
5446                 GP_0_16_FN, FN_IP0_18_16,
5447                 GP_0_15_FN, FN_IP0_15,
5448                 GP_0_14_FN, FN_IP0_14,
5449                 GP_0_13_FN, FN_IP0_13,
5450                 GP_0_12_FN, FN_IP0_12,
5451                 GP_0_11_FN, FN_IP0_11,
5452                 GP_0_10_FN, FN_IP0_10,
5453                 GP_0_9_FN, FN_IP0_9,
5454                 GP_0_8_FN, FN_IP0_8,
5455                 GP_0_7_FN, FN_IP0_7,
5456                 GP_0_6_FN, FN_IP0_6,
5457                 GP_0_5_FN, FN_IP0_5,
5458                 GP_0_4_FN, FN_IP0_4,
5459                 GP_0_3_FN, FN_IP0_3,
5460                 GP_0_2_FN, FN_IP0_2,
5461                 GP_0_1_FN, FN_IP0_1,
5462                 GP_0_0_FN, FN_IP0_0, }
5463         },
5464         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5465                 0, 0,
5466                 0, 0,
5467                 0, 0,
5468                 0, 0,
5469                 0, 0,
5470                 0, 0,
5471                 GP_1_25_FN, FN_IP3_21_20,
5472                 GP_1_24_FN, FN_IP3_19_18,
5473                 GP_1_23_FN, FN_IP3_17_16,
5474                 GP_1_22_FN, FN_IP3_15_14,
5475                 GP_1_21_FN, FN_IP3_13_12,
5476                 GP_1_20_FN, FN_IP3_11_9,
5477                 GP_1_19_FN, FN_RD_N,
5478                 GP_1_18_FN, FN_IP3_8_6,
5479                 GP_1_17_FN, FN_IP3_5_3,
5480                 GP_1_16_FN, FN_IP3_2_0,
5481                 GP_1_15_FN, FN_IP2_29_27,
5482                 GP_1_14_FN, FN_IP2_26_25,
5483                 GP_1_13_FN, FN_IP2_24_23,
5484                 GP_1_12_FN, FN_EX_CS0_N,
5485                 GP_1_11_FN, FN_IP2_22_21,
5486                 GP_1_10_FN, FN_IP2_20_19,
5487                 GP_1_9_FN, FN_IP2_18_16,
5488                 GP_1_8_FN, FN_IP2_15_13,
5489                 GP_1_7_FN, FN_IP2_12_10,
5490                 GP_1_6_FN, FN_IP2_9_7,
5491                 GP_1_5_FN, FN_IP2_6_5,
5492                 GP_1_4_FN, FN_IP2_4_3,
5493                 GP_1_3_FN, FN_IP2_2_0,
5494                 GP_1_2_FN, FN_IP1_31_29,
5495                 GP_1_1_FN, FN_IP1_28_26,
5496                 GP_1_0_FN, FN_IP1_25_23, }
5497         },
5498         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5499                 GP_2_31_FN, FN_IP6_7_6,
5500                 GP_2_30_FN, FN_IP6_5_3,
5501                 GP_2_29_FN, FN_IP6_2_0,
5502                 GP_2_28_FN, FN_AUDIO_CLKA,
5503                 GP_2_27_FN, FN_IP5_31_29,
5504                 GP_2_26_FN, FN_IP5_28_26,
5505                 GP_2_25_FN, FN_IP5_25_24,
5506                 GP_2_24_FN, FN_IP5_23_22,
5507                 GP_2_23_FN, FN_IP5_21_20,
5508                 GP_2_22_FN, FN_IP5_19_17,
5509                 GP_2_21_FN, FN_IP5_16_15,
5510                 GP_2_20_FN, FN_IP5_14_12,
5511                 GP_2_19_FN, FN_IP5_11_9,
5512                 GP_2_18_FN, FN_IP5_8_6,
5513                 GP_2_17_FN, FN_IP5_5_3,
5514                 GP_2_16_FN, FN_IP5_2_0,
5515                 GP_2_15_FN, FN_IP4_30_28,
5516                 GP_2_14_FN, FN_IP4_27_26,
5517                 GP_2_13_FN, FN_IP4_25_24,
5518                 GP_2_12_FN, FN_IP4_23_22,
5519                 GP_2_11_FN, FN_IP4_21,
5520                 GP_2_10_FN, FN_IP4_20,
5521                 GP_2_9_FN, FN_IP4_19,
5522                 GP_2_8_FN, FN_IP4_18_16,
5523                 GP_2_7_FN, FN_IP4_15_13,
5524                 GP_2_6_FN, FN_IP4_12_10,
5525                 GP_2_5_FN, FN_IP4_9_8,
5526                 GP_2_4_FN, FN_IP4_7_5,
5527                 GP_2_3_FN, FN_IP4_4_2,
5528                 GP_2_2_FN, FN_IP4_1_0,
5529                 GP_2_1_FN, FN_IP3_30_28,
5530                 GP_2_0_FN, FN_IP3_27_25 }
5531         },
5532         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5533                 GP_3_31_FN, FN_IP9_18_17,
5534                 GP_3_30_FN, FN_IP9_16,
5535                 GP_3_29_FN, FN_IP9_15_13,
5536                 GP_3_28_FN, FN_IP9_12,
5537                 GP_3_27_FN, FN_IP9_11,
5538                 GP_3_26_FN, FN_IP9_10_8,
5539                 GP_3_25_FN, FN_IP9_7,
5540                 GP_3_24_FN, FN_IP9_6,
5541                 GP_3_23_FN, FN_IP9_5_3,
5542                 GP_3_22_FN, FN_IP9_2_0,
5543                 GP_3_21_FN, FN_IP8_30_28,
5544                 GP_3_20_FN, FN_IP8_27_26,
5545                 GP_3_19_FN, FN_IP8_25_24,
5546                 GP_3_18_FN, FN_IP8_23_21,
5547                 GP_3_17_FN, FN_IP8_20_18,
5548                 GP_3_16_FN, FN_IP8_17_15,
5549                 GP_3_15_FN, FN_IP8_14_12,
5550                 GP_3_14_FN, FN_IP8_11_9,
5551                 GP_3_13_FN, FN_IP8_8_6,
5552                 GP_3_12_FN, FN_IP8_5_3,
5553                 GP_3_11_FN, FN_IP8_2_0,
5554                 GP_3_10_FN, FN_IP7_29_27,
5555                 GP_3_9_FN, FN_IP7_26_24,
5556                 GP_3_8_FN, FN_IP7_23_21,
5557                 GP_3_7_FN, FN_IP7_20_19,
5558                 GP_3_6_FN, FN_IP7_18_17,
5559                 GP_3_5_FN, FN_IP7_16_15,
5560                 GP_3_4_FN, FN_IP7_14_13,
5561                 GP_3_3_FN, FN_IP7_12_11,
5562                 GP_3_2_FN, FN_IP7_10_9,
5563                 GP_3_1_FN, FN_IP7_8_6,
5564                 GP_3_0_FN, FN_IP7_5_3 }
5565         },
5566         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5567                 GP_4_31_FN, FN_IP15_5_4,
5568                 GP_4_30_FN, FN_IP15_3_2,
5569                 GP_4_29_FN, FN_IP15_1_0,
5570                 GP_4_28_FN, FN_IP11_8_6,
5571                 GP_4_27_FN, FN_IP11_5_3,
5572                 GP_4_26_FN, FN_IP11_2_0,
5573                 GP_4_25_FN, FN_IP10_31_29,
5574                 GP_4_24_FN, FN_IP10_28_27,
5575                 GP_4_23_FN, FN_IP10_26_25,
5576                 GP_4_22_FN, FN_IP10_24_22,
5577                 GP_4_21_FN, FN_IP10_21_19,
5578                 GP_4_20_FN, FN_IP10_18_17,
5579                 GP_4_19_FN, FN_IP10_16_15,
5580                 GP_4_18_FN, FN_IP10_14_12,
5581                 GP_4_17_FN, FN_IP10_11_9,
5582                 GP_4_16_FN, FN_IP10_8_6,
5583                 GP_4_15_FN, FN_IP10_5_3,
5584                 GP_4_14_FN, FN_IP10_2_0,
5585                 GP_4_13_FN, FN_IP9_31_29,
5586                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5587                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5588                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5589                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5590                 GP_4_8_FN, FN_IP9_28_27,
5591                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5592                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5593                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5594                 GP_4_4_FN, FN_IP9_26_25,
5595                 GP_4_3_FN, FN_IP9_24_23,
5596                 GP_4_2_FN, FN_IP9_22_21,
5597                 GP_4_1_FN, FN_IP9_20_19,
5598                 GP_4_0_FN, FN_VI0_CLK }
5599         },
5600         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5601                 GP_5_31_FN, FN_IP3_24_22,
5602                 GP_5_30_FN, FN_IP13_9_7,
5603                 GP_5_29_FN, FN_IP13_6_5,
5604                 GP_5_28_FN, FN_IP13_4_3,
5605                 GP_5_27_FN, FN_IP13_2_0,
5606                 GP_5_26_FN, FN_IP12_29_27,
5607                 GP_5_25_FN, FN_IP12_26_24,
5608                 GP_5_24_FN, FN_IP12_23_22,
5609                 GP_5_23_FN, FN_IP12_21_20,
5610                 GP_5_22_FN, FN_IP12_19_18,
5611                 GP_5_21_FN, FN_IP12_17_16,
5612                 GP_5_20_FN, FN_IP12_15_13,
5613                 GP_5_19_FN, FN_IP12_12_10,
5614                 GP_5_18_FN, FN_IP12_9_7,
5615                 GP_5_17_FN, FN_IP12_6_4,
5616                 GP_5_16_FN, FN_IP12_3_2,
5617                 GP_5_15_FN, FN_IP12_1_0,
5618                 GP_5_14_FN, FN_IP11_31_30,
5619                 GP_5_13_FN, FN_IP11_29_28,
5620                 GP_5_12_FN, FN_IP11_27,
5621                 GP_5_11_FN, FN_IP11_26,
5622                 GP_5_10_FN, FN_IP11_25,
5623                 GP_5_9_FN, FN_IP11_24,
5624                 GP_5_8_FN, FN_IP11_23,
5625                 GP_5_7_FN, FN_IP11_22,
5626                 GP_5_6_FN, FN_IP11_21,
5627                 GP_5_5_FN, FN_IP11_20,
5628                 GP_5_4_FN, FN_IP11_19,
5629                 GP_5_3_FN, FN_IP11_18_17,
5630                 GP_5_2_FN, FN_IP11_16_15,
5631                 GP_5_1_FN, FN_IP11_14_12,
5632                 GP_5_0_FN, FN_IP11_11_9 }
5633         },
5634         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5635                 GP_6_31_FN, FN_DU0_DOTCLKIN,
5636                 GP_6_30_FN, FN_USB1_OVC,
5637                 GP_6_29_FN, FN_IP14_31_29,
5638                 GP_6_28_FN, FN_IP14_28_26,
5639                 GP_6_27_FN, FN_IP14_25_23,
5640                 GP_6_26_FN, FN_IP14_22_20,
5641                 GP_6_25_FN, FN_IP14_19_17,
5642                 GP_6_24_FN, FN_IP14_16_14,
5643                 GP_6_23_FN, FN_IP14_13_11,
5644                 GP_6_22_FN, FN_IP14_10_8,
5645                 GP_6_21_FN, FN_IP14_7,
5646                 GP_6_20_FN, FN_IP14_6,
5647                 GP_6_19_FN, FN_IP14_5,
5648                 GP_6_18_FN, FN_IP14_4,
5649                 GP_6_17_FN, FN_IP14_3,
5650                 GP_6_16_FN, FN_IP14_2,
5651                 GP_6_15_FN, FN_IP14_1_0,
5652                 GP_6_14_FN, FN_IP13_30_28,
5653                 GP_6_13_FN, FN_IP13_27,
5654                 GP_6_12_FN, FN_IP13_26,
5655                 GP_6_11_FN, FN_IP13_25,
5656                 GP_6_10_FN, FN_IP13_24_23,
5657                 GP_6_9_FN, FN_IP13_22,
5658                 GP_6_8_FN, FN_SD1_CLK,
5659                 GP_6_7_FN, FN_IP13_21_19,
5660                 GP_6_6_FN, FN_IP13_18_16,
5661                 GP_6_5_FN, FN_IP13_15,
5662                 GP_6_4_FN, FN_IP13_14,
5663                 GP_6_3_FN, FN_IP13_13,
5664                 GP_6_2_FN, FN_IP13_12,
5665                 GP_6_1_FN, FN_IP13_11,
5666                 GP_6_0_FN, FN_IP13_10 }
5667         },
5668         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5669                 0, 0,
5670                 0, 0,
5671                 0, 0,
5672                 0, 0,
5673                 0, 0,
5674                 0, 0,
5675                 GP_7_25_FN, FN_USB1_PWEN,
5676                 GP_7_24_FN, FN_USB0_OVC,
5677                 GP_7_23_FN, FN_USB0_PWEN,
5678                 GP_7_22_FN, FN_IP15_14_12,
5679                 GP_7_21_FN, FN_IP15_11_9,
5680                 GP_7_20_FN, FN_IP15_8_6,
5681                 GP_7_19_FN, FN_IP7_2_0,
5682                 GP_7_18_FN, FN_IP6_29_27,
5683                 GP_7_17_FN, FN_IP6_26_24,
5684                 GP_7_16_FN, FN_IP6_23_21,
5685                 GP_7_15_FN, FN_IP6_20_19,
5686                 GP_7_14_FN, FN_IP6_18_16,
5687                 GP_7_13_FN, FN_IP6_15_14,
5688                 GP_7_12_FN, FN_IP6_13_12,
5689                 GP_7_11_FN, FN_IP6_11_10,
5690                 GP_7_10_FN, FN_IP6_9_8,
5691                 GP_7_9_FN, FN_IP16_11_10,
5692                 GP_7_8_FN, FN_IP16_9_8,
5693                 GP_7_7_FN, FN_IP16_7_6,
5694                 GP_7_6_FN, FN_IP16_5_3,
5695                 GP_7_5_FN, FN_IP16_2_0,
5696                 GP_7_4_FN, FN_IP15_29_27,
5697                 GP_7_3_FN, FN_IP15_26_24,
5698                 GP_7_2_FN, FN_IP15_23_21,
5699                 GP_7_1_FN, FN_IP15_20_18,
5700                 GP_7_0_FN, FN_IP15_17_15 }
5701         },
5702         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5703                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5704                              1, 1, 1, 1, 1, 1, 1, 1) {
5705                 /* IP0_31 [1] */
5706                 0, 0,
5707                 /* IP0_30_29 [2] */
5708                 FN_A6, FN_MSIOF1_SCK,
5709                 0, 0,
5710                 /* IP0_28_27 [2] */
5711                 FN_A5, FN_MSIOF0_RXD_B,
5712                 0, 0,
5713                 /* IP0_26_25 [2] */
5714                 FN_A4, FN_MSIOF0_TXD_B,
5715                 0, 0,
5716                 /* IP0_24_23 [2] */
5717                 FN_A3, FN_MSIOF0_SS2_B,
5718                 0, 0,
5719                 /* IP0_22_21 [2] */
5720                 FN_A2, FN_MSIOF0_SS1_B,
5721                 0, 0,
5722                 /* IP0_20_19 [2] */
5723                 FN_A1, FN_MSIOF0_SYNC_B,
5724                 0, 0,
5725                 /* IP0_18_16 [3] */
5726                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5727                 0, 0, 0,
5728                 /* IP0_15 [1] */
5729                 FN_D15, 0,
5730                 /* IP0_14 [1] */
5731                 FN_D14, 0,
5732                 /* IP0_13 [1] */
5733                 FN_D13, 0,
5734                 /* IP0_12 [1] */
5735                 FN_D12, 0,
5736                 /* IP0_11 [1] */
5737                 FN_D11, 0,
5738                 /* IP0_10 [1] */
5739                 FN_D10, 0,
5740                 /* IP0_9 [1] */
5741                 FN_D9, 0,
5742                 /* IP0_8 [1] */
5743                 FN_D8, 0,
5744                 /* IP0_7 [1] */
5745                 FN_D7, 0,
5746                 /* IP0_6 [1] */
5747                 FN_D6, 0,
5748                 /* IP0_5 [1] */
5749                 FN_D5, 0,
5750                 /* IP0_4 [1] */
5751                 FN_D4, 0,
5752                 /* IP0_3 [1] */
5753                 FN_D3, 0,
5754                 /* IP0_2 [1] */
5755                 FN_D2, 0,
5756                 /* IP0_1 [1] */
5757                 FN_D1, 0,
5758                 /* IP0_0 [1] */
5759                 FN_D0, 0, }
5760         },
5761         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5762                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5763                 /* IP1_31_29 [3] */
5764                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5765                 0, 0, 0,
5766                 /* IP1_28_26 [3] */
5767                 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5768                 0, 0, 0, 0,
5769                 /* IP1_25_23 [3] */
5770                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5771                 0, 0, 0,
5772                 /* IP1_22_20 [3] */
5773                 FN_A15, FN_BPFCLK_C,
5774                 0, 0, 0, 0, 0, 0,
5775                 /* IP1_19_17 [3] */
5776                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5777                 0, 0, 0,
5778                 /* IP1_16_14 [3] */
5779                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5780                 0, 0, 0, 0,
5781                 /* IP1_13_11 [3] */
5782                 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5783                 0, 0, 0, 0,
5784                 /* IP1_10_8 [3] */
5785                 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5786                 0, 0, 0, 0,
5787                 /* IP1_7_6 [2] */
5788                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5789                 /* IP1_5_4 [2] */
5790                 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5791                 /* IP1_3_2 [2] */
5792                 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5793                 /* IP1_1_0 [2] */
5794                 FN_A7, FN_MSIOF1_SYNC,
5795                 0, 0, }
5796         },
5797         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5798                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5799                 /* IP2_31_30 [2] */
5800                 0, 0, 0, 0,
5801                 /* IP2_29_27 [3] */
5802                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5803                 FN_ATAG0_N, 0, FN_EX_WAIT1,
5804                 0, 0,
5805                 /* IP2_26_25 [2] */
5806                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5807                 /* IP2_24_23 [2] */
5808                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5809                 /* IP2_22_21 [2] */
5810                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5811                 /* IP2_20_19 [2] */
5812                 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5813                 /* IP2_18_16 [3] */
5814                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5815                 0, 0,
5816                 /* IP2_15_13 [3] */
5817                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5818                 0, 0, 0,
5819                 /* IP2_12_10 [3] */
5820                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5821                 0, 0, 0,
5822                 /* IP2_9_7 [3] */
5823                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5824                 0, 0, 0,
5825                 /* IP2_6_5 [2] */
5826                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5827                 /* IP2_4_3 [2] */
5828                 FN_A20, FN_SPCLK, 0, 0,
5829                 /* IP2_2_0 [3] */
5830                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5831                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5832         },
5833         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5834                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5835                 /* IP3_31 [1] */
5836                 0, 0,
5837                 /* IP3_30_28 [3] */
5838                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5839                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5840                 0, 0, 0,
5841                 /* IP3_27_25 [3] */
5842                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5843                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5844                 0, 0, 0,
5845                 /* IP3_24_22 [3] */
5846                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5847                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5848                 /* IP3_21_20 [2] */
5849                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5850                 /* IP3_19_18 [2] */
5851                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5852                 /* IP3_17_16 [2] */
5853                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5854                 /* IP3_15_14 [2] */
5855                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5856                 /* IP3_13_12 [2] */
5857                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5858                 /* IP3_11_9 [3] */
5859                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5860                 0, 0, 0,
5861                 /* IP3_8_6 [3] */
5862                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5863                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5864                 /* IP3_5_3 [3] */
5865                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5866                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5867                 /* IP3_2_0 [3] */
5868                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5869                 0, 0, 0, }
5870         },
5871         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5872                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5873                 /* IP4_31 [1] */
5874                 0, 0,
5875                 /* IP4_30_28 [3] */
5876                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5877                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5878                 0, 0,
5879                 /* IP4_27_26 [2] */
5880                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5881                 /* IP4_25_24 [2] */
5882                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5883                 /* IP4_23_22 [2] */
5884                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5885                 /* IP4_21 [1] */
5886                 FN_SSI_SDATA3, 0,
5887                 /* IP4_20 [1] */
5888                 FN_SSI_WS34, 0,
5889                 /* IP4_19 [1] */
5890                 FN_SSI_SCK34, 0,
5891                 /* IP4_18_16 [3] */
5892                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5893                 0, 0, 0, 0,
5894                 /* IP4_15_13 [3] */
5895                 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5896                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5897                 0, 0,
5898                 /* IP4_12_10 [3] */
5899                 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5900                 0, 0, 0,
5901                 /* IP4_9_8 [2] */
5902                 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5903                 /* IP4_7_5 [3] */
5904                 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5905                 FN_GLO_I1_D, 0, 0, 0,
5906                 /* IP4_4_2 [3] */
5907                 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5908                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5909                 0, 0, 0,
5910                 /* IP4_1_0 [2] */
5911                 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
5912         },
5913         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5914                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5915                 /* IP5_31_29 [3] */
5916                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5917                 0, 0, 0, 0, 0,
5918                 /* IP5_28_26 [3] */
5919                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5920                 0, 0, 0, 0,
5921                 /* IP5_25_24 [2] */
5922                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5923                 /* IP5_23_22 [2] */
5924                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5925                 /* IP5_21_20 [2] */
5926                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5927                 /* IP5_19_17 [3] */
5928                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5929                 0, 0, 0, 0,
5930                 /* IP5_16_15 [2] */
5931                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5932                 /* IP5_14_12 [3] */
5933                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5934                 0, 0, 0, 0,
5935                 /* IP5_11_9 [3] */
5936                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5937                 0, 0, 0, 0,
5938                 /* IP5_8_6 [3] */
5939                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5940                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5941                 0, 0,
5942                 /* IP5_5_3 [3] */
5943                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5944                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5945                 0, 0,
5946                 /* IP5_2_0 [3] */
5947                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5948                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5949                 0, 0, }
5950         },
5951         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5952                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5953                 /* IP6_31_30 [2] */
5954                 0, 0, 0, 0,
5955                 /* IP6_29_27 [3] */
5956                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5957                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5958                 0, 0, 0,
5959                 /* IP6_26_24 [3] */
5960                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5961                 FN_GPS_CLK_C, FN_GPS_CLK_D,
5962                 0, 0, 0,
5963                 /* IP6_23_21 [3] */
5964                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5965                 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5966                 0, 0, 0,
5967                 /* IP6_20_19 [2] */
5968                 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
5969                 /* IP6_18_16 [3] */
5970                 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
5971                 FN_INTC_IRQ4_N, 0, 0, 0,
5972                 /* IP6_15_14 [2] */
5973                 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5974                 /* IP6_13_12 [2] */
5975                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5976                 /* IP6_11_10 [2] */
5977                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5978                 /* IP6_9_8 [2] */
5979                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5980                 /* IP6_7_6 [2] */
5981                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5982                 /* IP6_5_3 [3] */
5983                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5984                 FN_SCIFA2_RXD, FN_FMIN_E,
5985                 0, 0,
5986                 /* IP6_2_0 [3] */
5987                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5988                 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5989                 0, 0, }
5990         },
5991         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5992                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5993                 /* IP7_31_30 [2] */
5994                 0, 0, 0, 0,
5995                 /* IP7_29_27 [3] */
5996                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5997                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5998                 0, 0,
5999                 /* IP7_26_24 [3] */
6000                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
6001                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
6002                 0, 0,
6003                 /* IP7_23_21 [3] */
6004                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
6005                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
6006                 0, 0,
6007                 /* IP7_20_19 [2] */
6008                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6009                 /* IP7_18_17 [2] */
6010                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6011                 /* IP7_16_15 [2] */
6012                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6013                 /* IP7_14_13 [2] */
6014                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6015                 /* IP7_12_11 [2] */
6016                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6017                 /* IP7_10_9 [2] */
6018                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6019                 /* IP7_8_6 [3] */
6020                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
6021                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
6022                 0, 0,
6023                 /* IP7_5_3 [3] */
6024                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
6025                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
6026                 0, 0,
6027                 /* IP7_2_0 [3] */
6028                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
6029                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
6030                 0, 0, }
6031         },
6032         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6033                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
6034                 /* IP8_31 [1] */
6035                 0, 0,
6036                 /* IP8_30_28 [3] */
6037                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
6038                 0, 0, 0,
6039                 /* IP8_27_26 [2] */
6040                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
6041                 /* IP8_25_24 [2] */
6042                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6043                 /* IP8_23_21 [3] */
6044                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
6045                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
6046                 0, 0,
6047                 /* IP8_20_18 [3] */
6048                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
6049                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6050                 0, 0,
6051                 /* IP8_17_15 [3] */
6052                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6053                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6054                 0, 0,
6055                 /* IP8_14_12 [3] */
6056                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6057                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6058                 0, 0, 0,
6059                 /* IP8_11_9 [3] */
6060                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6061                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6062                 0, 0, 0,
6063                 /* IP8_8_6 [3] */
6064                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6065                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6066                 0, 0,
6067                 /* IP8_5_3 [3] */
6068                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6069                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6070                 0, 0,
6071                 /* IP8_2_0 [3] */
6072                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6073                 0, 0, 0, }
6074         },
6075         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6076                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
6077                 /* IP9_31_29 [3] */
6078                 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6079                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6080                 /* IP9_28_27 [2] */
6081                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6082                 /* IP9_26_25 [2] */
6083                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6084                 /* IP9_24_23 [2] */
6085                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6086                 /* IP9_22_21 [2] */
6087                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6088                 /* IP9_20_19 [2] */
6089                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6090                 /* IP9_18_17 [2] */
6091                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6092                 /* IP9_16 [1] */
6093                 FN_DU1_DISP, FN_QPOLA,
6094                 /* IP9_15_13 [3] */
6095                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6096                 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6097                 0, 0, 0,
6098                 /* IP9_12 [1] */
6099                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6100                 /* IP9_11 [1] */
6101                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6102                 /* IP9_10_8 [3] */
6103                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6104                 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6105                 0, 0,
6106                 /* IP9_7 [1] */
6107                 FN_DU1_DOTCLKOUT0, FN_QCLK,
6108                 /* IP9_6 [1] */
6109                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6110                 /* IP9_5_3 [3] */
6111                 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6112                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6113                 0, 0, 0,
6114                 /* IP9_2_0 [3] */
6115                 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6116                 0, 0, 0, }
6117         },
6118         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6119                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
6120                 /* IP10_31_29 [3] */
6121                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6122                 0, 0, 0,
6123                 /* IP10_28_27 [2] */
6124                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6125                 /* IP10_26_25 [2] */
6126                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6127                 /* IP10_24_22 [3] */
6128                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6129                 0, 0, 0,
6130                 /* IP10_21_19 [3] */
6131                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6132                 FN_TS_SDATA0_C, FN_ATACS11_N,
6133                 0, 0, 0,
6134                 /* IP10_18_17 [2] */
6135                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6136                 /* IP10_16_15 [2] */
6137                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6138                 /* IP10_14_12 [3] */
6139                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6140                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6141                 /* IP10_11_9 [3] */
6142                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6143                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6144                 0, 0,
6145                 /* IP10_8_6 [3] */
6146                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6147                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6148                 /* IP10_5_3 [3] */
6149                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6150                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6151                 /* IP10_2_0 [3] */
6152                 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6153                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
6154         },
6155         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6156                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
6157                              3, 3, 3, 3, 3) {
6158                 /* IP11_31_30 [2] */
6159                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6160                 /* IP11_29_28 [2] */
6161                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6162                 /* IP11_27 [1] */
6163                 FN_VI1_DATA7, FN_AVB_MDC,
6164                 /* IP11_26 [1] */
6165                 FN_VI1_DATA6, FN_AVB_MAGIC,
6166                 /* IP11_25 [1] */
6167                 FN_VI1_DATA5, FN_AVB_RX_DV,
6168                 /* IP11_24 [1] */
6169                 FN_VI1_DATA4, FN_AVB_MDIO,
6170                 /* IP11_23 [1] */
6171                 FN_VI1_DATA3, FN_AVB_RX_ER,
6172                 /* IP11_22 [1] */
6173                 FN_VI1_DATA2, FN_AVB_RXD7,
6174                 /* IP11_21 [1] */
6175                 FN_VI1_DATA1, FN_AVB_RXD6,
6176                 /* IP11_20 [1] */
6177                 FN_VI1_DATA0, FN_AVB_RXD5,
6178                 /* IP11_19 [1] */
6179                 FN_VI1_CLK, FN_AVB_RXD4,
6180                 /* IP11_18_17 [2] */
6181                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6182                 /* IP11_16_15 [2] */
6183                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6184                 /* IP11_14_12 [3] */
6185                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6186                 FN_RX4_B, FN_SCIFA4_RXD_B,
6187                 0, 0, 0,
6188                 /* IP11_11_9 [3] */
6189                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6190                 FN_TX4_B, FN_SCIFA4_TXD_B,
6191                 0, 0, 0,
6192                 /* IP11_8_6 [3] */
6193                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6194                 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6195                 /* IP11_5_3 [3] */
6196                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6197                 0, 0, 0,
6198                 /* IP11_2_0 [3] */
6199                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6200                 FN_I2C1_SDA_D, 0, 0, 0, }
6201         },
6202         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6203                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6204                 /* IP12_31_30 [2] */
6205                 0, 0, 0, 0,
6206                 /* IP12_29_27 [3] */
6207                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6208                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6209                 0, 0, 0,
6210                 /* IP12_26_24 [3] */
6211                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6212                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6213                 0, 0, 0,
6214                 /* IP12_23_22 [2] */
6215                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6216                 /* IP12_21_20 [2] */
6217                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6218                 /* IP12_19_18 [2] */
6219                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6220                 /* IP12_17_16 [2] */
6221                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6222                 /* IP12_15_13 [3] */
6223                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6224                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6225                 0, 0, 0,
6226                 /* IP12_12_10 [3] */
6227                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6228                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6229                 0, 0, 0,
6230                 /* IP12_9_7 [3] */
6231                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6232                 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6233                 0, 0, 0,
6234                 /* IP12_6_4 [3] */
6235                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6236                 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6237                 0, 0, 0,
6238                 /* IP12_3_2 [2] */
6239                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6240                 /* IP12_1_0 [2] */
6241                 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
6242         },
6243         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6244                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6245                              3, 2, 2, 3) {
6246                 /* IP13_31 [1] */
6247                 0, 0,
6248                 /* IP13_30_28 [3] */
6249                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6250                 0, 0, 0, 0,
6251                 /* IP13_27 [1] */
6252                 FN_SD1_DATA3, FN_IERX_B,
6253                 /* IP13_26 [1] */
6254                 FN_SD1_DATA2, FN_IECLK_B,
6255                 /* IP13_25 [1] */
6256                 FN_SD1_DATA1, FN_IETX_B,
6257                 /* IP13_24_23 [2] */
6258                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6259                 /* IP13_22 [1] */
6260                 FN_SD1_CMD, FN_REMOCON_B,
6261                 /* IP13_21_19 [3] */
6262                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6263                 FN_SCIFA5_RXD_B, FN_RX3_C,
6264                 0, 0,
6265                 /* IP13_18_16 [3] */
6266                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6267                 FN_SCIFA5_TXD_B, FN_TX3_C,
6268                 0, 0,
6269                 /* IP13_15 [1] */
6270                 FN_SD0_DATA3, FN_SSL_B,
6271                 /* IP13_14 [1] */
6272                 FN_SD0_DATA2, FN_IO3_B,
6273                 /* IP13_13 [1] */
6274                 FN_SD0_DATA1, FN_IO2_B,
6275                 /* IP13_12 [1] */
6276                 FN_SD0_DATA0, FN_MISO_IO1_B,
6277                 /* IP13_11 [1] */
6278                 FN_SD0_CMD, FN_MOSI_IO0_B,
6279                 /* IP13_10 [1] */
6280                 FN_SD0_CLK, FN_SPCLK_B,
6281                 /* IP13_9_7 [3] */
6282                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6283                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6284                 0, 0, 0,
6285                 /* IP13_6_5 [2] */
6286                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6287                 /* IP13_4_3 [2] */
6288                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6289                 /* IP13_2_0 [3] */
6290                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6291                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6292                 0, 0, 0, }
6293         },
6294         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6295                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6296                 /* IP14_31_29 [3] */
6297                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6298                 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6299                 /* IP14_28_26 [3] */
6300                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6301                 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6302                 /* IP14_25_23 [3] */
6303                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6304                 0, 0, 0,
6305                 /* IP14_22_20 [3] */
6306                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6307                 0, 0, 0,
6308                 /* IP14_19_17 [3] */
6309                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6310                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6311                 0, 0,
6312                 /* IP14_16_14 [3] */
6313                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6314                 FN_VI1_CLK_C, FN_VI1_G0_B,
6315                 0, 0,
6316                 /* IP14_13_11 [3] */
6317                 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6318                 0, 0, 0,
6319                 /* IP14_10_8 [3] */
6320                 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6321                 0, 0, 0,
6322                 /* IP14_7 [1] */
6323                 FN_SD2_DATA3, FN_MMC_D3,
6324                 /* IP14_6 [1] */
6325                 FN_SD2_DATA2, FN_MMC_D2,
6326                 /* IP14_5 [1] */
6327                 FN_SD2_DATA1, FN_MMC_D1,
6328                 /* IP14_4 [1] */
6329                 FN_SD2_DATA0, FN_MMC_D0,
6330                 /* IP14_3 [1] */
6331                 FN_SD2_CMD, FN_MMC_CMD,
6332                 /* IP14_2 [1] */
6333                 FN_SD2_CLK, FN_MMC_CLK,
6334                 /* IP14_1_0 [2] */
6335                 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
6336         },
6337         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6338                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6339                 /* IP15_31_30 [2] */
6340                 0, 0, 0, 0,
6341                 /* IP15_29_27 [3] */
6342                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6343                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6344                 0, 0,
6345                 /* IP15_26_24 [3] */
6346                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6347                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6348                 0, 0,
6349                 /* IP15_23_21 [3] */
6350                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6351                 FN_TCLK2, FN_VI1_DATA3_C, 0,
6352                 /* IP15_20_18 [3] */
6353                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6354                 0, 0, 0,
6355                 /* IP15_17_15 [3] */
6356                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6357                 FN_TCLK1, FN_VI1_DATA1_C,
6358                 0, 0,
6359                 /* IP15_14_12 [3] */
6360                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6361                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6362                 0, 0,
6363                 /* IP15_11_9 [3] */
6364                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6365                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6366                 0, 0,
6367                 /* IP15_8_6 [3] */
6368                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6369                 FN_PWM5_B, FN_SCIFA3_TXD_C,
6370                 0, 0, 0,
6371                 /* IP15_5_4 [2] */
6372                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6373                 /* IP15_3_2 [2] */
6374                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6375                 /* IP15_1_0 [2] */
6376                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6377         },
6378         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6379                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6380                 /* IP16_31_28 [4] */
6381                 0, 0, 0, 0, 0, 0, 0, 0,
6382                 0, 0, 0, 0, 0, 0, 0, 0,
6383                 /* IP16_27_24 [4] */
6384                 0, 0, 0, 0, 0, 0, 0, 0,
6385                 0, 0, 0, 0, 0, 0, 0, 0,
6386                 /* IP16_23_20 [4] */
6387                 0, 0, 0, 0, 0, 0, 0, 0,
6388                 0, 0, 0, 0, 0, 0, 0, 0,
6389                 /* IP16_19_16 [4] */
6390                 0, 0, 0, 0, 0, 0, 0, 0,
6391                 0, 0, 0, 0, 0, 0, 0, 0,
6392                 /* IP16_15_12 [4] */
6393                 0, 0, 0, 0, 0, 0, 0, 0,
6394                 0, 0, 0, 0, 0, 0, 0, 0,
6395                 /* IP16_11_10 [2] */
6396                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6397                 /* IP16_9_8 [2] */
6398                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6399                 /* IP16_7_6 [2] */
6400                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6401                 /* IP16_5_3 [3] */
6402                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6403                 FN_GLO_SS_C, FN_VI1_DATA7_C,
6404                 0, 0, 0,
6405                 /* IP16_2_0 [3] */
6406                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6407                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6408                 0, 0, 0, }
6409         },
6410         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6411                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6412                              3, 2, 2, 2, 1, 2, 2, 2) {
6413                 /* RESERVED [1] */
6414                 0, 0,
6415                 /* SEL_SCIF1 [2] */
6416                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6417                 /* SEL_SCIFB [2] */
6418                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6419                 /* SEL_SCIFB2 [2] */
6420                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6421                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6422                 /* SEL_SCIFB1 [3] */
6423                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6424                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6425                 0, 0, 0, 0,
6426                 /* SEL_SCIFA1 [2] */
6427                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6428                 /* SEL_SSI9 [1] */
6429                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6430                 /* SEL_SCFA [1] */
6431                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6432                 /* SEL_QSP [1] */
6433                 FN_SEL_QSP_0, FN_SEL_QSP_1,
6434                 /* SEL_SSI7 [1] */
6435                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6436                 /* SEL_HSCIF1 [3] */
6437                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6438                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6439                 0, 0, 0,
6440                 /* RESERVED [2] */
6441                 0, 0, 0, 0,
6442                 /* SEL_VI1 [2] */
6443                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6444                 /* RESERVED [2] */
6445                 0, 0, 0, 0,
6446                 /* SEL_TMU [1] */
6447                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6448                 /* SEL_LBS [2] */
6449                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6450                 /* SEL_TSIF0 [2] */
6451                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6452                 /* SEL_SOF0 [2] */
6453                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6454         },
6455         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6456                              3, 1, 1, 3, 2, 1, 1, 2, 2,
6457                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6458                 /* SEL_SCIF0 [3] */
6459                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6460                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6461                 0, 0, 0,
6462                 /* RESERVED [1] */
6463                 0, 0,
6464                 /* SEL_SCIF [1] */
6465                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6466                 /* SEL_CAN0 [3] */
6467                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6468                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6469                 0, 0,
6470                 /* SEL_CAN1 [2] */
6471                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6472                 /* RESERVED [1] */
6473                 0, 0,
6474                 /* SEL_SCIFA2 [1] */
6475                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6476                 /* SEL_SCIF4 [2] */
6477                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6478                 /* RESERVED [2] */
6479                 0, 0, 0, 0,
6480                 /* SEL_ADG [1] */
6481                 FN_SEL_ADG_0, FN_SEL_ADG_1,
6482                 /* SEL_FM [3] */
6483                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6484                 FN_SEL_FM_3, FN_SEL_FM_4,
6485                 0, 0, 0,
6486                 /* SEL_SCIFA5 [2] */
6487                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6488                 /* RESERVED [1] */
6489                 0, 0,
6490                 /* SEL_GPS [2] */
6491                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6492                 /* SEL_SCIFA4 [2] */
6493                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6494                 /* SEL_SCIFA3 [2] */
6495                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6496                 /* SEL_SIM [1] */
6497                 FN_SEL_SIM_0, FN_SEL_SIM_1,
6498                 /* RESERVED [1] */
6499                 0, 0,
6500                 /* SEL_SSI8 [1] */
6501                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6502         },
6503         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6504                              2, 2, 2, 2, 2, 2, 2, 2,
6505                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
6506                 /* SEL_HSCIF2 [2] */
6507                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6508                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6509                 /* SEL_CANCLK [2] */
6510                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6511                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6512                 /* SEL_IIC1 [2] */
6513                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6514                 /* SEL_IIC0 [2] */
6515                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6516                 /* SEL_I2C4 [2] */
6517                 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6518                 /* SEL_I2C3 [2] */
6519                 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6520                 /* SEL_SCIF3 [2] */
6521                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6522                 /* SEL_IEB [2] */
6523                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6524                 /* SEL_MMC [1] */
6525                 FN_SEL_MMC_0, FN_SEL_MMC_1,
6526                 /* SEL_SCIF5 [1] */
6527                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6528                 /* RESERVED [2] */
6529                 0, 0, 0, 0,
6530                 /* SEL_I2C2 [2] */
6531                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6532                 /* SEL_I2C1 [3] */
6533                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6534                 FN_SEL_I2C1_4,
6535                 0, 0, 0,
6536                 /* SEL_I2C0 [2] */
6537                 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6538                 /* RESERVED [2] */
6539                 0, 0, 0, 0,
6540                 /* RESERVED [2] */
6541                 0, 0, 0, 0,
6542                 /* RESERVED [1] */
6543                 0, 0, }
6544         },
6545         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6546                              3, 2, 2, 1, 1, 1, 1, 3, 2,
6547                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
6548                 /* SEL_SOF1 [3] */
6549                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6550                 FN_SEL_SOF1_4,
6551                 0, 0, 0,
6552                 /* SEL_HSCIF0 [2] */
6553                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6554                 /* SEL_DIS [2] */
6555                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6556                 /* RESERVED [1] */
6557                 0, 0,
6558                 /* SEL_RAD [1] */
6559                 FN_SEL_RAD_0, FN_SEL_RAD_1,
6560                 /* SEL_RCN [1] */
6561                 FN_SEL_RCN_0, FN_SEL_RCN_1,
6562                 /* SEL_RSP [1] */
6563                 FN_SEL_RSP_0, FN_SEL_RSP_1,
6564                 /* SEL_SCIF2 [3] */
6565                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6566                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6567                 0, 0, 0,
6568                 /* RESERVED [2] */
6569                 0, 0, 0, 0,
6570                 /* RESERVED [2] */
6571                 0, 0, 0, 0,
6572                 /* SEL_SOF2 [3] */
6573                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6574                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6575                 0, 0, 0,
6576                 /* RESERVED [1] */
6577                 0, 0,
6578                 /* SEL_SSI1 [1] */
6579                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6580                 /* SEL_SSI0 [1] */
6581                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6582                 /* SEL_SSP [2] */
6583                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6584                 /* RESERVED [2] */
6585                 0, 0, 0, 0,
6586                 /* RESERVED [2] */
6587                 0, 0, 0, 0,
6588                 /* RESERVED [2] */
6589                 0, 0, 0, 0, }
6590         },
6591         { },
6592 };
6593
6594 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6595 {
6596         if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6597                 return -EINVAL;
6598
6599         *pocctrl = 0xe606008c;
6600
6601         return 31 - (pin & 0x1f);
6602 }
6603
6604 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6605         .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6606 };
6607
6608 #ifdef CONFIG_PINCTRL_PFC_R8A7743
6609 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
6610         .name = "r8a77430_pfc",
6611         .ops = &r8a7791_pinmux_ops,
6612         .unlock_reg = 0xe6060000, /* PMMR */
6613
6614         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6615
6616         .pins = pinmux_pins,
6617         .nr_pins = ARRAY_SIZE(pinmux_pins),
6618         .groups = pinmux_groups.common,
6619         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6620         .functions = pinmux_functions.common,
6621         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6622
6623         .cfg_regs = pinmux_config_regs,
6624
6625         .pinmux_data = pinmux_data,
6626         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6627 };
6628 #endif
6629
6630 #ifdef CONFIG_PINCTRL_PFC_R8A7744
6631 const struct sh_pfc_soc_info r8a7744_pinmux_info = {
6632         .name = "r8a77440_pfc",
6633         .ops = &r8a7791_pinmux_ops,
6634         .unlock_reg = 0xe6060000, /* PMMR */
6635
6636         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6637
6638         .pins = pinmux_pins,
6639         .nr_pins = ARRAY_SIZE(pinmux_pins),
6640         .groups = pinmux_groups.common,
6641         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6642         .functions = pinmux_functions.common,
6643         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6644
6645         .cfg_regs = pinmux_config_regs,
6646
6647         .pinmux_data = pinmux_data,
6648         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6649 };
6650 #endif
6651
6652 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6653 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6654         .name = "r8a77910_pfc",
6655         .ops = &r8a7791_pinmux_ops,
6656         .unlock_reg = 0xe6060000, /* PMMR */
6657
6658         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6659
6660         .pins = pinmux_pins,
6661         .nr_pins = ARRAY_SIZE(pinmux_pins),
6662         .groups = pinmux_groups.common,
6663         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6664                      ARRAY_SIZE(pinmux_groups.automotive),
6665         .functions = pinmux_functions.common,
6666         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6667                         ARRAY_SIZE(pinmux_functions.automotive),
6668
6669         .cfg_regs = pinmux_config_regs,
6670
6671         .pinmux_data = pinmux_data,
6672         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6673 };
6674 #endif
6675
6676 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6677 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6678         .name = "r8a77930_pfc",
6679         .ops = &r8a7791_pinmux_ops,
6680         .unlock_reg = 0xe6060000, /* PMMR */
6681
6682         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6683
6684         .pins = pinmux_pins,
6685         .nr_pins = ARRAY_SIZE(pinmux_pins),
6686         .groups = pinmux_groups.common,
6687         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6688                      ARRAY_SIZE(pinmux_groups.automotive),
6689         .functions = pinmux_functions.common,
6690         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6691                         ARRAY_SIZE(pinmux_functions.automotive),
6692
6693         .cfg_regs = pinmux_config_regs,
6694
6695         .pinmux_data = pinmux_data,
6696         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6697 };
6698 #endif