drivers/pinctrl/qcom/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/reboot.h>
  31 #include <linux/pm.h>
  32 #include <linux/log2.h>
  33
  34 #include "../core.h"
  35 #include "../pinconf.h"
  36 #include "pinctrl-msm.h"
  37 #include "../pinctrl-utils.h"
  38
  39 #define MAX_NR_GPIO 300
  40 #define PS_HOLD_OFFSET 0x820
  41
  42 /**
  43  * struct msm_pinctrl - state for a pinctrl-msm device
  44  * @dev:            device handle.
  45  * @pctrl:          pinctrl handle.
  46  * @chip:           gpiochip handle.
  47  * @restart_nb:     restart notifier block.
  48  * @irq:            parent irq for the TLMM irq_chip.
  49  * @lock:           Spinlock to protect register resources as well
  50  *                  as msm_pinctrl data structures.
  51  * @enabled_irqs:   Bitmap of currently enabled irqs.
  52  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  53  *                  detection.
  54  * @soc;            Reference to soc_data of platform specific data.
  55  * @regs:           Base address for the TLMM register map.
  56  */
  57 struct msm_pinctrl {
  58         struct device *dev;
  59         struct pinctrl_dev *pctrl;
  60         struct gpio_chip chip;
  61         struct notifier_block restart_nb;
  62         int irq;
  63
  64         raw_spinlock_t lock;
  65
  66         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  67         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  68
  69         const struct msm_pinctrl_soc_data *soc;
  70         void __iomem *regs;
  71 };
  72
  73 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  74 {
  75         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  76
  77         return pctrl->soc->ngroups;
  78 }
  79
  80 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  81                                       unsigned group)
  82 {
  83         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  84
  85         return pctrl->soc->groups[group].name;
  86 }
  87
  88 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  89                               unsigned group,
  90                               const unsigned **pins,
  91                               unsigned *num_pins)
  92 {
  93         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  94
  95         *pins = pctrl->soc->groups[group].pins;
  96         *num_pins = pctrl->soc->groups[group].npins;
  97         return 0;
  98 }
  99
 100 static const struct pinctrl_ops msm_pinctrl_ops = {
 101         .get_groups_count       = msm_get_groups_count,
 102         .get_group_name         = msm_get_group_name,
 103         .get_group_pins         = msm_get_group_pins,
 104         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 105         .dt_free_map            = pinctrl_utils_free_map,
 106 };
 107
 108 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 109 {
 110         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 111
 112         return pctrl->soc->nfunctions;
 113 }
 114
 115 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 116                                          unsigned function)
 117 {
 118         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 119
 120         return pctrl->soc->functions[function].name;
 121 }
 122
 123 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 124                                    unsigned function,
 125                                    const char * const **groups,
 126                                    unsigned * const num_groups)
 127 {
 128         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 129
 130         *groups = pctrl->soc->functions[function].groups;
 131         *num_groups = pctrl->soc->functions[function].ngroups;
 132         return 0;
 133 }
 134
 135 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 136                               unsigned function,
 137                               unsigned group)
 138 {
 139         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 140         const struct msm_pingroup *g;
 141         unsigned long flags;
 142         u32 val, mask;
 143         int i;
 144
 145         g = &pctrl->soc->groups[group];
 146         mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
 147
 148         for (i = 0; i < g->nfuncs; i++) {
 149                 if (g->funcs[i] == function)
 150                         break;
 151         }
 152
 153         if (WARN_ON(i == g->nfuncs))
 154                 return -EINVAL;
 155
 156         raw_spin_lock_irqsave(&pctrl->lock, flags);
 157
 158         val = readl(pctrl->regs + g->ctl_reg);
 159         val &= ~mask;
 160         val |= i << g->mux_bit;
 161         writel(val, pctrl->regs + g->ctl_reg);
 162
 163         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 164
 165         return 0;
 166 }
 167
 168 static const struct pinmux_ops msm_pinmux_ops = {
 169         .get_functions_count    = msm_get_functions_count,
 170         .get_function_name      = msm_get_function_name,
 171         .get_function_groups    = msm_get_function_groups,
 172         .set_mux                = msm_pinmux_set_mux,
 173 };
 174
 175 static int msm_config_reg(struct msm_pinctrl *pctrl,
 176                           const struct msm_pingroup *g,
 177                           unsigned param,
 178                           unsigned *mask,
 179                           unsigned *bit)
 180 {
 181         switch (param) {
 182         case PIN_CONFIG_BIAS_DISABLE:
 183         case PIN_CONFIG_BIAS_PULL_DOWN:
 184         case PIN_CONFIG_BIAS_BUS_HOLD:
 185         case PIN_CONFIG_BIAS_PULL_UP:
 186                 *bit = g->pull_bit;
 187                 *mask = 3;
 188                 break;
 189         case PIN_CONFIG_DRIVE_STRENGTH:
 190                 *bit = g->drv_bit;
 191                 *mask = 7;
 192                 break;
 193         case PIN_CONFIG_OUTPUT:
 194         case PIN_CONFIG_INPUT_ENABLE:
 195                 *bit = g->oe_bit;
 196                 *mask = 1;
 197                 break;
 198         default:
 199                 return -ENOTSUPP;
 200         }
 201
 202         return 0;
 203 }
 204
 205 #define MSM_NO_PULL     0
 206 #define MSM_PULL_DOWN   1
 207 #define MSM_KEEPER      2
 208 #define MSM_PULL_UP     3
 209
 210 static unsigned msm_regval_to_drive(u32 val)
 211 {
 212         return (val + 1) * 2;
 213 }
 214
 215 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 216                                 unsigned int group,
 217                                 unsigned long *config)
 218 {
 219         const struct msm_pingroup *g;
 220         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 221         unsigned param = pinconf_to_config_param(*config);
 222         unsigned mask;
 223         unsigned arg;
 224         unsigned bit;
 225         int ret;
 226         u32 val;
 227
 228         g = &pctrl->soc->groups[group];
 229
 230         ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 231         if (ret < 0)
 232                 return ret;
 233
 234         val = readl(pctrl->regs + g->ctl_reg);
 235         arg = (val >> bit) & mask;
 236
 237         /* Convert register value to pinconf value */
 238         switch (param) {
 239         case PIN_CONFIG_BIAS_DISABLE:
 240                 arg = arg == MSM_NO_PULL;
 241                 break;
 242         case PIN_CONFIG_BIAS_PULL_DOWN:
 243                 arg = arg == MSM_PULL_DOWN;
 244                 break;
 245         case PIN_CONFIG_BIAS_BUS_HOLD:
 246                 arg = arg == MSM_KEEPER;
 247                 break;
 248         case PIN_CONFIG_BIAS_PULL_UP:
 249                 arg = arg == MSM_PULL_UP;
 250                 break;
 251         case PIN_CONFIG_DRIVE_STRENGTH:
 252                 arg = msm_regval_to_drive(arg);
 253                 break;
 254         case PIN_CONFIG_OUTPUT:
 255                 /* Pin is not output */
 256                 if (!arg)
 257                         return -EINVAL;
 258
 259                 val = readl(pctrl->regs + g->io_reg);
 260                 arg = !!(val & BIT(g->in_bit));
 261                 break;
 262         case PIN_CONFIG_INPUT_ENABLE:
 263                 /* Pin is output */
 264                 if (arg)
 265                         return -EINVAL;
 266                 arg = 1;
 267                 break;
 268         default:
 269                 return -ENOTSUPP;
 270         }
 271
 272         *config = pinconf_to_config_packed(param, arg);
 273
 274         return 0;
 275 }
 276
 277 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 278                                 unsigned group,
 279                                 unsigned long *configs,
 280                                 unsigned num_configs)
 281 {
 282         const struct msm_pingroup *g;
 283         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 284         unsigned long flags;
 285         unsigned param;
 286         unsigned mask;
 287         unsigned arg;
 288         unsigned bit;
 289         int ret;
 290         u32 val;
 291         int i;
 292
 293         g = &pctrl->soc->groups[group];
 294
 295         for (i = 0; i < num_configs; i++) {
 296                 param = pinconf_to_config_param(configs[i]);
 297                 arg = pinconf_to_config_argument(configs[i]);
 298
 299                 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 300                 if (ret < 0)
 301                         return ret;
 302
 303                 /* Convert pinconf values to register values */
 304                 switch (param) {
 305                 case PIN_CONFIG_BIAS_DISABLE:
 306                         arg = MSM_NO_PULL;
 307                         break;
 308                 case PIN_CONFIG_BIAS_PULL_DOWN:
 309                         arg = MSM_PULL_DOWN;
 310                         break;
 311                 case PIN_CONFIG_BIAS_BUS_HOLD:
 312                         arg = MSM_KEEPER;
 313                         break;
 314                 case PIN_CONFIG_BIAS_PULL_UP:
 315                         arg = MSM_PULL_UP;
 316                         break;
 317                 case PIN_CONFIG_DRIVE_STRENGTH:
 318                         /* Check for invalid values */
 319                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 320                                 arg = -1;
 321                         else
 322                                 arg = (arg / 2) - 1;
 323                         break;
 324                 case PIN_CONFIG_OUTPUT:
 325                         /* set output value */
 326                         raw_spin_lock_irqsave(&pctrl->lock, flags);
 327                         val = readl(pctrl->regs + g->io_reg);
 328                         if (arg)
 329                                 val |= BIT(g->out_bit);
 330                         else
 331                                 val &= ~BIT(g->out_bit);
 332                         writel(val, pctrl->regs + g->io_reg);
 333                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 334
 335                         /* enable output */
 336                         arg = 1;
 337                         break;
 338                 case PIN_CONFIG_INPUT_ENABLE:
 339                         /* disable output */
 340                         arg = 0;
 341                         break;
 342                 default:
 343                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 344                                 param);
 345                         return -EINVAL;
 346                 }
 347
 348                 /* Range-check user-supplied value */
 349                 if (arg & ~mask) {
 350                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 351                         return -EINVAL;
 352                 }
 353
 354                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 355                 val = readl(pctrl->regs + g->ctl_reg);
 356                 val &= ~(mask << bit);
 357                 val |= arg << bit;
 358                 writel(val, pctrl->regs + g->ctl_reg);
 359                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 360         }
 361
 362         return 0;
 363 }
 364
 365 static const struct pinconf_ops msm_pinconf_ops = {
 366         .is_generic             = true,
 367         .pin_config_group_get   = msm_config_group_get,
 368         .pin_config_group_set   = msm_config_group_set,
 369 };
 370
 371 static struct pinctrl_desc msm_pinctrl_desc = {
 372         .pctlops = &msm_pinctrl_ops,
 373         .pmxops = &msm_pinmux_ops,
 374         .confops = &msm_pinconf_ops,
 375         .owner = THIS_MODULE,
 376 };
 377
 378 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 379 {
 380         const struct msm_pingroup *g;
 381         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 382         unsigned long flags;
 383         u32 val;
 384
 385         g = &pctrl->soc->groups[offset];
 386
 387         raw_spin_lock_irqsave(&pctrl->lock, flags);
 388
 389         val = readl(pctrl->regs + g->ctl_reg);
 390         val &= ~BIT(g->oe_bit);
 391         writel(val, pctrl->regs + g->ctl_reg);
 392
 393         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 394
 395         return 0;
 396 }
 397
 398 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 399 {
 400         const struct msm_pingroup *g;
 401         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 402         unsigned long flags;
 403         u32 val;
 404
 405         g = &pctrl->soc->groups[offset];
 406
 407         raw_spin_lock_irqsave(&pctrl->lock, flags);
 408
 409         val = readl(pctrl->regs + g->io_reg);
 410         if (value)
 411                 val |= BIT(g->out_bit);
 412         else
 413                 val &= ~BIT(g->out_bit);
 414         writel(val, pctrl->regs + g->io_reg);
 415
 416         val = readl(pctrl->regs + g->ctl_reg);
 417         val |= BIT(g->oe_bit);
 418         writel(val, pctrl->regs + g->ctl_reg);
 419
 420         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 421
 422         return 0;
 423 }
 424
 425 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 426 {
 427         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 428         const struct msm_pingroup *g;
 429         u32 val;
 430
 431         g = &pctrl->soc->groups[offset];
 432
 433         val = readl(pctrl->regs + g->ctl_reg);
 434
 435         /* 0 = output, 1 = input */
 436         return val & BIT(g->oe_bit) ? 0 : 1;
 437 }
 438
 439 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 440 {
 441         const struct msm_pingroup *g;
 442         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 443         u32 val;
 444
 445         g = &pctrl->soc->groups[offset];
 446
 447         val = readl(pctrl->regs + g->io_reg);
 448         return !!(val & BIT(g->in_bit));
 449 }
 450
 451 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 452 {
 453         const struct msm_pingroup *g;
 454         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 455         unsigned long flags;
 456         u32 val;
 457
 458         g = &pctrl->soc->groups[offset];
 459
 460         raw_spin_lock_irqsave(&pctrl->lock, flags);
 461
 462         val = readl(pctrl->regs + g->io_reg);
 463         if (value)
 464                 val |= BIT(g->out_bit);
 465         else
 466                 val &= ~BIT(g->out_bit);
 467         writel(val, pctrl->regs + g->io_reg);
 468
 469         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 470 }
 471
 472 #ifdef CONFIG_DEBUG_FS
 473 #include <linux/seq_file.h>
 474
 475 static void msm_gpio_dbg_show_one(struct seq_file *s,
 476                                   struct pinctrl_dev *pctldev,
 477                                   struct gpio_chip *chip,
 478                                   unsigned offset,
 479                                   unsigned gpio)
 480 {
 481         const struct msm_pingroup *g;
 482         struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 483         unsigned func;
 484         int is_out;
 485         int drive;
 486         int pull;
 487         u32 ctl_reg;
 488
 489         static const char * const pulls[] = {
 490                 "no pull",
 491                 "pull down",
 492                 "keeper",
 493                 "pull up"
 494         };
 495
 496         g = &pctrl->soc->groups[offset];
 497         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 498
 499         is_out = !!(ctl_reg & BIT(g->oe_bit));
 500         func = (ctl_reg >> g->mux_bit) & 7;
 501         drive = (ctl_reg >> g->drv_bit) & 7;
 502         pull = (ctl_reg >> g->pull_bit) & 3;
 503
 504         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 505         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 506         seq_printf(s, " %s", pulls[pull]);
 507 }
 508
 509 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 510 {
 511         unsigned gpio = chip->base;
 512         unsigned i;
 513
 514         for (i = 0; i < chip->ngpio; i++, gpio++) {
 515                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 516                 seq_puts(s, "\n");
 517         }
 518 }
 519
 520 #else
 521 #define msm_gpio_dbg_show NULL
 522 #endif
 523
 524 static struct gpio_chip msm_gpio_template = {
 525         .direction_input  = msm_gpio_direction_input,
 526         .direction_output = msm_gpio_direction_output,
 527         .get_direction    = msm_gpio_get_direction,
 528         .get              = msm_gpio_get,
 529         .set              = msm_gpio_set,
 530         .request          = gpiochip_generic_request,
 531         .free             = gpiochip_generic_free,
 532         .dbg_show         = msm_gpio_dbg_show,
 533 };
 534
 535 /* For dual-edge interrupts in software, since some hardware has no
 536  * such support:
 537  *
 538  * At appropriate moments, this function may be called to flip the polarity
 539  * settings of both-edge irq lines to try and catch the next edge.
 540  *
 541  * The attempt is considered successful if:
 542  * - the status bit goes high, indicating that an edge was caught, or
 543  * - the input value of the gpio doesn't change during the attempt.
 544  * If the value changes twice during the process, that would cause the first
 545  * test to fail but would force the second, as two opposite
 546  * transitions would cause a detection no matter the polarity setting.
 547  *
 548  * The do-loop tries to sledge-hammer closed the timing hole between
 549  * the initial value-read and the polarity-write - if the line value changes
 550  * during that window, an interrupt is lost, the new polarity setting is
 551  * incorrect, and the first success test will fail, causing a retry.
 552  *
 553  * Algorithm comes from Google's msmgpio driver.
 554  */
 555 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 556                                           const struct msm_pingroup *g,
 557                                           struct irq_data *d)
 558 {
 559         int loop_limit = 100;
 560         unsigned val, val2, intstat;
 561         unsigned pol;
 562
 563         do {
 564                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 565
 566                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 567                 pol ^= BIT(g->intr_polarity_bit);
 568                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 569
 570                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 571                 intstat = readl(pctrl->regs + g->intr_status_reg);
 572                 if (intstat || (val == val2))
 573                         return;
 574         } while (loop_limit-- > 0);
 575         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 576                 val, val2);
 577 }
 578
 579 static void msm_gpio_irq_mask(struct irq_data *d)
 580 {
 581         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 582         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 583         const struct msm_pingroup *g;
 584         unsigned long flags;
 585         u32 val;
 586
 587         g = &pctrl->soc->groups[d->hwirq];
 588
 589         raw_spin_lock_irqsave(&pctrl->lock, flags);
 590
 591         val = readl(pctrl->regs + g->intr_cfg_reg);
 592         val &= ~BIT(g->intr_enable_bit);
 593         writel(val, pctrl->regs + g->intr_cfg_reg);
 594
 595         clear_bit(d->hwirq, pctrl->enabled_irqs);
 596
 597         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 598 }
 599
 600 static void msm_gpio_irq_unmask(struct irq_data *d)
 601 {
 602         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 603         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 604         const struct msm_pingroup *g;
 605         unsigned long flags;
 606         u32 val;
 607
 608         g = &pctrl->soc->groups[d->hwirq];
 609
 610         raw_spin_lock_irqsave(&pctrl->lock, flags);
 611
 612         val = readl(pctrl->regs + g->intr_cfg_reg);
 613         val |= BIT(g->intr_enable_bit);
 614         writel(val, pctrl->regs + g->intr_cfg_reg);
 615
 616         set_bit(d->hwirq, pctrl->enabled_irqs);
 617
 618         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 619 }
 620
 621 static void msm_gpio_irq_ack(struct irq_data *d)
 622 {
 623         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 624         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 625         const struct msm_pingroup *g;
 626         unsigned long flags;
 627         u32 val;
 628
 629         g = &pctrl->soc->groups[d->hwirq];
 630
 631         raw_spin_lock_irqsave(&pctrl->lock, flags);
 632
 633         val = readl(pctrl->regs + g->intr_status_reg);
 634         if (g->intr_ack_high)
 635                 val |= BIT(g->intr_status_bit);
 636         else
 637                 val &= ~BIT(g->intr_status_bit);
 638         writel(val, pctrl->regs + g->intr_status_reg);
 639
 640         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 641                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 642
 643         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 644 }
 645
 646 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 647 {
 648         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 649         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 650         const struct msm_pingroup *g;
 651         unsigned long flags;
 652         u32 val;
 653
 654         g = &pctrl->soc->groups[d->hwirq];
 655
 656         raw_spin_lock_irqsave(&pctrl->lock, flags);
 657
 658         /*
 659          * For hw without possibility of detecting both edges
 660          */
 661         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 662                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 663         else
 664                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 665
 666         /* Route interrupts to application cpu */
 667         val = readl(pctrl->regs + g->intr_target_reg);
 668         val &= ~(7 << g->intr_target_bit);
 669         val |= g->intr_target_kpss_val << g->intr_target_bit;
 670         writel(val, pctrl->regs + g->intr_target_reg);
 671
 672         /* Update configuration for gpio.
 673          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 674          * internal circuitry of TLMM, toggling the RAW_STATUS
 675          * could cause the INTR_STATUS to be set for EDGE interrupts.
 676          */
 677         val = readl(pctrl->regs + g->intr_cfg_reg);
 678         val |= BIT(g->intr_raw_status_bit);
 679         if (g->intr_detection_width == 2) {
 680                 val &= ~(3 << g->intr_detection_bit);
 681                 val &= ~(1 << g->intr_polarity_bit);
 682                 switch (type) {
 683                 case IRQ_TYPE_EDGE_RISING:
 684                         val |= 1 << g->intr_detection_bit;
 685                         val |= BIT(g->intr_polarity_bit);
 686                         break;
 687                 case IRQ_TYPE_EDGE_FALLING:
 688                         val |= 2 << g->intr_detection_bit;
 689                         val |= BIT(g->intr_polarity_bit);
 690                         break;
 691                 case IRQ_TYPE_EDGE_BOTH:
 692                         val |= 3 << g->intr_detection_bit;
 693                         val |= BIT(g->intr_polarity_bit);
 694                         break;
 695                 case IRQ_TYPE_LEVEL_LOW:
 696                         break;
 697                 case IRQ_TYPE_LEVEL_HIGH:
 698                         val |= BIT(g->intr_polarity_bit);
 699                         break;
 700                 }
 701         } else if (g->intr_detection_width == 1) {
 702                 val &= ~(1 << g->intr_detection_bit);
 703                 val &= ~(1 << g->intr_polarity_bit);
 704                 switch (type) {
 705                 case IRQ_TYPE_EDGE_RISING:
 706                         val |= BIT(g->intr_detection_bit);
 707                         val |= BIT(g->intr_polarity_bit);
 708                         break;
 709                 case IRQ_TYPE_EDGE_FALLING:
 710                         val |= BIT(g->intr_detection_bit);
 711                         break;
 712                 case IRQ_TYPE_EDGE_BOTH:
 713                         val |= BIT(g->intr_detection_bit);
 714                         val |= BIT(g->intr_polarity_bit);
 715                         break;
 716                 case IRQ_TYPE_LEVEL_LOW:
 717                         break;
 718                 case IRQ_TYPE_LEVEL_HIGH:
 719                         val |= BIT(g->intr_polarity_bit);
 720                         break;
 721                 }
 722         } else {
 723                 BUG();
 724         }
 725         writel(val, pctrl->regs + g->intr_cfg_reg);
 726
 727         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 728                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 729
 730         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 731
 732         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 733                 irq_set_handler_locked(d, handle_level_irq);
 734         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 735                 irq_set_handler_locked(d, handle_edge_irq);
 736
 737         return 0;
 738 }
 739
 740 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 741 {
 742         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 743         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 744         unsigned long flags;
 745
 746         raw_spin_lock_irqsave(&pctrl->lock, flags);
 747
 748         irq_set_irq_wake(pctrl->irq, on);
 749
 750         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 751
 752         return 0;
 753 }
 754
 755 static struct irq_chip msm_gpio_irq_chip = {
 756         .name           = "msmgpio",
 757         .irq_mask       = msm_gpio_irq_mask,
 758         .irq_unmask     = msm_gpio_irq_unmask,
 759         .irq_ack        = msm_gpio_irq_ack,
 760         .irq_set_type   = msm_gpio_irq_set_type,
 761         .irq_set_wake   = msm_gpio_irq_set_wake,
 762 };
 763
 764 static void msm_gpio_irq_handler(struct irq_desc *desc)
 765 {
 766         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 767         const struct msm_pingroup *g;
 768         struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 769         struct irq_chip *chip = irq_desc_get_chip(desc);
 770         int irq_pin;
 771         int handled = 0;
 772         u32 val;
 773         int i;
 774
 775         chained_irq_enter(chip, desc);
 776
 777         /*
 778          * Each pin has it's own IRQ status register, so use
 779          * enabled_irq bitmap to limit the number of reads.
 780          */
 781         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 782                 g = &pctrl->soc->groups[i];
 783                 val = readl(pctrl->regs + g->intr_status_reg);
 784                 if (val & BIT(g->intr_status_bit)) {
 785                         irq_pin = irq_find_mapping(gc->irqdomain, i);
 786                         generic_handle_irq(irq_pin);
 787                         handled++;
 788                 }
 789         }
 790
 791         /* No interrupts were flagged */
 792         if (handled == 0)
 793                 handle_bad_irq(desc);
 794
 795         chained_irq_exit(chip, desc);
 796 }
 797
 798 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 799 {
 800         struct gpio_chip *chip;
 801         int ret;
 802         unsigned ngpio = pctrl->soc->ngpios;
 803
 804         if (WARN_ON(ngpio > MAX_NR_GPIO))
 805                 return -EINVAL;
 806
 807         chip = &pctrl->chip;
 808         chip->base = 0;
 809         chip->ngpio = ngpio;
 810         chip->label = dev_name(pctrl->dev);
 811         chip->parent = pctrl->dev;
 812         chip->owner = THIS_MODULE;
 813         chip->of_node = pctrl->dev->of_node;
 814
 815         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 816         if (ret) {
 817                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 818                 return ret;
 819         }
 820
 821         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 822         if (ret) {
 823                 dev_err(pctrl->dev, "Failed to add pin range\n");
 824                 gpiochip_remove(&pctrl->chip);
 825                 return ret;
 826         }
 827
 828         ret = gpiochip_irqchip_add(chip,
 829                                    &msm_gpio_irq_chip,
 830                                    0,
 831                                    handle_edge_irq,
 832                                    IRQ_TYPE_NONE);
 833         if (ret) {
 834                 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
 835                 gpiochip_remove(&pctrl->chip);
 836                 return -ENOSYS;
 837         }
 838
 839         gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
 840                                      msm_gpio_irq_handler);
 841
 842         return 0;
 843 }
 844
 845 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
 846                                void *data)
 847 {
 848         struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
 849
 850         writel(0, pctrl->regs + PS_HOLD_OFFSET);
 851         mdelay(1000);
 852         return NOTIFY_DONE;
 853 }
 854
 855 static struct msm_pinctrl *poweroff_pctrl;
 856
 857 static void msm_ps_hold_poweroff(void)
 858 {
 859         msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
 860 }
 861
 862 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
 863 {
 864         int i;
 865         const struct msm_function *func = pctrl->soc->functions;
 866
 867         for (i = 0; i < pctrl->soc->nfunctions; i++)
 868                 if (!strcmp(func[i].name, "ps_hold")) {
 869                         pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
 870                         pctrl->restart_nb.priority = 128;
 871                         if (register_restart_handler(&pctrl->restart_nb))
 872                                 dev_err(pctrl->dev,
 873                                         "failed to setup restart handler.\n");
 874                         poweroff_pctrl = pctrl;
 875                         pm_power_off = msm_ps_hold_poweroff;
 876                         break;
 877                 }
 878 }
 879
 880 int msm_pinctrl_probe(struct platform_device *pdev,
 881                       const struct msm_pinctrl_soc_data *soc_data)
 882 {
 883         struct msm_pinctrl *pctrl;
 884         struct resource *res;
 885         int ret;
 886
 887         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 888         if (!pctrl) {
 889                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 890                 return -ENOMEM;
 891         }
 892         pctrl->dev = &pdev->dev;
 893         pctrl->soc = soc_data;
 894         pctrl->chip = msm_gpio_template;
 895
 896         raw_spin_lock_init(&pctrl->lock);
 897
 898         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 899         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 900         if (IS_ERR(pctrl->regs))
 901                 return PTR_ERR(pctrl->regs);
 902
 903         msm_pinctrl_setup_pm_reset(pctrl);
 904
 905         pctrl->irq = platform_get_irq(pdev, 0);
 906         if (pctrl->irq < 0) {
 907                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 908                 return pctrl->irq;
 909         }
 910
 911         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 912         msm_pinctrl_desc.pins = pctrl->soc->pins;
 913         msm_pinctrl_desc.npins = pctrl->soc->npins;
 914         pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
 915                                              pctrl);
 916         if (IS_ERR(pctrl->pctrl)) {
 917                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 918                 return PTR_ERR(pctrl->pctrl);
 919         }
 920
 921         ret = msm_gpio_init(pctrl);
 922         if (ret)
 923                 return ret;
 924
 925         platform_set_drvdata(pdev, pctrl);
 926
 927         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 928
 929         return 0;
 930 }
 931 EXPORT_SYMBOL(msm_pinctrl_probe);
 932
 933 int msm_pinctrl_remove(struct platform_device *pdev)
 934 {
 935         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 936
 937         gpiochip_remove(&pctrl->chip);
 938
 939         unregister_restart_handler(&pctrl->restart_nb);
 940
 941         return 0;
 942 }
 943 EXPORT_SYMBOL(msm_pinctrl_remove);
 944