drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  */
  46 struct pcs_func_vals {
  47         void __iomem *reg;
  48         unsigned val;
  49         unsigned mask;
  50 };
  51
  52 /**
  53  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  54  * and value, enable, disable, mask
  55  * @param:      config parameter
  56  * @val:        user input bits in the pinconf register
  57  * @enable:     enable bits in the pinconf register
  58  * @disable:    disable bits in the pinconf register
  59  * @mask:       mask bits in the register value
  60  */
  61 struct pcs_conf_vals {
  62         enum pin_config_param param;
  63         unsigned val;
  64         unsigned enable;
  65         unsigned disable;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_type - pinconf property name, pinconf param pair
  71  * @name:       property name in DTS file
  72  * @param:      config parameter
  73  */
  74 struct pcs_conf_type {
  75         const char *name;
  76         enum pin_config_param param;
  77 };
  78
  79 /**
  80  * struct pcs_function - pinctrl function
  81  * @name:       pinctrl function name
  82  * @vals:       register and vals array
  83  * @nvals:      number of entries in vals array
  84  * @pgnames:    array of pingroup names the function uses
  85  * @npgnames:   number of pingroup names the function uses
  86  * @node:       list node
  87  */
  88 struct pcs_function {
  89         const char *name;
  90         struct pcs_func_vals *vals;
  91         unsigned nvals;
  92         const char **pgnames;
  93         int npgnames;
  94         struct pcs_conf_vals *conf;
  95         int nconfs;
  96         struct list_head node;
  97 };
  98
  99 /**
 100  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 101  * @offset:     offset base of pins
 102  * @npins:      number pins with the same mux value of gpio function
 103  * @gpiofunc:   mux value of gpio function
 104  * @node:       list node
 105  */
 106 struct pcs_gpiofunc_range {
 107         unsigned offset;
 108         unsigned npins;
 109         unsigned gpiofunc;
 110         struct list_head node;
 111 };
 112
 113 /**
 114  * struct pcs_data - wrapper for data needed by pinctrl framework
 115  * @pa:         pindesc array
 116  * @cur:        index to current element
 117  *
 118  * REVISIT: We should be able to drop this eventually by adding
 119  * support for registering pins individually in the pinctrl
 120  * framework for those drivers that don't need a static array.
 121  */
 122 struct pcs_data {
 123         struct pinctrl_pin_desc *pa;
 124         int cur;
 125 };
 126
 127 /**
 128  * struct pcs_soc_data - SoC specific settings
 129  * @flags:      initial SoC specific PCS_FEAT_xxx values
 130  * @irq:        optional interrupt for the controller
 131  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 132  * @irq_status_mask:    optional SoC specific interrupt status mask
 133  * @rearm:      optional SoC specific wake-up rearm function
 134  */
 135 struct pcs_soc_data {
 136         unsigned flags;
 137         int irq;
 138         unsigned irq_enable_mask;
 139         unsigned irq_status_mask;
 140         void (*rearm)(void);
 141 };
 142
 143 /**
 144  * struct pcs_device - pinctrl device instance
 145  * @res:        resources
 146  * @base:       virtual address of the controller
 147  * @size:       size of the ioremapped area
 148  * @dev:        device entry
 149  * @np:         device tree node
 150  * @pctl:       pin controller device
 151  * @flags:      mask of PCS_FEAT_xxx values
 152  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 153  * @socdata:    soc specific data
 154  * @lock:       spinlock for register access
 155  * @mutex:      mutex protecting the lists
 156  * @width:      bits per mux register
 157  * @fmask:      function register mask
 158  * @fshift:     function register shift
 159  * @foff:       value to turn mux off
 160  * @fmax:       max number of functions in fmask
 161  * @bits_per_mux: number of bits per mux
 162  * @bits_per_pin: number of bits per pin
 163  * @pins:       physical pins on the SoC
 164  * @gpiofuncs:  list of gpio functions
 165  * @irqs:       list of interrupt registers
 166  * @chip:       chip container for this instance
 167  * @domain:     IRQ domain for this instance
 168  * @desc:       pin controller descriptor
 169  * @read:       register read function to use
 170  * @write:      register write function to use
 171  */
 172 struct pcs_device {
 173         struct resource *res;
 174         void __iomem *base;
 175         unsigned size;
 176         struct device *dev;
 177         struct device_node *np;
 178         struct pinctrl_dev *pctl;
 179         unsigned flags;
 180 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 181 #define PCS_FEAT_IRQ            (1 << 1)
 182 #define PCS_FEAT_PINCONF        (1 << 0)
 183         struct property *missing_nr_pinctrl_cells;
 184         struct pcs_soc_data socdata;
 185         raw_spinlock_t lock;
 186         struct mutex mutex;
 187         unsigned width;
 188         unsigned fmask;
 189         unsigned fshift;
 190         unsigned foff;
 191         unsigned fmax;
 192         bool bits_per_mux;
 193         unsigned bits_per_pin;
 194         struct pcs_data pins;
 195         struct list_head gpiofuncs;
 196         struct list_head irqs;
 197         struct irq_chip chip;
 198         struct irq_domain *domain;
 199         struct pinctrl_desc desc;
 200         unsigned (*read)(void __iomem *reg);
 201         void (*write)(unsigned val, void __iomem *reg);
 202 };
 203
 204 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 205 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 206 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 207
 208 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 209                            unsigned long *config);
 210 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 211                            unsigned long *configs, unsigned num_configs);
 212
 213 static enum pin_config_param pcs_bias[] = {
 214         PIN_CONFIG_BIAS_PULL_DOWN,
 215         PIN_CONFIG_BIAS_PULL_UP,
 216 };
 217
 218 /*
 219  * This lock class tells lockdep that irqchip core that this single
 220  * pinctrl can be in a different category than its parents, so it won't
 221  * report false recursion.
 222  */
 223 static struct lock_class_key pcs_lock_class;
 224
 225 /* Class for the IRQ request mutex */
 226 static struct lock_class_key pcs_request_class;
 227
 228 /*
 229  * REVISIT: Reads and writes could eventually use regmap or something
 230  * generic. But at least on omaps, some mux registers are performance
 231  * critical as they may need to be remuxed every time before and after
 232  * idle. Adding tests for register access width for every read and
 233  * write like regmap is doing is not desired, and caching the registers
 234  * does not help in this case.
 235  */
 236
 237 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 238 {
 239         return readb(reg);
 240 }
 241
 242 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 243 {
 244         return readw(reg);
 245 }
 246
 247 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 248 {
 249         return readl(reg);
 250 }
 251
 252 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 253 {
 254         writeb(val, reg);
 255 }
 256
 257 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 258 {
 259         writew(val, reg);
 260 }
 261
 262 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 263 {
 264         writel(val, reg);
 265 }
 266
 267 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 268                                         struct seq_file *s,
 269                                         unsigned pin)
 270 {
 271         struct pcs_device *pcs;
 272         unsigned val, mux_bytes;
 273         unsigned long offset;
 274         size_t pa;
 275
 276         pcs = pinctrl_dev_get_drvdata(pctldev);
 277
 278         mux_bytes = pcs->width / BITS_PER_BYTE;
 279         offset = pin * mux_bytes;
 280         val = pcs->read(pcs->base + offset);
 281         pa = pcs->res->start + offset;
 282
 283         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 284 }
 285
 286 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 287                                 struct pinctrl_map *map, unsigned num_maps)
 288 {
 289         struct pcs_device *pcs;
 290
 291         pcs = pinctrl_dev_get_drvdata(pctldev);
 292         devm_kfree(pcs->dev, map);
 293 }
 294
 295 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 296                                 struct device_node *np_config,
 297                                 struct pinctrl_map **map, unsigned *num_maps);
 298
 299 static const struct pinctrl_ops pcs_pinctrl_ops = {
 300         .get_groups_count = pinctrl_generic_get_group_count,
 301         .get_group_name = pinctrl_generic_get_group_name,
 302         .get_group_pins = pinctrl_generic_get_group_pins,
 303         .pin_dbg_show = pcs_pin_dbg_show,
 304         .dt_node_to_map = pcs_dt_node_to_map,
 305         .dt_free_map = pcs_dt_free_map,
 306 };
 307
 308 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 309                             struct pcs_function **func)
 310 {
 311         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 312         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 313         const struct pinctrl_setting_mux *setting;
 314         struct function_desc *function;
 315         unsigned fselector;
 316
 317         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 318         setting = pdesc->mux_setting;
 319         if (!setting)
 320                 return -ENOTSUPP;
 321         fselector = setting->func;
 322         function = pinmux_generic_get_function(pctldev, fselector);
 323         *func = function->data;
 324         if (!(*func)) {
 325                 dev_err(pcs->dev, "%s could not find function%i\n",
 326                         __func__, fselector);
 327                 return -ENOTSUPP;
 328         }
 329         return 0;
 330 }
 331
 332 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 333         unsigned group)
 334 {
 335         struct pcs_device *pcs;
 336         struct function_desc *function;
 337         struct pcs_function *func;
 338         int i;
 339
 340         pcs = pinctrl_dev_get_drvdata(pctldev);
 341         /* If function mask is null, needn't enable it. */
 342         if (!pcs->fmask)
 343                 return 0;
 344         function = pinmux_generic_get_function(pctldev, fselector);
 345         func = function->data;
 346         if (!func)
 347                 return -EINVAL;
 348
 349         dev_dbg(pcs->dev, "enabling %s function%i\n",
 350                 func->name, fselector);
 351
 352         for (i = 0; i < func->nvals; i++) {
 353                 struct pcs_func_vals *vals;
 354                 unsigned long flags;
 355                 unsigned val, mask;
 356
 357                 vals = &func->vals[i];
 358                 raw_spin_lock_irqsave(&pcs->lock, flags);
 359                 val = pcs->read(vals->reg);
 360
 361                 if (pcs->bits_per_mux)
 362                         mask = vals->mask;
 363                 else
 364                         mask = pcs->fmask;
 365
 366                 val &= ~mask;
 367                 val |= (vals->val & mask);
 368                 pcs->write(val, vals->reg);
 369                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 370         }
 371
 372         return 0;
 373 }
 374
 375 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 376                             struct pinctrl_gpio_range *range, unsigned pin)
 377 {
 378         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 379         struct pcs_gpiofunc_range *frange = NULL;
 380         struct list_head *pos, *tmp;
 381         int mux_bytes = 0;
 382         unsigned data;
 383
 384         /* If function mask is null, return directly. */
 385         if (!pcs->fmask)
 386                 return -ENOTSUPP;
 387
 388         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 389                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 390                 if (pin >= frange->offset + frange->npins
 391                         || pin < frange->offset)
 392                         continue;
 393                 mux_bytes = pcs->width / BITS_PER_BYTE;
 394                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
 395                 data |= frange->gpiofunc;
 396                 pcs->write(data, pcs->base + pin * mux_bytes);
 397                 break;
 398         }
 399         return 0;
 400 }
 401
 402 static const struct pinmux_ops pcs_pinmux_ops = {
 403         .get_functions_count = pinmux_generic_get_function_count,
 404         .get_function_name = pinmux_generic_get_function_name,
 405         .get_function_groups = pinmux_generic_get_function_groups,
 406         .set_mux = pcs_set_mux,
 407         .gpio_request_enable = pcs_request_gpio,
 408 };
 409
 410 /* Clear BIAS value */
 411 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 412 {
 413         unsigned long config;
 414         int i;
 415         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 416                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 417                 pcs_pinconf_set(pctldev, pin, &config, 1);
 418         }
 419 }
 420
 421 /*
 422  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 423  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 424  */
 425 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 426 {
 427         unsigned long config;
 428         int i;
 429
 430         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 431                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 432                 if (!pcs_pinconf_get(pctldev, pin, &config))
 433                         goto out;
 434         }
 435         return true;
 436 out:
 437         return false;
 438 }
 439
 440 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 441                                 unsigned pin, unsigned long *config)
 442 {
 443         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 444         struct pcs_function *func;
 445         enum pin_config_param param;
 446         unsigned offset = 0, data = 0, i, j, ret;
 447
 448         ret = pcs_get_function(pctldev, pin, &func);
 449         if (ret)
 450                 return ret;
 451
 452         for (i = 0; i < func->nconfs; i++) {
 453                 param = pinconf_to_config_param(*config);
 454                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 455                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 456                                 *config = 0;
 457                                 return 0;
 458                         } else {
 459                                 return -ENOTSUPP;
 460                         }
 461                 } else if (param != func->conf[i].param) {
 462                         continue;
 463                 }
 464
 465                 offset = pin * (pcs->width / BITS_PER_BYTE);
 466                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 467                 switch (func->conf[i].param) {
 468                 /* 4 parameters */
 469                 case PIN_CONFIG_BIAS_PULL_DOWN:
 470                 case PIN_CONFIG_BIAS_PULL_UP:
 471                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 472                         if ((data != func->conf[i].enable) ||
 473                             (data == func->conf[i].disable))
 474                                 return -ENOTSUPP;
 475                         *config = 0;
 476                         break;
 477                 /* 2 parameters */
 478                 case PIN_CONFIG_INPUT_SCHMITT:
 479                         for (j = 0; j < func->nconfs; j++) {
 480                                 switch (func->conf[j].param) {
 481                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 482                                         if (data != func->conf[j].enable)
 483                                                 return -ENOTSUPP;
 484                                         break;
 485                                 default:
 486                                         break;
 487                                 }
 488                         }
 489                         *config = data;
 490                         break;
 491                 case PIN_CONFIG_DRIVE_STRENGTH:
 492                 case PIN_CONFIG_SLEW_RATE:
 493                 case PIN_CONFIG_LOW_POWER_MODE:
 494                 default:
 495                         *config = data;
 496                         break;
 497                 }
 498                 return 0;
 499         }
 500         return -ENOTSUPP;
 501 }
 502
 503 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 504                                 unsigned pin, unsigned long *configs,
 505                                 unsigned num_configs)
 506 {
 507         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 508         struct pcs_function *func;
 509         unsigned offset = 0, shift = 0, i, data, ret;
 510         u32 arg;
 511         int j;
 512
 513         ret = pcs_get_function(pctldev, pin, &func);
 514         if (ret)
 515                 return ret;
 516
 517         for (j = 0; j < num_configs; j++) {
 518                 for (i = 0; i < func->nconfs; i++) {
 519                         if (pinconf_to_config_param(configs[j])
 520                                 != func->conf[i].param)
 521                                 continue;
 522
 523                         offset = pin * (pcs->width / BITS_PER_BYTE);
 524                         data = pcs->read(pcs->base + offset);
 525                         arg = pinconf_to_config_argument(configs[j]);
 526                         switch (func->conf[i].param) {
 527                         /* 2 parameters */
 528                         case PIN_CONFIG_INPUT_SCHMITT:
 529                         case PIN_CONFIG_DRIVE_STRENGTH:
 530                         case PIN_CONFIG_SLEW_RATE:
 531                         case PIN_CONFIG_LOW_POWER_MODE:
 532                                 shift = ffs(func->conf[i].mask) - 1;
 533                                 data &= ~func->conf[i].mask;
 534                                 data |= (arg << shift) & func->conf[i].mask;
 535                                 break;
 536                         /* 4 parameters */
 537                         case PIN_CONFIG_BIAS_DISABLE:
 538                                 pcs_pinconf_clear_bias(pctldev, pin);
 539                                 break;
 540                         case PIN_CONFIG_BIAS_PULL_DOWN:
 541                         case PIN_CONFIG_BIAS_PULL_UP:
 542                                 if (arg)
 543                                         pcs_pinconf_clear_bias(pctldev, pin);
 544                                 /* fall through */
 545                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 546                                 data &= ~func->conf[i].mask;
 547                                 if (arg)
 548                                         data |= func->conf[i].enable;
 549                                 else
 550                                         data |= func->conf[i].disable;
 551                                 break;
 552                         default:
 553                                 return -ENOTSUPP;
 554                         }
 555                         pcs->write(data, pcs->base + offset);
 556
 557                         break;
 558                 }
 559                 if (i >= func->nconfs)
 560                         return -ENOTSUPP;
 561         } /* for each config */
 562
 563         return 0;
 564 }
 565
 566 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 567                                 unsigned group, unsigned long *config)
 568 {
 569         const unsigned *pins;
 570         unsigned npins, old = 0;
 571         int i, ret;
 572
 573         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 574         if (ret)
 575                 return ret;
 576         for (i = 0; i < npins; i++) {
 577                 if (pcs_pinconf_get(pctldev, pins[i], config))
 578                         return -ENOTSUPP;
 579                 /* configs do not match between two pins */
 580                 if (i && (old != *config))
 581                         return -ENOTSUPP;
 582                 old = *config;
 583         }
 584         return 0;
 585 }
 586
 587 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 588                                 unsigned group, unsigned long *configs,
 589                                 unsigned num_configs)
 590 {
 591         const unsigned *pins;
 592         unsigned npins;
 593         int i, ret;
 594
 595         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 596         if (ret)
 597                 return ret;
 598         for (i = 0; i < npins; i++) {
 599                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 600                         return -ENOTSUPP;
 601         }
 602         return 0;
 603 }
 604
 605 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 606                                 struct seq_file *s, unsigned pin)
 607 {
 608 }
 609
 610 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 611                                 struct seq_file *s, unsigned selector)
 612 {
 613 }
 614
 615 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 616                                         struct seq_file *s,
 617                                         unsigned long config)
 618 {
 619         pinconf_generic_dump_config(pctldev, s, config);
 620 }
 621
 622 static const struct pinconf_ops pcs_pinconf_ops = {
 623         .pin_config_get = pcs_pinconf_get,
 624         .pin_config_set = pcs_pinconf_set,
 625         .pin_config_group_get = pcs_pinconf_group_get,
 626         .pin_config_group_set = pcs_pinconf_group_set,
 627         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 628         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 629         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 630         .is_generic = true,
 631 };
 632
 633 /**
 634  * pcs_add_pin() - add a pin to the static per controller pin array
 635  * @pcs: pcs driver instance
 636  * @offset: register offset from base
 637  */
 638 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 639                 unsigned pin_pos)
 640 {
 641         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 642         struct pinctrl_pin_desc *pin;
 643         int i;
 644
 645         i = pcs->pins.cur;
 646         if (i >= pcs->desc.npins) {
 647                 dev_err(pcs->dev, "too many pins, max %i\n",
 648                         pcs->desc.npins);
 649                 return -ENOMEM;
 650         }
 651
 652         if (pcs_soc->irq_enable_mask) {
 653                 unsigned val;
 654
 655                 val = pcs->read(pcs->base + offset);
 656                 if (val & pcs_soc->irq_enable_mask) {
 657                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 658                                 (unsigned long)pcs->res->start + offset, val);
 659                         val &= ~pcs_soc->irq_enable_mask;
 660                         pcs->write(val, pcs->base + offset);
 661                 }
 662         }
 663
 664         pin = &pcs->pins.pa[i];
 665         pin->number = i;
 666         pcs->pins.cur++;
 667
 668         return i;
 669 }
 670
 671 /**
 672  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 673  * @pcs: pcs driver instance
 674  *
 675  * In case of errors, resources are freed in pcs_free_resources.
 676  *
 677  * If your hardware needs holes in the address space, then just set
 678  * up multiple driver instances.
 679  */
 680 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 681 {
 682         int mux_bytes, nr_pins, i;
 683         int num_pins_in_register = 0;
 684
 685         mux_bytes = pcs->width / BITS_PER_BYTE;
 686
 687         if (pcs->bits_per_mux) {
 688                 pcs->bits_per_pin = fls(pcs->fmask);
 689                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 690                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 691         } else {
 692                 nr_pins = pcs->size / mux_bytes;
 693         }
 694
 695         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 696         pcs->pins.pa = devm_kzalloc(pcs->dev,
 697                                 sizeof(*pcs->pins.pa) * nr_pins,
 698                                 GFP_KERNEL);
 699         if (!pcs->pins.pa)
 700                 return -ENOMEM;
 701
 702         pcs->desc.pins = pcs->pins.pa;
 703         pcs->desc.npins = nr_pins;
 704
 705         for (i = 0; i < pcs->desc.npins; i++) {
 706                 unsigned offset;
 707                 int res;
 708                 int byte_num;
 709                 int pin_pos = 0;
 710
 711                 if (pcs->bits_per_mux) {
 712                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 713                         offset = (byte_num / mux_bytes) * mux_bytes;
 714                         pin_pos = i % num_pins_in_register;
 715                 } else {
 716                         offset = i * mux_bytes;
 717                 }
 718                 res = pcs_add_pin(pcs, offset, pin_pos);
 719                 if (res < 0) {
 720                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 721                         return res;
 722                 }
 723         }
 724
 725         return 0;
 726 }
 727
 728 /**
 729  * pcs_add_function() - adds a new function to the function list
 730  * @pcs: pcs driver instance
 731  * @np: device node of the mux entry
 732  * @name: name of the function
 733  * @vals: array of mux register value pairs used by the function
 734  * @nvals: number of mux register value pairs
 735  * @pgnames: array of pingroup names for the function
 736  * @npgnames: number of pingroup names
 737  */
 738 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 739                                         struct device_node *np,
 740                                         const char *name,
 741                                         struct pcs_func_vals *vals,
 742                                         unsigned nvals,
 743                                         const char **pgnames,
 744                                         unsigned npgnames)
 745 {
 746         struct pcs_function *function;
 747         int res;
 748
 749         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 750         if (!function)
 751                 return NULL;
 752
 753         function->vals = vals;
 754         function->nvals = nvals;
 755
 756         res = pinmux_generic_add_function(pcs->pctl, name,
 757                                           pgnames, npgnames,
 758                                           function);
 759         if (res)
 760                 return NULL;
 761
 762         return function;
 763 }
 764
 765 /**
 766  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 767  * @pcs: pcs driver instance
 768  * @offset: register offset from the base
 769  *
 770  * Note that this is OK as long as the pins are in a static array.
 771  */
 772 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 773 {
 774         unsigned index;
 775
 776         if (offset >= pcs->size) {
 777                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 778                         offset, pcs->size);
 779                 return -EINVAL;
 780         }
 781
 782         if (pcs->bits_per_mux)
 783                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 784         else
 785                 index = offset / (pcs->width / BITS_PER_BYTE);
 786
 787         return index;
 788 }
 789
 790 /*
 791  * check whether data matches enable bits or disable bits
 792  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 793  *               and negative value for matching failure.
 794  */
 795 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 796 {
 797         int ret = -EINVAL;
 798
 799         if (data == enable)
 800                 ret = 1;
 801         else if (data == disable)
 802                 ret = 0;
 803         return ret;
 804 }
 805
 806 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 807                        unsigned value, unsigned enable, unsigned disable,
 808                        unsigned mask)
 809 {
 810         (*conf)->param = param;
 811         (*conf)->val = value;
 812         (*conf)->enable = enable;
 813         (*conf)->disable = disable;
 814         (*conf)->mask = mask;
 815         (*conf)++;
 816 }
 817
 818 static void add_setting(unsigned long **setting, enum pin_config_param param,
 819                         unsigned arg)
 820 {
 821         **setting = pinconf_to_config_packed(param, arg);
 822         (*setting)++;
 823 }
 824
 825 /* add pinconf setting with 2 parameters */
 826 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 827                           const char *name, enum pin_config_param param,
 828                           struct pcs_conf_vals **conf, unsigned long **settings)
 829 {
 830         unsigned value[2], shift;
 831         int ret;
 832
 833         ret = of_property_read_u32_array(np, name, value, 2);
 834         if (ret)
 835                 return;
 836         /* set value & mask */
 837         value[0] &= value[1];
 838         shift = ffs(value[1]) - 1;
 839         /* skip enable & disable */
 840         add_config(conf, param, value[0], 0, 0, value[1]);
 841         add_setting(settings, param, value[0] >> shift);
 842 }
 843
 844 /* add pinconf setting with 4 parameters */
 845 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 846                           const char *name, enum pin_config_param param,
 847                           struct pcs_conf_vals **conf, unsigned long **settings)
 848 {
 849         unsigned value[4];
 850         int ret;
 851
 852         /* value to set, enable, disable, mask */
 853         ret = of_property_read_u32_array(np, name, value, 4);
 854         if (ret)
 855                 return;
 856         if (!value[3]) {
 857                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 858                 return;
 859         }
 860         value[0] &= value[3];
 861         value[1] &= value[3];
 862         value[2] &= value[3];
 863         ret = pcs_config_match(value[0], value[1], value[2]);
 864         if (ret < 0)
 865                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 866         add_config(conf, param, value[0], value[1], value[2], value[3]);
 867         add_setting(settings, param, ret);
 868 }
 869
 870 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 871                              struct pcs_function *func,
 872                              struct pinctrl_map **map)
 873
 874 {
 875         struct pinctrl_map *m = *map;
 876         int i = 0, nconfs = 0;
 877         unsigned long *settings = NULL, *s = NULL;
 878         struct pcs_conf_vals *conf = NULL;
 879         static const struct pcs_conf_type prop2[] = {
 880                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 881                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 882                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 883                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 884         };
 885         static const struct pcs_conf_type prop4[] = {
 886                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 887                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 888                 { "pinctrl-single,input-schmitt-enable",
 889                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 890         };
 891
 892         /* If pinconf isn't supported, don't parse properties in below. */
 893         if (!PCS_HAS_PINCONF)
 894                 return 0;
 895
 896         /* cacluate how much properties are supported in current node */
 897         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 898                 if (of_find_property(np, prop2[i].name, NULL))
 899                         nconfs++;
 900         }
 901         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 902                 if (of_find_property(np, prop4[i].name, NULL))
 903                         nconfs++;
 904         }
 905         if (!nconfs)
 906                 return 0;
 907
 908         func->conf = devm_kzalloc(pcs->dev,
 909                                   sizeof(struct pcs_conf_vals) * nconfs,
 910                                   GFP_KERNEL);
 911         if (!func->conf)
 912                 return -ENOMEM;
 913         func->nconfs = nconfs;
 914         conf = &(func->conf[0]);
 915         m++;
 916         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
 917                                 GFP_KERNEL);
 918         if (!settings)
 919                 return -ENOMEM;
 920         s = &settings[0];
 921
 922         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 923                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 924                               &conf, &s);
 925         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 926                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 927                               &conf, &s);
 928         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 929         m->data.configs.group_or_pin = np->name;
 930         m->data.configs.configs = settings;
 931         m->data.configs.num_configs = nconfs;
 932         return 0;
 933 }
 934
 935 /**
 936  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
 937  * @pctldev: pin controller device
 938  * @pcs: pinctrl driver instance
 939  * @np: device node of the mux entry
 940  * @map: map entry
 941  * @num_maps: number of map
 942  * @pgnames: pingroup names
 943  *
 944  * Note that this binding currently supports only sets of one register + value.
 945  *
 946  * Also note that this driver tries to avoid understanding pin and function
 947  * names because of the extra bloat they would cause especially in the case of
 948  * a large number of pins. This driver just sets what is specified for the board
 949  * in the .dts file. Further user space debugging tools can be developed to
 950  * decipher the pin and function names using debugfs.
 951  *
 952  * If you are concerned about the boot time, set up the static pins in
 953  * the bootloader, and only set up selected pins as device tree entries.
 954  */
 955 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 956                                                 struct device_node *np,
 957                                                 struct pinctrl_map **map,
 958                                                 unsigned *num_maps,
 959                                                 const char **pgnames)
 960 {
 961         const char *name = "pinctrl-single,pins";
 962         struct pcs_func_vals *vals;
 963         int rows, *pins, found = 0, res = -ENOMEM, i;
 964         struct pcs_function *function;
 965
 966         rows = pinctrl_count_index_with_args(np, name);
 967         if (rows <= 0) {
 968                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 969                 return -EINVAL;
 970         }
 971
 972         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
 973         if (!vals)
 974                 return -ENOMEM;
 975
 976         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
 977         if (!pins)
 978                 goto free_vals;
 979
 980         for (i = 0; i < rows; i++) {
 981                 struct of_phandle_args pinctrl_spec;
 982                 unsigned int offset;
 983                 int pin;
 984
 985                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
 986                 if (res)
 987                         return res;
 988
 989                 if (pinctrl_spec.args_count < 2) {
 990                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
 991                                 pinctrl_spec.args_count);
 992                         break;
 993                 }
 994
 995                 /* Index plus one value cell */
 996                 offset = pinctrl_spec.args[0];
 997                 vals[found].reg = pcs->base + offset;
 998                 vals[found].val = pinctrl_spec.args[1];
 999
1000                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1001                         pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1002
1003                 pin = pcs_get_pin_by_offset(pcs, offset);
1004                 if (pin < 0) {
1005                         dev_err(pcs->dev,
1006                                 "could not add functions for %s %ux\n",
1007                                 np->name, offset);
1008                         break;
1009                 }
1010                 pins[found++] = pin;
1011         }
1012
1013         pgnames[0] = np->name;
1014         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1015         if (!function) {
1016                 res = -ENOMEM;
1017                 goto free_pins;
1018         }
1019
1020         res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1021         if (res < 0)
1022                 goto free_function;
1023
1024         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1025         (*map)->data.mux.group = np->name;
1026         (*map)->data.mux.function = np->name;
1027
1028         if (PCS_HAS_PINCONF) {
1029                 res = pcs_parse_pinconf(pcs, np, function, map);
1030                 if (res)
1031                         goto free_pingroups;
1032                 *num_maps = 2;
1033         } else {
1034                 *num_maps = 1;
1035         }
1036         return 0;
1037
1038 free_pingroups:
1039         pinctrl_generic_remove_last_group(pcs->pctl);
1040         *num_maps = 1;
1041 free_function:
1042         pinmux_generic_remove_last_function(pcs->pctl);
1043
1044 free_pins:
1045         devm_kfree(pcs->dev, pins);
1046
1047 free_vals:
1048         devm_kfree(pcs->dev, vals);
1049
1050         return res;
1051 }
1052
1053 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1054                                                 struct device_node *np,
1055                                                 struct pinctrl_map **map,
1056                                                 unsigned *num_maps,
1057                                                 const char **pgnames)
1058 {
1059         const char *name = "pinctrl-single,bits";
1060         struct pcs_func_vals *vals;
1061         int rows, *pins, found = 0, res = -ENOMEM, i;
1062         int npins_in_row;
1063         struct pcs_function *function;
1064
1065         rows = pinctrl_count_index_with_args(np, name);
1066         if (rows <= 0) {
1067                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1068                 return -EINVAL;
1069         }
1070
1071         npins_in_row = pcs->width / pcs->bits_per_pin;
1072
1073         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1074                         GFP_KERNEL);
1075         if (!vals)
1076                 return -ENOMEM;
1077
1078         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1079                         GFP_KERNEL);
1080         if (!pins)
1081                 goto free_vals;
1082
1083         for (i = 0; i < rows; i++) {
1084                 struct of_phandle_args pinctrl_spec;
1085                 unsigned offset, val;
1086                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1087                 unsigned pin_num_from_lsb;
1088                 int pin;
1089
1090                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1091                 if (res)
1092                         return res;
1093
1094                 if (pinctrl_spec.args_count < 3) {
1095                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1096                                 pinctrl_spec.args_count);
1097                         break;
1098                 }
1099
1100                 /* Index plus two value cells */
1101                 offset = pinctrl_spec.args[0];
1102                 val = pinctrl_spec.args[1];
1103                 mask = pinctrl_spec.args[2];
1104
1105                 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1106                         pinctrl_spec.np->name, offset, val, mask);
1107
1108                 /* Parse pins in each row from LSB */
1109                 while (mask) {
1110                         bit_pos = __ffs(mask);
1111                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1112                         mask_pos = ((pcs->fmask) << bit_pos);
1113                         val_pos = val & mask_pos;
1114                         submask = mask & mask_pos;
1115
1116                         if ((mask & mask_pos) == 0) {
1117                                 dev_err(pcs->dev,
1118                                         "Invalid mask for %s at 0x%x\n",
1119                                         np->name, offset);
1120                                 break;
1121                         }
1122
1123                         mask &= ~mask_pos;
1124
1125                         if (submask != mask_pos) {
1126                                 dev_warn(pcs->dev,
1127                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1128                                                 submask, np->name, offset);
1129                                 continue;
1130                         }
1131
1132                         vals[found].mask = submask;
1133                         vals[found].reg = pcs->base + offset;
1134                         vals[found].val = val_pos;
1135
1136                         pin = pcs_get_pin_by_offset(pcs, offset);
1137                         if (pin < 0) {
1138                                 dev_err(pcs->dev,
1139                                         "could not add functions for %s %ux\n",
1140                                         np->name, offset);
1141                                 break;
1142                         }
1143                         pins[found++] = pin + pin_num_from_lsb;
1144                 }
1145         }
1146
1147         pgnames[0] = np->name;
1148         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1149         if (!function) {
1150                 res = -ENOMEM;
1151                 goto free_pins;
1152         }
1153
1154         res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1155         if (res < 0)
1156                 goto free_function;
1157
1158         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1159         (*map)->data.mux.group = np->name;
1160         (*map)->data.mux.function = np->name;
1161
1162         if (PCS_HAS_PINCONF) {
1163                 dev_err(pcs->dev, "pinconf not supported\n");
1164                 goto free_pingroups;
1165         }
1166
1167         *num_maps = 1;
1168         return 0;
1169
1170 free_pingroups:
1171         pinctrl_generic_remove_last_group(pcs->pctl);
1172         *num_maps = 1;
1173 free_function:
1174         pinmux_generic_remove_last_function(pcs->pctl);
1175 free_pins:
1176         devm_kfree(pcs->dev, pins);
1177
1178 free_vals:
1179         devm_kfree(pcs->dev, vals);
1180
1181         return res;
1182 }
1183 /**
1184  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1185  * @pctldev: pinctrl instance
1186  * @np_config: device tree pinmux entry
1187  * @map: array of map entries
1188  * @num_maps: number of maps
1189  */
1190 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1191                                 struct device_node *np_config,
1192                                 struct pinctrl_map **map, unsigned *num_maps)
1193 {
1194         struct pcs_device *pcs;
1195         const char **pgnames;
1196         int ret;
1197
1198         pcs = pinctrl_dev_get_drvdata(pctldev);
1199
1200         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1201         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1202         if (!*map)
1203                 return -ENOMEM;
1204
1205         *num_maps = 0;
1206
1207         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1208         if (!pgnames) {
1209                 ret = -ENOMEM;
1210                 goto free_map;
1211         }
1212
1213         if (pcs->bits_per_mux) {
1214                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1215                                 num_maps, pgnames);
1216                 if (ret < 0) {
1217                         dev_err(pcs->dev, "no pins entries for %s\n",
1218                                 np_config->name);
1219                         goto free_pgnames;
1220                 }
1221         } else {
1222                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1223                                 num_maps, pgnames);
1224                 if (ret < 0) {
1225                         dev_err(pcs->dev, "no pins entries for %s\n",
1226                                 np_config->name);
1227                         goto free_pgnames;
1228                 }
1229         }
1230
1231         return 0;
1232
1233 free_pgnames:
1234         devm_kfree(pcs->dev, pgnames);
1235 free_map:
1236         devm_kfree(pcs->dev, *map);
1237
1238         return ret;
1239 }
1240
1241 /**
1242  * pcs_irq_free() - free interrupt
1243  * @pcs: pcs driver instance
1244  */
1245 static void pcs_irq_free(struct pcs_device *pcs)
1246 {
1247         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1248
1249         if (pcs_soc->irq < 0)
1250                 return;
1251
1252         if (pcs->domain)
1253                 irq_domain_remove(pcs->domain);
1254
1255         if (PCS_QUIRK_HAS_SHARED_IRQ)
1256                 free_irq(pcs_soc->irq, pcs_soc);
1257         else
1258                 irq_set_chained_handler(pcs_soc->irq, NULL);
1259 }
1260
1261 /**
1262  * pcs_free_resources() - free memory used by this driver
1263  * @pcs: pcs driver instance
1264  */
1265 static void pcs_free_resources(struct pcs_device *pcs)
1266 {
1267         pcs_irq_free(pcs);
1268         pinctrl_unregister(pcs->pctl);
1269
1270 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1271         if (pcs->missing_nr_pinctrl_cells)
1272                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1273 #endif
1274 }
1275
1276 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1277 {
1278         const char *propname = "pinctrl-single,gpio-range";
1279         const char *cellname = "#pinctrl-single,gpio-range-cells";
1280         struct of_phandle_args gpiospec;
1281         struct pcs_gpiofunc_range *range;
1282         int ret, i;
1283
1284         for (i = 0; ; i++) {
1285                 ret = of_parse_phandle_with_args(node, propname, cellname,
1286                                                  i, &gpiospec);
1287                 /* Do not treat it as error. Only treat it as end condition. */
1288                 if (ret) {
1289                         ret = 0;
1290                         break;
1291                 }
1292                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1293                 if (!range) {
1294                         ret = -ENOMEM;
1295                         break;
1296                 }
1297                 range->offset = gpiospec.args[0];
1298                 range->npins = gpiospec.args[1];
1299                 range->gpiofunc = gpiospec.args[2];
1300                 mutex_lock(&pcs->mutex);
1301                 list_add_tail(&range->node, &pcs->gpiofuncs);
1302                 mutex_unlock(&pcs->mutex);
1303         }
1304         return ret;
1305 }
1306 /**
1307  * @reg:        virtual address of interrupt register
1308  * @hwirq:      hardware irq number
1309  * @irq:        virtual irq number
1310  * @node:       list node
1311  */
1312 struct pcs_interrupt {
1313         void __iomem *reg;
1314         irq_hw_number_t hwirq;
1315         unsigned int irq;
1316         struct list_head node;
1317 };
1318
1319 /**
1320  * pcs_irq_set() - enables or disables an interrupt
1321  *
1322  * Note that this currently assumes one interrupt per pinctrl
1323  * register that is typically used for wake-up events.
1324  */
1325 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1326                                int irq, const bool enable)
1327 {
1328         struct pcs_device *pcs;
1329         struct list_head *pos;
1330         unsigned mask;
1331
1332         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1333         list_for_each(pos, &pcs->irqs) {
1334                 struct pcs_interrupt *pcswi;
1335                 unsigned soc_mask;
1336
1337                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1338                 if (irq != pcswi->irq)
1339                         continue;
1340
1341                 soc_mask = pcs_soc->irq_enable_mask;
1342                 raw_spin_lock(&pcs->lock);
1343                 mask = pcs->read(pcswi->reg);
1344                 if (enable)
1345                         mask |= soc_mask;
1346                 else
1347                         mask &= ~soc_mask;
1348                 pcs->write(mask, pcswi->reg);
1349
1350                 /* flush posted write */
1351                 mask = pcs->read(pcswi->reg);
1352                 raw_spin_unlock(&pcs->lock);
1353         }
1354
1355         if (pcs_soc->rearm)
1356                 pcs_soc->rearm();
1357 }
1358
1359 /**
1360  * pcs_irq_mask() - mask pinctrl interrupt
1361  * @d: interrupt data
1362  */
1363 static void pcs_irq_mask(struct irq_data *d)
1364 {
1365         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1366
1367         pcs_irq_set(pcs_soc, d->irq, false);
1368 }
1369
1370 /**
1371  * pcs_irq_unmask() - unmask pinctrl interrupt
1372  * @d: interrupt data
1373  */
1374 static void pcs_irq_unmask(struct irq_data *d)
1375 {
1376         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1377
1378         pcs_irq_set(pcs_soc, d->irq, true);
1379 }
1380
1381 /**
1382  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1383  * @d: interrupt data
1384  * @state: wake-up state
1385  *
1386  * Note that this should be called only for suspend and resume.
1387  * For runtime PM, the wake-up events should be enabled by default.
1388  */
1389 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1390 {
1391         if (state)
1392                 pcs_irq_unmask(d);
1393         else
1394                 pcs_irq_mask(d);
1395
1396         return 0;
1397 }
1398
1399 /**
1400  * pcs_irq_handle() - common interrupt handler
1401  * @pcs_irq: interrupt data
1402  *
1403  * Note that this currently assumes we have one interrupt bit per
1404  * mux register. This interrupt is typically used for wake-up events.
1405  * For more complex interrupts different handlers can be specified.
1406  */
1407 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1408 {
1409         struct pcs_device *pcs;
1410         struct list_head *pos;
1411         int count = 0;
1412
1413         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1414         list_for_each(pos, &pcs->irqs) {
1415                 struct pcs_interrupt *pcswi;
1416                 unsigned mask;
1417
1418                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1419                 raw_spin_lock(&pcs->lock);
1420                 mask = pcs->read(pcswi->reg);
1421                 raw_spin_unlock(&pcs->lock);
1422                 if (mask & pcs_soc->irq_status_mask) {
1423                         generic_handle_irq(irq_find_mapping(pcs->domain,
1424                                                             pcswi->hwirq));
1425                         count++;
1426                 }
1427         }
1428
1429         return count;
1430 }
1431
1432 /**
1433  * pcs_irq_handler() - handler for the shared interrupt case
1434  * @irq: interrupt
1435  * @d: data
1436  *
1437  * Use this for cases where multiple instances of
1438  * pinctrl-single share a single interrupt like on omaps.
1439  */
1440 static irqreturn_t pcs_irq_handler(int irq, void *d)
1441 {
1442         struct pcs_soc_data *pcs_soc = d;
1443
1444         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1445 }
1446
1447 /**
1448  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1449  * @irq: interrupt
1450  * @desc: interrupt descriptor
1451  *
1452  * Use this if you have a separate interrupt for each
1453  * pinctrl-single instance.
1454  */
1455 static void pcs_irq_chain_handler(struct irq_desc *desc)
1456 {
1457         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1458         struct irq_chip *chip;
1459
1460         chip = irq_desc_get_chip(desc);
1461         chained_irq_enter(chip, desc);
1462         pcs_irq_handle(pcs_soc);
1463         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1464         chained_irq_exit(chip, desc);
1465
1466         return;
1467 }
1468
1469 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1470                              irq_hw_number_t hwirq)
1471 {
1472         struct pcs_soc_data *pcs_soc = d->host_data;
1473         struct pcs_device *pcs;
1474         struct pcs_interrupt *pcswi;
1475
1476         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1477         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1478         if (!pcswi)
1479                 return -ENOMEM;
1480
1481         pcswi->reg = pcs->base + hwirq;
1482         pcswi->hwirq = hwirq;
1483         pcswi->irq = irq;
1484
1485         mutex_lock(&pcs->mutex);
1486         list_add_tail(&pcswi->node, &pcs->irqs);
1487         mutex_unlock(&pcs->mutex);
1488
1489         irq_set_chip_data(irq, pcs_soc);
1490         irq_set_chip_and_handler(irq, &pcs->chip,
1491                                  handle_level_irq);
1492         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1493         irq_set_noprobe(irq);
1494
1495         return 0;
1496 }
1497
1498 static const struct irq_domain_ops pcs_irqdomain_ops = {
1499         .map = pcs_irqdomain_map,
1500         .xlate = irq_domain_xlate_onecell,
1501 };
1502
1503 /**
1504  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1505  * @pcs: pcs driver instance
1506  * @np: device node pointer
1507  */
1508 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1509                                         struct device_node *np)
1510 {
1511         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1512         const char *name = "pinctrl";
1513         int num_irqs;
1514
1515         if (!pcs_soc->irq_enable_mask ||
1516             !pcs_soc->irq_status_mask) {
1517                 pcs_soc->irq = -1;
1518                 return -EINVAL;
1519         }
1520
1521         INIT_LIST_HEAD(&pcs->irqs);
1522         pcs->chip.name = name;
1523         pcs->chip.irq_ack = pcs_irq_mask;
1524         pcs->chip.irq_mask = pcs_irq_mask;
1525         pcs->chip.irq_unmask = pcs_irq_unmask;
1526         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1527
1528         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1529                 int res;
1530
1531                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1532                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1533                                   IRQF_NO_THREAD,
1534                                   name, pcs_soc);
1535                 if (res) {
1536                         pcs_soc->irq = -1;
1537                         return res;
1538                 }
1539         } else {
1540                 irq_set_chained_handler_and_data(pcs_soc->irq,
1541                                                  pcs_irq_chain_handler,
1542                                                  pcs_soc);
1543         }
1544
1545         /*
1546          * We can use the register offset as the hardirq
1547          * number as irq_domain_add_simple maps them lazily.
1548          * This way we can easily support more than one
1549          * interrupt per function if needed.
1550          */
1551         num_irqs = pcs->size;
1552
1553         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1554                                             &pcs_irqdomain_ops,
1555                                             pcs_soc);
1556         if (!pcs->domain) {
1557                 irq_set_chained_handler(pcs_soc->irq, NULL);
1558                 return -EINVAL;
1559         }
1560
1561         return 0;
1562 }
1563
1564 #ifdef CONFIG_PM
1565 static int pinctrl_single_suspend(struct platform_device *pdev,
1566                                         pm_message_t state)
1567 {
1568         struct pcs_device *pcs;
1569
1570         pcs = platform_get_drvdata(pdev);
1571         if (!pcs)
1572                 return -EINVAL;
1573
1574         return pinctrl_force_sleep(pcs->pctl);
1575 }
1576
1577 static int pinctrl_single_resume(struct platform_device *pdev)
1578 {
1579         struct pcs_device *pcs;
1580
1581         pcs = platform_get_drvdata(pdev);
1582         if (!pcs)
1583                 return -EINVAL;
1584
1585         return pinctrl_force_default(pcs->pctl);
1586 }
1587 #endif
1588
1589 /**
1590  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1591  * @pcs: pinctrl driver instance
1592  * @np: device tree node
1593  * @cells: number of cells
1594  *
1595  * Handle legacy binding with no #pinctrl-cells. This should be
1596  * always two pinctrl-single,bit-per-mux and one for others.
1597  * At some point we may want to consider removing this.
1598  */
1599 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1600                                            struct device_node *np,
1601                                            int cells)
1602 {
1603         struct property *p;
1604         const char *name = "#pinctrl-cells";
1605         int error;
1606         u32 val;
1607
1608         error = of_property_read_u32(np, name, &val);
1609         if (!error)
1610                 return 0;
1611
1612         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1613                  name, cells);
1614
1615         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1616         if (!p)
1617                 return -ENOMEM;
1618
1619         p->length = sizeof(__be32);
1620         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1621         if (!p->value)
1622                 return -ENOMEM;
1623         *(__be32 *)p->value = cpu_to_be32(cells);
1624
1625         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1626         if (!p->name)
1627                 return -ENOMEM;
1628
1629         pcs->missing_nr_pinctrl_cells = p;
1630
1631 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1632         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1633 #endif
1634
1635         return error;
1636 }
1637
1638 static int pcs_probe(struct platform_device *pdev)
1639 {
1640         struct device_node *np = pdev->dev.of_node;
1641         struct pcs_pdata *pdata;
1642         struct resource *res;
1643         struct pcs_device *pcs;
1644         const struct pcs_soc_data *soc;
1645         int ret;
1646
1647         soc = of_device_get_match_data(&pdev->dev);
1648         if (WARN_ON(!soc))
1649                 return -EINVAL;
1650
1651         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1652         if (!pcs) {
1653                 dev_err(&pdev->dev, "could not allocate\n");
1654                 return -ENOMEM;
1655         }
1656         pcs->dev = &pdev->dev;
1657         pcs->np = np;
1658         raw_spin_lock_init(&pcs->lock);
1659         mutex_init(&pcs->mutex);
1660         INIT_LIST_HEAD(&pcs->gpiofuncs);
1661         pcs->flags = soc->flags;
1662         memcpy(&pcs->socdata, soc, sizeof(*soc));
1663
1664         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1665                                    &pcs->width);
1666         if (ret) {
1667                 dev_err(pcs->dev, "register width not specified\n");
1668
1669                 return ret;
1670         }
1671
1672         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1673                                    &pcs->fmask);
1674         if (!ret) {
1675                 pcs->fshift = __ffs(pcs->fmask);
1676                 pcs->fmax = pcs->fmask >> pcs->fshift;
1677         } else {
1678                 /* If mask property doesn't exist, function mux is invalid. */
1679                 pcs->fmask = 0;
1680                 pcs->fshift = 0;
1681                 pcs->fmax = 0;
1682         }
1683
1684         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1685                                         &pcs->foff);
1686         if (ret)
1687                 pcs->foff = PCS_OFF_DISABLED;
1688
1689         pcs->bits_per_mux = of_property_read_bool(np,
1690                                                   "pinctrl-single,bit-per-mux");
1691         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1692                                               pcs->bits_per_mux ? 2 : 1);
1693         if (ret) {
1694                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1695
1696                 return ret;
1697         }
1698
1699         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1700         if (!res) {
1701                 dev_err(pcs->dev, "could not get resource\n");
1702                 return -ENODEV;
1703         }
1704
1705         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1706                         resource_size(res), DRIVER_NAME);
1707         if (!pcs->res) {
1708                 dev_err(pcs->dev, "could not get mem_region\n");
1709                 return -EBUSY;
1710         }
1711
1712         pcs->size = resource_size(pcs->res);
1713         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1714         if (!pcs->base) {
1715                 dev_err(pcs->dev, "could not ioremap\n");
1716                 return -ENODEV;
1717         }
1718
1719         platform_set_drvdata(pdev, pcs);
1720
1721         switch (pcs->width) {
1722         case 8:
1723                 pcs->read = pcs_readb;
1724                 pcs->write = pcs_writeb;
1725                 break;
1726         case 16:
1727                 pcs->read = pcs_readw;
1728                 pcs->write = pcs_writew;
1729                 break;
1730         case 32:
1731                 pcs->read = pcs_readl;
1732                 pcs->write = pcs_writel;
1733                 break;
1734         default:
1735                 break;
1736         }
1737
1738         pcs->desc.name = DRIVER_NAME;
1739         pcs->desc.pctlops = &pcs_pinctrl_ops;
1740         pcs->desc.pmxops = &pcs_pinmux_ops;
1741         if (PCS_HAS_PINCONF)
1742                 pcs->desc.confops = &pcs_pinconf_ops;
1743         pcs->desc.owner = THIS_MODULE;
1744
1745         ret = pcs_allocate_pin_table(pcs);
1746         if (ret < 0)
1747                 goto free;
1748
1749         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1750         if (ret) {
1751                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1752                 goto free;
1753         }
1754
1755         ret = pcs_add_gpio_func(np, pcs);
1756         if (ret < 0)
1757                 goto free;
1758
1759         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1760         if (pcs->socdata.irq)
1761                 pcs->flags |= PCS_FEAT_IRQ;
1762
1763         /* We still need auxdata for some omaps for PRM interrupts */
1764         pdata = dev_get_platdata(&pdev->dev);
1765         if (pdata) {
1766                 if (pdata->rearm)
1767                         pcs->socdata.rearm = pdata->rearm;
1768                 if (pdata->irq) {
1769                         pcs->socdata.irq = pdata->irq;
1770                         pcs->flags |= PCS_FEAT_IRQ;
1771                 }
1772         }
1773
1774         if (PCS_HAS_IRQ) {
1775                 ret = pcs_irq_init_chained_handler(pcs, np);
1776                 if (ret < 0)
1777                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1778         }
1779
1780         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1781                  pcs->desc.npins, pcs->base, pcs->size);
1782
1783         return pinctrl_enable(pcs->pctl);
1784
1785 free:
1786         pcs_free_resources(pcs);
1787
1788         return ret;
1789 }
1790
1791 static int pcs_remove(struct platform_device *pdev)
1792 {
1793         struct pcs_device *pcs = platform_get_drvdata(pdev);
1794
1795         if (!pcs)
1796                 return 0;
1797
1798         pcs_free_resources(pcs);
1799
1800         return 0;
1801 }
1802
1803 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1804         .flags = PCS_QUIRK_SHARED_IRQ,
1805         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1806         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1807 };
1808
1809 static const struct pcs_soc_data pinctrl_single_dra7 = {
1810         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1811         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1812 };
1813
1814 static const struct pcs_soc_data pinctrl_single_am437x = {
1815         .flags = PCS_QUIRK_SHARED_IRQ,
1816         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1817         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1818 };
1819
1820 static const struct pcs_soc_data pinctrl_single = {
1821 };
1822
1823 static const struct pcs_soc_data pinconf_single = {
1824         .flags = PCS_FEAT_PINCONF,
1825 };
1826
1827 static const struct of_device_id pcs_of_match[] = {
1828         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1829         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1830         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1831         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1832         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1833         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1834         { .compatible = "pinconf-single", .data = &pinconf_single },
1835         { },
1836 };
1837 MODULE_DEVICE_TABLE(of, pcs_of_match);
1838
1839 static struct platform_driver pcs_driver = {
1840         .probe          = pcs_probe,
1841         .remove         = pcs_remove,
1842         .driver = {
1843                 .name           = DRIVER_NAME,
1844                 .of_match_table = pcs_of_match,
1845         },
1846 #ifdef CONFIG_PM
1847         .suspend = pinctrl_single_suspend,
1848         .resume = pinctrl_single_resume,
1849 #endif
1850 };
1851
1852 module_platform_driver(pcs_driver);
1853
1854 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1855 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1856 MODULE_LICENSE("GPL v2");