Merge tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[sfrench/cifs-2.6.git] / drivers / pinctrl / intel / pinctrl-sunrisepoint.c
1 /*
2  * Intel Sunrisepoint PCH pinctrl/GPIO driver
3  *
4  * Copyright (C) 2015, Intel Corporation
5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/acpi.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm.h>
17 #include <linux/pinctrl/pinctrl.h>
18
19 #include "pinctrl-intel.h"
20
21 #define SPT_PAD_OWN     0x020
22 #define SPT_PADCFGLOCK  0x0a0
23 #define SPT_HOSTSW_OWN  0x0d0
24 #define SPT_GPI_IE      0x120
25
26 #define SPT_COMMUNITY(b, s, e)                          \
27         {                                               \
28                 .barno = (b),                           \
29                 .padown_offset = SPT_PAD_OWN,           \
30                 .padcfglock_offset = SPT_PADCFGLOCK,    \
31                 .hostown_offset = SPT_HOSTSW_OWN,       \
32                 .ie_offset = SPT_GPI_IE,                \
33                 .gpp_size = 24,                         \
34                 .gpp_num_padown_regs = 4,               \
35                 .pin_base = (s),                        \
36                 .npins = ((e) - (s) + 1),               \
37         }
38
39 /* Sunrisepoint-LP */
40 static const struct pinctrl_pin_desc sptlp_pins[] = {
41         /* GPP_A */
42         PINCTRL_PIN(0, "RCINB"),
43         PINCTRL_PIN(1, "LAD_0"),
44         PINCTRL_PIN(2, "LAD_1"),
45         PINCTRL_PIN(3, "LAD_2"),
46         PINCTRL_PIN(4, "LAD_3"),
47         PINCTRL_PIN(5, "LFRAMEB"),
48         PINCTRL_PIN(6, "SERIQ"),
49         PINCTRL_PIN(7, "PIRQAB"),
50         PINCTRL_PIN(8, "CLKRUNB"),
51         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
52         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
53         PINCTRL_PIN(11, "PMEB"),
54         PINCTRL_PIN(12, "BM_BUSYB"),
55         PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
56         PINCTRL_PIN(14, "SUS_STATB"),
57         PINCTRL_PIN(15, "SUSACKB"),
58         PINCTRL_PIN(16, "SD_1P8_SEL"),
59         PINCTRL_PIN(17, "SD_PWR_EN_B"),
60         PINCTRL_PIN(18, "ISH_GP_0"),
61         PINCTRL_PIN(19, "ISH_GP_1"),
62         PINCTRL_PIN(20, "ISH_GP_2"),
63         PINCTRL_PIN(21, "ISH_GP_3"),
64         PINCTRL_PIN(22, "ISH_GP_4"),
65         PINCTRL_PIN(23, "ISH_GP_5"),
66         /* GPP_B */
67         PINCTRL_PIN(24, "CORE_VID_0"),
68         PINCTRL_PIN(25, "CORE_VID_1"),
69         PINCTRL_PIN(26, "VRALERTB"),
70         PINCTRL_PIN(27, "CPU_GP_2"),
71         PINCTRL_PIN(28, "CPU_GP_3"),
72         PINCTRL_PIN(29, "SRCCLKREQB_0"),
73         PINCTRL_PIN(30, "SRCCLKREQB_1"),
74         PINCTRL_PIN(31, "SRCCLKREQB_2"),
75         PINCTRL_PIN(32, "SRCCLKREQB_3"),
76         PINCTRL_PIN(33, "SRCCLKREQB_4"),
77         PINCTRL_PIN(34, "SRCCLKREQB_5"),
78         PINCTRL_PIN(35, "EXT_PWR_GATEB"),
79         PINCTRL_PIN(36, "SLP_S0B"),
80         PINCTRL_PIN(37, "PLTRSTB"),
81         PINCTRL_PIN(38, "SPKR"),
82         PINCTRL_PIN(39, "GSPI0_CSB"),
83         PINCTRL_PIN(40, "GSPI0_CLK"),
84         PINCTRL_PIN(41, "GSPI0_MISO"),
85         PINCTRL_PIN(42, "GSPI0_MOSI"),
86         PINCTRL_PIN(43, "GSPI1_CSB"),
87         PINCTRL_PIN(44, "GSPI1_CLK"),
88         PINCTRL_PIN(45, "GSPI1_MISO"),
89         PINCTRL_PIN(46, "GSPI1_MOSI"),
90         PINCTRL_PIN(47, "SML1ALERTB"),
91         /* GPP_C */
92         PINCTRL_PIN(48, "SMBCLK"),
93         PINCTRL_PIN(49, "SMBDATA"),
94         PINCTRL_PIN(50, "SMBALERTB"),
95         PINCTRL_PIN(51, "SML0CLK"),
96         PINCTRL_PIN(52, "SML0DATA"),
97         PINCTRL_PIN(53, "SML0ALERTB"),
98         PINCTRL_PIN(54, "SML1CLK"),
99         PINCTRL_PIN(55, "SML1DATA"),
100         PINCTRL_PIN(56, "UART0_RXD"),
101         PINCTRL_PIN(57, "UART0_TXD"),
102         PINCTRL_PIN(58, "UART0_RTSB"),
103         PINCTRL_PIN(59, "UART0_CTSB"),
104         PINCTRL_PIN(60, "UART1_RXD"),
105         PINCTRL_PIN(61, "UART1_TXD"),
106         PINCTRL_PIN(62, "UART1_RTSB"),
107         PINCTRL_PIN(63, "UART1_CTSB"),
108         PINCTRL_PIN(64, "I2C0_SDA"),
109         PINCTRL_PIN(65, "I2C0_SCL"),
110         PINCTRL_PIN(66, "I2C1_SDA"),
111         PINCTRL_PIN(67, "I2C1_SCL"),
112         PINCTRL_PIN(68, "UART2_RXD"),
113         PINCTRL_PIN(69, "UART2_TXD"),
114         PINCTRL_PIN(70, "UART2_RTSB"),
115         PINCTRL_PIN(71, "UART2_CTSB"),
116         /* GPP_D */
117         PINCTRL_PIN(72, "SPI1_CSB"),
118         PINCTRL_PIN(73, "SPI1_CLK"),
119         PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
120         PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
121         PINCTRL_PIN(76, "FLASHTRIG"),
122         PINCTRL_PIN(77, "ISH_I2C0_SDA"),
123         PINCTRL_PIN(78, "ISH_I2C0_SCL"),
124         PINCTRL_PIN(79, "ISH_I2C1_SDA"),
125         PINCTRL_PIN(80, "ISH_I2C1_SCL"),
126         PINCTRL_PIN(81, "ISH_SPI_CSB"),
127         PINCTRL_PIN(82, "ISH_SPI_CLK"),
128         PINCTRL_PIN(83, "ISH_SPI_MISO"),
129         PINCTRL_PIN(84, "ISH_SPI_MOSI"),
130         PINCTRL_PIN(85, "ISH_UART0_RXD"),
131         PINCTRL_PIN(86, "ISH_UART0_TXD"),
132         PINCTRL_PIN(87, "ISH_UART0_RTSB"),
133         PINCTRL_PIN(88, "ISH_UART0_CTSB"),
134         PINCTRL_PIN(89, "DMIC_CLK_1"),
135         PINCTRL_PIN(90, "DMIC_DATA_1"),
136         PINCTRL_PIN(91, "DMIC_CLK_0"),
137         PINCTRL_PIN(92, "DMIC_DATA_0"),
138         PINCTRL_PIN(93, "SPI1_IO_2"),
139         PINCTRL_PIN(94, "SPI1_IO_3"),
140         PINCTRL_PIN(95, "SSP_MCLK"),
141         /* GPP_E */
142         PINCTRL_PIN(96, "SATAXPCIE_0"),
143         PINCTRL_PIN(97, "SATAXPCIE_1"),
144         PINCTRL_PIN(98, "SATAXPCIE_2"),
145         PINCTRL_PIN(99, "CPU_GP_0"),
146         PINCTRL_PIN(100, "SATA_DEVSLP_0"),
147         PINCTRL_PIN(101, "SATA_DEVSLP_1"),
148         PINCTRL_PIN(102, "SATA_DEVSLP_2"),
149         PINCTRL_PIN(103, "CPU_GP_1"),
150         PINCTRL_PIN(104, "SATA_LEDB"),
151         PINCTRL_PIN(105, "USB2_OCB_0"),
152         PINCTRL_PIN(106, "USB2_OCB_1"),
153         PINCTRL_PIN(107, "USB2_OCB_2"),
154         PINCTRL_PIN(108, "USB2_OCB_3"),
155         PINCTRL_PIN(109, "DDSP_HPD_0"),
156         PINCTRL_PIN(110, "DDSP_HPD_1"),
157         PINCTRL_PIN(111, "DDSP_HPD_2"),
158         PINCTRL_PIN(112, "DDSP_HPD_3"),
159         PINCTRL_PIN(113, "EDP_HPD"),
160         PINCTRL_PIN(114, "DDPB_CTRLCLK"),
161         PINCTRL_PIN(115, "DDPB_CTRLDATA"),
162         PINCTRL_PIN(116, "DDPC_CTRLCLK"),
163         PINCTRL_PIN(117, "DDPC_CTRLDATA"),
164         PINCTRL_PIN(118, "DDPD_CTRLCLK"),
165         PINCTRL_PIN(119, "DDPD_CTRLDATA"),
166         /* GPP_F */
167         PINCTRL_PIN(120, "SSP2_SCLK"),
168         PINCTRL_PIN(121, "SSP2_SFRM"),
169         PINCTRL_PIN(122, "SSP2_TXD"),
170         PINCTRL_PIN(123, "SSP2_RXD"),
171         PINCTRL_PIN(124, "I2C2_SDA"),
172         PINCTRL_PIN(125, "I2C2_SCL"),
173         PINCTRL_PIN(126, "I2C3_SDA"),
174         PINCTRL_PIN(127, "I2C3_SCL"),
175         PINCTRL_PIN(128, "I2C4_SDA"),
176         PINCTRL_PIN(129, "I2C4_SCL"),
177         PINCTRL_PIN(130, "I2C5_SDA"),
178         PINCTRL_PIN(131, "I2C5_SCL"),
179         PINCTRL_PIN(132, "EMMC_CMD"),
180         PINCTRL_PIN(133, "EMMC_DATA_0"),
181         PINCTRL_PIN(134, "EMMC_DATA_1"),
182         PINCTRL_PIN(135, "EMMC_DATA_2"),
183         PINCTRL_PIN(136, "EMMC_DATA_3"),
184         PINCTRL_PIN(137, "EMMC_DATA_4"),
185         PINCTRL_PIN(138, "EMMC_DATA_5"),
186         PINCTRL_PIN(139, "EMMC_DATA_6"),
187         PINCTRL_PIN(140, "EMMC_DATA_7"),
188         PINCTRL_PIN(141, "EMMC_RCLK"),
189         PINCTRL_PIN(142, "EMMC_CLK"),
190         PINCTRL_PIN(143, "GPP_F_23"),
191         /* GPP_G */
192         PINCTRL_PIN(144, "SD_CMD"),
193         PINCTRL_PIN(145, "SD_DATA_0"),
194         PINCTRL_PIN(146, "SD_DATA_1"),
195         PINCTRL_PIN(147, "SD_DATA_2"),
196         PINCTRL_PIN(148, "SD_DATA_3"),
197         PINCTRL_PIN(149, "SD_CDB"),
198         PINCTRL_PIN(150, "SD_CLK"),
199         PINCTRL_PIN(151, "SD_WP"),
200 };
201
202 static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
203 static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
204 static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
205 static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
206 static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
207 static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
208 static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
209 static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
210 static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
211 static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
212 static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
213 static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
214 static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
215 static const unsigned sptlp_emmc_pins[] = {
216         132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
217 };
218 static const unsigned sptlp_sd_pins[] = {
219         144, 145, 146, 147, 148, 149, 150, 151,
220 };
221
222 static const struct intel_pingroup sptlp_groups[] = {
223         PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
224         PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
225         PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
226         PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
227         PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
228         PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
229         PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
230         PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
231         PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
232         PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
233         PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
234         PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
235         PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
236         PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
237         PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
238 };
239
240 static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
241 static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
242 static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
243 static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
244 static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
245 static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
246 static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
247 static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
248 static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
249 static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
250 static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
251 static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
252 static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
253 static const char * const sptlp_sd_groups[] = { "sd_grp" };
254
255 static const struct intel_function sptlp_functions[] = {
256         FUNCTION("spi0", sptlp_spi0_groups),
257         FUNCTION("spi1", sptlp_spi1_groups),
258         FUNCTION("uart0", sptlp_uart0_groups),
259         FUNCTION("uart1", sptlp_uart1_groups),
260         FUNCTION("uart2", sptlp_uart2_groups),
261         FUNCTION("i2c0", sptlp_i2c0_groups),
262         FUNCTION("i2c1", sptlp_i2c1_groups),
263         FUNCTION("i2c2", sptlp_i2c2_groups),
264         FUNCTION("i2c3", sptlp_i2c3_groups),
265         FUNCTION("i2c4", sptlp_i2c4_groups),
266         FUNCTION("i2c5", sptlp_i2c5_groups),
267         FUNCTION("ssp2", sptlp_ssp2_groups),
268         FUNCTION("emmc", sptlp_emmc_groups),
269         FUNCTION("sd", sptlp_sd_groups),
270 };
271
272 static const struct intel_community sptlp_communities[] = {
273         SPT_COMMUNITY(0, 0, 47),
274         SPT_COMMUNITY(1, 48, 119),
275         SPT_COMMUNITY(2, 120, 151),
276 };
277
278 static const struct intel_pinctrl_soc_data sptlp_soc_data = {
279         .pins = sptlp_pins,
280         .npins = ARRAY_SIZE(sptlp_pins),
281         .groups = sptlp_groups,
282         .ngroups = ARRAY_SIZE(sptlp_groups),
283         .functions = sptlp_functions,
284         .nfunctions = ARRAY_SIZE(sptlp_functions),
285         .communities = sptlp_communities,
286         .ncommunities = ARRAY_SIZE(sptlp_communities),
287 };
288
289 /* Sunrisepoint-H */
290 static const struct pinctrl_pin_desc spth_pins[] = {
291         /* GPP_A */
292         PINCTRL_PIN(0, "RCINB"),
293         PINCTRL_PIN(1, "LAD_0"),
294         PINCTRL_PIN(2, "LAD_1"),
295         PINCTRL_PIN(3, "LAD_2"),
296         PINCTRL_PIN(4, "LAD_3"),
297         PINCTRL_PIN(5, "LFRAMEB"),
298         PINCTRL_PIN(6, "SERIQ"),
299         PINCTRL_PIN(7, "PIRQAB"),
300         PINCTRL_PIN(8, "CLKRUNB"),
301         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
302         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
303         PINCTRL_PIN(11, "PMEB"),
304         PINCTRL_PIN(12, "BM_BUSYB"),
305         PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
306         PINCTRL_PIN(14, "SUS_STATB"),
307         PINCTRL_PIN(15, "SUSACKB"),
308         PINCTRL_PIN(16, "CLKOUT_48"),
309         PINCTRL_PIN(17, "ISH_GP_7"),
310         PINCTRL_PIN(18, "ISH_GP_0"),
311         PINCTRL_PIN(19, "ISH_GP_1"),
312         PINCTRL_PIN(20, "ISH_GP_2"),
313         PINCTRL_PIN(21, "ISH_GP_3"),
314         PINCTRL_PIN(22, "ISH_GP_4"),
315         PINCTRL_PIN(23, "ISH_GP_5"),
316         /* GPP_B */
317         PINCTRL_PIN(24, "CORE_VID_0"),
318         PINCTRL_PIN(25, "CORE_VID_1"),
319         PINCTRL_PIN(26, "VRALERTB"),
320         PINCTRL_PIN(27, "CPU_GP_2"),
321         PINCTRL_PIN(28, "CPU_GP_3"),
322         PINCTRL_PIN(29, "SRCCLKREQB_0"),
323         PINCTRL_PIN(30, "SRCCLKREQB_1"),
324         PINCTRL_PIN(31, "SRCCLKREQB_2"),
325         PINCTRL_PIN(32, "SRCCLKREQB_3"),
326         PINCTRL_PIN(33, "SRCCLKREQB_4"),
327         PINCTRL_PIN(34, "SRCCLKREQB_5"),
328         PINCTRL_PIN(35, "EXT_PWR_GATEB"),
329         PINCTRL_PIN(36, "SLP_S0B"),
330         PINCTRL_PIN(37, "PLTRSTB"),
331         PINCTRL_PIN(38, "SPKR"),
332         PINCTRL_PIN(39, "GSPI0_CSB"),
333         PINCTRL_PIN(40, "GSPI0_CLK"),
334         PINCTRL_PIN(41, "GSPI0_MISO"),
335         PINCTRL_PIN(42, "GSPI0_MOSI"),
336         PINCTRL_PIN(43, "GSPI1_CSB"),
337         PINCTRL_PIN(44, "GSPI1_CLK"),
338         PINCTRL_PIN(45, "GSPI1_MISO"),
339         PINCTRL_PIN(46, "GSPI1_MOSI"),
340         PINCTRL_PIN(47, "SML1ALERTB"),
341         /* GPP_C */
342         PINCTRL_PIN(48, "SMBCLK"),
343         PINCTRL_PIN(49, "SMBDATA"),
344         PINCTRL_PIN(50, "SMBALERTB"),
345         PINCTRL_PIN(51, "SML0CLK"),
346         PINCTRL_PIN(52, "SML0DATA"),
347         PINCTRL_PIN(53, "SML0ALERTB"),
348         PINCTRL_PIN(54, "SML1CLK"),
349         PINCTRL_PIN(55, "SML1DATA"),
350         PINCTRL_PIN(56, "UART0_RXD"),
351         PINCTRL_PIN(57, "UART0_TXD"),
352         PINCTRL_PIN(58, "UART0_RTSB"),
353         PINCTRL_PIN(59, "UART0_CTSB"),
354         PINCTRL_PIN(60, "UART1_RXD"),
355         PINCTRL_PIN(61, "UART1_TXD"),
356         PINCTRL_PIN(62, "UART1_RTSB"),
357         PINCTRL_PIN(63, "UART1_CTSB"),
358         PINCTRL_PIN(64, "I2C0_SDA"),
359         PINCTRL_PIN(65, "I2C0_SCL"),
360         PINCTRL_PIN(66, "I2C1_SDA"),
361         PINCTRL_PIN(67, "I2C1_SCL"),
362         PINCTRL_PIN(68, "UART2_RXD"),
363         PINCTRL_PIN(69, "UART2_TXD"),
364         PINCTRL_PIN(70, "UART2_RTSB"),
365         PINCTRL_PIN(71, "UART2_CTSB"),
366         /* GPP_D */
367         PINCTRL_PIN(72, "SPI1_CSB"),
368         PINCTRL_PIN(73, "SPI1_CLK"),
369         PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
370         PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
371         PINCTRL_PIN(76, "ISH_I2C2_SDA"),
372         PINCTRL_PIN(77, "SSP0_SFRM"),
373         PINCTRL_PIN(78, "SSP0_TXD"),
374         PINCTRL_PIN(79, "SSP0_RXD"),
375         PINCTRL_PIN(80, "SSP0_SCLK"),
376         PINCTRL_PIN(81, "ISH_SPI_CSB"),
377         PINCTRL_PIN(82, "ISH_SPI_CLK"),
378         PINCTRL_PIN(83, "ISH_SPI_MISO"),
379         PINCTRL_PIN(84, "ISH_SPI_MOSI"),
380         PINCTRL_PIN(85, "ISH_UART0_RXD"),
381         PINCTRL_PIN(86, "ISH_UART0_TXD"),
382         PINCTRL_PIN(87, "ISH_UART0_RTSB"),
383         PINCTRL_PIN(88, "ISH_UART0_CTSB"),
384         PINCTRL_PIN(89, "DMIC_CLK_1"),
385         PINCTRL_PIN(90, "DMIC_DATA_1"),
386         PINCTRL_PIN(91, "DMIC_CLK_0"),
387         PINCTRL_PIN(92, "DMIC_DATA_0"),
388         PINCTRL_PIN(93, "SPI1_IO_2"),
389         PINCTRL_PIN(94, "SPI1_IO_3"),
390         PINCTRL_PIN(95, "ISH_I2C2_SCL"),
391         /* GPP_E */
392         PINCTRL_PIN(96, "SATAXPCIE_0"),
393         PINCTRL_PIN(97, "SATAXPCIE_1"),
394         PINCTRL_PIN(98, "SATAXPCIE_2"),
395         PINCTRL_PIN(99, "CPU_GP_0"),
396         PINCTRL_PIN(100, "SATA_DEVSLP_0"),
397         PINCTRL_PIN(101, "SATA_DEVSLP_1"),
398         PINCTRL_PIN(102, "SATA_DEVSLP_2"),
399         PINCTRL_PIN(103, "CPU_GP_1"),
400         PINCTRL_PIN(104, "SATA_LEDB"),
401         PINCTRL_PIN(105, "USB2_OCB_0"),
402         PINCTRL_PIN(106, "USB2_OCB_1"),
403         PINCTRL_PIN(107, "USB2_OCB_2"),
404         PINCTRL_PIN(108, "USB2_OCB_3"),
405         /* GPP_F */
406         PINCTRL_PIN(109, "SATAXPCIE_3"),
407         PINCTRL_PIN(110, "SATAXPCIE_4"),
408         PINCTRL_PIN(111, "SATAXPCIE_5"),
409         PINCTRL_PIN(112, "SATAXPCIE_6"),
410         PINCTRL_PIN(113, "SATAXPCIE_7"),
411         PINCTRL_PIN(114, "SATA_DEVSLP_3"),
412         PINCTRL_PIN(115, "SATA_DEVSLP_4"),
413         PINCTRL_PIN(116, "SATA_DEVSLP_5"),
414         PINCTRL_PIN(117, "SATA_DEVSLP_6"),
415         PINCTRL_PIN(118, "SATA_DEVSLP_7"),
416         PINCTRL_PIN(119, "SATA_SCLOCK"),
417         PINCTRL_PIN(120, "SATA_SLOAD"),
418         PINCTRL_PIN(121, "SATA_SDATAOUT1"),
419         PINCTRL_PIN(122, "SATA_SDATAOUT0"),
420         PINCTRL_PIN(123, "GPP_F_14"),
421         PINCTRL_PIN(124, "USB_OCB_4"),
422         PINCTRL_PIN(125, "USB_OCB_5"),
423         PINCTRL_PIN(126, "USB_OCB_6"),
424         PINCTRL_PIN(127, "USB_OCB_7"),
425         PINCTRL_PIN(128, "L_VDDEN"),
426         PINCTRL_PIN(129, "L_BKLTEN"),
427         PINCTRL_PIN(130, "L_BKLTCTL"),
428         PINCTRL_PIN(131, "GPP_F_22"),
429         PINCTRL_PIN(132, "GPP_F_23"),
430         /* GPP_G */
431         PINCTRL_PIN(133, "FAN_TACH_0"),
432         PINCTRL_PIN(134, "FAN_TACH_1"),
433         PINCTRL_PIN(135, "FAN_TACH_2"),
434         PINCTRL_PIN(136, "FAN_TACH_3"),
435         PINCTRL_PIN(137, "FAN_TACH_4"),
436         PINCTRL_PIN(138, "FAN_TACH_5"),
437         PINCTRL_PIN(139, "FAN_TACH_6"),
438         PINCTRL_PIN(140, "FAN_TACH_7"),
439         PINCTRL_PIN(141, "FAN_PWM_0"),
440         PINCTRL_PIN(142, "FAN_PWM_1"),
441         PINCTRL_PIN(143, "FAN_PWM_2"),
442         PINCTRL_PIN(144, "FAN_PWM_3"),
443         PINCTRL_PIN(145, "GSXDOUT"),
444         PINCTRL_PIN(146, "GSXSLOAD"),
445         PINCTRL_PIN(147, "GSXDIN"),
446         PINCTRL_PIN(148, "GSXRESETB"),
447         PINCTRL_PIN(149, "GSXCLK"),
448         PINCTRL_PIN(150, "ADR_COMPLETE"),
449         PINCTRL_PIN(151, "NMIB"),
450         PINCTRL_PIN(152, "SMIB"),
451         PINCTRL_PIN(153, "GPP_G_20"),
452         PINCTRL_PIN(154, "GPP_G_21"),
453         PINCTRL_PIN(155, "GPP_G_22"),
454         PINCTRL_PIN(156, "GPP_G_23"),
455         /* GPP_H */
456         PINCTRL_PIN(157, "SRCCLKREQB_6"),
457         PINCTRL_PIN(158, "SRCCLKREQB_7"),
458         PINCTRL_PIN(159, "SRCCLKREQB_8"),
459         PINCTRL_PIN(160, "SRCCLKREQB_9"),
460         PINCTRL_PIN(161, "SRCCLKREQB_10"),
461         PINCTRL_PIN(162, "SRCCLKREQB_11"),
462         PINCTRL_PIN(163, "SRCCLKREQB_12"),
463         PINCTRL_PIN(164, "SRCCLKREQB_13"),
464         PINCTRL_PIN(165, "SRCCLKREQB_14"),
465         PINCTRL_PIN(166, "SRCCLKREQB_15"),
466         PINCTRL_PIN(167, "SML2CLK"),
467         PINCTRL_PIN(168, "SML2DATA"),
468         PINCTRL_PIN(169, "SML2ALERTB"),
469         PINCTRL_PIN(170, "SML3CLK"),
470         PINCTRL_PIN(171, "SML3DATA"),
471         PINCTRL_PIN(172, "SML3ALERTB"),
472         PINCTRL_PIN(173, "SML4CLK"),
473         PINCTRL_PIN(174, "SML4DATA"),
474         PINCTRL_PIN(175, "SML4ALERTB"),
475         PINCTRL_PIN(176, "ISH_I2C0_SDA"),
476         PINCTRL_PIN(177, "ISH_I2C0_SCL"),
477         PINCTRL_PIN(178, "ISH_I2C1_SDA"),
478         PINCTRL_PIN(179, "ISH_I2C1_SCL"),
479         PINCTRL_PIN(180, "GPP_H_23"),
480         /* GPP_I */
481         PINCTRL_PIN(181, "DDSP_HDP_0"),
482         PINCTRL_PIN(182, "DDSP_HDP_1"),
483         PINCTRL_PIN(183, "DDSP_HDP_2"),
484         PINCTRL_PIN(184, "DDSP_HDP_3"),
485         PINCTRL_PIN(185, "EDP_HPD"),
486         PINCTRL_PIN(186, "DDPB_CTRLCLK"),
487         PINCTRL_PIN(187, "DDPB_CTRLDATA"),
488         PINCTRL_PIN(188, "DDPC_CTRLCLK"),
489         PINCTRL_PIN(189, "DDPC_CTRLDATA"),
490         PINCTRL_PIN(190, "DDPD_CTRLCLK"),
491         PINCTRL_PIN(191, "DDPD_CTRLDATA"),
492 };
493
494 static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
495 static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
496 static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
497 static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
498 static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
499 static const unsigned spth_i2c0_pins[] = { 64, 65 };
500 static const unsigned spth_i2c1_pins[] = { 66, 67 };
501 static const unsigned spth_i2c2_pins[] = { 76, 95 };
502
503 static const struct intel_pingroup spth_groups[] = {
504         PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
505         PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
506         PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
507         PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
508         PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
509         PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
510         PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
511         PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
512 };
513
514 static const char * const spth_spi0_groups[] = { "spi0_grp" };
515 static const char * const spth_spi1_groups[] = { "spi0_grp" };
516 static const char * const spth_uart0_groups[] = { "uart0_grp" };
517 static const char * const spth_uart1_groups[] = { "uart1_grp" };
518 static const char * const spth_uart2_groups[] = { "uart2_grp" };
519 static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
520 static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
521 static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
522
523 static const struct intel_function spth_functions[] = {
524         FUNCTION("spi0", spth_spi0_groups),
525         FUNCTION("spi1", spth_spi1_groups),
526         FUNCTION("uart0", spth_uart0_groups),
527         FUNCTION("uart1", spth_uart1_groups),
528         FUNCTION("uart2", spth_uart2_groups),
529         FUNCTION("i2c0", spth_i2c0_groups),
530         FUNCTION("i2c1", spth_i2c1_groups),
531         FUNCTION("i2c2", spth_i2c2_groups),
532 };
533
534 static const struct intel_community spth_communities[] = {
535         SPT_COMMUNITY(0, 0, 47),
536         SPT_COMMUNITY(1, 48, 180),
537         SPT_COMMUNITY(2, 181, 191),
538 };
539
540 static const struct intel_pinctrl_soc_data spth_soc_data = {
541         .pins = spth_pins,
542         .npins = ARRAY_SIZE(spth_pins),
543         .groups = spth_groups,
544         .ngroups = ARRAY_SIZE(spth_groups),
545         .functions = spth_functions,
546         .nfunctions = ARRAY_SIZE(spth_functions),
547         .communities = spth_communities,
548         .ncommunities = ARRAY_SIZE(spth_communities),
549 };
550
551 static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
552         { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
553         { "INT345D", (kernel_ulong_t)&spth_soc_data },
554         { }
555 };
556 MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
557
558 static int spt_pinctrl_probe(struct platform_device *pdev)
559 {
560         const struct intel_pinctrl_soc_data *soc_data;
561         const struct acpi_device_id *id;
562
563         id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev);
564         if (!id || !id->driver_data)
565                 return -ENODEV;
566
567         soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
568         return intel_pinctrl_probe(pdev, soc_data);
569 }
570
571 static const struct dev_pm_ops spt_pinctrl_pm_ops = {
572         SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
573                                      intel_pinctrl_resume)
574 };
575
576 static struct platform_driver spt_pinctrl_driver = {
577         .probe = spt_pinctrl_probe,
578         .driver = {
579                 .name = "sunrisepoint-pinctrl",
580                 .acpi_match_table = spt_pinctrl_acpi_match,
581                 .pm = &spt_pinctrl_pm_ops,
582         },
583 };
584
585 static int __init spt_pinctrl_init(void)
586 {
587         return platform_driver_register(&spt_pinctrl_driver);
588 }
589 subsys_initcall(spt_pinctrl_init);
590
591 static void __exit spt_pinctrl_exit(void)
592 {
593         platform_driver_unregister(&spt_pinctrl_driver);
594 }
595 module_exit(spt_pinctrl_exit);
596
597 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
598 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
599 MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
600 MODULE_LICENSE("GPL v2");