Merge tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[sfrench/cifs-2.6.git] / drivers / pinctrl / intel / pinctrl-intel.c
1 /*
2  * Intel pinctrl/GPIO core driver.
3  *
4  * Copyright (C) 2015, Intel Corporation
5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/log2.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22
23 #include "../core.h"
24 #include "pinctrl-intel.h"
25
26 /* Offset from regs */
27 #define REVID                           0x000
28 #define REVID_SHIFT                     16
29 #define REVID_MASK                      GENMASK(31, 16)
30
31 #define PADBAR                          0x00c
32 #define GPI_IS                          0x100
33
34 #define PADOWN_BITS                     4
35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
36 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
37 #define PADOWN_GPP(p)                   ((p) / 8)
38
39 /* Offset from pad_regs */
40 #define PADCFG0                         0x000
41 #define PADCFG0_RXEVCFG_SHIFT           25
42 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
43 #define PADCFG0_RXEVCFG_LEVEL           0
44 #define PADCFG0_RXEVCFG_EDGE            1
45 #define PADCFG0_RXEVCFG_DISABLED        2
46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
47 #define PADCFG0_PREGFRXSEL              BIT(24)
48 #define PADCFG0_RXINV                   BIT(23)
49 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
50 #define PADCFG0_GPIROUTSCI              BIT(19)
51 #define PADCFG0_GPIROUTSMI              BIT(18)
52 #define PADCFG0_GPIROUTNMI              BIT(17)
53 #define PADCFG0_PMODE_SHIFT             10
54 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
55 #define PADCFG0_GPIORXDIS               BIT(9)
56 #define PADCFG0_GPIOTXDIS               BIT(8)
57 #define PADCFG0_GPIORXSTATE             BIT(1)
58 #define PADCFG0_GPIOTXSTATE             BIT(0)
59
60 #define PADCFG1                         0x004
61 #define PADCFG1_TERM_UP                 BIT(13)
62 #define PADCFG1_TERM_SHIFT              10
63 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
64 #define PADCFG1_TERM_20K                4
65 #define PADCFG1_TERM_2K                 3
66 #define PADCFG1_TERM_5K                 2
67 #define PADCFG1_TERM_1K                 1
68
69 #define PADCFG2                         0x008
70 #define PADCFG2_DEBEN                   BIT(0)
71 #define PADCFG2_DEBOUNCE_SHIFT          1
72 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
73
74 #define DEBOUNCE_PERIOD                 31250 /* ns */
75
76 struct intel_pad_context {
77         u32 padcfg0;
78         u32 padcfg1;
79         u32 padcfg2;
80 };
81
82 struct intel_community_context {
83         u32 *intmask;
84 };
85
86 struct intel_pinctrl_context {
87         struct intel_pad_context *pads;
88         struct intel_community_context *communities;
89 };
90
91 /**
92  * struct intel_pinctrl - Intel pinctrl private structure
93  * @dev: Pointer to the device structure
94  * @lock: Lock to serialize register access
95  * @pctldesc: Pin controller description
96  * @pctldev: Pointer to the pin controller device
97  * @chip: GPIO chip in this pin controller
98  * @soc: SoC/PCH specific pin configuration data
99  * @communities: All communities in this pin controller
100  * @ncommunities: Number of communities in this pin controller
101  * @context: Configuration saved over system sleep
102  * @irq: pinctrl/GPIO chip irq number
103  */
104 struct intel_pinctrl {
105         struct device *dev;
106         raw_spinlock_t lock;
107         struct pinctrl_desc pctldesc;
108         struct pinctrl_dev *pctldev;
109         struct gpio_chip chip;
110         const struct intel_pinctrl_soc_data *soc;
111         struct intel_community *communities;
112         size_t ncommunities;
113         struct intel_pinctrl_context context;
114         int irq;
115 };
116
117 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
118 #define padgroup_offset(g, p)   ((p) - (g)->base)
119
120 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
121                                                    unsigned pin)
122 {
123         struct intel_community *community;
124         int i;
125
126         for (i = 0; i < pctrl->ncommunities; i++) {
127                 community = &pctrl->communities[i];
128                 if (pin >= community->pin_base &&
129                     pin < community->pin_base + community->npins)
130                         return community;
131         }
132
133         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
134         return NULL;
135 }
136
137 static const struct intel_padgroup *
138 intel_community_get_padgroup(const struct intel_community *community,
139                              unsigned pin)
140 {
141         int i;
142
143         for (i = 0; i < community->ngpps; i++) {
144                 const struct intel_padgroup *padgrp = &community->gpps[i];
145
146                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
147                         return padgrp;
148         }
149
150         return NULL;
151 }
152
153 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
154                                       unsigned reg)
155 {
156         const struct intel_community *community;
157         unsigned padno;
158         size_t nregs;
159
160         community = intel_get_community(pctrl, pin);
161         if (!community)
162                 return NULL;
163
164         padno = pin_to_padno(community, pin);
165         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
166
167         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
168                 return NULL;
169
170         return community->pad_regs + reg + padno * nregs * 4;
171 }
172
173 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
174 {
175         const struct intel_community *community;
176         const struct intel_padgroup *padgrp;
177         unsigned gpp, offset, gpp_offset;
178         void __iomem *padown;
179
180         community = intel_get_community(pctrl, pin);
181         if (!community)
182                 return false;
183         if (!community->padown_offset)
184                 return true;
185
186         padgrp = intel_community_get_padgroup(community, pin);
187         if (!padgrp)
188                 return false;
189
190         gpp_offset = padgroup_offset(padgrp, pin);
191         gpp = PADOWN_GPP(gpp_offset);
192         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
193         padown = community->regs + offset;
194
195         return !(readl(padown) & PADOWN_MASK(gpp_offset));
196 }
197
198 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
199 {
200         const struct intel_community *community;
201         const struct intel_padgroup *padgrp;
202         unsigned offset, gpp_offset;
203         void __iomem *hostown;
204
205         community = intel_get_community(pctrl, pin);
206         if (!community)
207                 return true;
208         if (!community->hostown_offset)
209                 return false;
210
211         padgrp = intel_community_get_padgroup(community, pin);
212         if (!padgrp)
213                 return true;
214
215         gpp_offset = padgroup_offset(padgrp, pin);
216         offset = community->hostown_offset + padgrp->reg_num * 4;
217         hostown = community->regs + offset;
218
219         return !(readl(hostown) & BIT(gpp_offset));
220 }
221
222 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
223 {
224         struct intel_community *community;
225         const struct intel_padgroup *padgrp;
226         unsigned offset, gpp_offset;
227         u32 value;
228
229         community = intel_get_community(pctrl, pin);
230         if (!community)
231                 return true;
232         if (!community->padcfglock_offset)
233                 return false;
234
235         padgrp = intel_community_get_padgroup(community, pin);
236         if (!padgrp)
237                 return true;
238
239         gpp_offset = padgroup_offset(padgrp, pin);
240
241         /*
242          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
243          * the pad is considered unlocked. Any other case means that it is
244          * either fully or partially locked and we don't touch it.
245          */
246         offset = community->padcfglock_offset + padgrp->reg_num * 8;
247         value = readl(community->regs + offset);
248         if (value & BIT(gpp_offset))
249                 return true;
250
251         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
252         value = readl(community->regs + offset);
253         if (value & BIT(gpp_offset))
254                 return true;
255
256         return false;
257 }
258
259 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
260 {
261         return intel_pad_owned_by_host(pctrl, pin) &&
262                 !intel_pad_locked(pctrl, pin);
263 }
264
265 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
266 {
267         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
268
269         return pctrl->soc->ngroups;
270 }
271
272 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
273                                       unsigned group)
274 {
275         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
276
277         return pctrl->soc->groups[group].name;
278 }
279
280 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
281                               const unsigned **pins, unsigned *npins)
282 {
283         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
284
285         *pins = pctrl->soc->groups[group].pins;
286         *npins = pctrl->soc->groups[group].npins;
287         return 0;
288 }
289
290 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
291                                unsigned pin)
292 {
293         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
294         void __iomem *padcfg;
295         u32 cfg0, cfg1, mode;
296         bool locked, acpi;
297
298         if (!intel_pad_owned_by_host(pctrl, pin)) {
299                 seq_puts(s, "not available");
300                 return;
301         }
302
303         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
304         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
305
306         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
307         if (!mode)
308                 seq_puts(s, "GPIO ");
309         else
310                 seq_printf(s, "mode %d ", mode);
311
312         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
313
314         /* Dump the additional PADCFG registers if available */
315         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
316         if (padcfg)
317                 seq_printf(s, " 0x%08x", readl(padcfg));
318
319         locked = intel_pad_locked(pctrl, pin);
320         acpi = intel_pad_acpi_mode(pctrl, pin);
321
322         if (locked || acpi) {
323                 seq_puts(s, " [");
324                 if (locked) {
325                         seq_puts(s, "LOCKED");
326                         if (acpi)
327                                 seq_puts(s, ", ");
328                 }
329                 if (acpi)
330                         seq_puts(s, "ACPI");
331                 seq_puts(s, "]");
332         }
333 }
334
335 static const struct pinctrl_ops intel_pinctrl_ops = {
336         .get_groups_count = intel_get_groups_count,
337         .get_group_name = intel_get_group_name,
338         .get_group_pins = intel_get_group_pins,
339         .pin_dbg_show = intel_pin_dbg_show,
340 };
341
342 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
343 {
344         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
345
346         return pctrl->soc->nfunctions;
347 }
348
349 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
350                                            unsigned function)
351 {
352         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
353
354         return pctrl->soc->functions[function].name;
355 }
356
357 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
358                                      unsigned function,
359                                      const char * const **groups,
360                                      unsigned * const ngroups)
361 {
362         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
363
364         *groups = pctrl->soc->functions[function].groups;
365         *ngroups = pctrl->soc->functions[function].ngroups;
366         return 0;
367 }
368
369 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
370                                 unsigned group)
371 {
372         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
373         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
374         unsigned long flags;
375         int i;
376
377         raw_spin_lock_irqsave(&pctrl->lock, flags);
378
379         /*
380          * All pins in the groups needs to be accessible and writable
381          * before we can enable the mux for this group.
382          */
383         for (i = 0; i < grp->npins; i++) {
384                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
385                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
386                         return -EBUSY;
387                 }
388         }
389
390         /* Now enable the mux setting for each pin in the group */
391         for (i = 0; i < grp->npins; i++) {
392                 void __iomem *padcfg0;
393                 u32 value;
394
395                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
396                 value = readl(padcfg0);
397
398                 value &= ~PADCFG0_PMODE_MASK;
399
400                 if (grp->modes)
401                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
402                 else
403                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
404
405                 writel(value, padcfg0);
406         }
407
408         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
409
410         return 0;
411 }
412
413 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
414 {
415         u32 value;
416
417         value = readl(padcfg0);
418         if (input) {
419                 value &= ~PADCFG0_GPIORXDIS;
420                 value |= PADCFG0_GPIOTXDIS;
421         } else {
422                 value &= ~PADCFG0_GPIOTXDIS;
423                 value |= PADCFG0_GPIORXDIS;
424         }
425         writel(value, padcfg0);
426 }
427
428 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
429                                      struct pinctrl_gpio_range *range,
430                                      unsigned pin)
431 {
432         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
433         void __iomem *padcfg0;
434         unsigned long flags;
435         u32 value;
436
437         raw_spin_lock_irqsave(&pctrl->lock, flags);
438
439         if (!intel_pad_usable(pctrl, pin)) {
440                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
441                 return -EBUSY;
442         }
443
444         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
445         /* Put the pad into GPIO mode */
446         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
447         /* Disable SCI/SMI/NMI generation */
448         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
449         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
450         writel(value, padcfg0);
451
452         /* Disable TX buffer and enable RX (this will be input) */
453         __intel_gpio_set_direction(padcfg0, true);
454
455         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
456
457         return 0;
458 }
459
460 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
461                                     struct pinctrl_gpio_range *range,
462                                     unsigned pin, bool input)
463 {
464         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
465         void __iomem *padcfg0;
466         unsigned long flags;
467
468         raw_spin_lock_irqsave(&pctrl->lock, flags);
469
470         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
471         __intel_gpio_set_direction(padcfg0, input);
472
473         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
474
475         return 0;
476 }
477
478 static const struct pinmux_ops intel_pinmux_ops = {
479         .get_functions_count = intel_get_functions_count,
480         .get_function_name = intel_get_function_name,
481         .get_function_groups = intel_get_function_groups,
482         .set_mux = intel_pinmux_set_mux,
483         .gpio_request_enable = intel_gpio_request_enable,
484         .gpio_set_direction = intel_gpio_set_direction,
485 };
486
487 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
488                             unsigned long *config)
489 {
490         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
491         enum pin_config_param param = pinconf_to_config_param(*config);
492         const struct intel_community *community;
493         u32 value, term;
494         u32 arg = 0;
495
496         if (!intel_pad_owned_by_host(pctrl, pin))
497                 return -ENOTSUPP;
498
499         community = intel_get_community(pctrl, pin);
500         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
501         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
502
503         switch (param) {
504         case PIN_CONFIG_BIAS_DISABLE:
505                 if (term)
506                         return -EINVAL;
507                 break;
508
509         case PIN_CONFIG_BIAS_PULL_UP:
510                 if (!term || !(value & PADCFG1_TERM_UP))
511                         return -EINVAL;
512
513                 switch (term) {
514                 case PADCFG1_TERM_1K:
515                         arg = 1000;
516                         break;
517                 case PADCFG1_TERM_2K:
518                         arg = 2000;
519                         break;
520                 case PADCFG1_TERM_5K:
521                         arg = 5000;
522                         break;
523                 case PADCFG1_TERM_20K:
524                         arg = 20000;
525                         break;
526                 }
527
528                 break;
529
530         case PIN_CONFIG_BIAS_PULL_DOWN:
531                 if (!term || value & PADCFG1_TERM_UP)
532                         return -EINVAL;
533
534                 switch (term) {
535                 case PADCFG1_TERM_1K:
536                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
537                                 return -EINVAL;
538                         arg = 1000;
539                         break;
540                 case PADCFG1_TERM_5K:
541                         arg = 5000;
542                         break;
543                 case PADCFG1_TERM_20K:
544                         arg = 20000;
545                         break;
546                 }
547
548                 break;
549
550         case PIN_CONFIG_INPUT_DEBOUNCE: {
551                 void __iomem *padcfg2;
552                 u32 v;
553
554                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
555                 if (!padcfg2)
556                         return -ENOTSUPP;
557
558                 v = readl(padcfg2);
559                 if (!(v & PADCFG2_DEBEN))
560                         return -EINVAL;
561
562                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
563                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
564
565                 break;
566         }
567
568         default:
569                 return -ENOTSUPP;
570         }
571
572         *config = pinconf_to_config_packed(param, arg);
573         return 0;
574 }
575
576 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
577                                  unsigned long config)
578 {
579         unsigned param = pinconf_to_config_param(config);
580         unsigned arg = pinconf_to_config_argument(config);
581         const struct intel_community *community;
582         void __iomem *padcfg1;
583         unsigned long flags;
584         int ret = 0;
585         u32 value;
586
587         raw_spin_lock_irqsave(&pctrl->lock, flags);
588
589         community = intel_get_community(pctrl, pin);
590         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
591         value = readl(padcfg1);
592
593         switch (param) {
594         case PIN_CONFIG_BIAS_DISABLE:
595                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
596                 break;
597
598         case PIN_CONFIG_BIAS_PULL_UP:
599                 value &= ~PADCFG1_TERM_MASK;
600
601                 value |= PADCFG1_TERM_UP;
602
603                 switch (arg) {
604                 case 20000:
605                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
606                         break;
607                 case 5000:
608                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
609                         break;
610                 case 2000:
611                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
612                         break;
613                 case 1000:
614                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
615                         break;
616                 default:
617                         ret = -EINVAL;
618                 }
619
620                 break;
621
622         case PIN_CONFIG_BIAS_PULL_DOWN:
623                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
624
625                 switch (arg) {
626                 case 20000:
627                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
628                         break;
629                 case 5000:
630                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
631                         break;
632                 case 1000:
633                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
634                                 ret = -EINVAL;
635                                 break;
636                         }
637                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
638                         break;
639                 default:
640                         ret = -EINVAL;
641                 }
642
643                 break;
644         }
645
646         if (!ret)
647                 writel(value, padcfg1);
648
649         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
650
651         return ret;
652 }
653
654 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
655                                      unsigned debounce)
656 {
657         void __iomem *padcfg0, *padcfg2;
658         unsigned long flags;
659         u32 value0, value2;
660         int ret = 0;
661
662         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
663         if (!padcfg2)
664                 return -ENOTSUPP;
665
666         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
667
668         raw_spin_lock_irqsave(&pctrl->lock, flags);
669
670         value0 = readl(padcfg0);
671         value2 = readl(padcfg2);
672
673         /* Disable glitch filter and debouncer */
674         value0 &= ~PADCFG0_PREGFRXSEL;
675         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
676
677         if (debounce) {
678                 unsigned long v;
679
680                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
681                 if (v < 3 || v > 15) {
682                         ret = -EINVAL;
683                         goto exit_unlock;
684                 } else {
685                         /* Enable glitch filter and debouncer */
686                         value0 |= PADCFG0_PREGFRXSEL;
687                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
688                         value2 |= PADCFG2_DEBEN;
689                 }
690         }
691
692         writel(value0, padcfg0);
693         writel(value2, padcfg2);
694
695 exit_unlock:
696         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
697
698         return ret;
699 }
700
701 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
702                           unsigned long *configs, unsigned nconfigs)
703 {
704         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
705         int i, ret;
706
707         if (!intel_pad_usable(pctrl, pin))
708                 return -ENOTSUPP;
709
710         for (i = 0; i < nconfigs; i++) {
711                 switch (pinconf_to_config_param(configs[i])) {
712                 case PIN_CONFIG_BIAS_DISABLE:
713                 case PIN_CONFIG_BIAS_PULL_UP:
714                 case PIN_CONFIG_BIAS_PULL_DOWN:
715                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
716                         if (ret)
717                                 return ret;
718                         break;
719
720                 case PIN_CONFIG_INPUT_DEBOUNCE:
721                         ret = intel_config_set_debounce(pctrl, pin,
722                                 pinconf_to_config_argument(configs[i]));
723                         if (ret)
724                                 return ret;
725                         break;
726
727                 default:
728                         return -ENOTSUPP;
729                 }
730         }
731
732         return 0;
733 }
734
735 static const struct pinconf_ops intel_pinconf_ops = {
736         .is_generic = true,
737         .pin_config_get = intel_config_get,
738         .pin_config_set = intel_config_set,
739 };
740
741 static const struct pinctrl_desc intel_pinctrl_desc = {
742         .pctlops = &intel_pinctrl_ops,
743         .pmxops = &intel_pinmux_ops,
744         .confops = &intel_pinconf_ops,
745         .owner = THIS_MODULE,
746 };
747
748 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
749 {
750         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
751         void __iomem *reg;
752         u32 padcfg0;
753
754         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
755         if (!reg)
756                 return -EINVAL;
757
758         padcfg0 = readl(reg);
759         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
760                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
761
762         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
763 }
764
765 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
766 {
767         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
768         unsigned long flags;
769         void __iomem *reg;
770         u32 padcfg0;
771
772         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
773         if (!reg)
774                 return;
775
776         raw_spin_lock_irqsave(&pctrl->lock, flags);
777         padcfg0 = readl(reg);
778         if (value)
779                 padcfg0 |= PADCFG0_GPIOTXSTATE;
780         else
781                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
782         writel(padcfg0, reg);
783         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
784 }
785
786 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
787 {
788         return pinctrl_gpio_direction_input(chip->base + offset);
789 }
790
791 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
792                                        int value)
793 {
794         intel_gpio_set(chip, offset, value);
795         return pinctrl_gpio_direction_output(chip->base + offset);
796 }
797
798 static const struct gpio_chip intel_gpio_chip = {
799         .owner = THIS_MODULE,
800         .request = gpiochip_generic_request,
801         .free = gpiochip_generic_free,
802         .direction_input = intel_gpio_direction_input,
803         .direction_output = intel_gpio_direction_output,
804         .get = intel_gpio_get,
805         .set = intel_gpio_set,
806         .set_config = gpiochip_generic_config,
807 };
808
809 static void intel_gpio_irq_ack(struct irq_data *d)
810 {
811         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
812         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
813         const struct intel_community *community;
814         unsigned pin = irqd_to_hwirq(d);
815
816         community = intel_get_community(pctrl, pin);
817         if (community) {
818                 const struct intel_padgroup *padgrp;
819                 unsigned gpp, gpp_offset, is_offset;
820
821                 padgrp = intel_community_get_padgroup(community, pin);
822                 if (!padgrp)
823                         return;
824
825                 gpp = padgrp->reg_num;
826                 gpp_offset = padgroup_offset(padgrp, pin);
827                 is_offset = community->is_offset + gpp * 4;
828
829                 raw_spin_lock(&pctrl->lock);
830                 writel(BIT(gpp_offset), community->regs + is_offset);
831                 raw_spin_unlock(&pctrl->lock);
832         }
833 }
834
835 static void intel_gpio_irq_enable(struct irq_data *d)
836 {
837         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
838         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
839         const struct intel_community *community;
840         unsigned pin = irqd_to_hwirq(d);
841
842         community = intel_get_community(pctrl, pin);
843         if (community) {
844                 const struct intel_padgroup *padgrp;
845                 unsigned gpp, gpp_offset, is_offset;
846                 unsigned long flags;
847                 u32 value;
848
849                 padgrp = intel_community_get_padgroup(community, pin);
850                 if (!padgrp)
851                         return;
852
853                 gpp = padgrp->reg_num;
854                 gpp_offset = padgroup_offset(padgrp, pin);
855                 is_offset = community->is_offset + gpp * 4;
856
857                 raw_spin_lock_irqsave(&pctrl->lock, flags);
858                 /* Clear interrupt status first to avoid unexpected interrupt */
859                 writel(BIT(gpp_offset), community->regs + is_offset);
860
861                 value = readl(community->regs + community->ie_offset + gpp * 4);
862                 value |= BIT(gpp_offset);
863                 writel(value, community->regs + community->ie_offset + gpp * 4);
864                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
865         }
866 }
867
868 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
869 {
870         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
871         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
872         const struct intel_community *community;
873         unsigned pin = irqd_to_hwirq(d);
874
875         community = intel_get_community(pctrl, pin);
876         if (community) {
877                 const struct intel_padgroup *padgrp;
878                 unsigned gpp, gpp_offset;
879                 unsigned long flags;
880                 void __iomem *reg;
881                 u32 value;
882
883                 padgrp = intel_community_get_padgroup(community, pin);
884                 if (!padgrp)
885                         return;
886
887                 gpp = padgrp->reg_num;
888                 gpp_offset = padgroup_offset(padgrp, pin);
889
890                 reg = community->regs + community->ie_offset + gpp * 4;
891
892                 raw_spin_lock_irqsave(&pctrl->lock, flags);
893                 value = readl(reg);
894                 if (mask)
895                         value &= ~BIT(gpp_offset);
896                 else
897                         value |= BIT(gpp_offset);
898                 writel(value, reg);
899                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
900         }
901 }
902
903 static void intel_gpio_irq_mask(struct irq_data *d)
904 {
905         intel_gpio_irq_mask_unmask(d, true);
906 }
907
908 static void intel_gpio_irq_unmask(struct irq_data *d)
909 {
910         intel_gpio_irq_mask_unmask(d, false);
911 }
912
913 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
914 {
915         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
916         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
917         unsigned pin = irqd_to_hwirq(d);
918         unsigned long flags;
919         void __iomem *reg;
920         u32 value;
921
922         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
923         if (!reg)
924                 return -EINVAL;
925
926         /*
927          * If the pin is in ACPI mode it is still usable as a GPIO but it
928          * cannot be used as IRQ because GPI_IS status bit will not be
929          * updated by the host controller hardware.
930          */
931         if (intel_pad_acpi_mode(pctrl, pin)) {
932                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
933                 return -EPERM;
934         }
935
936         raw_spin_lock_irqsave(&pctrl->lock, flags);
937
938         value = readl(reg);
939
940         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
941
942         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
943                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
944         } else if (type & IRQ_TYPE_EDGE_FALLING) {
945                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
946                 value |= PADCFG0_RXINV;
947         } else if (type & IRQ_TYPE_EDGE_RISING) {
948                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
949         } else if (type & IRQ_TYPE_LEVEL_MASK) {
950                 if (type & IRQ_TYPE_LEVEL_LOW)
951                         value |= PADCFG0_RXINV;
952         } else {
953                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
954         }
955
956         writel(value, reg);
957
958         if (type & IRQ_TYPE_EDGE_BOTH)
959                 irq_set_handler_locked(d, handle_edge_irq);
960         else if (type & IRQ_TYPE_LEVEL_MASK)
961                 irq_set_handler_locked(d, handle_level_irq);
962
963         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
964
965         return 0;
966 }
967
968 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
969 {
970         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
971         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
972         unsigned pin = irqd_to_hwirq(d);
973
974         if (on)
975                 enable_irq_wake(pctrl->irq);
976         else
977                 disable_irq_wake(pctrl->irq);
978
979         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
980         return 0;
981 }
982
983 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
984         const struct intel_community *community)
985 {
986         struct gpio_chip *gc = &pctrl->chip;
987         irqreturn_t ret = IRQ_NONE;
988         int gpp;
989
990         for (gpp = 0; gpp < community->ngpps; gpp++) {
991                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
992                 unsigned long pending, enabled, gpp_offset;
993
994                 pending = readl(community->regs + community->is_offset +
995                                 padgrp->reg_num * 4);
996                 enabled = readl(community->regs + community->ie_offset +
997                                 padgrp->reg_num * 4);
998
999                 /* Only interrupts that are enabled */
1000                 pending &= enabled;
1001
1002                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1003                         unsigned padno, irq;
1004
1005                         padno = padgrp->base - community->pin_base + gpp_offset;
1006                         if (padno >= community->npins)
1007                                 break;
1008
1009                         irq = irq_find_mapping(gc->irq.domain,
1010                                                community->pin_base + padno);
1011                         generic_handle_irq(irq);
1012
1013                         ret |= IRQ_HANDLED;
1014                 }
1015         }
1016
1017         return ret;
1018 }
1019
1020 static irqreturn_t intel_gpio_irq(int irq, void *data)
1021 {
1022         const struct intel_community *community;
1023         struct intel_pinctrl *pctrl = data;
1024         irqreturn_t ret = IRQ_NONE;
1025         int i;
1026
1027         /* Need to check all communities for pending interrupts */
1028         for (i = 0; i < pctrl->ncommunities; i++) {
1029                 community = &pctrl->communities[i];
1030                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1031         }
1032
1033         return ret;
1034 }
1035
1036 static struct irq_chip intel_gpio_irqchip = {
1037         .name = "intel-gpio",
1038         .irq_enable = intel_gpio_irq_enable,
1039         .irq_ack = intel_gpio_irq_ack,
1040         .irq_mask = intel_gpio_irq_mask,
1041         .irq_unmask = intel_gpio_irq_unmask,
1042         .irq_set_type = intel_gpio_irq_type,
1043         .irq_set_wake = intel_gpio_irq_wake,
1044         .flags = IRQCHIP_MASK_ON_SUSPEND,
1045 };
1046
1047 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1048 {
1049         int ret;
1050
1051         pctrl->chip = intel_gpio_chip;
1052
1053         pctrl->chip.ngpio = pctrl->soc->npins;
1054         pctrl->chip.label = dev_name(pctrl->dev);
1055         pctrl->chip.parent = pctrl->dev;
1056         pctrl->chip.base = -1;
1057         pctrl->irq = irq;
1058
1059         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1060         if (ret) {
1061                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1062                 return ret;
1063         }
1064
1065         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1066                                      0, 0, pctrl->soc->npins);
1067         if (ret) {
1068                 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1069                 return ret;
1070         }
1071
1072         /*
1073          * We need to request the interrupt here (instead of providing chip
1074          * to the irq directly) because on some platforms several GPIO
1075          * controllers share the same interrupt line.
1076          */
1077         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1078                                IRQF_SHARED | IRQF_NO_THREAD,
1079                                dev_name(pctrl->dev), pctrl);
1080         if (ret) {
1081                 dev_err(pctrl->dev, "failed to request interrupt\n");
1082                 return ret;
1083         }
1084
1085         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1086                                    handle_bad_irq, IRQ_TYPE_NONE);
1087         if (ret) {
1088                 dev_err(pctrl->dev, "failed to add irqchip\n");
1089                 return ret;
1090         }
1091
1092         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1093                                      NULL);
1094         return 0;
1095 }
1096
1097 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1098                                        struct intel_community *community)
1099 {
1100         struct intel_padgroup *gpps;
1101         unsigned npins = community->npins;
1102         unsigned padown_num = 0;
1103         size_t ngpps, i;
1104
1105         if (community->gpps)
1106                 ngpps = community->ngpps;
1107         else
1108                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1109
1110         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1111         if (!gpps)
1112                 return -ENOMEM;
1113
1114         for (i = 0; i < ngpps; i++) {
1115                 if (community->gpps) {
1116                         gpps[i] = community->gpps[i];
1117                 } else {
1118                         unsigned gpp_size = community->gpp_size;
1119
1120                         gpps[i].reg_num = i;
1121                         gpps[i].base = community->pin_base + i * gpp_size;
1122                         gpps[i].size = min(gpp_size, npins);
1123                         npins -= gpps[i].size;
1124                 }
1125
1126                 if (gpps[i].size > 32)
1127                         return -EINVAL;
1128
1129                 gpps[i].padown_num = padown_num;
1130
1131                 /*
1132                  * In older hardware the number of padown registers per
1133                  * group is fixed regardless of the group size.
1134                  */
1135                 if (community->gpp_num_padown_regs)
1136                         padown_num += community->gpp_num_padown_regs;
1137                 else
1138                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1139         }
1140
1141         community->ngpps = ngpps;
1142         community->gpps = gpps;
1143
1144         return 0;
1145 }
1146
1147 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1148 {
1149 #ifdef CONFIG_PM_SLEEP
1150         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1151         struct intel_community_context *communities;
1152         struct intel_pad_context *pads;
1153         int i;
1154
1155         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1156         if (!pads)
1157                 return -ENOMEM;
1158
1159         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1160                                    sizeof(*communities), GFP_KERNEL);
1161         if (!communities)
1162                 return -ENOMEM;
1163
1164
1165         for (i = 0; i < pctrl->ncommunities; i++) {
1166                 struct intel_community *community = &pctrl->communities[i];
1167                 u32 *intmask;
1168
1169                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1170                                        sizeof(*intmask), GFP_KERNEL);
1171                 if (!intmask)
1172                         return -ENOMEM;
1173
1174                 communities[i].intmask = intmask;
1175         }
1176
1177         pctrl->context.pads = pads;
1178         pctrl->context.communities = communities;
1179 #endif
1180
1181         return 0;
1182 }
1183
1184 int intel_pinctrl_probe(struct platform_device *pdev,
1185                         const struct intel_pinctrl_soc_data *soc_data)
1186 {
1187         struct intel_pinctrl *pctrl;
1188         int i, ret, irq;
1189
1190         if (!soc_data)
1191                 return -EINVAL;
1192
1193         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1194         if (!pctrl)
1195                 return -ENOMEM;
1196
1197         pctrl->dev = &pdev->dev;
1198         pctrl->soc = soc_data;
1199         raw_spin_lock_init(&pctrl->lock);
1200
1201         /*
1202          * Make a copy of the communities which we can use to hold pointers
1203          * to the registers.
1204          */
1205         pctrl->ncommunities = pctrl->soc->ncommunities;
1206         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1207                                   sizeof(*pctrl->communities), GFP_KERNEL);
1208         if (!pctrl->communities)
1209                 return -ENOMEM;
1210
1211         for (i = 0; i < pctrl->ncommunities; i++) {
1212                 struct intel_community *community = &pctrl->communities[i];
1213                 struct resource *res;
1214                 void __iomem *regs;
1215                 u32 padbar;
1216
1217                 *community = pctrl->soc->communities[i];
1218
1219                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1220                                             community->barno);
1221                 regs = devm_ioremap_resource(&pdev->dev, res);
1222                 if (IS_ERR(regs))
1223                         return PTR_ERR(regs);
1224
1225                 /*
1226                  * Determine community features based on the revision if
1227                  * not specified already.
1228                  */
1229                 if (!community->features) {
1230                         u32 rev;
1231
1232                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1233                         if (rev >= 0x94) {
1234                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1235                                 community->features |= PINCTRL_FEATURE_1K_PD;
1236                         }
1237                 }
1238
1239                 /* Read offset of the pad configuration registers */
1240                 padbar = readl(regs + PADBAR);
1241
1242                 community->regs = regs;
1243                 community->pad_regs = regs + padbar;
1244
1245                 if (!community->is_offset)
1246                         community->is_offset = GPI_IS;
1247
1248                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1249                 if (ret)
1250                         return ret;
1251         }
1252
1253         irq = platform_get_irq(pdev, 0);
1254         if (irq < 0) {
1255                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1256                 return irq;
1257         }
1258
1259         ret = intel_pinctrl_pm_init(pctrl);
1260         if (ret)
1261                 return ret;
1262
1263         pctrl->pctldesc = intel_pinctrl_desc;
1264         pctrl->pctldesc.name = dev_name(&pdev->dev);
1265         pctrl->pctldesc.pins = pctrl->soc->pins;
1266         pctrl->pctldesc.npins = pctrl->soc->npins;
1267
1268         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1269                                                pctrl);
1270         if (IS_ERR(pctrl->pctldev)) {
1271                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1272                 return PTR_ERR(pctrl->pctldev);
1273         }
1274
1275         ret = intel_gpio_probe(pctrl, irq);
1276         if (ret)
1277                 return ret;
1278
1279         platform_set_drvdata(pdev, pctrl);
1280
1281         return 0;
1282 }
1283 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1284
1285 #ifdef CONFIG_PM_SLEEP
1286 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1287 {
1288         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1289
1290         if (!pd || !intel_pad_usable(pctrl, pin))
1291                 return false;
1292
1293         /*
1294          * Only restore the pin if it is actually in use by the kernel (or
1295          * by userspace). It is possible that some pins are used by the
1296          * BIOS during resume and those are not always locked down so leave
1297          * them alone.
1298          */
1299         if (pd->mux_owner || pd->gpio_owner ||
1300             gpiochip_line_is_irq(&pctrl->chip, pin))
1301                 return true;
1302
1303         return false;
1304 }
1305
1306 int intel_pinctrl_suspend(struct device *dev)
1307 {
1308         struct platform_device *pdev = to_platform_device(dev);
1309         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1310         struct intel_community_context *communities;
1311         struct intel_pad_context *pads;
1312         int i;
1313
1314         pads = pctrl->context.pads;
1315         for (i = 0; i < pctrl->soc->npins; i++) {
1316                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1317                 void __iomem *padcfg;
1318                 u32 val;
1319
1320                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1321                         continue;
1322
1323                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1324                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1325                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1326                 pads[i].padcfg1 = val;
1327
1328                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1329                 if (padcfg)
1330                         pads[i].padcfg2 = readl(padcfg);
1331         }
1332
1333         communities = pctrl->context.communities;
1334         for (i = 0; i < pctrl->ncommunities; i++) {
1335                 struct intel_community *community = &pctrl->communities[i];
1336                 void __iomem *base;
1337                 unsigned gpp;
1338
1339                 base = community->regs + community->ie_offset;
1340                 for (gpp = 0; gpp < community->ngpps; gpp++)
1341                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1342         }
1343
1344         return 0;
1345 }
1346 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1347
1348 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1349 {
1350         size_t i;
1351
1352         for (i = 0; i < pctrl->ncommunities; i++) {
1353                 const struct intel_community *community;
1354                 void __iomem *base;
1355                 unsigned gpp;
1356
1357                 community = &pctrl->communities[i];
1358                 base = community->regs;
1359
1360                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1361                         /* Mask and clear all interrupts */
1362                         writel(0, base + community->ie_offset + gpp * 4);
1363                         writel(0xffff, base + community->is_offset + gpp * 4);
1364                 }
1365         }
1366 }
1367
1368 int intel_pinctrl_resume(struct device *dev)
1369 {
1370         struct platform_device *pdev = to_platform_device(dev);
1371         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1372         const struct intel_community_context *communities;
1373         const struct intel_pad_context *pads;
1374         int i;
1375
1376         /* Mask all interrupts */
1377         intel_gpio_irq_init(pctrl);
1378
1379         pads = pctrl->context.pads;
1380         for (i = 0; i < pctrl->soc->npins; i++) {
1381                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1382                 void __iomem *padcfg;
1383                 u32 val;
1384
1385                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1386                         continue;
1387
1388                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1389                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1390                 if (val != pads[i].padcfg0) {
1391                         writel(pads[i].padcfg0, padcfg);
1392                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1393                                 desc->number, readl(padcfg));
1394                 }
1395
1396                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1397                 val = readl(padcfg);
1398                 if (val != pads[i].padcfg1) {
1399                         writel(pads[i].padcfg1, padcfg);
1400                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1401                                 desc->number, readl(padcfg));
1402                 }
1403
1404                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1405                 if (padcfg) {
1406                         val = readl(padcfg);
1407                         if (val != pads[i].padcfg2) {
1408                                 writel(pads[i].padcfg2, padcfg);
1409                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1410                                         desc->number, readl(padcfg));
1411                         }
1412                 }
1413         }
1414
1415         communities = pctrl->context.communities;
1416         for (i = 0; i < pctrl->ncommunities; i++) {
1417                 struct intel_community *community = &pctrl->communities[i];
1418                 void __iomem *base;
1419                 unsigned gpp;
1420
1421                 base = community->regs + community->ie_offset;
1422                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1423                         writel(communities[i].intmask[gpp], base + gpp * 4);
1424                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1425                                 readl(base + gpp * 4));
1426                 }
1427         }
1428
1429         return 0;
1430 }
1431 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1432 #endif
1433
1434 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1435 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1436 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1437 MODULE_LICENSE("GPL v2");