drivers/pinctrl/intel/pinctrl-denverton.c

   1 /*
   2  * Intel Denverton SoC pinctrl/GPIO driver
   3  *
   4  * Copyright (C) 2017, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/acpi.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm.h>
  16 #include <linux/pinctrl/pinctrl.h>
  17
  18 #include "pinctrl-intel.h"
  19
  20 #define DNV_PAD_OWN     0x020
  21 #define DNV_HOSTSW_OWN  0x0C0
  22 #define DNV_PADCFGLOCK  0x090
  23 #define DNV_GPI_IE      0x120
  24
  25 #define DNV_GPP(n, s, e)                                \
  26         {                                               \
  27                 .reg_num = (n),                         \
  28                 .base = (s),                            \
  29                 .size = ((e) - (s) + 1),                \
  30         }
  31
  32 #define DNV_COMMUNITY(b, s, e, g)                       \
  33         {                                               \
  34                 .barno = (b),                           \
  35                 .padown_offset = DNV_PAD_OWN,           \
  36                 .padcfglock_offset = DNV_PADCFGLOCK,    \
  37                 .hostown_offset = DNV_HOSTSW_OWN,       \
  38                 .ie_offset = DNV_GPI_IE,                \
  39                 .pin_base = (s),                        \
  40                 .npins = ((e) - (s) + 1),               \
  41                 .gpps = (g),                            \
  42                 .ngpps = ARRAY_SIZE(g),                 \
  43         }
  44
  45 static const struct pinctrl_pin_desc dnv_pins[] = {
  46         /* North ALL */
  47         PINCTRL_PIN(0, "GBE0_SDP0"),
  48         PINCTRL_PIN(1, "GBE1_SDP0"),
  49         PINCTRL_PIN(2, "GBE0_SDP1"),
  50         PINCTRL_PIN(3, "GBE1_SDP1"),
  51         PINCTRL_PIN(4, "GBE0_SDP2"),
  52         PINCTRL_PIN(5, "GBE1_SDP2"),
  53         PINCTRL_PIN(6, "GBE0_SDP3"),
  54         PINCTRL_PIN(7, "GBE1_SDP3"),
  55         PINCTRL_PIN(8, "GBE2_LED0"),
  56         PINCTRL_PIN(9, "GBE2_LED1"),
  57         PINCTRL_PIN(10, "GBE0_I2C_CLK"),
  58         PINCTRL_PIN(11, "GBE0_I2C_DATA"),
  59         PINCTRL_PIN(12, "GBE1_I2C_CLK"),
  60         PINCTRL_PIN(13, "GBE1_I2C_DATA"),
  61         PINCTRL_PIN(14, "NCSI_RXD0"),
  62         PINCTRL_PIN(15, "NCSI_CLK_IN"),
  63         PINCTRL_PIN(16, "NCSI_RXD1"),
  64         PINCTRL_PIN(17, "NCSI_CRS_DV"),
  65         PINCTRL_PIN(18, "NCSI_ARB_IN"),
  66         PINCTRL_PIN(19, "NCSI_TX_EN"),
  67         PINCTRL_PIN(20, "NCSI_TXD0"),
  68         PINCTRL_PIN(21, "NCSI_TXD1"),
  69         PINCTRL_PIN(22, "NCSI_ARB_OUT"),
  70         PINCTRL_PIN(23, "GBE0_LED0"),
  71         PINCTRL_PIN(24, "GBE0_LED1"),
  72         PINCTRL_PIN(25, "GBE1_LED0"),
  73         PINCTRL_PIN(26, "GBE1_LED1"),
  74         PINCTRL_PIN(27, "GPIO_0"),
  75         PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
  76         PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
  77         PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
  78         PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
  79         PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
  80         PINCTRL_PIN(33, "GPIO_1"),
  81         PINCTRL_PIN(34, "GPIO_2"),
  82         PINCTRL_PIN(35, "SVID_ALERT_N"),
  83         PINCTRL_PIN(36, "SVID_DATA"),
  84         PINCTRL_PIN(37, "SVID_CLK"),
  85         PINCTRL_PIN(38, "THERMTRIP_N"),
  86         PINCTRL_PIN(39, "PROCHOT_N"),
  87         PINCTRL_PIN(40, "MEMHOT_N"),
  88         /* South DFX */
  89         PINCTRL_PIN(41, "DFX_PORT_CLK0"),
  90         PINCTRL_PIN(42, "DFX_PORT_CLK1"),
  91         PINCTRL_PIN(43, "DFX_PORT0"),
  92         PINCTRL_PIN(44, "DFX_PORT1"),
  93         PINCTRL_PIN(45, "DFX_PORT2"),
  94         PINCTRL_PIN(46, "DFX_PORT3"),
  95         PINCTRL_PIN(47, "DFX_PORT4"),
  96         PINCTRL_PIN(48, "DFX_PORT5"),
  97         PINCTRL_PIN(49, "DFX_PORT6"),
  98         PINCTRL_PIN(50, "DFX_PORT7"),
  99         PINCTRL_PIN(51, "DFX_PORT8"),
 100         PINCTRL_PIN(52, "DFX_PORT9"),
 101         PINCTRL_PIN(53, "DFX_PORT10"),
 102         PINCTRL_PIN(54, "DFX_PORT11"),
 103         PINCTRL_PIN(55, "DFX_PORT12"),
 104         PINCTRL_PIN(56, "DFX_PORT13"),
 105         PINCTRL_PIN(57, "DFX_PORT14"),
 106         PINCTRL_PIN(58, "DFX_PORT15"),
 107         /* South GPP0 */
 108         PINCTRL_PIN(59, "GPIO_12"),
 109         PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"),
 110         PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
 111         PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
 112         PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
 113         PINCTRL_PIN(64, "UART0_RXD"),
 114         PINCTRL_PIN(65, "UART0_TXD"),
 115         PINCTRL_PIN(66, "SMB5_GBE_CLK"),
 116         PINCTRL_PIN(67, "SMB5_GBE_DATA"),
 117         PINCTRL_PIN(68, "ERROR2_N"),
 118         PINCTRL_PIN(69, "ERROR1_N"),
 119         PINCTRL_PIN(70, "ERROR0_N"),
 120         PINCTRL_PIN(71, "IERR_N"),
 121         PINCTRL_PIN(72, "MCERR_N"),
 122         PINCTRL_PIN(73, "SMB0_LEG_CLK"),
 123         PINCTRL_PIN(74, "SMB0_LEG_DATA"),
 124         PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
 125         PINCTRL_PIN(76, "SMB1_HOST_DATA"),
 126         PINCTRL_PIN(77, "SMB1_HOST_CLK"),
 127         PINCTRL_PIN(78, "SMB2_PECI_DATA"),
 128         PINCTRL_PIN(79, "SMB2_PECI_CLK"),
 129         PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
 130         PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
 131         PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
 132         PINCTRL_PIN(83, "USB_OC0_N"),
 133         PINCTRL_PIN(84, "FLEX_CLK_SE0"),
 134         PINCTRL_PIN(85, "FLEX_CLK_SE1"),
 135         PINCTRL_PIN(86, "GPIO_4"),
 136         PINCTRL_PIN(87, "GPIO_5"),
 137         PINCTRL_PIN(88, "GPIO_6"),
 138         PINCTRL_PIN(89, "GPIO_7"),
 139         PINCTRL_PIN(90, "SATA0_LED_N"),
 140         PINCTRL_PIN(91, "SATA1_LED_N"),
 141         PINCTRL_PIN(92, "SATA_PDETECT0"),
 142         PINCTRL_PIN(93, "SATA_PDETECT1"),
 143         PINCTRL_PIN(94, "SATA0_SDOUT"),
 144         PINCTRL_PIN(95, "SATA1_SDOUT"),
 145         PINCTRL_PIN(96, "UART1_RXD"),
 146         PINCTRL_PIN(97, "UART1_TXD"),
 147         PINCTRL_PIN(98, "GPIO_8"),
 148         PINCTRL_PIN(99, "GPIO_9"),
 149         PINCTRL_PIN(100, "TCK"),
 150         PINCTRL_PIN(101, "TRST_N"),
 151         PINCTRL_PIN(102, "TMS"),
 152         PINCTRL_PIN(103, "TDI"),
 153         PINCTRL_PIN(104, "TDO"),
 154         PINCTRL_PIN(105, "CX_PRDY_N"),
 155         PINCTRL_PIN(106, "CX_PREQ_N"),
 156         PINCTRL_PIN(107, "CTBTRIGINOUT"),
 157         PINCTRL_PIN(108, "CTBTRIGOUT"),
 158         PINCTRL_PIN(109, "DFX_SPARE2"),
 159         PINCTRL_PIN(110, "DFX_SPARE3"),
 160         PINCTRL_PIN(111, "DFX_SPARE4"),
 161         /* South GPP1 */
 162         PINCTRL_PIN(112, "SUSPWRDNACK"),
 163         PINCTRL_PIN(113, "PMU_SUSCLK"),
 164         PINCTRL_PIN(114, "ADR_TRIGGER"),
 165         PINCTRL_PIN(115, "PMU_SLP_S45_N"),
 166         PINCTRL_PIN(116, "PMU_SLP_S3_N"),
 167         PINCTRL_PIN(117, "PMU_WAKE_N"),
 168         PINCTRL_PIN(118, "PMU_PWRBTN_N"),
 169         PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
 170         PINCTRL_PIN(120, "PMU_PLTRST_N"),
 171         PINCTRL_PIN(121, "SUS_STAT_N"),
 172         PINCTRL_PIN(122, "SLP_S0IX_N"),
 173         PINCTRL_PIN(123, "SPI_CS0_N"),
 174         PINCTRL_PIN(124, "SPI_CS1_N"),
 175         PINCTRL_PIN(125, "SPI_MOSI_IO0"),
 176         PINCTRL_PIN(126, "SPI_MISO_IO1"),
 177         PINCTRL_PIN(127, "SPI_IO2"),
 178         PINCTRL_PIN(128, "SPI_IO3"),
 179         PINCTRL_PIN(129, "SPI_CLK"),
 180         PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
 181         PINCTRL_PIN(131, "ESPI_IO0"),
 182         PINCTRL_PIN(132, "ESPI_IO1"),
 183         PINCTRL_PIN(133, "ESPI_IO2"),
 184         PINCTRL_PIN(134, "ESPI_IO3"),
 185         PINCTRL_PIN(135, "ESPI_CS0_N"),
 186         PINCTRL_PIN(136, "ESPI_CLK"),
 187         PINCTRL_PIN(137, "ESPI_RST_N"),
 188         PINCTRL_PIN(138, "ESPI_ALRT0_N"),
 189         PINCTRL_PIN(139, "GPIO_10"),
 190         PINCTRL_PIN(140, "GPIO_11"),
 191         PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
 192         PINCTRL_PIN(142, "EMMC_CMD"),
 193         PINCTRL_PIN(143, "EMMC_STROBE"),
 194         PINCTRL_PIN(144, "EMMC_CLK"),
 195         PINCTRL_PIN(145, "EMMC_D0"),
 196         PINCTRL_PIN(146, "EMMC_D1"),
 197         PINCTRL_PIN(147, "EMMC_D2"),
 198         PINCTRL_PIN(148, "EMMC_D3"),
 199         PINCTRL_PIN(149, "EMMC_D4"),
 200         PINCTRL_PIN(150, "EMMC_D5"),
 201         PINCTRL_PIN(151, "EMMC_D6"),
 202         PINCTRL_PIN(152, "EMMC_D7"),
 203         PINCTRL_PIN(153, "GPIO_3"),
 204 };
 205
 206 static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
 207 static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
 208 static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
 209 static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
 210 static const unsigned int dnv_uart2_modes[] = { 1, 1, 2, 2 };
 211 static const unsigned int dnv_emmc_pins[] = {
 212         142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
 213 };
 214
 215 static const struct intel_pingroup dnv_groups[] = {
 216         PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
 217         PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
 218         PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
 219         PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
 220 };
 221
 222 static const char * const dnv_uart0_groups[] = { "uart0_grp" };
 223 static const char * const dnv_uart1_groups[] = { "uart1_grp" };
 224 static const char * const dnv_uart2_groups[] = { "uart2_grp" };
 225 static const char * const dnv_emmc_groups[] = { "emmc_grp" };
 226
 227 static const struct intel_function dnv_functions[] = {
 228         FUNCTION("uart0", dnv_uart0_groups),
 229         FUNCTION("uart1", dnv_uart1_groups),
 230         FUNCTION("uart2", dnv_uart2_groups),
 231         FUNCTION("emmc", dnv_emmc_groups),
 232 };
 233
 234 static const struct intel_padgroup dnv_north_gpps[] = {
 235         DNV_GPP(0, 0, 31),      /* North ALL_0 */
 236         DNV_GPP(1, 32, 40),     /* North ALL_1 */
 237 };
 238
 239 static const struct intel_padgroup dnv_south_gpps[] = {
 240         DNV_GPP(0, 41, 58),     /* South DFX */
 241         DNV_GPP(1, 59, 90),     /* South GPP0_0 */
 242         DNV_GPP(2, 91, 111),    /* South GPP0_1 */
 243         DNV_GPP(3, 112, 143),   /* South GPP1_0 */
 244         DNV_GPP(4, 144, 153),   /* South GPP1_1 */
 245 };
 246
 247 static const struct intel_community dnv_communities[] = {
 248         DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
 249         DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
 250 };
 251
 252 static const struct intel_pinctrl_soc_data dnv_soc_data = {
 253         .pins = dnv_pins,
 254         .npins = ARRAY_SIZE(dnv_pins),
 255         .groups = dnv_groups,
 256         .ngroups = ARRAY_SIZE(dnv_groups),
 257         .functions = dnv_functions,
 258         .nfunctions = ARRAY_SIZE(dnv_functions),
 259         .communities = dnv_communities,
 260         .ncommunities = ARRAY_SIZE(dnv_communities),
 261 };
 262
 263 static int dnv_pinctrl_probe(struct platform_device *pdev)
 264 {
 265         return intel_pinctrl_probe(pdev, &dnv_soc_data);
 266 }
 267
 268 static const struct dev_pm_ops dnv_pinctrl_pm_ops = {
 269         SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
 270                                      intel_pinctrl_resume)
 271 };
 272
 273 static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
 274         { "INTC3000" },
 275         { }
 276 };
 277 MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
 278
 279 static struct platform_driver dnv_pinctrl_driver = {
 280         .probe = dnv_pinctrl_probe,
 281         .driver = {
 282                 .name = "denverton-pinctrl",
 283                 .acpi_match_table = dnv_pinctrl_acpi_match,
 284                 .pm = &dnv_pinctrl_pm_ops,
 285         },
 286 };
 287
 288 static int __init dnv_pinctrl_init(void)
 289 {
 290         return platform_driver_register(&dnv_pinctrl_driver);
 291 }
 292 subsys_initcall(dnv_pinctrl_init);
 293
 294 static void __exit dnv_pinctrl_exit(void)
 295 {
 296         platform_driver_unregister(&dnv_pinctrl_driver);
 297 }
 298 module_exit(dnv_pinctrl_exit);
 299
 300 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 301 MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
 302 MODULE_LICENSE("GPL v2");