Merge tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[sfrench/cifs-2.6.git] / drivers / pinctrl / intel / pinctrl-cannonlake.c
1 /*
2  * Intel Cannon Lake PCH pinctrl/GPIO driver
3  *
4  * Copyright (C) 2017, Intel Corporation
5  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/acpi.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm.h>
17 #include <linux/pinctrl/pinctrl.h>
18
19 #include "pinctrl-intel.h"
20
21 #define CNL_PAD_OWN     0x020
22 #define CNL_PADCFGLOCK  0x080
23 #define CNL_HOSTSW_OWN  0x0b0
24 #define CNL_GPI_IE      0x120
25
26 #define CNL_GPP(r, s, e)                                \
27         {                                               \
28                 .reg_num = (r),                         \
29                 .base = (s),                            \
30                 .size = ((e) - (s) + 1),                \
31         }
32
33 #define CNL_COMMUNITY(b, s, e, g)                       \
34         {                                               \
35                 .barno = (b),                           \
36                 .padown_offset = CNL_PAD_OWN,           \
37                 .padcfglock_offset = CNL_PADCFGLOCK,    \
38                 .hostown_offset = CNL_HOSTSW_OWN,       \
39                 .ie_offset = CNL_GPI_IE,                \
40                 .pin_base = (s),                        \
41                 .npins = ((e) - (s) + 1),               \
42                 .gpps = (g),                            \
43                 .ngpps = ARRAY_SIZE(g),                 \
44         }
45
46 /* Cannon Lake-H */
47 static const struct pinctrl_pin_desc cnlh_pins[] = {
48         /* GPP_A */
49         PINCTRL_PIN(0, "RCINB"),
50         PINCTRL_PIN(1, "LAD_0"),
51         PINCTRL_PIN(2, "LAD_1"),
52         PINCTRL_PIN(3, "LAD_2"),
53         PINCTRL_PIN(4, "LAD_3"),
54         PINCTRL_PIN(5, "LFRAMEB"),
55         PINCTRL_PIN(6, "SERIRQ"),
56         PINCTRL_PIN(7, "PIRQAB"),
57         PINCTRL_PIN(8, "CLKRUNB"),
58         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
59         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
60         PINCTRL_PIN(11, "PMEB"),
61         PINCTRL_PIN(12, "BM_BUSYB"),
62         PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
63         PINCTRL_PIN(14, "SUS_STATB"),
64         PINCTRL_PIN(15, "SUSACKB"),
65         PINCTRL_PIN(16, "CLKOUT_48"),
66         PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
67         PINCTRL_PIN(18, "ISH_GP_0"),
68         PINCTRL_PIN(19, "ISH_GP_1"),
69         PINCTRL_PIN(20, "ISH_GP_2"),
70         PINCTRL_PIN(21, "ISH_GP_3"),
71         PINCTRL_PIN(22, "ISH_GP_4"),
72         PINCTRL_PIN(23, "ISH_GP_5"),
73         PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
74         /* GPP_B */
75         PINCTRL_PIN(25, "GSPI0_CS1B"),
76         PINCTRL_PIN(26, "GSPI1_CS1B"),
77         PINCTRL_PIN(27, "VRALERTB"),
78         PINCTRL_PIN(28, "CPU_GP_2"),
79         PINCTRL_PIN(29, "CPU_GP_3"),
80         PINCTRL_PIN(30, "SRCCLKREQB_0"),
81         PINCTRL_PIN(31, "SRCCLKREQB_1"),
82         PINCTRL_PIN(32, "SRCCLKREQB_2"),
83         PINCTRL_PIN(33, "SRCCLKREQB_3"),
84         PINCTRL_PIN(34, "SRCCLKREQB_4"),
85         PINCTRL_PIN(35, "SRCCLKREQB_5"),
86         PINCTRL_PIN(36, "SSP_MCLK"),
87         PINCTRL_PIN(37, "SLP_S0B"),
88         PINCTRL_PIN(38, "PLTRSTB"),
89         PINCTRL_PIN(39, "SPKR"),
90         PINCTRL_PIN(40, "GSPI0_CS0B"),
91         PINCTRL_PIN(41, "GSPI0_CLK"),
92         PINCTRL_PIN(42, "GSPI0_MISO"),
93         PINCTRL_PIN(43, "GSPI0_MOSI"),
94         PINCTRL_PIN(44, "GSPI1_CS0B"),
95         PINCTRL_PIN(45, "GSPI1_CLK"),
96         PINCTRL_PIN(46, "GSPI1_MISO"),
97         PINCTRL_PIN(47, "GSPI1_MOSI"),
98         PINCTRL_PIN(48, "SML1ALERTB"),
99         PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
100         PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
101         /* GPP_C */
102         PINCTRL_PIN(51, "SMBCLK"),
103         PINCTRL_PIN(52, "SMBDATA"),
104         PINCTRL_PIN(53, "SMBALERTB"),
105         PINCTRL_PIN(54, "SML0CLK"),
106         PINCTRL_PIN(55, "SML0DATA"),
107         PINCTRL_PIN(56, "SML0ALERTB"),
108         PINCTRL_PIN(57, "SML1CLK"),
109         PINCTRL_PIN(58, "SML1DATA"),
110         PINCTRL_PIN(59, "UART0_RXD"),
111         PINCTRL_PIN(60, "UART0_TXD"),
112         PINCTRL_PIN(61, "UART0_RTSB"),
113         PINCTRL_PIN(62, "UART0_CTSB"),
114         PINCTRL_PIN(63, "UART1_RXD"),
115         PINCTRL_PIN(64, "UART1_TXD"),
116         PINCTRL_PIN(65, "UART1_RTSB"),
117         PINCTRL_PIN(66, "UART1_CTSB"),
118         PINCTRL_PIN(67, "I2C0_SDA"),
119         PINCTRL_PIN(68, "I2C0_SCL"),
120         PINCTRL_PIN(69, "I2C1_SDA"),
121         PINCTRL_PIN(70, "I2C1_SCL"),
122         PINCTRL_PIN(71, "UART2_RXD"),
123         PINCTRL_PIN(72, "UART2_TXD"),
124         PINCTRL_PIN(73, "UART2_RTSB"),
125         PINCTRL_PIN(74, "UART2_CTSB"),
126         /* GPP_D */
127         PINCTRL_PIN(75, "SPI1_CSB"),
128         PINCTRL_PIN(76, "SPI1_CLK"),
129         PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
130         PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
131         PINCTRL_PIN(79, "ISH_I2C2_SDA"),
132         PINCTRL_PIN(80, "SSP2_SFRM"),
133         PINCTRL_PIN(81, "SSP2_TXD"),
134         PINCTRL_PIN(82, "SSP2_RXD"),
135         PINCTRL_PIN(83, "SSP2_SCLK"),
136         PINCTRL_PIN(84, "ISH_SPI_CSB"),
137         PINCTRL_PIN(85, "ISH_SPI_CLK"),
138         PINCTRL_PIN(86, "ISH_SPI_MISO"),
139         PINCTRL_PIN(87, "ISH_SPI_MOSI"),
140         PINCTRL_PIN(88, "ISH_UART0_RXD"),
141         PINCTRL_PIN(89, "ISH_UART0_TXD"),
142         PINCTRL_PIN(90, "ISH_UART0_RTSB"),
143         PINCTRL_PIN(91, "ISH_UART0_CTSB"),
144         PINCTRL_PIN(92, "DMIC_CLK_1"),
145         PINCTRL_PIN(93, "DMIC_DATA_1"),
146         PINCTRL_PIN(94, "DMIC_CLK_0"),
147         PINCTRL_PIN(95, "DMIC_DATA_0"),
148         PINCTRL_PIN(96, "SPI1_IO_2"),
149         PINCTRL_PIN(97, "SPI1_IO_3"),
150         PINCTRL_PIN(98, "ISH_I2C2_SCL"),
151         /* GPP_G */
152         PINCTRL_PIN(99, "SD3_CMD"),
153         PINCTRL_PIN(100, "SD3_D0"),
154         PINCTRL_PIN(101, "SD3_D1"),
155         PINCTRL_PIN(102, "SD3_D2"),
156         PINCTRL_PIN(103, "SD3_D3"),
157         PINCTRL_PIN(104, "SD3_CDB"),
158         PINCTRL_PIN(105, "SD3_CLK"),
159         PINCTRL_PIN(106, "SD3_WP"),
160         /* AZA */
161         PINCTRL_PIN(107, "HDA_BCLK"),
162         PINCTRL_PIN(108, "HDA_RSTB"),
163         PINCTRL_PIN(109, "HDA_SYNC"),
164         PINCTRL_PIN(110, "HDA_SDO"),
165         PINCTRL_PIN(111, "HDA_SDI_0"),
166         PINCTRL_PIN(112, "HDA_SDI_1"),
167         PINCTRL_PIN(113, "SSP1_SFRM"),
168         PINCTRL_PIN(114, "SSP1_TXD"),
169         /* vGPIO */
170         PINCTRL_PIN(115, "CNV_BTEN"),
171         PINCTRL_PIN(116, "CNV_GNEN"),
172         PINCTRL_PIN(117, "CNV_WFEN"),
173         PINCTRL_PIN(118, "CNV_WCEN"),
174         PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
175         PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
176         PINCTRL_PIN(121, "vSD3_CD_B"),
177         PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
178         PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
179         PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
180         PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
181         PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
182         PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
183         PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
184         PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
185         PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
186         PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
187         PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
188         PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
189         PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
190         PINCTRL_PIN(135, "vUART0_TXD"),
191         PINCTRL_PIN(136, "vUART0_RXD"),
192         PINCTRL_PIN(137, "vUART0_CTS_B"),
193         PINCTRL_PIN(138, "vUART0_RTSB"),
194         PINCTRL_PIN(139, "vISH_UART0_TXD"),
195         PINCTRL_PIN(140, "vISH_UART0_RXD"),
196         PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
197         PINCTRL_PIN(142, "vISH_UART0_RTSB"),
198         PINCTRL_PIN(143, "vISH_UART1_TXD"),
199         PINCTRL_PIN(144, "vISH_UART1_RXD"),
200         PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
201         PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
202         PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
203         PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
204         PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
205         PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
206         PINCTRL_PIN(151, "vSSP2_SCLK"),
207         PINCTRL_PIN(152, "vSSP2_SFRM"),
208         PINCTRL_PIN(153, "vSSP2_TXD"),
209         PINCTRL_PIN(154, "vSSP2_RXD"),
210         /* GPP_K */
211         PINCTRL_PIN(155, "FAN_TACH_0"),
212         PINCTRL_PIN(156, "FAN_TACH_1"),
213         PINCTRL_PIN(157, "FAN_TACH_2"),
214         PINCTRL_PIN(158, "FAN_TACH_3"),
215         PINCTRL_PIN(159, "FAN_TACH_4"),
216         PINCTRL_PIN(160, "FAN_TACH_5"),
217         PINCTRL_PIN(161, "FAN_TACH_6"),
218         PINCTRL_PIN(162, "FAN_TACH_7"),
219         PINCTRL_PIN(163, "FAN_PWM_0"),
220         PINCTRL_PIN(164, "FAN_PWM_1"),
221         PINCTRL_PIN(165, "FAN_PWM_2"),
222         PINCTRL_PIN(166, "FAN_PWM_3"),
223         PINCTRL_PIN(167, "GSXDOUT"),
224         PINCTRL_PIN(168, "GSXSLOAD"),
225         PINCTRL_PIN(169, "GSXDIN"),
226         PINCTRL_PIN(170, "GSXSRESETB"),
227         PINCTRL_PIN(171, "GSXCLK"),
228         PINCTRL_PIN(172, "ADR_COMPLETE"),
229         PINCTRL_PIN(173, "NMIB"),
230         PINCTRL_PIN(174, "SMIB"),
231         PINCTRL_PIN(175, "CORE_VID_0"),
232         PINCTRL_PIN(176, "CORE_VID_1"),
233         PINCTRL_PIN(177, "IMGCLKOUT_0"),
234         PINCTRL_PIN(178, "IMGCLKOUT_1"),
235         /* GPP_H */
236         PINCTRL_PIN(179, "SRCCLKREQB_6"),
237         PINCTRL_PIN(180, "SRCCLKREQB_7"),
238         PINCTRL_PIN(181, "SRCCLKREQB_8"),
239         PINCTRL_PIN(182, "SRCCLKREQB_9"),
240         PINCTRL_PIN(183, "SRCCLKREQB_10"),
241         PINCTRL_PIN(184, "SRCCLKREQB_11"),
242         PINCTRL_PIN(185, "SRCCLKREQB_12"),
243         PINCTRL_PIN(186, "SRCCLKREQB_13"),
244         PINCTRL_PIN(187, "SRCCLKREQB_14"),
245         PINCTRL_PIN(188, "SRCCLKREQB_15"),
246         PINCTRL_PIN(189, "SML2CLK"),
247         PINCTRL_PIN(190, "SML2DATA"),
248         PINCTRL_PIN(191, "SML2ALERTB"),
249         PINCTRL_PIN(192, "SML3CLK"),
250         PINCTRL_PIN(193, "SML3DATA"),
251         PINCTRL_PIN(194, "SML3ALERTB"),
252         PINCTRL_PIN(195, "SML4CLK"),
253         PINCTRL_PIN(196, "SML4DATA"),
254         PINCTRL_PIN(197, "SML4ALERTB"),
255         PINCTRL_PIN(198, "ISH_I2C0_SDA"),
256         PINCTRL_PIN(199, "ISH_I2C0_SCL"),
257         PINCTRL_PIN(200, "ISH_I2C1_SDA"),
258         PINCTRL_PIN(201, "ISH_I2C1_SCL"),
259         PINCTRL_PIN(202, "TIME_SYNC_0"),
260         /* GPP_E */
261         PINCTRL_PIN(203, "SATAXPCIE_0"),
262         PINCTRL_PIN(204, "SATAXPCIE_1"),
263         PINCTRL_PIN(205, "SATAXPCIE_2"),
264         PINCTRL_PIN(206, "CPU_GP_0"),
265         PINCTRL_PIN(207, "SATA_DEVSLP_0"),
266         PINCTRL_PIN(208, "SATA_DEVSLP_1"),
267         PINCTRL_PIN(209, "SATA_DEVSLP_2"),
268         PINCTRL_PIN(210, "CPU_GP_1"),
269         PINCTRL_PIN(211, "SATA_LEDB"),
270         PINCTRL_PIN(212, "USB2_OCB_0"),
271         PINCTRL_PIN(213, "USB2_OCB_1"),
272         PINCTRL_PIN(214, "USB2_OCB_2"),
273         PINCTRL_PIN(215, "USB2_OCB_3"),
274         /* GPP_F */
275         PINCTRL_PIN(216, "SATAXPCIE_3"),
276         PINCTRL_PIN(217, "SATAXPCIE_4"),
277         PINCTRL_PIN(218, "SATAXPCIE_5"),
278         PINCTRL_PIN(219, "SATAXPCIE_6"),
279         PINCTRL_PIN(220, "SATAXPCIE_7"),
280         PINCTRL_PIN(221, "SATA_DEVSLP_3"),
281         PINCTRL_PIN(222, "SATA_DEVSLP_4"),
282         PINCTRL_PIN(223, "SATA_DEVSLP_5"),
283         PINCTRL_PIN(224, "SATA_DEVSLP_6"),
284         PINCTRL_PIN(225, "SATA_DEVSLP_7"),
285         PINCTRL_PIN(226, "SATA_SCLOCK"),
286         PINCTRL_PIN(227, "SATA_SLOAD"),
287         PINCTRL_PIN(228, "SATA_SDATAOUT1"),
288         PINCTRL_PIN(229, "SATA_SDATAOUT0"),
289         PINCTRL_PIN(230, "EXT_PWR_GATEB"),
290         PINCTRL_PIN(231, "USB2_OCB_4"),
291         PINCTRL_PIN(232, "USB2_OCB_5"),
292         PINCTRL_PIN(233, "USB2_OCB_6"),
293         PINCTRL_PIN(234, "USB2_OCB_7"),
294         PINCTRL_PIN(235, "L_VDDEN"),
295         PINCTRL_PIN(236, "L_BKLTEN"),
296         PINCTRL_PIN(237, "L_BKLTCTL"),
297         PINCTRL_PIN(238, "DDPF_CTRLCLK"),
298         PINCTRL_PIN(239, "DDPF_CTRLDATA"),
299         /* SPI */
300         PINCTRL_PIN(240, "SPI0_IO_2"),
301         PINCTRL_PIN(241, "SPI0_IO_3"),
302         PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
303         PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
304         PINCTRL_PIN(244, "SPI0_TPM_CSB"),
305         PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
306         PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
307         PINCTRL_PIN(247, "SPI0_CLK"),
308         PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
309         /* CPU */
310         PINCTRL_PIN(249, "HDACPU_SDI"),
311         PINCTRL_PIN(250, "HDACPU_SDO"),
312         PINCTRL_PIN(251, "HDACPU_SCLK"),
313         PINCTRL_PIN(252, "PM_SYNC"),
314         PINCTRL_PIN(253, "PECI"),
315         PINCTRL_PIN(254, "CPUPWRGD"),
316         PINCTRL_PIN(255, "THRMTRIPB"),
317         PINCTRL_PIN(256, "PLTRST_CPUB"),
318         PINCTRL_PIN(257, "PM_DOWN"),
319         PINCTRL_PIN(258, "TRIGGER_IN"),
320         PINCTRL_PIN(259, "TRIGGER_OUT"),
321         /* JTAG */
322         PINCTRL_PIN(260, "JTAG_TDO"),
323         PINCTRL_PIN(261, "JTAGX"),
324         PINCTRL_PIN(262, "PRDYB"),
325         PINCTRL_PIN(263, "PREQB"),
326         PINCTRL_PIN(264, "CPU_TRSTB"),
327         PINCTRL_PIN(265, "JTAG_TDI"),
328         PINCTRL_PIN(266, "JTAG_TMS"),
329         PINCTRL_PIN(267, "JTAG_TCK"),
330         PINCTRL_PIN(268, "ITP_PMODE"),
331         /* GPP_I */
332         PINCTRL_PIN(269, "DDSP_HPD_0"),
333         PINCTRL_PIN(270, "DDSP_HPD_1"),
334         PINCTRL_PIN(271, "DDSP_HPD_2"),
335         PINCTRL_PIN(272, "DDSP_HPD_3"),
336         PINCTRL_PIN(273, "EDP_HPD"),
337         PINCTRL_PIN(274, "DDPB_CTRLCLK"),
338         PINCTRL_PIN(275, "DDPB_CTRLDATA"),
339         PINCTRL_PIN(276, "DDPC_CTRLCLK"),
340         PINCTRL_PIN(277, "DDPC_CTRLDATA"),
341         PINCTRL_PIN(278, "DDPD_CTRLCLK"),
342         PINCTRL_PIN(279, "DDPD_CTRLDATA"),
343         PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
344         PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
345         PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
346         PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
347         PINCTRL_PIN(284, "SYS_PWROK"),
348         PINCTRL_PIN(285, "SYS_RESETB"),
349         PINCTRL_PIN(286, "MLK_RSTB"),
350         /* GPP_J */
351         PINCTRL_PIN(287, "CNV_PA_BLANKING"),
352         PINCTRL_PIN(288, "CNV_GNSS_FTA"),
353         PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
354         PINCTRL_PIN(290, "CNV_RF_RESET_B"),
355         PINCTRL_PIN(291, "CNV_BRI_DT"),
356         PINCTRL_PIN(292, "CNV_BRI_RSP"),
357         PINCTRL_PIN(293, "CNV_RGI_DT"),
358         PINCTRL_PIN(294, "CNV_RGI_RSP"),
359         PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
360         PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
361         PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
362         PINCTRL_PIN(298, "A4WP_PRESENT"),
363 };
364
365 static const struct intel_padgroup cnlh_community0_gpps[] = {
366         CNL_GPP(0, 0, 24),      /* GPP_A */
367         CNL_GPP(1, 25, 50),     /* GPP_B */
368 };
369
370 static const struct intel_padgroup cnlh_community1_gpps[] = {
371         CNL_GPP(0, 51, 74),     /* GPP_C */
372         CNL_GPP(1, 75, 98),     /* GPP_D */
373         CNL_GPP(2, 99, 106),    /* GPP_G */
374         CNL_GPP(3, 107, 114),   /* AZA */
375         CNL_GPP(4, 115, 146),   /* vGPIO_0 */
376         CNL_GPP(5, 147, 154),   /* vGPIO_1 */
377 };
378
379 static const struct intel_padgroup cnlh_community3_gpps[] = {
380         CNL_GPP(0, 155, 178),   /* GPP_K */
381         CNL_GPP(1, 179, 202),   /* GPP_H */
382         CNL_GPP(2, 203, 215),   /* GPP_E */
383         CNL_GPP(3, 216, 239),   /* GPP_F */
384         CNL_GPP(4, 240, 248),   /* SPI */
385 };
386
387 static const struct intel_padgroup cnlh_community4_gpps[] = {
388         CNL_GPP(0, 249, 259),   /* CPU */
389         CNL_GPP(1, 260, 268),   /* JTAG */
390         CNL_GPP(2, 269, 286),   /* GPP_I */
391         CNL_GPP(3, 287, 298),   /* GPP_J */
392 };
393
394 static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
395 static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
396 static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
397
398 static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
399 static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
400 static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
401
402 static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
403 static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
404 static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
405 static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
406
407 static const struct intel_pingroup cnlh_groups[] = {
408         PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
409         PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
410         PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
411         PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
412         PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
413         PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
414         PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
415         PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
416         PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
417         PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
418 };
419
420 static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
421 static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
422 static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
423 static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
424 static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
425 static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
426 static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
427 static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
428 static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
429 static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
430
431 static const struct intel_function cnlh_functions[] = {
432         FUNCTION("spi0", cnlh_spi0_groups),
433         FUNCTION("spi1", cnlh_spi1_groups),
434         FUNCTION("spi2", cnlh_spi2_groups),
435         FUNCTION("uart0", cnlh_uart0_groups),
436         FUNCTION("uart1", cnlh_uart1_groups),
437         FUNCTION("uart2", cnlh_uart2_groups),
438         FUNCTION("i2c0", cnlh_i2c0_groups),
439         FUNCTION("i2c1", cnlh_i2c1_groups),
440         FUNCTION("i2c2", cnlh_i2c2_groups),
441         FUNCTION("i2c3", cnlh_i2c3_groups),
442 };
443
444 static const struct intel_community cnlh_communities[] = {
445         CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
446         CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
447         /*
448          * ACPI MMIO resources are returned in reverse order for
449          * communities 3 and 4.
450          */
451         CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
452         CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
453 };
454
455 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
456         .pins = cnlh_pins,
457         .npins = ARRAY_SIZE(cnlh_pins),
458         .groups = cnlh_groups,
459         .ngroups = ARRAY_SIZE(cnlh_groups),
460         .functions = cnlh_functions,
461         .nfunctions = ARRAY_SIZE(cnlh_functions),
462         .communities = cnlh_communities,
463         .ncommunities = ARRAY_SIZE(cnlh_communities),
464 };
465
466 /* Cannon Lake-LP */
467 static const struct pinctrl_pin_desc cnllp_pins[] = {
468         /* GPP_A */
469         PINCTRL_PIN(0, "RCINB"),
470         PINCTRL_PIN(1, "LAD_0"),
471         PINCTRL_PIN(2, "LAD_1"),
472         PINCTRL_PIN(3, "LAD_2"),
473         PINCTRL_PIN(4, "LAD_3"),
474         PINCTRL_PIN(5, "LFRAMEB"),
475         PINCTRL_PIN(6, "SERIRQ"),
476         PINCTRL_PIN(7, "PIRQAB"),
477         PINCTRL_PIN(8, "CLKRUNB"),
478         PINCTRL_PIN(9, "CLKOUT_LPC_0"),
479         PINCTRL_PIN(10, "CLKOUT_LPC_1"),
480         PINCTRL_PIN(11, "PMEB"),
481         PINCTRL_PIN(12, "BM_BUSYB"),
482         PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
483         PINCTRL_PIN(14, "SUS_STATB"),
484         PINCTRL_PIN(15, "SUSACKB"),
485         PINCTRL_PIN(16, "SD_1P8_SEL"),
486         PINCTRL_PIN(17, "SD_PWR_EN_B"),
487         PINCTRL_PIN(18, "ISH_GP_0"),
488         PINCTRL_PIN(19, "ISH_GP_1"),
489         PINCTRL_PIN(20, "ISH_GP_2"),
490         PINCTRL_PIN(21, "ISH_GP_3"),
491         PINCTRL_PIN(22, "ISH_GP_4"),
492         PINCTRL_PIN(23, "ISH_GP_5"),
493         PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
494         /* GPP_B */
495         PINCTRL_PIN(25, "CORE_VID_0"),
496         PINCTRL_PIN(26, "CORE_VID_1"),
497         PINCTRL_PIN(27, "VRALERTB"),
498         PINCTRL_PIN(28, "CPU_GP_2"),
499         PINCTRL_PIN(29, "CPU_GP_3"),
500         PINCTRL_PIN(30, "SRCCLKREQB_0"),
501         PINCTRL_PIN(31, "SRCCLKREQB_1"),
502         PINCTRL_PIN(32, "SRCCLKREQB_2"),
503         PINCTRL_PIN(33, "SRCCLKREQB_3"),
504         PINCTRL_PIN(34, "SRCCLKREQB_4"),
505         PINCTRL_PIN(35, "SRCCLKREQB_5"),
506         PINCTRL_PIN(36, "EXT_PWR_GATEB"),
507         PINCTRL_PIN(37, "SLP_S0B"),
508         PINCTRL_PIN(38, "PLTRSTB"),
509         PINCTRL_PIN(39, "SPKR"),
510         PINCTRL_PIN(40, "GSPI0_CS0B"),
511         PINCTRL_PIN(41, "GSPI0_CLK"),
512         PINCTRL_PIN(42, "GSPI0_MISO"),
513         PINCTRL_PIN(43, "GSPI0_MOSI"),
514         PINCTRL_PIN(44, "GSPI1_CS0B"),
515         PINCTRL_PIN(45, "GSPI1_CLK"),
516         PINCTRL_PIN(46, "GSPI1_MISO"),
517         PINCTRL_PIN(47, "GSPI1_MOSI"),
518         PINCTRL_PIN(48, "SML1ALERTB"),
519         PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
520         PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
521         /* GPP_G */
522         PINCTRL_PIN(51, "SD3_CMD"),
523         PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
524         PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
525         PINCTRL_PIN(54, "SD3_D2"),
526         PINCTRL_PIN(55, "SD3_D3"),
527         PINCTRL_PIN(56, "SD3_CDB"),
528         PINCTRL_PIN(57, "SD3_CLK"),
529         PINCTRL_PIN(58, "SD3_WP"),
530         /* SPI */
531         PINCTRL_PIN(59, "SPI0_IO_2"),
532         PINCTRL_PIN(60, "SPI0_IO_3"),
533         PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
534         PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
535         PINCTRL_PIN(63, "SPI0_TPM_CSB"),
536         PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
537         PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
538         PINCTRL_PIN(66, "SPI0_CLK"),
539         PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
540         /* GPP_D */
541         PINCTRL_PIN(68, "SPI1_CSB"),
542         PINCTRL_PIN(69, "SPI1_CLK"),
543         PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
544         PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
545         PINCTRL_PIN(72, "IMGCLKOUT_0"),
546         PINCTRL_PIN(73, "ISH_I2C0_SDA"),
547         PINCTRL_PIN(74, "ISH_I2C0_SCL"),
548         PINCTRL_PIN(75, "ISH_I2C1_SDA"),
549         PINCTRL_PIN(76, "ISH_I2C1_SCL"),
550         PINCTRL_PIN(77, "ISH_SPI_CSB"),
551         PINCTRL_PIN(78, "ISH_SPI_CLK"),
552         PINCTRL_PIN(79, "ISH_SPI_MISO"),
553         PINCTRL_PIN(80, "ISH_SPI_MOSI"),
554         PINCTRL_PIN(81, "ISH_UART0_RXD"),
555         PINCTRL_PIN(82, "ISH_UART0_TXD"),
556         PINCTRL_PIN(83, "ISH_UART0_RTSB"),
557         PINCTRL_PIN(84, "ISH_UART0_CTSB"),
558         PINCTRL_PIN(85, "DMIC_CLK_1"),
559         PINCTRL_PIN(86, "DMIC_DATA_1"),
560         PINCTRL_PIN(87, "DMIC_CLK_0"),
561         PINCTRL_PIN(88, "DMIC_DATA_0"),
562         PINCTRL_PIN(89, "SPI1_IO_2"),
563         PINCTRL_PIN(90, "SPI1_IO_3"),
564         PINCTRL_PIN(91, "SSP_MCLK"),
565         PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
566         /* GPP_F */
567         PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
568         PINCTRL_PIN(94, "CNV_GNSS_FTA"),
569         PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
570         PINCTRL_PIN(96, "EMMC_HIP_MON"),
571         PINCTRL_PIN(97, "CNV_BRI_DT"),
572         PINCTRL_PIN(98, "CNV_BRI_RSP"),
573         PINCTRL_PIN(99, "CNV_RGI_DT"),
574         PINCTRL_PIN(100, "CNV_RGI_RSP"),
575         PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
576         PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
577         PINCTRL_PIN(103, "GPP_F_10"),
578         PINCTRL_PIN(104, "EMMC_CMD"),
579         PINCTRL_PIN(105, "EMMC_DATA_0"),
580         PINCTRL_PIN(106, "EMMC_DATA_1"),
581         PINCTRL_PIN(107, "EMMC_DATA_2"),
582         PINCTRL_PIN(108, "EMMC_DATA_3"),
583         PINCTRL_PIN(109, "EMMC_DATA_4"),
584         PINCTRL_PIN(110, "EMMC_DATA_5"),
585         PINCTRL_PIN(111, "EMMC_DATA_6"),
586         PINCTRL_PIN(112, "EMMC_DATA_7"),
587         PINCTRL_PIN(113, "EMMC_RCLK"),
588         PINCTRL_PIN(114, "EMMC_CLK"),
589         PINCTRL_PIN(115, "EMMC_RESETB"),
590         PINCTRL_PIN(116, "A4WP_PRESENT"),
591         /* GPP_H */
592         PINCTRL_PIN(117, "SSP2_SCLK"),
593         PINCTRL_PIN(118, "SSP2_SFRM"),
594         PINCTRL_PIN(119, "SSP2_TXD"),
595         PINCTRL_PIN(120, "SSP2_RXD"),
596         PINCTRL_PIN(121, "I2C2_SDA"),
597         PINCTRL_PIN(122, "I2C2_SCL"),
598         PINCTRL_PIN(123, "I2C3_SDA"),
599         PINCTRL_PIN(124, "I2C3_SCL"),
600         PINCTRL_PIN(125, "I2C4_SDA"),
601         PINCTRL_PIN(126, "I2C4_SCL"),
602         PINCTRL_PIN(127, "I2C5_SDA"),
603         PINCTRL_PIN(128, "I2C5_SCL"),
604         PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
605         PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
606         PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
607         PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
608         PINCTRL_PIN(133, "DDPF_CTRLCLK"),
609         PINCTRL_PIN(134, "DDPF_CTRLDATA"),
610         PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
611         PINCTRL_PIN(136, "TIMESYNC_0"),
612         PINCTRL_PIN(137, "IMGCLKOUT_1"),
613         PINCTRL_PIN(138, "GPPC_H_21"),
614         PINCTRL_PIN(139, "GPPC_H_22"),
615         PINCTRL_PIN(140, "GPPC_H_23"),
616         /* vGPIO */
617         PINCTRL_PIN(141, "CNV_BTEN"),
618         PINCTRL_PIN(142, "CNV_GNEN"),
619         PINCTRL_PIN(143, "CNV_WFEN"),
620         PINCTRL_PIN(144, "CNV_WCEN"),
621         PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
622         PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
623         PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
624         PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
625         PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
626         PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
627         PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
628         PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
629         PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
630         PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
631         PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
632         PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
633         PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
634         PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
635         PINCTRL_PIN(159, "vUART0_TXD"),
636         PINCTRL_PIN(160, "vUART0_RXD"),
637         PINCTRL_PIN(161, "vUART0_CTS_B"),
638         PINCTRL_PIN(162, "vUART0_RTS_B"),
639         PINCTRL_PIN(163, "vISH_UART0_TXD"),
640         PINCTRL_PIN(164, "vISH_UART0_RXD"),
641         PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
642         PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
643         PINCTRL_PIN(167, "vISH_UART1_TXD"),
644         PINCTRL_PIN(168, "vISH_UART1_RXD"),
645         PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
646         PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
647         PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
648         PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
649         PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
650         PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
651         PINCTRL_PIN(175, "vSSP2_SCLK"),
652         PINCTRL_PIN(176, "vSSP2_SFRM"),
653         PINCTRL_PIN(177, "vSSP2_TXD"),
654         PINCTRL_PIN(178, "vSSP2_RXD"),
655         PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
656         PINCTRL_PIN(180, "vSD3_CD_B"),
657         /* GPP_C */
658         PINCTRL_PIN(181, "SMBCLK"),
659         PINCTRL_PIN(182, "SMBDATA"),
660         PINCTRL_PIN(183, "SMBALERTB"),
661         PINCTRL_PIN(184, "SML0CLK"),
662         PINCTRL_PIN(185, "SML0DATA"),
663         PINCTRL_PIN(186, "SML0ALERTB"),
664         PINCTRL_PIN(187, "SML1CLK"),
665         PINCTRL_PIN(188, "SML1DATA"),
666         PINCTRL_PIN(189, "UART0_RXD"),
667         PINCTRL_PIN(190, "UART0_TXD"),
668         PINCTRL_PIN(191, "UART0_RTSB"),
669         PINCTRL_PIN(192, "UART0_CTSB"),
670         PINCTRL_PIN(193, "UART1_RXD"),
671         PINCTRL_PIN(194, "UART1_TXD"),
672         PINCTRL_PIN(195, "UART1_RTSB"),
673         PINCTRL_PIN(196, "UART1_CTSB"),
674         PINCTRL_PIN(197, "I2C0_SDA"),
675         PINCTRL_PIN(198, "I2C0_SCL"),
676         PINCTRL_PIN(199, "I2C1_SDA"),
677         PINCTRL_PIN(200, "I2C1_SCL"),
678         PINCTRL_PIN(201, "UART2_RXD"),
679         PINCTRL_PIN(202, "UART2_TXD"),
680         PINCTRL_PIN(203, "UART2_RTSB"),
681         PINCTRL_PIN(204, "UART2_CTSB"),
682         /* GPP_E */
683         PINCTRL_PIN(205, "SATAXPCIE_0"),
684         PINCTRL_PIN(206, "SATAXPCIE_1"),
685         PINCTRL_PIN(207, "SATAXPCIE_2"),
686         PINCTRL_PIN(208, "CPU_GP_0"),
687         PINCTRL_PIN(209, "SATA_DEVSLP_0"),
688         PINCTRL_PIN(210, "SATA_DEVSLP_1"),
689         PINCTRL_PIN(211, "SATA_DEVSLP_2"),
690         PINCTRL_PIN(212, "CPU_GP_1"),
691         PINCTRL_PIN(213, "SATA_LEDB"),
692         PINCTRL_PIN(214, "USB2_OCB_0"),
693         PINCTRL_PIN(215, "USB2_OCB_1"),
694         PINCTRL_PIN(216, "USB2_OCB_2"),
695         PINCTRL_PIN(217, "USB2_OCB_3"),
696         PINCTRL_PIN(218, "DDSP_HPD_0"),
697         PINCTRL_PIN(219, "DDSP_HPD_1"),
698         PINCTRL_PIN(220, "DDSP_HPD_2"),
699         PINCTRL_PIN(221, "DDSP_HPD_3"),
700         PINCTRL_PIN(222, "EDP_HPD"),
701         PINCTRL_PIN(223, "DDPB_CTRLCLK"),
702         PINCTRL_PIN(224, "DDPB_CTRLDATA"),
703         PINCTRL_PIN(225, "DDPC_CTRLCLK"),
704         PINCTRL_PIN(226, "DDPC_CTRLDATA"),
705         PINCTRL_PIN(227, "DDPD_CTRLCLK"),
706         PINCTRL_PIN(228, "DDPD_CTRLDATA"),
707         /* JTAG */
708         PINCTRL_PIN(229, "JTAG_TDO"),
709         PINCTRL_PIN(230, "JTAGX"),
710         PINCTRL_PIN(231, "PRDYB"),
711         PINCTRL_PIN(232, "PREQB"),
712         PINCTRL_PIN(233, "CPU_TRSTB"),
713         PINCTRL_PIN(234, "JTAG_TDI"),
714         PINCTRL_PIN(235, "JTAG_TMS"),
715         PINCTRL_PIN(236, "JTAG_TCK"),
716         PINCTRL_PIN(237, "ITP_PMODE"),
717         /* HVCMOS */
718         PINCTRL_PIN(238, "L_BKLTEN"),
719         PINCTRL_PIN(239, "L_BKLTCTL"),
720         PINCTRL_PIN(240, "L_VDDEN"),
721         PINCTRL_PIN(241, "SYS_PWROK"),
722         PINCTRL_PIN(242, "SYS_RESETB"),
723         PINCTRL_PIN(243, "MLK_RSTB"),
724 };
725
726 static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
727 static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
728 static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
729 static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
730 static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
731 static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
732
733 static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
734 static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
735 static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
736 static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
737 static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
738 static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
739
740 static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
741 static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
742 static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
743
744 static const struct intel_pingroup cnllp_groups[] = {
745         PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
746         PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
747         PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
748         PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
749         PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
750         PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
751         PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
752         PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
753         PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
754         PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
755         PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
756         PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
757 };
758
759 static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
760 static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
761 static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
762 static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
763 static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
764 static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
765 static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
766 static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
767 static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
768 static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
769 static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
770 static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
771
772 static const struct intel_function cnllp_functions[] = {
773         FUNCTION("spi0", cnllp_spi0_groups),
774         FUNCTION("spi1", cnllp_spi1_groups),
775         FUNCTION("spi2", cnllp_spi2_groups),
776         FUNCTION("i2c0", cnllp_i2c0_groups),
777         FUNCTION("i2c1", cnllp_i2c1_groups),
778         FUNCTION("i2c2", cnllp_i2c2_groups),
779         FUNCTION("i2c3", cnllp_i2c3_groups),
780         FUNCTION("i2c4", cnllp_i2c4_groups),
781         FUNCTION("i2c5", cnllp_i2c5_groups),
782         FUNCTION("uart0", cnllp_uart0_groups),
783         FUNCTION("uart1", cnllp_uart1_groups),
784         FUNCTION("uart2", cnllp_uart2_groups),
785 };
786
787 static const struct intel_padgroup cnllp_community0_gpps[] = {
788         CNL_GPP(0, 0, 24),      /* GPP_A */
789         CNL_GPP(1, 25, 50),     /* GPP_B */
790         CNL_GPP(2, 51, 58),     /* GPP_G */
791         CNL_GPP(3, 59, 67),     /* SPI */
792 };
793
794 static const struct intel_padgroup cnllp_community1_gpps[] = {
795         CNL_GPP(0, 68, 92),     /* GPP_D */
796         CNL_GPP(1, 93, 116),    /* GPP_F */
797         CNL_GPP(2, 117, 140),   /* GPP_H */
798         CNL_GPP(3, 141, 172),   /* vGPIO */
799         CNL_GPP(4, 173, 180),   /* vGPIO */
800 };
801
802 static const struct intel_padgroup cnllp_community4_gpps[] = {
803         CNL_GPP(0, 181, 204),   /* GPP_C */
804         CNL_GPP(1, 205, 228),   /* GPP_E */
805         CNL_GPP(2, 229, 237),   /* JTAG */
806         CNL_GPP(3, 238, 243),   /* HVCMOS */
807 };
808
809 static const struct intel_community cnllp_communities[] = {
810         CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
811         CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
812         CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
813 };
814
815 static const struct intel_pinctrl_soc_data cnllp_soc_data = {
816         .pins = cnllp_pins,
817         .npins = ARRAY_SIZE(cnllp_pins),
818         .groups = cnllp_groups,
819         .ngroups = ARRAY_SIZE(cnllp_groups),
820         .functions = cnllp_functions,
821         .nfunctions = ARRAY_SIZE(cnllp_functions),
822         .communities = cnllp_communities,
823         .ncommunities = ARRAY_SIZE(cnllp_communities),
824 };
825
826 static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
827         { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
828         { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
829         { },
830 };
831 MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
832
833 static int cnl_pinctrl_probe(struct platform_device *pdev)
834 {
835         const struct intel_pinctrl_soc_data *soc_data;
836         const struct acpi_device_id *id;
837
838         id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
839         if (!id || !id->driver_data)
840                 return -ENODEV;
841
842         soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
843         return intel_pinctrl_probe(pdev, soc_data);
844 }
845
846 static const struct dev_pm_ops cnl_pinctrl_pm_ops = {
847         SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
848                                      intel_pinctrl_resume)
849 };
850
851 static struct platform_driver cnl_pinctrl_driver = {
852         .probe = cnl_pinctrl_probe,
853         .driver = {
854                 .name = "cannonlake-pinctrl",
855                 .acpi_match_table = cnl_pinctrl_acpi_match,
856                 .pm = &cnl_pinctrl_pm_ops,
857         },
858 };
859
860 module_platform_driver(cnl_pinctrl_driver);
861
862 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
863 MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
864 MODULE_LICENSE("GPL v2");