Merge tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[sfrench/cifs-2.6.git] / drivers / pinctrl / intel / pinctrl-broxton.c
1 /*
2  * Intel Broxton SoC pinctrl/GPIO driver
3  *
4  * Copyright (C) 2015, 2016 Intel Corporation
5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/acpi.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm.h>
16 #include <linux/pinctrl/pinctrl.h>
17
18 #include "pinctrl-intel.h"
19
20 #define BXT_PAD_OWN     0x020
21 #define BXT_HOSTSW_OWN  0x080
22 #define BXT_PADCFGLOCK  0x060
23 #define BXT_GPI_IE      0x110
24
25 #define BXT_COMMUNITY(s, e)                             \
26         {                                               \
27                 .padown_offset = BXT_PAD_OWN,           \
28                 .padcfglock_offset = BXT_PADCFGLOCK,    \
29                 .hostown_offset = BXT_HOSTSW_OWN,       \
30                 .ie_offset = BXT_GPI_IE,                \
31                 .gpp_size = 32,                         \
32                 .pin_base = (s),                        \
33                 .npins = ((e) - (s) + 1),               \
34         }
35
36 /* BXT */
37 static const struct pinctrl_pin_desc bxt_north_pins[] = {
38         PINCTRL_PIN(0, "GPIO_0"),
39         PINCTRL_PIN(1, "GPIO_1"),
40         PINCTRL_PIN(2, "GPIO_2"),
41         PINCTRL_PIN(3, "GPIO_3"),
42         PINCTRL_PIN(4, "GPIO_4"),
43         PINCTRL_PIN(5, "GPIO_5"),
44         PINCTRL_PIN(6, "GPIO_6"),
45         PINCTRL_PIN(7, "GPIO_7"),
46         PINCTRL_PIN(8, "GPIO_8"),
47         PINCTRL_PIN(9, "GPIO_9"),
48         PINCTRL_PIN(10, "GPIO_10"),
49         PINCTRL_PIN(11, "GPIO_11"),
50         PINCTRL_PIN(12, "GPIO_12"),
51         PINCTRL_PIN(13, "GPIO_13"),
52         PINCTRL_PIN(14, "GPIO_14"),
53         PINCTRL_PIN(15, "GPIO_15"),
54         PINCTRL_PIN(16, "GPIO_16"),
55         PINCTRL_PIN(17, "GPIO_17"),
56         PINCTRL_PIN(18, "GPIO_18"),
57         PINCTRL_PIN(19, "GPIO_19"),
58         PINCTRL_PIN(20, "GPIO_20"),
59         PINCTRL_PIN(21, "GPIO_21"),
60         PINCTRL_PIN(22, "GPIO_22"),
61         PINCTRL_PIN(23, "GPIO_23"),
62         PINCTRL_PIN(24, "GPIO_24"),
63         PINCTRL_PIN(25, "GPIO_25"),
64         PINCTRL_PIN(26, "GPIO_26"),
65         PINCTRL_PIN(27, "GPIO_27"),
66         PINCTRL_PIN(28, "GPIO_28"),
67         PINCTRL_PIN(29, "GPIO_29"),
68         PINCTRL_PIN(30, "GPIO_30"),
69         PINCTRL_PIN(31, "GPIO_31"),
70         PINCTRL_PIN(32, "GPIO_32"),
71         PINCTRL_PIN(33, "GPIO_33"),
72         PINCTRL_PIN(34, "PWM0"),
73         PINCTRL_PIN(35, "PWM1"),
74         PINCTRL_PIN(36, "PWM2"),
75         PINCTRL_PIN(37, "PWM3"),
76         PINCTRL_PIN(38, "LPSS_UART0_RXD"),
77         PINCTRL_PIN(39, "LPSS_UART0_TXD"),
78         PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
79         PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
80         PINCTRL_PIN(42, "LPSS_UART1_RXD"),
81         PINCTRL_PIN(43, "LPSS_UART1_TXD"),
82         PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
83         PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
84         PINCTRL_PIN(46, "LPSS_UART2_RXD"),
85         PINCTRL_PIN(47, "LPSS_UART2_TXD"),
86         PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
87         PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
88         PINCTRL_PIN(50, "ISH_UART0_RXD"),
89         PINCTRL_PIN(51, "ISH_UART0_TXT"),
90         PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
91         PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
92         PINCTRL_PIN(54, "ISH_UART1_RXD"),
93         PINCTRL_PIN(55, "ISH_UART1_TXT"),
94         PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
95         PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
96         PINCTRL_PIN(58, "ISH_UART2_RXD"),
97         PINCTRL_PIN(59, "ISH_UART2_TXD"),
98         PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
99         PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
100         PINCTRL_PIN(62, "GP_CAMERASB00"),
101         PINCTRL_PIN(63, "GP_CAMERASB01"),
102         PINCTRL_PIN(64, "GP_CAMERASB02"),
103         PINCTRL_PIN(65, "GP_CAMERASB03"),
104         PINCTRL_PIN(66, "GP_CAMERASB04"),
105         PINCTRL_PIN(67, "GP_CAMERASB05"),
106         PINCTRL_PIN(68, "GP_CAMERASB06"),
107         PINCTRL_PIN(69, "GP_CAMERASB07"),
108         PINCTRL_PIN(70, "GP_CAMERASB08"),
109         PINCTRL_PIN(71, "GP_CAMERASB09"),
110         PINCTRL_PIN(72, "GP_CAMERASB10"),
111         PINCTRL_PIN(73, "GP_CAMERASB11"),
112         PINCTRL_PIN(74, "TCK"),
113         PINCTRL_PIN(75, "TRST_B"),
114         PINCTRL_PIN(76, "TMS"),
115         PINCTRL_PIN(77, "TDI"),
116         PINCTRL_PIN(78, "CX_PMODE"),
117         PINCTRL_PIN(79, "CX_PREQ_B"),
118         PINCTRL_PIN(80, "JTAGX"),
119         PINCTRL_PIN(81, "CX_PRDY_B"),
120         PINCTRL_PIN(82, "TDO"),
121 };
122
123 static const unsigned bxt_north_pwm0_pins[] = { 34 };
124 static const unsigned bxt_north_pwm1_pins[] = { 35 };
125 static const unsigned bxt_north_pwm2_pins[] = { 36 };
126 static const unsigned bxt_north_pwm3_pins[] = { 37 };
127 static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
128 static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
129 static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
130 static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
131 static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
132 static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
133 static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
134
135 static const struct intel_pingroup bxt_north_groups[] = {
136         PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
137         PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
138         PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
139         PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
140         PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
141         PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
142         PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
143         PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
144         PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
145         PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
146         PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
147 };
148
149 static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
150 static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
151 static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
152 static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
153 static const char * const bxt_north_uart0_groups[] = {
154         "uart0_grp", "uart0b_grp",
155 };
156 static const char * const bxt_north_uart1_groups[] = {
157         "uart1_grp", "uart1b_grp",
158 };
159 static const char * const bxt_north_uart2_groups[] = {
160         "uart2_grp", "uart2b_grp",
161 };
162 static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
163
164 static const struct intel_function bxt_north_functions[] = {
165         FUNCTION("pwm0", bxt_north_pwm0_groups),
166         FUNCTION("pwm1", bxt_north_pwm1_groups),
167         FUNCTION("pwm2", bxt_north_pwm2_groups),
168         FUNCTION("pwm3", bxt_north_pwm3_groups),
169         FUNCTION("uart0", bxt_north_uart0_groups),
170         FUNCTION("uart1", bxt_north_uart1_groups),
171         FUNCTION("uart2", bxt_north_uart2_groups),
172         FUNCTION("uart3", bxt_north_uart3_groups),
173 };
174
175 static const struct intel_community bxt_north_communities[] = {
176         BXT_COMMUNITY(0, 82),
177 };
178
179 static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
180         .uid = "1",
181         .pins = bxt_north_pins,
182         .npins = ARRAY_SIZE(bxt_north_pins),
183         .groups = bxt_north_groups,
184         .ngroups = ARRAY_SIZE(bxt_north_groups),
185         .functions = bxt_north_functions,
186         .nfunctions = ARRAY_SIZE(bxt_north_functions),
187         .communities = bxt_north_communities,
188         .ncommunities = ARRAY_SIZE(bxt_north_communities),
189 };
190
191 static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
192         PINCTRL_PIN(0, "PMC_SPI_FS0"),
193         PINCTRL_PIN(1, "PMC_SPI_FS1"),
194         PINCTRL_PIN(2, "PMC_SPI_FS2"),
195         PINCTRL_PIN(3, "PMC_SPI_RXD"),
196         PINCTRL_PIN(4, "PMC_SPI_TXD"),
197         PINCTRL_PIN(5, "PMC_SPI_CLK"),
198         PINCTRL_PIN(6, "PMC_UART_RXD"),
199         PINCTRL_PIN(7, "PMC_UART_TXD"),
200         PINCTRL_PIN(8, "PMIC_PWRGOOD"),
201         PINCTRL_PIN(9, "PMIC_RESET_B"),
202         PINCTRL_PIN(10, "RTC_CLK"),
203         PINCTRL_PIN(11, "PMIC_SDWN_B"),
204         PINCTRL_PIN(12, "PMIC_BCUDISW2"),
205         PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
206         PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
207         PINCTRL_PIN(15, "PMIC_STDBY"),
208         PINCTRL_PIN(16, "SVID0_ALERT_B"),
209         PINCTRL_PIN(17, "SVID0_DATA"),
210         PINCTRL_PIN(18, "SVID0_CLK"),
211         PINCTRL_PIN(19, "PMIC_I2C_SCL"),
212         PINCTRL_PIN(20, "PMIC_I2C_SDA"),
213         PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
214         PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
215         PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
216         PINCTRL_PIN(24, "AVS_I2S1_SDI"),
217         PINCTRL_PIN(25, "AVS_I2S1_SDO"),
218         PINCTRL_PIN(26, "AVS_M_CLK_A1"),
219         PINCTRL_PIN(27, "AVS_M_CLK_B1"),
220         PINCTRL_PIN(28, "AVS_M_DATA_1"),
221         PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
222         PINCTRL_PIN(30, "AVS_M_DATA_2"),
223         PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
224         PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
225         PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
226         PINCTRL_PIN(34, "AVS_I2S2_SDI"),
227         PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
228         PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
229         PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
230         PINCTRL_PIN(38, "AVS_I2S3_SDI"),
231         PINCTRL_PIN(39, "AVS_I2S3_SDO"),
232         PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
233         PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
234         PINCTRL_PIN(42, "AVS_I2S4_SDI"),
235         PINCTRL_PIN(43, "AVS_I2S4_SDO"),
236         PINCTRL_PIN(44, "PROCHOT_B"),
237         PINCTRL_PIN(45, "FST_SPI_CS0_B"),
238         PINCTRL_PIN(46, "FST_SPI_CS1_B"),
239         PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
240         PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
241         PINCTRL_PIN(49, "FST_SPI_IO2"),
242         PINCTRL_PIN(50, "FST_SPI_IO3"),
243         PINCTRL_PIN(51, "FST_SPI_CLK"),
244         PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
245         PINCTRL_PIN(53, "GP_SSP_0_CLK"),
246         PINCTRL_PIN(54, "GP_SSP_0_FS0"),
247         PINCTRL_PIN(55, "GP_SSP_0_FS1"),
248         PINCTRL_PIN(56, "GP_SSP_0_FS2"),
249         PINCTRL_PIN(57, "GP_SSP_0_RXD"),
250         PINCTRL_PIN(58, "GP_SSP_0_TXD"),
251         PINCTRL_PIN(59, "GP_SSP_1_CLK"),
252         PINCTRL_PIN(60, "GP_SSP_1_FS0"),
253         PINCTRL_PIN(61, "GP_SSP_1_FS1"),
254         PINCTRL_PIN(62, "GP_SSP_1_FS2"),
255         PINCTRL_PIN(63, "GP_SSP_1_FS3"),
256         PINCTRL_PIN(64, "GP_SSP_1_RXD"),
257         PINCTRL_PIN(65, "GP_SSP_1_TXD"),
258         PINCTRL_PIN(66, "GP_SSP_2_CLK"),
259         PINCTRL_PIN(67, "GP_SSP_2_FS0"),
260         PINCTRL_PIN(68, "GP_SSP_2_FS1"),
261         PINCTRL_PIN(69, "GP_SSP_2_FS2"),
262         PINCTRL_PIN(70, "GP_SSP_2_RXD"),
263         PINCTRL_PIN(71, "GP_SSP_2_TXD"),
264 };
265
266 static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
267 static const unsigned bxt_northwest_ssp1_pins[] = {
268         59, 60, 61, 62, 63, 64, 65
269 };
270 static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
271 static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
272
273 static const struct intel_pingroup bxt_northwest_groups[] = {
274         PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
275         PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
276         PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
277         PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
278 };
279
280 static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
281 static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
282 static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
283 static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
284
285 static const struct intel_function bxt_northwest_functions[] = {
286         FUNCTION("ssp0", bxt_northwest_ssp0_groups),
287         FUNCTION("ssp1", bxt_northwest_ssp1_groups),
288         FUNCTION("ssp2", bxt_northwest_ssp2_groups),
289         FUNCTION("uart3", bxt_northwest_uart3_groups),
290 };
291
292 static const struct intel_community bxt_northwest_communities[] = {
293         BXT_COMMUNITY(0, 71),
294 };
295
296 static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
297         .uid = "2",
298         .pins = bxt_northwest_pins,
299         .npins = ARRAY_SIZE(bxt_northwest_pins),
300         .groups = bxt_northwest_groups,
301         .ngroups = ARRAY_SIZE(bxt_northwest_groups),
302         .functions = bxt_northwest_functions,
303         .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
304         .communities = bxt_northwest_communities,
305         .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
306 };
307
308 static const struct pinctrl_pin_desc bxt_west_pins[] = {
309         PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
310         PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
311         PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
312         PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
313         PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
314         PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
315         PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
316         PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
317         PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
318         PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
319         PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
320         PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
321         PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
322         PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
323         PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
324         PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
325         PINCTRL_PIN(16, "ISH_I2C0_SDA"),
326         PINCTRL_PIN(17, "ISH_I2C0_SCL"),
327         PINCTRL_PIN(18, "ISH_I2C1_SDA"),
328         PINCTRL_PIN(19, "ISH_I2C1_SCL"),
329         PINCTRL_PIN(20, "ISH_I2C2_SDA"),
330         PINCTRL_PIN(21, "ISH_I2C2_SCL"),
331         PINCTRL_PIN(22, "ISH_GPIO_0"),
332         PINCTRL_PIN(23, "ISH_GPIO_1"),
333         PINCTRL_PIN(24, "ISH_GPIO_2"),
334         PINCTRL_PIN(25, "ISH_GPIO_3"),
335         PINCTRL_PIN(26, "ISH_GPIO_4"),
336         PINCTRL_PIN(27, "ISH_GPIO_5"),
337         PINCTRL_PIN(28, "ISH_GPIO_6"),
338         PINCTRL_PIN(29, "ISH_GPIO_7"),
339         PINCTRL_PIN(30, "ISH_GPIO_8"),
340         PINCTRL_PIN(31, "ISH_GPIO_9"),
341         PINCTRL_PIN(32, "MODEM_CLKREQ"),
342         PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
343         PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
344         PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
345         PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
346         PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
347         PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
348         PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
349         PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
350         PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
351 };
352
353 static const unsigned bxt_west_i2c0_pins[] = { 0, 1 };
354 static const unsigned bxt_west_i2c1_pins[] = { 2, 3 };
355 static const unsigned bxt_west_i2c2_pins[] = { 4, 5 };
356 static const unsigned bxt_west_i2c3_pins[] = { 6, 7 };
357 static const unsigned bxt_west_i2c4_pins[] = { 8, 9 };
358 static const unsigned bxt_west_i2c5_pins[] = { 10, 11 };
359 static const unsigned bxt_west_i2c6_pins[] = { 12, 13 };
360 static const unsigned bxt_west_i2c7_pins[] = { 14, 15 };
361 static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 };
362 static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 };
363 static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 };
364
365 static const struct intel_pingroup bxt_west_groups[] = {
366         PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
367         PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
368         PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
369         PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
370         PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
371         PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
372         PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
373         PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
374         PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
375         PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
376         PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
377 };
378
379 static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
380 static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
381 static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
382 static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
383 static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
384 static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
385 static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
386 static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
387
388 static const struct intel_function bxt_west_functions[] = {
389         FUNCTION("i2c0", bxt_west_i2c0_groups),
390         FUNCTION("i2c1", bxt_west_i2c1_groups),
391         FUNCTION("i2c2", bxt_west_i2c2_groups),
392         FUNCTION("i2c3", bxt_west_i2c3_groups),
393         FUNCTION("i2c4", bxt_west_i2c4_groups),
394         FUNCTION("i2c5", bxt_west_i2c5_groups),
395         FUNCTION("i2c6", bxt_west_i2c6_groups),
396         FUNCTION("i2c7", bxt_west_i2c7_groups),
397 };
398
399 static const struct intel_community bxt_west_communities[] = {
400         BXT_COMMUNITY(0, 41),
401 };
402
403 static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
404         .uid = "3",
405         .pins = bxt_west_pins,
406         .npins = ARRAY_SIZE(bxt_west_pins),
407         .groups = bxt_west_groups,
408         .ngroups = ARRAY_SIZE(bxt_west_groups),
409         .functions = bxt_west_functions,
410         .nfunctions = ARRAY_SIZE(bxt_west_functions),
411         .communities = bxt_west_communities,
412         .ncommunities = ARRAY_SIZE(bxt_west_communities),
413 };
414
415 static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
416         PINCTRL_PIN(0, "EMMC0_CLK"),
417         PINCTRL_PIN(1, "EMMC0_D0"),
418         PINCTRL_PIN(2, "EMMC0_D1"),
419         PINCTRL_PIN(3, "EMMC0_D2"),
420         PINCTRL_PIN(4, "EMMC0_D3"),
421         PINCTRL_PIN(5, "EMMC0_D4"),
422         PINCTRL_PIN(6, "EMMC0_D5"),
423         PINCTRL_PIN(7, "EMMC0_D6"),
424         PINCTRL_PIN(8, "EMMC0_D7"),
425         PINCTRL_PIN(9, "EMMC0_CMD"),
426         PINCTRL_PIN(10, "SDIO_CLK"),
427         PINCTRL_PIN(11, "SDIO_D0"),
428         PINCTRL_PIN(12, "SDIO_D1"),
429         PINCTRL_PIN(13, "SDIO_D2"),
430         PINCTRL_PIN(14, "SDIO_D3"),
431         PINCTRL_PIN(15, "SDIO_CMD"),
432         PINCTRL_PIN(16, "SDCARD_CLK"),
433         PINCTRL_PIN(17, "SDCARD_D0"),
434         PINCTRL_PIN(18, "SDCARD_D1"),
435         PINCTRL_PIN(19, "SDCARD_D2"),
436         PINCTRL_PIN(20, "SDCARD_D3"),
437         PINCTRL_PIN(21, "SDCARD_CD_B"),
438         PINCTRL_PIN(22, "SDCARD_CMD"),
439         PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
440         PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
441         PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
442         PINCTRL_PIN(26, "EMMC0_STROBE"),
443         PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
444         PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
445         PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
446         PINCTRL_PIN(30, "SDCARD_LVL_WP"),
447 };
448
449 static const unsigned bxt_southwest_emmc0_pins[] = {
450         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
451 };
452 static const unsigned bxt_southwest_sdio_pins[] = {
453         10, 11, 12, 13, 14, 15, 27,
454 };
455 static const unsigned bxt_southwest_sdcard_pins[] = {
456         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
457 };
458
459 static const struct intel_pingroup bxt_southwest_groups[] = {
460         PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
461         PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
462         PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
463 };
464
465 static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
466 static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
467 static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
468
469 static const struct intel_function bxt_southwest_functions[] = {
470         FUNCTION("emmc0", bxt_southwest_emmc0_groups),
471         FUNCTION("sdio", bxt_southwest_sdio_groups),
472         FUNCTION("sdcard", bxt_southwest_sdcard_groups),
473 };
474
475 static const struct intel_community bxt_southwest_communities[] = {
476         BXT_COMMUNITY(0, 30),
477 };
478
479 static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
480         .uid = "4",
481         .pins = bxt_southwest_pins,
482         .npins = ARRAY_SIZE(bxt_southwest_pins),
483         .groups = bxt_southwest_groups,
484         .ngroups = ARRAY_SIZE(bxt_southwest_groups),
485         .functions = bxt_southwest_functions,
486         .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
487         .communities = bxt_southwest_communities,
488         .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
489 };
490
491 static const struct pinctrl_pin_desc bxt_south_pins[] = {
492         PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
493         PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
494         PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
495         PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
496         PINCTRL_PIN(4, "DBI_SDA"),
497         PINCTRL_PIN(5, "DBI_SCL"),
498         PINCTRL_PIN(6, "PANEL0_VDDEN"),
499         PINCTRL_PIN(7, "PANEL0_BKLTEN"),
500         PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
501         PINCTRL_PIN(9, "PANEL1_VDDEN"),
502         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
503         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
504         PINCTRL_PIN(12, "DBI_CSX"),
505         PINCTRL_PIN(13, "DBI_RESX"),
506         PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
507         PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
508         PINCTRL_PIN(16, "USB_OC0_B"),
509         PINCTRL_PIN(17, "USB_OC1_B"),
510         PINCTRL_PIN(18, "MEX_WAKE0_B"),
511         PINCTRL_PIN(19, "MEX_WAKE1_B"),
512 };
513
514 static const struct intel_community bxt_south_communities[] = {
515         BXT_COMMUNITY(0, 19),
516 };
517
518 static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
519         .uid = "5",
520         .pins = bxt_south_pins,
521         .npins = ARRAY_SIZE(bxt_south_pins),
522         .communities = bxt_south_communities,
523         .ncommunities = ARRAY_SIZE(bxt_south_communities),
524 };
525
526 static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
527         &bxt_north_soc_data,
528         &bxt_northwest_soc_data,
529         &bxt_west_soc_data,
530         &bxt_southwest_soc_data,
531         &bxt_south_soc_data,
532         NULL,
533 };
534
535 /* APL */
536 static const struct pinctrl_pin_desc apl_north_pins[] = {
537         PINCTRL_PIN(0, "GPIO_0"),
538         PINCTRL_PIN(1, "GPIO_1"),
539         PINCTRL_PIN(2, "GPIO_2"),
540         PINCTRL_PIN(3, "GPIO_3"),
541         PINCTRL_PIN(4, "GPIO_4"),
542         PINCTRL_PIN(5, "GPIO_5"),
543         PINCTRL_PIN(6, "GPIO_6"),
544         PINCTRL_PIN(7, "GPIO_7"),
545         PINCTRL_PIN(8, "GPIO_8"),
546         PINCTRL_PIN(9, "GPIO_9"),
547         PINCTRL_PIN(10, "GPIO_10"),
548         PINCTRL_PIN(11, "GPIO_11"),
549         PINCTRL_PIN(12, "GPIO_12"),
550         PINCTRL_PIN(13, "GPIO_13"),
551         PINCTRL_PIN(14, "GPIO_14"),
552         PINCTRL_PIN(15, "GPIO_15"),
553         PINCTRL_PIN(16, "GPIO_16"),
554         PINCTRL_PIN(17, "GPIO_17"),
555         PINCTRL_PIN(18, "GPIO_18"),
556         PINCTRL_PIN(19, "GPIO_19"),
557         PINCTRL_PIN(20, "GPIO_20"),
558         PINCTRL_PIN(21, "GPIO_21"),
559         PINCTRL_PIN(22, "GPIO_22"),
560         PINCTRL_PIN(23, "GPIO_23"),
561         PINCTRL_PIN(24, "GPIO_24"),
562         PINCTRL_PIN(25, "GPIO_25"),
563         PINCTRL_PIN(26, "GPIO_26"),
564         PINCTRL_PIN(27, "GPIO_27"),
565         PINCTRL_PIN(28, "GPIO_28"),
566         PINCTRL_PIN(29, "GPIO_29"),
567         PINCTRL_PIN(30, "GPIO_30"),
568         PINCTRL_PIN(31, "GPIO_31"),
569         PINCTRL_PIN(32, "GPIO_32"),
570         PINCTRL_PIN(33, "GPIO_33"),
571         PINCTRL_PIN(34, "PWM0"),
572         PINCTRL_PIN(35, "PWM1"),
573         PINCTRL_PIN(36, "PWM2"),
574         PINCTRL_PIN(37, "PWM3"),
575         PINCTRL_PIN(38, "LPSS_UART0_RXD"),
576         PINCTRL_PIN(39, "LPSS_UART0_TXD"),
577         PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
578         PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
579         PINCTRL_PIN(42, "LPSS_UART1_RXD"),
580         PINCTRL_PIN(43, "LPSS_UART1_TXD"),
581         PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
582         PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
583         PINCTRL_PIN(46, "LPSS_UART2_RXD"),
584         PINCTRL_PIN(47, "LPSS_UART2_TXD"),
585         PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
586         PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
587         PINCTRL_PIN(50, "GP_CAMERASB00"),
588         PINCTRL_PIN(51, "GP_CAMERASB01"),
589         PINCTRL_PIN(52, "GP_CAMERASB02"),
590         PINCTRL_PIN(53, "GP_CAMERASB03"),
591         PINCTRL_PIN(54, "GP_CAMERASB04"),
592         PINCTRL_PIN(55, "GP_CAMERASB05"),
593         PINCTRL_PIN(56, "GP_CAMERASB06"),
594         PINCTRL_PIN(57, "GP_CAMERASB07"),
595         PINCTRL_PIN(58, "GP_CAMERASB08"),
596         PINCTRL_PIN(59, "GP_CAMERASB09"),
597         PINCTRL_PIN(60, "GP_CAMERASB10"),
598         PINCTRL_PIN(61, "GP_CAMERASB11"),
599         PINCTRL_PIN(62, "TCK"),
600         PINCTRL_PIN(63, "TRST_B"),
601         PINCTRL_PIN(64, "TMS"),
602         PINCTRL_PIN(65, "TDI"),
603         PINCTRL_PIN(66, "CX_PMODE"),
604         PINCTRL_PIN(67, "CX_PREQ_B"),
605         PINCTRL_PIN(68, "JTAGX"),
606         PINCTRL_PIN(69, "CX_PRDY_B"),
607         PINCTRL_PIN(70, "TDO"),
608         PINCTRL_PIN(71, "CNV_BRI_DT"),
609         PINCTRL_PIN(72, "CNV_BRI_RSP"),
610         PINCTRL_PIN(73, "CNV_RGI_DT"),
611         PINCTRL_PIN(74, "CNV_RGI_RSP"),
612         PINCTRL_PIN(75, "SVID0_ALERT_B"),
613         PINCTRL_PIN(76, "SVID0_DATA"),
614         PINCTRL_PIN(77, "SVID0_CLK"),
615 };
616
617 static const unsigned apl_north_pwm0_pins[] = { 34 };
618 static const unsigned apl_north_pwm1_pins[] = { 35 };
619 static const unsigned apl_north_pwm2_pins[] = { 36 };
620 static const unsigned apl_north_pwm3_pins[] = { 37 };
621 static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 };
622 static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 };
623 static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 };
624
625 static const struct intel_pingroup apl_north_groups[] = {
626         PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
627         PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
628         PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
629         PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
630         PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
631         PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
632         PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
633 };
634
635 static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
636 static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
637 static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
638 static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
639 static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
640 static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
641 static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
642
643 static const struct intel_function apl_north_functions[] = {
644         FUNCTION("pwm0", apl_north_pwm0_groups),
645         FUNCTION("pwm1", apl_north_pwm1_groups),
646         FUNCTION("pwm2", apl_north_pwm2_groups),
647         FUNCTION("pwm3", apl_north_pwm3_groups),
648         FUNCTION("uart0", apl_north_uart0_groups),
649         FUNCTION("uart1", apl_north_uart1_groups),
650         FUNCTION("uart2", apl_north_uart2_groups),
651 };
652
653 static const struct intel_community apl_north_communities[] = {
654         BXT_COMMUNITY(0, 77),
655 };
656
657 static const struct intel_pinctrl_soc_data apl_north_soc_data = {
658         .uid = "1",
659         .pins = apl_north_pins,
660         .npins = ARRAY_SIZE(apl_north_pins),
661         .groups = apl_north_groups,
662         .ngroups = ARRAY_SIZE(apl_north_groups),
663         .functions = apl_north_functions,
664         .nfunctions = ARRAY_SIZE(apl_north_functions),
665         .communities = apl_north_communities,
666         .ncommunities = ARRAY_SIZE(apl_north_communities),
667 };
668
669 static const struct pinctrl_pin_desc apl_northwest_pins[] = {
670         PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
671         PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
672         PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
673         PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
674         PINCTRL_PIN(4, "DBI_SDA"),
675         PINCTRL_PIN(5, "DBI_SCL"),
676         PINCTRL_PIN(6, "PANEL0_VDDEN"),
677         PINCTRL_PIN(7, "PANEL0_BKLTEN"),
678         PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
679         PINCTRL_PIN(9, "PANEL1_VDDEN"),
680         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
681         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
682         PINCTRL_PIN(12, "DBI_CSX"),
683         PINCTRL_PIN(13, "DBI_RESX"),
684         PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
685         PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
686         PINCTRL_PIN(16, "USB_OC0_B"),
687         PINCTRL_PIN(17, "USB_OC1_B"),
688         PINCTRL_PIN(18, "PMC_SPI_FS0"),
689         PINCTRL_PIN(19, "PMC_SPI_FS1"),
690         PINCTRL_PIN(20, "PMC_SPI_FS2"),
691         PINCTRL_PIN(21, "PMC_SPI_RXD"),
692         PINCTRL_PIN(22, "PMC_SPI_TXD"),
693         PINCTRL_PIN(23, "PMC_SPI_CLK"),
694         PINCTRL_PIN(24, "PMIC_PWRGOOD"),
695         PINCTRL_PIN(25, "PMIC_RESET_B"),
696         PINCTRL_PIN(26, "PMIC_SDWN_B"),
697         PINCTRL_PIN(27, "PMIC_BCUDISW2"),
698         PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
699         PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
700         PINCTRL_PIN(30, "PMIC_STDBY"),
701         PINCTRL_PIN(31, "PROCHOT_B"),
702         PINCTRL_PIN(32, "PMIC_I2C_SCL"),
703         PINCTRL_PIN(33, "PMIC_I2C_SDA"),
704         PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
705         PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
706         PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
707         PINCTRL_PIN(37, "AVS_I2S1_SDI"),
708         PINCTRL_PIN(38, "AVS_I2S1_SDO"),
709         PINCTRL_PIN(39, "AVS_M_CLK_A1"),
710         PINCTRL_PIN(40, "AVS_M_CLK_B1"),
711         PINCTRL_PIN(41, "AVS_M_DATA_1"),
712         PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
713         PINCTRL_PIN(43, "AVS_M_DATA_2"),
714         PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
715         PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
716         PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
717         PINCTRL_PIN(47, "AVS_I2S2_SDI"),
718         PINCTRL_PIN(48, "AVS_I2S2_SDO"),
719         PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
720         PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
721         PINCTRL_PIN(51, "AVS_I2S3_SDI"),
722         PINCTRL_PIN(52, "AVS_I2S3_SDO"),
723         PINCTRL_PIN(53, "FST_SPI_CS0_B"),
724         PINCTRL_PIN(54, "FST_SPI_CS1_B"),
725         PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
726         PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
727         PINCTRL_PIN(57, "FST_SPI_IO2"),
728         PINCTRL_PIN(58, "FST_SPI_IO3"),
729         PINCTRL_PIN(59, "FST_SPI_CLK"),
730         PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
731         PINCTRL_PIN(61, "GP_SSP_0_CLK"),
732         PINCTRL_PIN(62, "GP_SSP_0_FS0"),
733         PINCTRL_PIN(63, "GP_SSP_0_FS1"),
734         PINCTRL_PIN(64, "GP_SSP_0_RXD"),
735         PINCTRL_PIN(65, "GP_SSP_0_TXD"),
736         PINCTRL_PIN(66, "GP_SSP_1_CLK"),
737         PINCTRL_PIN(67, "GP_SSP_1_FS0"),
738         PINCTRL_PIN(68, "GP_SSP_1_FS1"),
739         PINCTRL_PIN(69, "GP_SSP_1_RXD"),
740         PINCTRL_PIN(70, "GP_SSP_1_TXD"),
741         PINCTRL_PIN(71, "GP_SSP_2_CLK"),
742         PINCTRL_PIN(72, "GP_SSP_2_FS0"),
743         PINCTRL_PIN(73, "GP_SSP_2_FS1"),
744         PINCTRL_PIN(74, "GP_SSP_2_FS2"),
745         PINCTRL_PIN(75, "GP_SSP_2_RXD"),
746         PINCTRL_PIN(76, "GP_SSP_2_TXD"),
747 };
748
749 static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
750 static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
751 static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
752 static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
753
754 static const struct intel_pingroup apl_northwest_groups[] = {
755         PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
756         PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
757         PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
758         PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
759 };
760
761 static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
762 static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
763 static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
764 static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
765
766 static const struct intel_function apl_northwest_functions[] = {
767         FUNCTION("ssp0", apl_northwest_ssp0_groups),
768         FUNCTION("ssp1", apl_northwest_ssp1_groups),
769         FUNCTION("ssp2", apl_northwest_ssp2_groups),
770         FUNCTION("uart3", apl_northwest_uart3_groups),
771 };
772
773 static const struct intel_community apl_northwest_communities[] = {
774         BXT_COMMUNITY(0, 76),
775 };
776
777 static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
778         .uid = "2",
779         .pins = apl_northwest_pins,
780         .npins = ARRAY_SIZE(apl_northwest_pins),
781         .groups = apl_northwest_groups,
782         .ngroups = ARRAY_SIZE(apl_northwest_groups),
783         .functions = apl_northwest_functions,
784         .nfunctions = ARRAY_SIZE(apl_northwest_functions),
785         .communities = apl_northwest_communities,
786         .ncommunities = ARRAY_SIZE(apl_northwest_communities),
787 };
788
789 static const struct pinctrl_pin_desc apl_west_pins[] = {
790         PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
791         PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
792         PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
793         PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
794         PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
795         PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
796         PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
797         PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
798         PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
799         PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
800         PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
801         PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
802         PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
803         PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
804         PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
805         PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
806         PINCTRL_PIN(16, "ISH_GPIO_0"),
807         PINCTRL_PIN(17, "ISH_GPIO_1"),
808         PINCTRL_PIN(18, "ISH_GPIO_2"),
809         PINCTRL_PIN(19, "ISH_GPIO_3"),
810         PINCTRL_PIN(20, "ISH_GPIO_4"),
811         PINCTRL_PIN(21, "ISH_GPIO_5"),
812         PINCTRL_PIN(22, "ISH_GPIO_6"),
813         PINCTRL_PIN(23, "ISH_GPIO_7"),
814         PINCTRL_PIN(24, "ISH_GPIO_8"),
815         PINCTRL_PIN(25, "ISH_GPIO_9"),
816         PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
817         PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
818         PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
819         PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
820         PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
821         PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
822         PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
823         PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
824         PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
825         PINCTRL_PIN(35, "PMU_AC_PRESENT"),
826         PINCTRL_PIN(36, "PMU_BATLOW_B"),
827         PINCTRL_PIN(37, "PMU_PLTRST_B"),
828         PINCTRL_PIN(38, "PMU_PWRBTN_B"),
829         PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
830         PINCTRL_PIN(40, "PMU_SLP_S0_B"),
831         PINCTRL_PIN(41, "PMU_SLP_S3_B"),
832         PINCTRL_PIN(42, "PMU_SLP_S4_B"),
833         PINCTRL_PIN(43, "PMU_SUSCLK"),
834         PINCTRL_PIN(44, "PMU_WAKE_B"),
835         PINCTRL_PIN(45, "SUS_STAT_B"),
836         PINCTRL_PIN(46, "SUSPWRDNACK"),
837 };
838
839 static const unsigned apl_west_i2c0_pins[] = { 0, 1 };
840 static const unsigned apl_west_i2c1_pins[] = { 2, 3 };
841 static const unsigned apl_west_i2c2_pins[] = { 4, 5 };
842 static const unsigned apl_west_i2c3_pins[] = { 6, 7 };
843 static const unsigned apl_west_i2c4_pins[] = { 8, 9 };
844 static const unsigned apl_west_i2c5_pins[] = { 10, 11 };
845 static const unsigned apl_west_i2c6_pins[] = { 12, 13 };
846 static const unsigned apl_west_i2c7_pins[] = { 14, 15 };
847 static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 };
848
849 static const struct intel_pingroup apl_west_groups[] = {
850         PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
851         PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
852         PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
853         PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
854         PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
855         PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
856         PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
857         PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
858         PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
859 };
860
861 static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
862 static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
863 static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
864 static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
865 static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
866 static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
867 static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
868 static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
869 static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
870
871 static const struct intel_function apl_west_functions[] = {
872         FUNCTION("i2c0", apl_west_i2c0_groups),
873         FUNCTION("i2c1", apl_west_i2c1_groups),
874         FUNCTION("i2c2", apl_west_i2c2_groups),
875         FUNCTION("i2c3", apl_west_i2c3_groups),
876         FUNCTION("i2c4", apl_west_i2c4_groups),
877         FUNCTION("i2c5", apl_west_i2c5_groups),
878         FUNCTION("i2c6", apl_west_i2c6_groups),
879         FUNCTION("i2c7", apl_west_i2c7_groups),
880         FUNCTION("uart2", apl_west_uart2_groups),
881 };
882
883 static const struct intel_community apl_west_communities[] = {
884         BXT_COMMUNITY(0, 46),
885 };
886
887 static const struct intel_pinctrl_soc_data apl_west_soc_data = {
888         .uid = "3",
889         .pins = apl_west_pins,
890         .npins = ARRAY_SIZE(apl_west_pins),
891         .groups = apl_west_groups,
892         .ngroups = ARRAY_SIZE(apl_west_groups),
893         .functions = apl_west_functions,
894         .nfunctions = ARRAY_SIZE(apl_west_functions),
895         .communities = apl_west_communities,
896         .ncommunities = ARRAY_SIZE(apl_west_communities),
897 };
898
899 static const struct pinctrl_pin_desc apl_southwest_pins[] = {
900         PINCTRL_PIN(0, "PCIE_WAKE0_B"),
901         PINCTRL_PIN(1, "PCIE_WAKE1_B"),
902         PINCTRL_PIN(2, "PCIE_WAKE2_B"),
903         PINCTRL_PIN(3, "PCIE_WAKE3_B"),
904         PINCTRL_PIN(4, "EMMC0_CLK"),
905         PINCTRL_PIN(5, "EMMC0_D0"),
906         PINCTRL_PIN(6, "EMMC0_D1"),
907         PINCTRL_PIN(7, "EMMC0_D2"),
908         PINCTRL_PIN(8, "EMMC0_D3"),
909         PINCTRL_PIN(9, "EMMC0_D4"),
910         PINCTRL_PIN(10, "EMMC0_D5"),
911         PINCTRL_PIN(11, "EMMC0_D6"),
912         PINCTRL_PIN(12, "EMMC0_D7"),
913         PINCTRL_PIN(13, "EMMC0_CMD"),
914         PINCTRL_PIN(14, "SDIO_CLK"),
915         PINCTRL_PIN(15, "SDIO_D0"),
916         PINCTRL_PIN(16, "SDIO_D1"),
917         PINCTRL_PIN(17, "SDIO_D2"),
918         PINCTRL_PIN(18, "SDIO_D3"),
919         PINCTRL_PIN(19, "SDIO_CMD"),
920         PINCTRL_PIN(20, "SDCARD_CLK"),
921         PINCTRL_PIN(21, "SDCARD_CLK_FB"),
922         PINCTRL_PIN(22, "SDCARD_D0"),
923         PINCTRL_PIN(23, "SDCARD_D1"),
924         PINCTRL_PIN(24, "SDCARD_D2"),
925         PINCTRL_PIN(25, "SDCARD_D3"),
926         PINCTRL_PIN(26, "SDCARD_CD_B"),
927         PINCTRL_PIN(27, "SDCARD_CMD"),
928         PINCTRL_PIN(28, "SDCARD_LVL_WP"),
929         PINCTRL_PIN(29, "EMMC0_STROBE"),
930         PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
931         PINCTRL_PIN(31, "SMB_ALERTB"),
932         PINCTRL_PIN(32, "SMB_CLK"),
933         PINCTRL_PIN(33, "SMB_DATA"),
934         PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
935         PINCTRL_PIN(35, "LPC_CLKOUT0"),
936         PINCTRL_PIN(36, "LPC_CLKOUT1"),
937         PINCTRL_PIN(37, "LPC_AD0"),
938         PINCTRL_PIN(38, "LPC_AD1"),
939         PINCTRL_PIN(39, "LPC_AD2"),
940         PINCTRL_PIN(40, "LPC_AD3"),
941         PINCTRL_PIN(41, "LPC_CLKRUNB"),
942         PINCTRL_PIN(42, "LPC_FRAMEB"),
943 };
944
945 static const unsigned apl_southwest_emmc0_pins[] = {
946         4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
947 };
948 static const unsigned apl_southwest_sdio_pins[] = {
949         14, 15, 16, 17, 18, 19, 30,
950 };
951 static const unsigned apl_southwest_sdcard_pins[] = {
952         20, 21, 22, 23, 24, 25, 26, 27, 28,
953 };
954 static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 };
955
956 static const struct intel_pingroup apl_southwest_groups[] = {
957         PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
958         PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
959         PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
960         PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
961 };
962
963 static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
964 static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
965 static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
966 static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
967
968 static const struct intel_function apl_southwest_functions[] = {
969         FUNCTION("emmc0", apl_southwest_emmc0_groups),
970         FUNCTION("sdio", apl_southwest_sdio_groups),
971         FUNCTION("sdcard", apl_southwest_sdcard_groups),
972         FUNCTION("i2c7", apl_southwest_i2c7_groups),
973 };
974
975 static const struct intel_community apl_southwest_communities[] = {
976         BXT_COMMUNITY(0, 42),
977 };
978
979 static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
980         .uid = "4",
981         .pins = apl_southwest_pins,
982         .npins = ARRAY_SIZE(apl_southwest_pins),
983         .groups = apl_southwest_groups,
984         .ngroups = ARRAY_SIZE(apl_southwest_groups),
985         .functions = apl_southwest_functions,
986         .nfunctions = ARRAY_SIZE(apl_southwest_functions),
987         .communities = apl_southwest_communities,
988         .ncommunities = ARRAY_SIZE(apl_southwest_communities),
989 };
990
991 static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
992         &apl_north_soc_data,
993         &apl_northwest_soc_data,
994         &apl_west_soc_data,
995         &apl_southwest_soc_data,
996         NULL,
997 };
998
999 static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
1000         { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
1001         { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
1002         { }
1003 };
1004 MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
1005
1006 static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
1007         { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
1008         { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
1009         { },
1010 };
1011
1012 static int bxt_pinctrl_probe(struct platform_device *pdev)
1013 {
1014         const struct intel_pinctrl_soc_data *soc_data = NULL;
1015         const struct intel_pinctrl_soc_data **soc_table;
1016         struct acpi_device *adev;
1017         int i;
1018
1019         adev = ACPI_COMPANION(&pdev->dev);
1020         if (adev) {
1021                 const struct acpi_device_id *id;
1022
1023                 id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
1024                 if (!id)
1025                         return -ENODEV;
1026
1027                 soc_table = (const struct intel_pinctrl_soc_data **)
1028                         id->driver_data;
1029
1030                 for (i = 0; soc_table[i]; i++) {
1031                         if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
1032                                 soc_data = soc_table[i];
1033                                 break;
1034                         }
1035                 }
1036         } else {
1037                 const struct platform_device_id *pid;
1038
1039                 pid = platform_get_device_id(pdev);
1040                 if (!pid)
1041                         return -ENODEV;
1042
1043                 soc_table = (const struct intel_pinctrl_soc_data **)
1044                         pid->driver_data;
1045                 soc_data = soc_table[pdev->id];
1046         }
1047
1048         if (!soc_data)
1049                 return -ENODEV;
1050
1051         return intel_pinctrl_probe(pdev, soc_data);
1052 }
1053
1054 static const struct dev_pm_ops bxt_pinctrl_pm_ops = {
1055         SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
1056                                      intel_pinctrl_resume)
1057 };
1058
1059 static struct platform_driver bxt_pinctrl_driver = {
1060         .probe = bxt_pinctrl_probe,
1061         .driver = {
1062                 .name = "broxton-pinctrl",
1063                 .acpi_match_table = bxt_pinctrl_acpi_match,
1064                 .pm = &bxt_pinctrl_pm_ops,
1065         },
1066         .id_table = bxt_pinctrl_platform_ids,
1067 };
1068
1069 static int __init bxt_pinctrl_init(void)
1070 {
1071         return platform_driver_register(&bxt_pinctrl_driver);
1072 }
1073 subsys_initcall(bxt_pinctrl_init);
1074
1075 static void __exit bxt_pinctrl_exit(void)
1076 {
1077         platform_driver_unregister(&bxt_pinctrl_driver);
1078 }
1079 module_exit(bxt_pinctrl_exit);
1080
1081 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1082 MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
1083 MODULE_LICENSE("GPL v2");
1084 MODULE_ALIAS("platform:broxton-pinctrl");