2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include "phy-qcom-ufs-i.h"
17 #define MAX_PROP_NAME 32
18 #define VDDA_PHY_MIN_UV 1000000
19 #define VDDA_PHY_MAX_UV 1000000
20 #define VDDA_PLL_MIN_UV 1800000
21 #define VDDA_PLL_MAX_UV 1800000
22 #define VDDP_REF_CLK_MIN_UV 1200000
23 #define VDDP_REF_CLK_MAX_UV 1200000
25 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
26 struct ufs_qcom_phy_calibration *tbl_A,
28 struct ufs_qcom_phy_calibration *tbl_B,
29 int tbl_size_B, bool is_rate_B)
35 dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
40 for (i = 0; i < tbl_size_A; i++)
41 writel_relaxed(tbl_A[i].cfg_value,
42 ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
45 * In case we would like to work in rate B, we need
46 * to override a registers that were configured in rate A table
47 * with registers of rate B table.
52 dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
58 for (i = 0; i < tbl_size_B; i++)
59 writel_relaxed(tbl_B[i].cfg_value,
60 ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
63 /* flush buffered writes */
69 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate);
72 * This assumes the embedded phy structure inside generic_phy is of type
73 * struct ufs_qcom_phy. In order to function properly it's crucial
74 * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
75 * as the first inside generic_phy.
77 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
79 return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
81 EXPORT_SYMBOL_GPL(get_ufs_qcom_phy);
84 int ufs_qcom_phy_base_init(struct platform_device *pdev,
85 struct ufs_qcom_phy *phy_common)
87 struct device *dev = &pdev->dev;
91 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
92 phy_common->mmio = devm_ioremap_resource(dev, res);
93 if (IS_ERR((void const *)phy_common->mmio)) {
94 err = PTR_ERR((void const *)phy_common->mmio);
95 phy_common->mmio = NULL;
96 dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
101 /* "dev_ref_clk_ctrl_mem" is optional resource */
102 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
103 "dev_ref_clk_ctrl_mem");
104 phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
105 if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio))
106 phy_common->dev_ref_clk_ctrl_mmio = NULL;
111 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
112 struct ufs_qcom_phy *common_cfg,
113 const struct phy_ops *ufs_qcom_phy_gen_ops,
114 struct ufs_qcom_phy_specific_ops *phy_spec_ops)
117 struct device *dev = &pdev->dev;
118 struct phy *generic_phy = NULL;
119 struct phy_provider *phy_provider;
121 err = ufs_qcom_phy_base_init(pdev, common_cfg);
123 dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
127 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
128 if (IS_ERR(phy_provider)) {
129 err = PTR_ERR(phy_provider);
130 dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
134 generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
135 if (IS_ERR(generic_phy)) {
136 err = PTR_ERR(generic_phy);
137 dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
142 common_cfg->phy_spec_ops = phy_spec_ops;
143 common_cfg->dev = dev;
148 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
150 static int __ufs_qcom_phy_clk_get(struct device *dev,
151 const char *name, struct clk **clk_out, bool err_print)
156 clk = devm_clk_get(dev, name);
160 dev_err(dev, "failed to get %s err %d", name, err);
168 static int ufs_qcom_phy_clk_get(struct device *dev,
169 const char *name, struct clk **clk_out)
171 return __ufs_qcom_phy_clk_get(dev, name, clk_out, true);
174 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common)
178 if (of_device_is_compatible(phy_common->dev->of_node,
179 "qcom,msm8996-ufs-phy-qmp-14nm"))
182 err = ufs_qcom_phy_clk_get(phy_common->dev, "tx_iface_clk",
183 &phy_common->tx_iface_clk);
187 err = ufs_qcom_phy_clk_get(phy_common->dev, "rx_iface_clk",
188 &phy_common->rx_iface_clk);
193 err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_src",
194 &phy_common->ref_clk_src);
199 * "ref_clk_parent" is optional hence don't abort init if it's not
202 __ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_parent",
203 &phy_common->ref_clk_parent, false);
205 err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk",
206 &phy_common->ref_clk);
211 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks);
213 static int ufs_qcom_phy_init_vreg(struct device *dev,
214 struct ufs_qcom_phy_vreg *vreg,
219 char prop_name[MAX_PROP_NAME];
222 vreg->reg = devm_regulator_get(dev, name);
223 if (IS_ERR(vreg->reg)) {
224 err = PTR_ERR(vreg->reg);
225 dev_err(dev, "failed to get %s, %d\n", name, err);
230 snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
231 err = of_property_read_u32(dev->of_node,
232 prop_name, &vreg->max_uA);
233 if (err && err != -EINVAL) {
234 dev_err(dev, "%s: failed to read %s\n",
235 __func__, prop_name);
237 } else if (err == -EINVAL || !vreg->max_uA) {
238 if (regulator_count_voltages(vreg->reg) > 0) {
239 dev_err(dev, "%s: %s is mandatory\n",
240 __func__, prop_name);
247 if (!strcmp(name, "vdda-pll")) {
248 vreg->max_uV = VDDA_PLL_MAX_UV;
249 vreg->min_uV = VDDA_PLL_MIN_UV;
250 } else if (!strcmp(name, "vdda-phy")) {
251 vreg->max_uV = VDDA_PHY_MAX_UV;
252 vreg->min_uV = VDDA_PHY_MIN_UV;
253 } else if (!strcmp(name, "vddp-ref-clk")) {
254 vreg->max_uV = VDDP_REF_CLK_MAX_UV;
255 vreg->min_uV = VDDP_REF_CLK_MIN_UV;
262 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common)
266 err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_pll,
271 err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_phy,
277 err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vddp_ref_clk,
283 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators);
285 static int ufs_qcom_phy_cfg_vreg(struct device *dev,
286 struct ufs_qcom_phy_vreg *vreg, bool on)
289 struct regulator *reg = vreg->reg;
290 const char *name = vreg->name;
294 if (regulator_count_voltages(reg) > 0) {
295 min_uV = on ? vreg->min_uV : 0;
296 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
298 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
299 __func__, name, ret);
302 uA_load = on ? vreg->max_uA : 0;
303 ret = regulator_set_load(reg, uA_load);
306 * regulator_set_load() returns new regulator
311 dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
312 __func__, name, uA_load, ret);
320 static int ufs_qcom_phy_enable_vreg(struct device *dev,
321 struct ufs_qcom_phy_vreg *vreg)
325 if (!vreg || vreg->enabled)
328 ret = ufs_qcom_phy_cfg_vreg(dev, vreg, true);
330 dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
335 ret = regulator_enable(vreg->reg);
337 dev_err(dev, "%s: enable failed, err=%d\n",
342 vreg->enabled = true;
347 static int ufs_qcom_phy_enable_ref_clk(struct ufs_qcom_phy *phy)
351 if (phy->is_ref_clk_enabled)
355 * reference clock is propagated in a daisy-chained manner from
356 * source to phy, so ungate them at each stage.
358 ret = clk_prepare_enable(phy->ref_clk_src);
360 dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
366 * "ref_clk_parent" is optional clock hence make sure that clk reference
367 * is available before trying to enable the clock.
369 if (phy->ref_clk_parent) {
370 ret = clk_prepare_enable(phy->ref_clk_parent);
372 dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
374 goto out_disable_src;
378 ret = clk_prepare_enable(phy->ref_clk);
380 dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
382 goto out_disable_parent;
385 phy->is_ref_clk_enabled = true;
389 if (phy->ref_clk_parent)
390 clk_disable_unprepare(phy->ref_clk_parent);
392 clk_disable_unprepare(phy->ref_clk_src);
397 static int ufs_qcom_phy_disable_vreg(struct device *dev,
398 struct ufs_qcom_phy_vreg *vreg)
402 if (!vreg || !vreg->enabled)
405 ret = regulator_disable(vreg->reg);
408 /* ignore errors on applying disable config */
409 ufs_qcom_phy_cfg_vreg(dev, vreg, false);
410 vreg->enabled = false;
412 dev_err(dev, "%s: %s disable failed, err=%d\n",
413 __func__, vreg->name, ret);
419 static void ufs_qcom_phy_disable_ref_clk(struct ufs_qcom_phy *phy)
421 if (phy->is_ref_clk_enabled) {
422 clk_disable_unprepare(phy->ref_clk);
424 * "ref_clk_parent" is optional clock hence make sure that clk
425 * reference is available before trying to disable the clock.
427 if (phy->ref_clk_parent)
428 clk_disable_unprepare(phy->ref_clk_parent);
429 clk_disable_unprepare(phy->ref_clk_src);
430 phy->is_ref_clk_enabled = false;
434 /* Turn ON M-PHY RMMI interface clocks */
435 static int ufs_qcom_phy_enable_iface_clk(struct ufs_qcom_phy *phy)
439 if (phy->is_iface_clk_enabled)
442 ret = clk_prepare_enable(phy->tx_iface_clk);
444 dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
448 ret = clk_prepare_enable(phy->rx_iface_clk);
450 clk_disable_unprepare(phy->tx_iface_clk);
451 dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
455 phy->is_iface_clk_enabled = true;
461 /* Turn OFF M-PHY RMMI interface clocks */
462 static void ufs_qcom_phy_disable_iface_clk(struct ufs_qcom_phy *phy)
464 if (phy->is_iface_clk_enabled) {
465 clk_disable_unprepare(phy->tx_iface_clk);
466 clk_disable_unprepare(phy->rx_iface_clk);
467 phy->is_iface_clk_enabled = false;
471 static int ufs_qcom_phy_start_serdes(struct ufs_qcom_phy *ufs_qcom_phy)
475 if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
476 dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
480 ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
486 int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
488 struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
491 if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
492 dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
496 ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
502 EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
504 void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
505 u8 major, u16 minor, u16 step)
507 struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
509 ufs_qcom_phy->host_ctrl_rev_major = major;
510 ufs_qcom_phy->host_ctrl_rev_minor = minor;
511 ufs_qcom_phy->host_ctrl_rev_step = step;
513 EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
515 static int ufs_qcom_phy_is_pcs_ready(struct ufs_qcom_phy *ufs_qcom_phy)
517 if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
518 dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
523 return ufs_qcom_phy->phy_spec_ops->
524 is_physical_coding_sublayer_ready(ufs_qcom_phy);
527 int ufs_qcom_phy_power_on(struct phy *generic_phy)
529 struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
530 struct device *dev = phy_common->dev;
533 if (phy_common->is_powered_on)
536 if (!phy_common->is_started) {
537 err = ufs_qcom_phy_start_serdes(phy_common);
541 err = ufs_qcom_phy_is_pcs_ready(phy_common);
545 phy_common->is_started = true;
548 err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_phy);
550 dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
555 phy_common->phy_spec_ops->power_control(phy_common, true);
557 /* vdda_pll also enables ref clock LDOs so enable it first */
558 err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_pll);
560 dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
562 goto out_disable_phy;
565 err = ufs_qcom_phy_enable_iface_clk(phy_common);
567 dev_err(dev, "%s enable phy iface clock failed, err=%d\n",
569 goto out_disable_pll;
572 err = ufs_qcom_phy_enable_ref_clk(phy_common);
574 dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
576 goto out_disable_iface_clk;
579 /* enable device PHY ref_clk pad rail */
580 if (phy_common->vddp_ref_clk.reg) {
581 err = ufs_qcom_phy_enable_vreg(dev,
582 &phy_common->vddp_ref_clk);
584 dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
586 goto out_disable_ref_clk;
590 phy_common->is_powered_on = true;
594 ufs_qcom_phy_disable_ref_clk(phy_common);
595 out_disable_iface_clk:
596 ufs_qcom_phy_disable_iface_clk(phy_common);
598 ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_pll);
600 ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_phy);
604 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on);
606 int ufs_qcom_phy_power_off(struct phy *generic_phy)
608 struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
610 if (!phy_common->is_powered_on)
613 phy_common->phy_spec_ops->power_control(phy_common, false);
615 if (phy_common->vddp_ref_clk.reg)
616 ufs_qcom_phy_disable_vreg(phy_common->dev,
617 &phy_common->vddp_ref_clk);
618 ufs_qcom_phy_disable_ref_clk(phy_common);
619 ufs_qcom_phy_disable_iface_clk(phy_common);
621 ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_pll);
622 ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_phy);
623 phy_common->is_powered_on = false;
627 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off);
629 MODULE_AUTHOR("Yaniv Gardi <ygardi@codeaurora.org>");
630 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
631 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY");
632 MODULE_LICENSE("GPL v2");