drivers/pci/pcie/aer/aerdrv.h

   1 /*
   2  * Copyright (C) 2006 Intel Corp.
   3  *      Tom Long Nguyen (tom.l.nguyen@intel.com)
   4  *      Zhang Yanmin (yanmin.zhang@intel.com)
   5  *
   6  */
   7
   8 #ifndef _AERDRV_H_
   9 #define _AERDRV_H_
  10
  11 #include <linux/workqueue.h>
  12 #include <linux/pcieport_if.h>
  13 #include <linux/aer.h>
  14
  15 #define AER_NONFATAL                    0
  16 #define AER_FATAL                       1
  17 #define AER_CORRECTABLE                 2
  18 #define AER_UNCORRECTABLE               4
  19 #define AER_ERROR_MASK                  0x001fffff
  20 #define AER_ERROR(d)                    (d & AER_ERROR_MASK)
  21
  22 /* Root Error Status Register Bits */
  23 #define ROOT_ERR_STATUS_MASKS                   0x0f
  24
  25 #define SYSTEM_ERROR_INTR_ON_MESG_MASK  (PCI_EXP_RTCTL_SECEE|   \
  26                                         PCI_EXP_RTCTL_SENFEE|   \
  27                                         PCI_EXP_RTCTL_SEFEE)
  28 #define ROOT_PORT_INTR_ON_MESG_MASK     (PCI_ERR_ROOT_CMD_COR_EN|       \
  29                                         PCI_ERR_ROOT_CMD_NONFATAL_EN|   \
  30                                         PCI_ERR_ROOT_CMD_FATAL_EN)
  31 #define ERR_COR_ID(d)                   (d & 0xffff)
  32 #define ERR_UNCOR_ID(d)                 (d >> 16)
  33
  34 #define AER_SUCCESS                     0
  35 #define AER_UNSUCCESS                   1
  36 #define AER_ERROR_SOURCES_MAX           100
  37
  38 #define AER_LOG_TLP_MASKS               (PCI_ERR_UNC_POISON_TLP|        \
  39                                         PCI_ERR_UNC_ECRC|               \
  40                                         PCI_ERR_UNC_UNSUP|              \
  41                                         PCI_ERR_UNC_COMP_ABORT|         \
  42                                         PCI_ERR_UNC_UNX_COMP|           \
  43                                         PCI_ERR_UNC_MALF_TLP)
  44
  45 /* AER Error Info Flags */
  46 #define AER_TLP_HEADER_VALID_FLAG       0x00000001
  47 #define AER_MULTI_ERROR_VALID_FLAG      0x00000002
  48
  49 #define ERR_CORRECTABLE_ERROR_MASK      0x000031c1
  50 #define ERR_UNCORRECTABLE_ERROR_MASK    0x001ff010
  51
  52 struct header_log_regs {
  53         unsigned int dw0;
  54         unsigned int dw1;
  55         unsigned int dw2;
  56         unsigned int dw3;
  57 };
  58
  59 struct aer_err_info {
  60         int severity;                   /* 0:NONFATAL | 1:FATAL | 2:COR */
  61         int flags;
  62         unsigned int status;            /* COR/UNCOR Error Status */
  63         struct header_log_regs tlp;     /* TLP Header */
  64 };
  65
  66 struct aer_err_source {
  67         unsigned int status;
  68         unsigned int id;
  69 };
  70
  71 struct aer_rpc {
  72         struct pcie_device *rpd;        /* Root Port device */
  73         struct work_struct dpc_handler;
  74         struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
  75         unsigned short prod_idx;        /* Error Producer Index */
  76         unsigned short cons_idx;        /* Error Consumer Index */
  77         int isr;
  78         spinlock_t e_lock;              /*
  79                                          * Lock access to Error Status/ID Regs
  80                                          * and error producer/consumer index
  81                                          */
  82         struct mutex rpc_mutex;         /*
  83                                          * only one thread could do
  84                                          * recovery on the same
  85                                          * root port hierarchy
  86                                          */
  87         wait_queue_head_t wait_release;
  88 };
  89
  90 struct aer_broadcast_data {
  91         enum pci_channel_state state;
  92         enum pci_ers_result result;
  93 };
  94
  95 static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
  96                 enum pci_ers_result new)
  97 {
  98         if (new == PCI_ERS_RESULT_NONE)
  99                 return orig;
 100
 101         switch (orig) {
 102         case PCI_ERS_RESULT_CAN_RECOVER:
 103         case PCI_ERS_RESULT_RECOVERED:
 104                 orig = new;
 105                 break;
 106         case PCI_ERS_RESULT_DISCONNECT:
 107                 if (new == PCI_ERS_RESULT_NEED_RESET)
 108                         orig = new;
 109                 break;
 110         default:
 111                 break;
 112         }
 113
 114         return orig;
 115 }
 116
 117 extern struct bus_type pcie_port_bus_type;
 118 extern void aer_enable_rootport(struct aer_rpc *rpc);
 119 extern void aer_delete_rootport(struct aer_rpc *rpc);
 120 extern int aer_init(struct pcie_device *dev);
 121 extern void aer_isr(struct work_struct *work);
 122 extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 123
 124 #ifdef CONFIG_ACPI
 125 extern int aer_osc_setup(struct pcie_device *pciedev);
 126 #else
 127 static inline int aer_osc_setup(struct pcie_device *pciedev)
 128 {
 129         return 0;
 130 }
 131 #endif
 132
 133 #endif //_AERDRV_H_