1 // SPDX-License-Identifier: GPL-2.0
3 * Synopsys DesignWare PCIe host controller driver
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Author: Jingoo Han <jg1.han@samsung.com>
11 #include <linux/delay.h>
13 #include <linux/types.h>
15 #include "pcie-designware.h"
17 /* PCIe Port Logic registers */
18 #define PLR_OFFSET 0x700
19 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
20 #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
21 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
23 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
25 if ((uintptr_t)addr & (size - 1)) {
27 return PCIBIOS_BAD_REGISTER_NUMBER;
32 } else if (size == 2) {
34 } else if (size == 1) {
38 return PCIBIOS_BAD_REGISTER_NUMBER;
41 return PCIBIOS_SUCCESSFUL;
44 int dw_pcie_write(void __iomem *addr, int size, u32 val)
46 if ((uintptr_t)addr & (size - 1))
47 return PCIBIOS_BAD_REGISTER_NUMBER;
56 return PCIBIOS_BAD_REGISTER_NUMBER;
58 return PCIBIOS_SUCCESSFUL;
61 u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
67 if (pci->ops->read_dbi)
68 return pci->ops->read_dbi(pci, base, reg, size);
70 ret = dw_pcie_read(base + reg, size, &val);
72 dev_err(pci->dev, "Read DBI address failed\n");
77 void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
82 if (pci->ops->write_dbi) {
83 pci->ops->write_dbi(pci, base, reg, size, val);
87 ret = dw_pcie_write(base + reg, size, val);
89 dev_err(pci->dev, "Write DBI address failed\n");
92 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
94 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
96 return dw_pcie_readl_dbi(pci, offset + reg);
99 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
102 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
104 dw_pcie_writel_dbi(pci, offset + reg, val);
107 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
108 int type, u64 cpu_addr,
109 u64 pci_addr, u32 size)
113 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
114 lower_32_bits(cpu_addr));
115 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
116 upper_32_bits(cpu_addr));
117 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
118 lower_32_bits(cpu_addr + size - 1));
119 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
120 lower_32_bits(pci_addr));
121 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
122 upper_32_bits(pci_addr));
123 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
125 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
129 * Make sure ATU enable takes effect before any subsequent config
132 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
133 val = dw_pcie_readl_ob_unroll(pci, index,
134 PCIE_ATU_UNR_REGION_CTRL2);
135 if (val & PCIE_ATU_ENABLE)
138 mdelay(LINK_WAIT_IATU);
140 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
143 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
144 u64 cpu_addr, u64 pci_addr, u32 size)
148 if (pci->ops->cpu_addr_fixup)
149 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
151 if (pci->iatu_unroll_enabled) {
152 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
157 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
158 PCIE_ATU_REGION_OUTBOUND | index);
159 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
160 lower_32_bits(cpu_addr));
161 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
162 upper_32_bits(cpu_addr));
163 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
164 lower_32_bits(cpu_addr + size - 1));
165 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
166 lower_32_bits(pci_addr));
167 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
168 upper_32_bits(pci_addr));
169 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
170 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
173 * Make sure ATU enable takes effect before any subsequent config
176 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
177 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
178 if (val & PCIE_ATU_ENABLE)
181 mdelay(LINK_WAIT_IATU);
183 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
186 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
188 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
190 return dw_pcie_readl_dbi(pci, offset + reg);
193 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
196 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
198 dw_pcie_writel_dbi(pci, offset + reg, val);
201 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
202 int bar, u64 cpu_addr,
203 enum dw_pcie_as_type as_type)
208 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
209 lower_32_bits(cpu_addr));
210 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
211 upper_32_bits(cpu_addr));
215 type = PCIE_ATU_TYPE_MEM;
218 type = PCIE_ATU_TYPE_IO;
224 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
225 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
227 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
230 * Make sure ATU enable takes effect before any subsequent config
233 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
234 val = dw_pcie_readl_ib_unroll(pci, index,
235 PCIE_ATU_UNR_REGION_CTRL2);
236 if (val & PCIE_ATU_ENABLE)
239 mdelay(LINK_WAIT_IATU);
241 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
246 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
247 u64 cpu_addr, enum dw_pcie_as_type as_type)
252 if (pci->iatu_unroll_enabled)
253 return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
256 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
258 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
259 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
263 type = PCIE_ATU_TYPE_MEM;
266 type = PCIE_ATU_TYPE_IO;
272 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
273 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
274 | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
277 * Make sure ATU enable takes effect before any subsequent config
280 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
281 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
282 if (val & PCIE_ATU_ENABLE)
285 mdelay(LINK_WAIT_IATU);
287 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
292 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
293 enum dw_pcie_region_type type)
298 case DW_PCIE_REGION_INBOUND:
299 region = PCIE_ATU_REGION_INBOUND;
301 case DW_PCIE_REGION_OUTBOUND:
302 region = PCIE_ATU_REGION_OUTBOUND;
308 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
309 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
312 int dw_pcie_wait_for_link(struct dw_pcie *pci)
316 /* Check if the link is up or not */
317 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
318 if (dw_pcie_link_up(pci)) {
319 dev_info(pci->dev, "Link up\n");
322 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
325 dev_err(pci->dev, "Phy link never came up\n");
330 int dw_pcie_link_up(struct dw_pcie *pci)
334 if (pci->ops->link_up)
335 return pci->ops->link_up(pci);
337 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
338 return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
339 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
342 void dw_pcie_setup(struct dw_pcie *pci)
347 struct device *dev = pci->dev;
348 struct device_node *np = dev->of_node;
350 ret = of_property_read_u32(np, "num-lanes", &lanes);
354 /* Set the number of lanes */
355 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
356 val &= ~PORT_LINK_MODE_MASK;
359 val |= PORT_LINK_MODE_1_LANES;
362 val |= PORT_LINK_MODE_2_LANES;
365 val |= PORT_LINK_MODE_4_LANES;
368 val |= PORT_LINK_MODE_8_LANES;
371 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
374 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
376 /* Set link width speed control register */
377 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
378 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
381 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
384 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
387 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
390 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
393 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);