drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmi.h>
  23 #include <linux/errno.h>
  24 #include <linux/fs.h>
  25 #include <linux/genhd.h>
  26 #include <linux/hdreg.h>
  27 #include <linux/idr.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kdev_t.h>
  32 #include <linux/kernel.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/mutex.h>
  37 #include <linux/pci.h>
  38 #include <linux/poison.h>
  39 #include <linux/ptrace.h>
  40 #include <linux/sched.h>
  41 #include <linux/slab.h>
  42 #include <linux/t10-pi.h>
  43 #include <linux/timer.h>
  44 #include <linux/types.h>
  45 #include <linux/io-64-nonatomic-lo-hi.h>
  46 #include <asm/unaligned.h>
  47 #include <linux/sed-opal.h>
  48
  49 #include "nvme.h"
  50
  51 #define NVME_Q_DEPTH            1024
  52 #define NVME_AQ_DEPTH           256
  53 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  54 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  55
  56 /*
  57  * We handle AEN commands ourselves and don't even let the
  58  * block layer know about them.
  59  */
  60 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  61
  62 static int use_threaded_interrupts;
  63 module_param(use_threaded_interrupts, int, 0);
  64
  65 static bool use_cmb_sqes = true;
  66 module_param(use_cmb_sqes, bool, 0644);
  67 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  68
  69 static struct workqueue_struct *nvme_workq;
  70
  71 struct nvme_dev;
  72 struct nvme_queue;
  73
  74 static int nvme_reset(struct nvme_dev *dev);
  75 static void nvme_process_cq(struct nvme_queue *nvmeq);
  76 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  77
  78 /*
  79  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  80  */
  81 struct nvme_dev {
  82         struct nvme_queue **queues;
  83         struct blk_mq_tag_set tagset;
  84         struct blk_mq_tag_set admin_tagset;
  85         u32 __iomem *dbs;
  86         struct device *dev;
  87         struct dma_pool *prp_page_pool;
  88         struct dma_pool *prp_small_pool;
  89         unsigned queue_count;
  90         unsigned online_queues;
  91         unsigned max_qid;
  92         int q_depth;
  93         u32 db_stride;
  94         void __iomem *bar;
  95         struct work_struct reset_work;
  96         struct work_struct remove_work;
  97         struct timer_list watchdog_timer;
  98         struct mutex shutdown_lock;
  99         bool subsystem;
 100         void __iomem *cmb;
 101         dma_addr_t cmb_dma_addr;
 102         u64 cmb_size;
 103         u32 cmbsz;
 104         u32 cmbloc;
 105         struct nvme_ctrl ctrl;
 106         struct completion ioq_wait;
 107 };
 108
 109 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 110 {
 111         return container_of(ctrl, struct nvme_dev, ctrl);
 112 }
 113
 114 /*
 115  * An NVM Express queue.  Each device has at least two (one for admin
 116  * commands and one for I/O commands).
 117  */
 118 struct nvme_queue {
 119         struct device *q_dmadev;
 120         struct nvme_dev *dev;
 121         char irqname[24];       /* nvme4294967295-65535\0 */
 122         spinlock_t q_lock;
 123         struct nvme_command *sq_cmds;
 124         struct nvme_command __iomem *sq_cmds_io;
 125         volatile struct nvme_completion *cqes;
 126         struct blk_mq_tags **tags;
 127         dma_addr_t sq_dma_addr;
 128         dma_addr_t cq_dma_addr;
 129         u32 __iomem *q_db;
 130         u16 q_depth;
 131         s16 cq_vector;
 132         u16 sq_tail;
 133         u16 cq_head;
 134         u16 qid;
 135         u8 cq_phase;
 136         u8 cqe_seen;
 137 };
 138
 139 /*
 140  * The nvme_iod describes the data in an I/O, including the list of PRP
 141  * entries.  You can't see it in this data structure because C doesn't let
 142  * me express that.  Use nvme_init_iod to ensure there's enough space
 143  * allocated to store the PRP list.
 144  */
 145 struct nvme_iod {
 146         struct nvme_request req;
 147         struct nvme_queue *nvmeq;
 148         int aborted;
 149         int npages;             /* In the PRP list. 0 means small pool in use */
 150         int nents;              /* Used in scatterlist */
 151         int length;             /* Of data, in bytes */
 152         dma_addr_t first_dma;
 153         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 154         struct scatterlist *sg;
 155         struct scatterlist inline_sg[0];
 156 };
 157
 158 /*
 159  * Check we didin't inadvertently grow the command struct
 160  */
 161 static inline void _nvme_check_size(void)
 162 {
 163         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 171         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 172         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 173         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 174         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 175 }
 176
 177 /*
 178  * Max size of iod being embedded in the request payload
 179  */
 180 #define NVME_INT_PAGES          2
 181 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 182
 183 /*
 184  * Will slightly overestimate the number of pages needed.  This is OK
 185  * as it only leads to a small amount of wasted memory for the lifetime of
 186  * the I/O.
 187  */
 188 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 189 {
 190         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 191                                       dev->ctrl.page_size);
 192         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 193 }
 194
 195 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 196                 unsigned int size, unsigned int nseg)
 197 {
 198         return sizeof(__le64 *) * nvme_npages(size, dev) +
 199                         sizeof(struct scatterlist) * nseg;
 200 }
 201
 202 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 203 {
 204         return sizeof(struct nvme_iod) +
 205                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 206 }
 207
 208 static int nvmeq_irq(struct nvme_queue *nvmeq)
 209 {
 210         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 211 }
 212
 213 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 214                                 unsigned int hctx_idx)
 215 {
 216         struct nvme_dev *dev = data;
 217         struct nvme_queue *nvmeq = dev->queues[0];
 218
 219         WARN_ON(hctx_idx != 0);
 220         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 221         WARN_ON(nvmeq->tags);
 222
 223         hctx->driver_data = nvmeq;
 224         nvmeq->tags = &dev->admin_tagset.tags[0];
 225         return 0;
 226 }
 227
 228 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 229 {
 230         struct nvme_queue *nvmeq = hctx->driver_data;
 231
 232         nvmeq->tags = NULL;
 233 }
 234
 235 static int nvme_admin_init_request(void *data, struct request *req,
 236                                 unsigned int hctx_idx, unsigned int rq_idx,
 237                                 unsigned int numa_node)
 238 {
 239         struct nvme_dev *dev = data;
 240         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 241         struct nvme_queue *nvmeq = dev->queues[0];
 242
 243         BUG_ON(!nvmeq);
 244         iod->nvmeq = nvmeq;
 245         return 0;
 246 }
 247
 248 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 249                           unsigned int hctx_idx)
 250 {
 251         struct nvme_dev *dev = data;
 252         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 253
 254         if (!nvmeq->tags)
 255                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 256
 257         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 258         hctx->driver_data = nvmeq;
 259         return 0;
 260 }
 261
 262 static int nvme_init_request(void *data, struct request *req,
 263                                 unsigned int hctx_idx, unsigned int rq_idx,
 264                                 unsigned int numa_node)
 265 {
 266         struct nvme_dev *dev = data;
 267         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 268         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 269
 270         BUG_ON(!nvmeq);
 271         iod->nvmeq = nvmeq;
 272         return 0;
 273 }
 274
 275 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 276 {
 277         struct nvme_dev *dev = set->driver_data;
 278
 279         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 280 }
 281
 282 /**
 283  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 284  * @nvmeq: The queue to use
 285  * @cmd: The command to send
 286  *
 287  * Safe to use from interrupt context
 288  */
 289 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 290                                                 struct nvme_command *cmd)
 291 {
 292         u16 tail = nvmeq->sq_tail;
 293
 294         if (nvmeq->sq_cmds_io)
 295                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 296         else
 297                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 298
 299         if (++tail == nvmeq->q_depth)
 300                 tail = 0;
 301         writel(tail, nvmeq->q_db);
 302         nvmeq->sq_tail = tail;
 303 }
 304
 305 static __le64 **iod_list(struct request *req)
 306 {
 307         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 308         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 309 }
 310
 311 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 312 {
 313         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 314         int nseg = blk_rq_nr_phys_segments(rq);
 315         unsigned int size = blk_rq_payload_bytes(rq);
 316
 317         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 318                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 319                 if (!iod->sg)
 320                         return BLK_MQ_RQ_QUEUE_BUSY;
 321         } else {
 322                 iod->sg = iod->inline_sg;
 323         }
 324
 325         iod->aborted = 0;
 326         iod->npages = -1;
 327         iod->nents = 0;
 328         iod->length = size;
 329
 330         if (!(rq->rq_flags & RQF_DONTPREP)) {
 331                 rq->retries = 0;
 332                 rq->rq_flags |= RQF_DONTPREP;
 333         }
 334         return BLK_MQ_RQ_QUEUE_OK;
 335 }
 336
 337 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 338 {
 339         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 340         const int last_prp = dev->ctrl.page_size / 8 - 1;
 341         int i;
 342         __le64 **list = iod_list(req);
 343         dma_addr_t prp_dma = iod->first_dma;
 344
 345         if (iod->npages == 0)
 346                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 347         for (i = 0; i < iod->npages; i++) {
 348                 __le64 *prp_list = list[i];
 349                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 350                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 351                 prp_dma = next_prp_dma;
 352         }
 353
 354         if (iod->sg != iod->inline_sg)
 355                 kfree(iod->sg);
 356 }
 357
 358 #ifdef CONFIG_BLK_DEV_INTEGRITY
 359 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 360 {
 361         if (be32_to_cpu(pi->ref_tag) == v)
 362                 pi->ref_tag = cpu_to_be32(p);
 363 }
 364
 365 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 366 {
 367         if (be32_to_cpu(pi->ref_tag) == p)
 368                 pi->ref_tag = cpu_to_be32(v);
 369 }
 370
 371 /**
 372  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 373  *
 374  * The virtual start sector is the one that was originally submitted by the
 375  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 376  * start sector may be different. Remap protection information to match the
 377  * physical LBA on writes, and back to the original seed on reads.
 378  *
 379  * Type 0 and 3 do not have a ref tag, so no remapping required.
 380  */
 381 static void nvme_dif_remap(struct request *req,
 382                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 383 {
 384         struct nvme_ns *ns = req->rq_disk->private_data;
 385         struct bio_integrity_payload *bip;
 386         struct t10_pi_tuple *pi;
 387         void *p, *pmap;
 388         u32 i, nlb, ts, phys, virt;
 389
 390         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 391                 return;
 392
 393         bip = bio_integrity(req->bio);
 394         if (!bip)
 395                 return;
 396
 397         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 398
 399         p = pmap;
 400         virt = bip_get_seed(bip);
 401         phys = nvme_block_nr(ns, blk_rq_pos(req));
 402         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 403         ts = ns->disk->queue->integrity.tuple_size;
 404
 405         for (i = 0; i < nlb; i++, virt++, phys++) {
 406                 pi = (struct t10_pi_tuple *)p;
 407                 dif_swap(phys, virt, pi);
 408                 p += ts;
 409         }
 410         kunmap_atomic(pmap);
 411 }
 412 #else /* CONFIG_BLK_DEV_INTEGRITY */
 413 static void nvme_dif_remap(struct request *req,
 414                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 415 {
 416 }
 417 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 418 {
 419 }
 420 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 421 {
 422 }
 423 #endif
 424
 425 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 426 {
 427         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 428         struct dma_pool *pool;
 429         int length = blk_rq_payload_bytes(req);
 430         struct scatterlist *sg = iod->sg;
 431         int dma_len = sg_dma_len(sg);
 432         u64 dma_addr = sg_dma_address(sg);
 433         u32 page_size = dev->ctrl.page_size;
 434         int offset = dma_addr & (page_size - 1);
 435         __le64 *prp_list;
 436         __le64 **list = iod_list(req);
 437         dma_addr_t prp_dma;
 438         int nprps, i;
 439
 440         length -= (page_size - offset);
 441         if (length <= 0)
 442                 return true;
 443
 444         dma_len -= (page_size - offset);
 445         if (dma_len) {
 446                 dma_addr += (page_size - offset);
 447         } else {
 448                 sg = sg_next(sg);
 449                 dma_addr = sg_dma_address(sg);
 450                 dma_len = sg_dma_len(sg);
 451         }
 452
 453         if (length <= page_size) {
 454                 iod->first_dma = dma_addr;
 455                 return true;
 456         }
 457
 458         nprps = DIV_ROUND_UP(length, page_size);
 459         if (nprps <= (256 / 8)) {
 460                 pool = dev->prp_small_pool;
 461                 iod->npages = 0;
 462         } else {
 463                 pool = dev->prp_page_pool;
 464                 iod->npages = 1;
 465         }
 466
 467         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 468         if (!prp_list) {
 469                 iod->first_dma = dma_addr;
 470                 iod->npages = -1;
 471                 return false;
 472         }
 473         list[0] = prp_list;
 474         iod->first_dma = prp_dma;
 475         i = 0;
 476         for (;;) {
 477                 if (i == page_size >> 3) {
 478                         __le64 *old_prp_list = prp_list;
 479                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 480                         if (!prp_list)
 481                                 return false;
 482                         list[iod->npages++] = prp_list;
 483                         prp_list[0] = old_prp_list[i - 1];
 484                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 485                         i = 1;
 486                 }
 487                 prp_list[i++] = cpu_to_le64(dma_addr);
 488                 dma_len -= page_size;
 489                 dma_addr += page_size;
 490                 length -= page_size;
 491                 if (length <= 0)
 492                         break;
 493                 if (dma_len > 0)
 494                         continue;
 495                 BUG_ON(dma_len < 0);
 496                 sg = sg_next(sg);
 497                 dma_addr = sg_dma_address(sg);
 498                 dma_len = sg_dma_len(sg);
 499         }
 500
 501         return true;
 502 }
 503
 504 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 505                 struct nvme_command *cmnd)
 506 {
 507         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 508         struct request_queue *q = req->q;
 509         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 510                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 511         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 512
 513         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 514         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 515         if (!iod->nents)
 516                 goto out;
 517
 518         ret = BLK_MQ_RQ_QUEUE_BUSY;
 519         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 520                                 DMA_ATTR_NO_WARN))
 521                 goto out;
 522
 523         if (!nvme_setup_prps(dev, req))
 524                 goto out_unmap;
 525
 526         ret = BLK_MQ_RQ_QUEUE_ERROR;
 527         if (blk_integrity_rq(req)) {
 528                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 529                         goto out_unmap;
 530
 531                 sg_init_table(&iod->meta_sg, 1);
 532                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 533                         goto out_unmap;
 534
 535                 if (rq_data_dir(req))
 536                         nvme_dif_remap(req, nvme_dif_prep);
 537
 538                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 539                         goto out_unmap;
 540         }
 541
 542         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 543         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 544         if (blk_integrity_rq(req))
 545                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 546         return BLK_MQ_RQ_QUEUE_OK;
 547
 548 out_unmap:
 549         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 550 out:
 551         return ret;
 552 }
 553
 554 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 555 {
 556         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 557         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 558                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 559
 560         if (iod->nents) {
 561                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 562                 if (blk_integrity_rq(req)) {
 563                         if (!rq_data_dir(req))
 564                                 nvme_dif_remap(req, nvme_dif_complete);
 565                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 566                 }
 567         }
 568
 569         nvme_cleanup_cmd(req);
 570         nvme_free_iod(dev, req);
 571 }
 572
 573 /*
 574  * NOTE: ns is NULL when called on the admin queue.
 575  */
 576 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 577                          const struct blk_mq_queue_data *bd)
 578 {
 579         struct nvme_ns *ns = hctx->queue->queuedata;
 580         struct nvme_queue *nvmeq = hctx->driver_data;
 581         struct nvme_dev *dev = nvmeq->dev;
 582         struct request *req = bd->rq;
 583         struct nvme_command cmnd;
 584         int ret = BLK_MQ_RQ_QUEUE_OK;
 585
 586         /*
 587          * If formated with metadata, require the block layer provide a buffer
 588          * unless this namespace is formated such that the metadata can be
 589          * stripped/generated by the controller with PRACT=1.
 590          */
 591         if (ns && ns->ms && !blk_integrity_rq(req)) {
 592                 if (!(ns->pi_type && ns->ms == 8) &&
 593                     !blk_rq_is_passthrough(req)) {
 594                         blk_mq_end_request(req, -EFAULT);
 595                         return BLK_MQ_RQ_QUEUE_OK;
 596                 }
 597         }
 598
 599         ret = nvme_setup_cmd(ns, req, &cmnd);
 600         if (ret != BLK_MQ_RQ_QUEUE_OK)
 601                 return ret;
 602
 603         ret = nvme_init_iod(req, dev);
 604         if (ret != BLK_MQ_RQ_QUEUE_OK)
 605                 goto out_free_cmd;
 606
 607         if (blk_rq_nr_phys_segments(req))
 608                 ret = nvme_map_data(dev, req, &cmnd);
 609
 610         if (ret != BLK_MQ_RQ_QUEUE_OK)
 611                 goto out_cleanup_iod;
 612
 613         blk_mq_start_request(req);
 614
 615         spin_lock_irq(&nvmeq->q_lock);
 616         if (unlikely(nvmeq->cq_vector < 0)) {
 617                 ret = BLK_MQ_RQ_QUEUE_ERROR;
 618                 spin_unlock_irq(&nvmeq->q_lock);
 619                 goto out_cleanup_iod;
 620         }
 621         __nvme_submit_cmd(nvmeq, &cmnd);
 622         nvme_process_cq(nvmeq);
 623         spin_unlock_irq(&nvmeq->q_lock);
 624         return BLK_MQ_RQ_QUEUE_OK;
 625 out_cleanup_iod:
 626         nvme_free_iod(dev, req);
 627 out_free_cmd:
 628         nvme_cleanup_cmd(req);
 629         return ret;
 630 }
 631
 632 static void nvme_complete_rq(struct request *req)
 633 {
 634         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 635         struct nvme_dev *dev = iod->nvmeq->dev;
 636         int error = 0;
 637
 638         nvme_unmap_data(dev, req);
 639
 640         if (unlikely(req->errors)) {
 641                 if (nvme_req_needs_retry(req, req->errors)) {
 642                         req->retries++;
 643                         nvme_requeue_req(req);
 644                         return;
 645                 }
 646
 647                 if (blk_rq_is_passthrough(req))
 648                         error = req->errors;
 649                 else
 650                         error = nvme_error_status(req->errors);
 651         }
 652
 653         if (unlikely(iod->aborted)) {
 654                 dev_warn(dev->ctrl.device,
 655                         "completing aborted command with status: %04x\n",
 656                         req->errors);
 657         }
 658
 659         blk_mq_end_request(req, error);
 660 }
 661
 662 /* We read the CQE phase first to check if the rest of the entry is valid */
 663 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 664                 u16 phase)
 665 {
 666         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 667 }
 668
 669 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 670 {
 671         u16 head, phase;
 672
 673         head = nvmeq->cq_head;
 674         phase = nvmeq->cq_phase;
 675
 676         while (nvme_cqe_valid(nvmeq, head, phase)) {
 677                 struct nvme_completion cqe = nvmeq->cqes[head];
 678                 struct request *req;
 679
 680                 if (++head == nvmeq->q_depth) {
 681                         head = 0;
 682                         phase = !phase;
 683                 }
 684
 685                 if (tag && *tag == cqe.command_id)
 686                         *tag = -1;
 687
 688                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 689                         dev_warn(nvmeq->dev->ctrl.device,
 690                                 "invalid id %d completed on queue %d\n",
 691                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 692                         continue;
 693                 }
 694
 695                 /*
 696                  * AEN requests are special as they don't time out and can
 697                  * survive any kind of queue freeze and often don't respond to
 698                  * aborts.  We don't even bother to allocate a struct request
 699                  * for them but rather special case them here.
 700                  */
 701                 if (unlikely(nvmeq->qid == 0 &&
 702                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 703                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 704                                         cqe.status, &cqe.result);
 705                         continue;
 706                 }
 707
 708                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 709                 nvme_req(req)->result = cqe.result;
 710                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 711         }
 712
 713         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 714                 return;
 715
 716         if (likely(nvmeq->cq_vector >= 0))
 717                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 718         nvmeq->cq_head = head;
 719         nvmeq->cq_phase = phase;
 720
 721         nvmeq->cqe_seen = 1;
 722 }
 723
 724 static void nvme_process_cq(struct nvme_queue *nvmeq)
 725 {
 726         __nvme_process_cq(nvmeq, NULL);
 727 }
 728
 729 static irqreturn_t nvme_irq(int irq, void *data)
 730 {
 731         irqreturn_t result;
 732         struct nvme_queue *nvmeq = data;
 733         spin_lock(&nvmeq->q_lock);
 734         nvme_process_cq(nvmeq);
 735         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 736         nvmeq->cqe_seen = 0;
 737         spin_unlock(&nvmeq->q_lock);
 738         return result;
 739 }
 740
 741 static irqreturn_t nvme_irq_check(int irq, void *data)
 742 {
 743         struct nvme_queue *nvmeq = data;
 744         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 745                 return IRQ_WAKE_THREAD;
 746         return IRQ_NONE;
 747 }
 748
 749 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 750 {
 751         struct nvme_queue *nvmeq = hctx->driver_data;
 752
 753         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 754                 spin_lock_irq(&nvmeq->q_lock);
 755                 __nvme_process_cq(nvmeq, &tag);
 756                 spin_unlock_irq(&nvmeq->q_lock);
 757
 758                 if (tag == -1)
 759                         return 1;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 766 {
 767         struct nvme_dev *dev = to_nvme_dev(ctrl);
 768         struct nvme_queue *nvmeq = dev->queues[0];
 769         struct nvme_command c;
 770
 771         memset(&c, 0, sizeof(c));
 772         c.common.opcode = nvme_admin_async_event;
 773         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 774
 775         spin_lock_irq(&nvmeq->q_lock);
 776         __nvme_submit_cmd(nvmeq, &c);
 777         spin_unlock_irq(&nvmeq->q_lock);
 778 }
 779
 780 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 781 {
 782         struct nvme_command c;
 783
 784         memset(&c, 0, sizeof(c));
 785         c.delete_queue.opcode = opcode;
 786         c.delete_queue.qid = cpu_to_le16(id);
 787
 788         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 789 }
 790
 791 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 792                                                 struct nvme_queue *nvmeq)
 793 {
 794         struct nvme_command c;
 795         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 796
 797         /*
 798          * Note: we (ab)use the fact the the prp fields survive if no data
 799          * is attached to the request.
 800          */
 801         memset(&c, 0, sizeof(c));
 802         c.create_cq.opcode = nvme_admin_create_cq;
 803         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 804         c.create_cq.cqid = cpu_to_le16(qid);
 805         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 806         c.create_cq.cq_flags = cpu_to_le16(flags);
 807         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 808
 809         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 810 }
 811
 812 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 813                                                 struct nvme_queue *nvmeq)
 814 {
 815         struct nvme_command c;
 816         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 817
 818         /*
 819          * Note: we (ab)use the fact the the prp fields survive if no data
 820          * is attached to the request.
 821          */
 822         memset(&c, 0, sizeof(c));
 823         c.create_sq.opcode = nvme_admin_create_sq;
 824         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 825         c.create_sq.sqid = cpu_to_le16(qid);
 826         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 827         c.create_sq.sq_flags = cpu_to_le16(flags);
 828         c.create_sq.cqid = cpu_to_le16(qid);
 829
 830         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 831 }
 832
 833 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 834 {
 835         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 836 }
 837
 838 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 839 {
 840         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 841 }
 842
 843 static void abort_endio(struct request *req, int error)
 844 {
 845         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 846         struct nvme_queue *nvmeq = iod->nvmeq;
 847         u16 status = req->errors;
 848
 849         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 850         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 851         blk_mq_free_request(req);
 852 }
 853
 854 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 855 {
 856         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 857         struct nvme_queue *nvmeq = iod->nvmeq;
 858         struct nvme_dev *dev = nvmeq->dev;
 859         struct request *abort_req;
 860         struct nvme_command cmd;
 861
 862         /*
 863          * Shutdown immediately if controller times out while starting. The
 864          * reset work will see the pci device disabled when it gets the forced
 865          * cancellation error. All outstanding requests are completed on
 866          * shutdown, so we return BLK_EH_HANDLED.
 867          */
 868         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 869                 dev_warn(dev->ctrl.device,
 870                          "I/O %d QID %d timeout, disable controller\n",
 871                          req->tag, nvmeq->qid);
 872                 nvme_dev_disable(dev, false);
 873                 req->errors = NVME_SC_CANCELLED;
 874                 return BLK_EH_HANDLED;
 875         }
 876
 877         /*
 878          * Shutdown the controller immediately and schedule a reset if the
 879          * command was already aborted once before and still hasn't been
 880          * returned to the driver, or if this is the admin queue.
 881          */
 882         if (!nvmeq->qid || iod->aborted) {
 883                 dev_warn(dev->ctrl.device,
 884                          "I/O %d QID %d timeout, reset controller\n",
 885                          req->tag, nvmeq->qid);
 886                 nvme_dev_disable(dev, false);
 887                 nvme_reset(dev);
 888
 889                 /*
 890                  * Mark the request as handled, since the inline shutdown
 891                  * forces all outstanding requests to complete.
 892                  */
 893                 req->errors = NVME_SC_CANCELLED;
 894                 return BLK_EH_HANDLED;
 895         }
 896
 897         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 898                 atomic_inc(&dev->ctrl.abort_limit);
 899                 return BLK_EH_RESET_TIMER;
 900         }
 901         iod->aborted = 1;
 902
 903         memset(&cmd, 0, sizeof(cmd));
 904         cmd.abort.opcode = nvme_admin_abort_cmd;
 905         cmd.abort.cid = req->tag;
 906         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 907
 908         dev_warn(nvmeq->dev->ctrl.device,
 909                 "I/O %d QID %d timeout, aborting\n",
 910                  req->tag, nvmeq->qid);
 911
 912         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 913                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 914         if (IS_ERR(abort_req)) {
 915                 atomic_inc(&dev->ctrl.abort_limit);
 916                 return BLK_EH_RESET_TIMER;
 917         }
 918
 919         abort_req->timeout = ADMIN_TIMEOUT;
 920         abort_req->end_io_data = NULL;
 921         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 922
 923         /*
 924          * The aborted req will be completed on receiving the abort req.
 925          * We enable the timer again. If hit twice, it'll cause a device reset,
 926          * as the device then is in a faulty state.
 927          */
 928         return BLK_EH_RESET_TIMER;
 929 }
 930
 931 static void nvme_free_queue(struct nvme_queue *nvmeq)
 932 {
 933         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 934                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 935         if (nvmeq->sq_cmds)
 936                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 937                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 938         kfree(nvmeq);
 939 }
 940
 941 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 942 {
 943         int i;
 944
 945         for (i = dev->queue_count - 1; i >= lowest; i--) {
 946                 struct nvme_queue *nvmeq = dev->queues[i];
 947                 dev->queue_count--;
 948                 dev->queues[i] = NULL;
 949                 nvme_free_queue(nvmeq);
 950         }
 951 }
 952
 953 /**
 954  * nvme_suspend_queue - put queue into suspended state
 955  * @nvmeq - queue to suspend
 956  */
 957 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 958 {
 959         int vector;
 960
 961         spin_lock_irq(&nvmeq->q_lock);
 962         if (nvmeq->cq_vector == -1) {
 963                 spin_unlock_irq(&nvmeq->q_lock);
 964                 return 1;
 965         }
 966         vector = nvmeq_irq(nvmeq);
 967         nvmeq->dev->online_queues--;
 968         nvmeq->cq_vector = -1;
 969         spin_unlock_irq(&nvmeq->q_lock);
 970
 971         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 972                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 973
 974         free_irq(vector, nvmeq);
 975
 976         return 0;
 977 }
 978
 979 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 980 {
 981         struct nvme_queue *nvmeq = dev->queues[0];
 982
 983         if (!nvmeq)
 984                 return;
 985         if (nvme_suspend_queue(nvmeq))
 986                 return;
 987
 988         if (shutdown)
 989                 nvme_shutdown_ctrl(&dev->ctrl);
 990         else
 991                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 992                                                 dev->bar + NVME_REG_CAP));
 993
 994         spin_lock_irq(&nvmeq->q_lock);
 995         nvme_process_cq(nvmeq);
 996         spin_unlock_irq(&nvmeq->q_lock);
 997 }
 998
 999 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1000                                 int entry_size)
1001 {
1002         int q_depth = dev->q_depth;
1003         unsigned q_size_aligned = roundup(q_depth * entry_size,
1004                                           dev->ctrl.page_size);
1005
1006         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1007                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1008                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1009                 q_depth = div_u64(mem_per_q, entry_size);
1010
1011                 /*
1012                  * Ensure the reduced q_depth is above some threshold where it
1013                  * would be better to map queues in system memory with the
1014                  * original depth
1015                  */
1016                 if (q_depth < 64)
1017                         return -ENOMEM;
1018         }
1019
1020         return q_depth;
1021 }
1022
1023 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1024                                 int qid, int depth)
1025 {
1026         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1027                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1028                                                       dev->ctrl.page_size);
1029                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1030                 nvmeq->sq_cmds_io = dev->cmb + offset;
1031         } else {
1032                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1033                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1034                 if (!nvmeq->sq_cmds)
1035                         return -ENOMEM;
1036         }
1037
1038         return 0;
1039 }
1040
1041 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1042                                                         int depth, int node)
1043 {
1044         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1045                                                         node);
1046         if (!nvmeq)
1047                 return NULL;
1048
1049         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1050                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1051         if (!nvmeq->cqes)
1052                 goto free_nvmeq;
1053
1054         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1055                 goto free_cqdma;
1056
1057         nvmeq->q_dmadev = dev->dev;
1058         nvmeq->dev = dev;
1059         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1060                         dev->ctrl.instance, qid);
1061         spin_lock_init(&nvmeq->q_lock);
1062         nvmeq->cq_head = 0;
1063         nvmeq->cq_phase = 1;
1064         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1065         nvmeq->q_depth = depth;
1066         nvmeq->qid = qid;
1067         nvmeq->cq_vector = -1;
1068         dev->queues[qid] = nvmeq;
1069         dev->queue_count++;
1070
1071         return nvmeq;
1072
1073  free_cqdma:
1074         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1075                                                         nvmeq->cq_dma_addr);
1076  free_nvmeq:
1077         kfree(nvmeq);
1078         return NULL;
1079 }
1080
1081 static int queue_request_irq(struct nvme_queue *nvmeq)
1082 {
1083         if (use_threaded_interrupts)
1084                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1085                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1086         else
1087                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1088                                 nvmeq->irqname, nvmeq);
1089 }
1090
1091 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1092 {
1093         struct nvme_dev *dev = nvmeq->dev;
1094
1095         spin_lock_irq(&nvmeq->q_lock);
1096         nvmeq->sq_tail = 0;
1097         nvmeq->cq_head = 0;
1098         nvmeq->cq_phase = 1;
1099         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1100         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1101         dev->online_queues++;
1102         spin_unlock_irq(&nvmeq->q_lock);
1103 }
1104
1105 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1106 {
1107         struct nvme_dev *dev = nvmeq->dev;
1108         int result;
1109
1110         nvmeq->cq_vector = qid - 1;
1111         result = adapter_alloc_cq(dev, qid, nvmeq);
1112         if (result < 0)
1113                 return result;
1114
1115         result = adapter_alloc_sq(dev, qid, nvmeq);
1116         if (result < 0)
1117                 goto release_cq;
1118
1119         result = queue_request_irq(nvmeq);
1120         if (result < 0)
1121                 goto release_sq;
1122
1123         nvme_init_queue(nvmeq, qid);
1124         return result;
1125
1126  release_sq:
1127         adapter_delete_sq(dev, qid);
1128  release_cq:
1129         adapter_delete_cq(dev, qid);
1130         return result;
1131 }
1132
1133 static struct blk_mq_ops nvme_mq_admin_ops = {
1134         .queue_rq       = nvme_queue_rq,
1135         .complete       = nvme_complete_rq,
1136         .init_hctx      = nvme_admin_init_hctx,
1137         .exit_hctx      = nvme_admin_exit_hctx,
1138         .init_request   = nvme_admin_init_request,
1139         .timeout        = nvme_timeout,
1140 };
1141
1142 static struct blk_mq_ops nvme_mq_ops = {
1143         .queue_rq       = nvme_queue_rq,
1144         .complete       = nvme_complete_rq,
1145         .init_hctx      = nvme_init_hctx,
1146         .init_request   = nvme_init_request,
1147         .map_queues     = nvme_pci_map_queues,
1148         .timeout        = nvme_timeout,
1149         .poll           = nvme_poll,
1150 };
1151
1152 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1153 {
1154         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1155                 /*
1156                  * If the controller was reset during removal, it's possible
1157                  * user requests may be waiting on a stopped queue. Start the
1158                  * queue to flush these to completion.
1159                  */
1160                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1161                 blk_cleanup_queue(dev->ctrl.admin_q);
1162                 blk_mq_free_tag_set(&dev->admin_tagset);
1163         }
1164 }
1165
1166 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1167 {
1168         if (!dev->ctrl.admin_q) {
1169                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1170                 dev->admin_tagset.nr_hw_queues = 1;
1171
1172                 /*
1173                  * Subtract one to leave an empty queue entry for 'Full Queue'
1174                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1175                  */
1176                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1177                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1178                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1179                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1180                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1181                 dev->admin_tagset.driver_data = dev;
1182
1183                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1184                         return -ENOMEM;
1185
1186                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1187                 if (IS_ERR(dev->ctrl.admin_q)) {
1188                         blk_mq_free_tag_set(&dev->admin_tagset);
1189                         return -ENOMEM;
1190                 }
1191                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1192                         nvme_dev_remove_admin(dev);
1193                         dev->ctrl.admin_q = NULL;
1194                         return -ENODEV;
1195                 }
1196         } else
1197                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1198
1199         return 0;
1200 }
1201
1202 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1203 {
1204         int result;
1205         u32 aqa;
1206         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1207         struct nvme_queue *nvmeq;
1208
1209         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1210                                                 NVME_CAP_NSSRC(cap) : 0;
1211
1212         if (dev->subsystem &&
1213             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1214                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1215
1216         result = nvme_disable_ctrl(&dev->ctrl, cap);
1217         if (result < 0)
1218                 return result;
1219
1220         nvmeq = dev->queues[0];
1221         if (!nvmeq) {
1222                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1223                                         dev_to_node(dev->dev));
1224                 if (!nvmeq)
1225                         return -ENOMEM;
1226         }
1227
1228         aqa = nvmeq->q_depth - 1;
1229         aqa |= aqa << 16;
1230
1231         writel(aqa, dev->bar + NVME_REG_AQA);
1232         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1233         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1234
1235         result = nvme_enable_ctrl(&dev->ctrl, cap);
1236         if (result)
1237                 return result;
1238
1239         nvmeq->cq_vector = 0;
1240         result = queue_request_irq(nvmeq);
1241         if (result) {
1242                 nvmeq->cq_vector = -1;
1243                 return result;
1244         }
1245
1246         return result;
1247 }
1248
1249 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1250 {
1251
1252         /* If true, indicates loss of adapter communication, possibly by a
1253          * NVMe Subsystem reset.
1254          */
1255         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1256
1257         /* If there is a reset ongoing, we shouldn't reset again. */
1258         if (work_busy(&dev->reset_work))
1259                 return false;
1260
1261         /* We shouldn't reset unless the controller is on fatal error state
1262          * _or_ if we lost the communication with it.
1263          */
1264         if (!(csts & NVME_CSTS_CFS) && !nssro)
1265                 return false;
1266
1267         /* If PCI error recovery process is happening, we cannot reset or
1268          * the recovery mechanism will surely fail.
1269          */
1270         if (pci_channel_offline(to_pci_dev(dev->dev)))
1271                 return false;
1272
1273         return true;
1274 }
1275
1276 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1277 {
1278         /* Read a config register to help see what died. */
1279         u16 pci_status;
1280         int result;
1281
1282         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1283                                       &pci_status);
1284         if (result == PCIBIOS_SUCCESSFUL)
1285                 dev_warn(dev->dev,
1286                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1287                          csts, pci_status);
1288         else
1289                 dev_warn(dev->dev,
1290                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1291                          csts, result);
1292 }
1293
1294 static void nvme_watchdog_timer(unsigned long data)
1295 {
1296         struct nvme_dev *dev = (struct nvme_dev *)data;
1297         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1298
1299         /* Skip controllers under certain specific conditions. */
1300         if (nvme_should_reset(dev, csts)) {
1301                 if (!nvme_reset(dev))
1302                         nvme_warn_reset(dev, csts);
1303                 return;
1304         }
1305
1306         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1307 }
1308
1309 static int nvme_create_io_queues(struct nvme_dev *dev)
1310 {
1311         unsigned i, max;
1312         int ret = 0;
1313
1314         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1315                 /* vector == qid - 1, match nvme_create_queue */
1316                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1317                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1318                         ret = -ENOMEM;
1319                         break;
1320                 }
1321         }
1322
1323         max = min(dev->max_qid, dev->queue_count - 1);
1324         for (i = dev->online_queues; i <= max; i++) {
1325                 ret = nvme_create_queue(dev->queues[i], i);
1326                 if (ret)
1327                         break;
1328         }
1329
1330         /*
1331          * Ignore failing Create SQ/CQ commands, we can continue with less
1332          * than the desired aount of queues, and even a controller without
1333          * I/O queues an still be used to issue admin commands.  This might
1334          * be useful to upgrade a buggy firmware for example.
1335          */
1336         return ret >= 0 ? 0 : ret;
1337 }
1338
1339 static ssize_t nvme_cmb_show(struct device *dev,
1340                              struct device_attribute *attr,
1341                              char *buf)
1342 {
1343         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1344
1345         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1346                        ndev->cmbloc, ndev->cmbsz);
1347 }
1348 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1349
1350 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1351 {
1352         u64 szu, size, offset;
1353         resource_size_t bar_size;
1354         struct pci_dev *pdev = to_pci_dev(dev->dev);
1355         void __iomem *cmb;
1356         dma_addr_t dma_addr;
1357
1358         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1359         if (!(NVME_CMB_SZ(dev->cmbsz)))
1360                 return NULL;
1361         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1362
1363         if (!use_cmb_sqes)
1364                 return NULL;
1365
1366         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1367         size = szu * NVME_CMB_SZ(dev->cmbsz);
1368         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1369         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1370
1371         if (offset > bar_size)
1372                 return NULL;
1373
1374         /*
1375          * Controllers may support a CMB size larger than their BAR,
1376          * for example, due to being behind a bridge. Reduce the CMB to
1377          * the reported size of the BAR
1378          */
1379         if (size > bar_size - offset)
1380                 size = bar_size - offset;
1381
1382         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1383         cmb = ioremap_wc(dma_addr, size);
1384         if (!cmb)
1385                 return NULL;
1386
1387         dev->cmb_dma_addr = dma_addr;
1388         dev->cmb_size = size;
1389         return cmb;
1390 }
1391
1392 static inline void nvme_release_cmb(struct nvme_dev *dev)
1393 {
1394         if (dev->cmb) {
1395                 iounmap(dev->cmb);
1396                 dev->cmb = NULL;
1397         }
1398 }
1399
1400 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1401 {
1402         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1403 }
1404
1405 static int nvme_setup_io_queues(struct nvme_dev *dev)
1406 {
1407         struct nvme_queue *adminq = dev->queues[0];
1408         struct pci_dev *pdev = to_pci_dev(dev->dev);
1409         int result, nr_io_queues, size;
1410
1411         nr_io_queues = num_online_cpus();
1412         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1413         if (result < 0)
1414                 return result;
1415
1416         if (nr_io_queues == 0)
1417                 return 0;
1418
1419         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1420                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1421                                 sizeof(struct nvme_command));
1422                 if (result > 0)
1423                         dev->q_depth = result;
1424                 else
1425                         nvme_release_cmb(dev);
1426         }
1427
1428         size = db_bar_size(dev, nr_io_queues);
1429         if (size > 8192) {
1430                 iounmap(dev->bar);
1431                 do {
1432                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1433                         if (dev->bar)
1434                                 break;
1435                         if (!--nr_io_queues)
1436                                 return -ENOMEM;
1437                         size = db_bar_size(dev, nr_io_queues);
1438                 } while (1);
1439                 dev->dbs = dev->bar + 4096;
1440                 adminq->q_db = dev->dbs;
1441         }
1442
1443         /* Deregister the admin queue's interrupt */
1444         free_irq(pci_irq_vector(pdev, 0), adminq);
1445
1446         /*
1447          * If we enable msix early due to not intx, disable it again before
1448          * setting up the full range we need.
1449          */
1450         pci_free_irq_vectors(pdev);
1451         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1452                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1453         if (nr_io_queues <= 0)
1454                 return -EIO;
1455         dev->max_qid = nr_io_queues;
1456
1457         /*
1458          * Should investigate if there's a performance win from allocating
1459          * more queues than interrupt vectors; it might allow the submission
1460          * path to scale better, even if the receive path is limited by the
1461          * number of interrupts.
1462          */
1463
1464         result = queue_request_irq(adminq);
1465         if (result) {
1466                 adminq->cq_vector = -1;
1467                 return result;
1468         }
1469         return nvme_create_io_queues(dev);
1470 }
1471
1472 static void nvme_del_queue_end(struct request *req, int error)
1473 {
1474         struct nvme_queue *nvmeq = req->end_io_data;
1475
1476         blk_mq_free_request(req);
1477         complete(&nvmeq->dev->ioq_wait);
1478 }
1479
1480 static void nvme_del_cq_end(struct request *req, int error)
1481 {
1482         struct nvme_queue *nvmeq = req->end_io_data;
1483
1484         if (!error) {
1485                 unsigned long flags;
1486
1487                 /*
1488                  * We might be called with the AQ q_lock held
1489                  * and the I/O queue q_lock should always
1490                  * nest inside the AQ one.
1491                  */
1492                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1493                                         SINGLE_DEPTH_NESTING);
1494                 nvme_process_cq(nvmeq);
1495                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1496         }
1497
1498         nvme_del_queue_end(req, error);
1499 }
1500
1501 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1502 {
1503         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1504         struct request *req;
1505         struct nvme_command cmd;
1506
1507         memset(&cmd, 0, sizeof(cmd));
1508         cmd.delete_queue.opcode = opcode;
1509         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1510
1511         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1512         if (IS_ERR(req))
1513                 return PTR_ERR(req);
1514
1515         req->timeout = ADMIN_TIMEOUT;
1516         req->end_io_data = nvmeq;
1517
1518         blk_execute_rq_nowait(q, NULL, req, false,
1519                         opcode == nvme_admin_delete_cq ?
1520                                 nvme_del_cq_end : nvme_del_queue_end);
1521         return 0;
1522 }
1523
1524 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1525 {
1526         int pass;
1527         unsigned long timeout;
1528         u8 opcode = nvme_admin_delete_sq;
1529
1530         for (pass = 0; pass < 2; pass++) {
1531                 int sent = 0, i = queues;
1532
1533                 reinit_completion(&dev->ioq_wait);
1534  retry:
1535                 timeout = ADMIN_TIMEOUT;
1536                 for (; i > 0; i--, sent++)
1537                         if (nvme_delete_queue(dev->queues[i], opcode))
1538                                 break;
1539
1540                 while (sent--) {
1541                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1542                         if (timeout == 0)
1543                                 return;
1544                         if (i)
1545                                 goto retry;
1546                 }
1547                 opcode = nvme_admin_delete_cq;
1548         }
1549 }
1550
1551 /*
1552  * Return: error value if an error occurred setting up the queues or calling
1553  * Identify Device.  0 if these succeeded, even if adding some of the
1554  * namespaces failed.  At the moment, these failures are silent.  TBD which
1555  * failures should be reported.
1556  */
1557 static int nvme_dev_add(struct nvme_dev *dev)
1558 {
1559         if (!dev->ctrl.tagset) {
1560                 dev->tagset.ops = &nvme_mq_ops;
1561                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1562                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1563                 dev->tagset.numa_node = dev_to_node(dev->dev);
1564                 dev->tagset.queue_depth =
1565                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1566                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1567                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1568                 dev->tagset.driver_data = dev;
1569
1570                 if (blk_mq_alloc_tag_set(&dev->tagset))
1571                         return 0;
1572                 dev->ctrl.tagset = &dev->tagset;
1573         } else {
1574                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1575
1576                 /* Free previously allocated queues that are no longer usable */
1577                 nvme_free_queues(dev, dev->online_queues);
1578         }
1579
1580         return 0;
1581 }
1582
1583 static int nvme_pci_enable(struct nvme_dev *dev)
1584 {
1585         u64 cap;
1586         int result = -ENOMEM;
1587         struct pci_dev *pdev = to_pci_dev(dev->dev);
1588
1589         if (pci_enable_device_mem(pdev))
1590                 return result;
1591
1592         pci_set_master(pdev);
1593
1594         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1595             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1596                 goto disable;
1597
1598         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1599                 result = -ENODEV;
1600                 goto disable;
1601         }
1602
1603         /*
1604          * Some devices and/or platforms don't advertise or work with INTx
1605          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1606          * adjust this later.
1607          */
1608         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1609         if (result < 0)
1610                 return result;
1611
1612         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1613
1614         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1615         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1616         dev->dbs = dev->bar + 4096;
1617
1618         /*
1619          * Temporary fix for the Apple controller found in the MacBook8,1 and
1620          * some MacBook7,1 to avoid controller resets and data loss.
1621          */
1622         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1623                 dev->q_depth = 2;
1624                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1625                         "queue depth=%u to work around controller resets\n",
1626                         dev->q_depth);
1627         }
1628
1629         /*
1630          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1631          * populate sysfs if a CMB is implemented. Note that we add the
1632          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1633          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1634          * NULL as final argument to sysfs_add_file_to_group.
1635          */
1636
1637         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1638                 dev->cmb = nvme_map_cmb(dev);
1639
1640                 if (dev->cmbsz) {
1641                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1642                                                     &dev_attr_cmb.attr, NULL))
1643                                 dev_warn(dev->dev,
1644                                          "failed to add sysfs attribute for CMB\n");
1645                 }
1646         }
1647
1648         pci_enable_pcie_error_reporting(pdev);
1649         pci_save_state(pdev);
1650         return 0;
1651
1652  disable:
1653         pci_disable_device(pdev);
1654         return result;
1655 }
1656
1657 static void nvme_dev_unmap(struct nvme_dev *dev)
1658 {
1659         if (dev->bar)
1660                 iounmap(dev->bar);
1661         pci_release_mem_regions(to_pci_dev(dev->dev));
1662 }
1663
1664 static void nvme_pci_disable(struct nvme_dev *dev)
1665 {
1666         struct pci_dev *pdev = to_pci_dev(dev->dev);
1667
1668         pci_free_irq_vectors(pdev);
1669
1670         if (pci_is_enabled(pdev)) {
1671                 pci_disable_pcie_error_reporting(pdev);
1672                 pci_disable_device(pdev);
1673         }
1674 }
1675
1676 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1677 {
1678         int i, queues;
1679         bool dead = true;
1680         struct pci_dev *pdev = to_pci_dev(dev->dev);
1681
1682         del_timer_sync(&dev->watchdog_timer);
1683
1684         mutex_lock(&dev->shutdown_lock);
1685         if (pci_is_enabled(pdev)) {
1686                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1687
1688                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1689                         nvme_start_freeze(&dev->ctrl);
1690                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1691                         pdev->error_state  != pci_channel_io_normal);
1692         }
1693
1694         /*
1695          * Give the controller a chance to complete all entered requests if
1696          * doing a safe shutdown.
1697          */
1698         if (!dead && shutdown)
1699                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1700         nvme_stop_queues(&dev->ctrl);
1701
1702         queues = dev->online_queues - 1;
1703         for (i = dev->queue_count - 1; i > 0; i--)
1704                 nvme_suspend_queue(dev->queues[i]);
1705
1706         if (dead) {
1707                 /* A device might become IO incapable very soon during
1708                  * probe, before the admin queue is configured. Thus,
1709                  * queue_count can be 0 here.
1710                  */
1711                 if (dev->queue_count)
1712                         nvme_suspend_queue(dev->queues[0]);
1713         } else {
1714                 nvme_disable_io_queues(dev, queues);
1715                 nvme_disable_admin_queue(dev, shutdown);
1716         }
1717         nvme_pci_disable(dev);
1718
1719         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1720         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1721
1722         /*
1723          * The driver will not be starting up queues again if shutting down so
1724          * must flush all entered requests to their failed completion to avoid
1725          * deadlocking blk-mq hot-cpu notifier.
1726          */
1727         if (shutdown)
1728                 nvme_start_queues(&dev->ctrl);
1729         mutex_unlock(&dev->shutdown_lock);
1730 }
1731
1732 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1733 {
1734         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1735                                                 PAGE_SIZE, PAGE_SIZE, 0);
1736         if (!dev->prp_page_pool)
1737                 return -ENOMEM;
1738
1739         /* Optimisation for I/Os between 4k and 128k */
1740         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1741                                                 256, 256, 0);
1742         if (!dev->prp_small_pool) {
1743                 dma_pool_destroy(dev->prp_page_pool);
1744                 return -ENOMEM;
1745         }
1746         return 0;
1747 }
1748
1749 static void nvme_release_prp_pools(struct nvme_dev *dev)
1750 {
1751         dma_pool_destroy(dev->prp_page_pool);
1752         dma_pool_destroy(dev->prp_small_pool);
1753 }
1754
1755 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1756 {
1757         struct nvme_dev *dev = to_nvme_dev(ctrl);
1758
1759         put_device(dev->dev);
1760         if (dev->tagset.tags)
1761                 blk_mq_free_tag_set(&dev->tagset);
1762         if (dev->ctrl.admin_q)
1763                 blk_put_queue(dev->ctrl.admin_q);
1764         kfree(dev->queues);
1765         free_opal_dev(dev->ctrl.opal_dev);
1766         kfree(dev);
1767 }
1768
1769 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1770 {
1771         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1772
1773         kref_get(&dev->ctrl.kref);
1774         nvme_dev_disable(dev, false);
1775         if (!schedule_work(&dev->remove_work))
1776                 nvme_put_ctrl(&dev->ctrl);
1777 }
1778
1779 static void nvme_reset_work(struct work_struct *work)
1780 {
1781         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1782         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
1783         int result = -ENODEV;
1784
1785         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1786                 goto out;
1787
1788         /*
1789          * If we're called to reset a live controller first shut it down before
1790          * moving on.
1791          */
1792         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1793                 nvme_dev_disable(dev, false);
1794
1795         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1796                 goto out;
1797
1798         result = nvme_pci_enable(dev);
1799         if (result)
1800                 goto out;
1801
1802         result = nvme_configure_admin_queue(dev);
1803         if (result)
1804                 goto out;
1805
1806         nvme_init_queue(dev->queues[0], 0);
1807         result = nvme_alloc_admin_tags(dev);
1808         if (result)
1809                 goto out;
1810
1811         result = nvme_init_identify(&dev->ctrl);
1812         if (result)
1813                 goto out;
1814
1815         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
1816                 if (!dev->ctrl.opal_dev)
1817                         dev->ctrl.opal_dev =
1818                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
1819                 else if (was_suspend)
1820                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
1821         } else {
1822                 free_opal_dev(dev->ctrl.opal_dev);
1823                 dev->ctrl.opal_dev = NULL;
1824         }
1825
1826         result = nvme_setup_io_queues(dev);
1827         if (result)
1828                 goto out;
1829
1830         /*
1831          * A controller that can not execute IO typically requires user
1832          * intervention to correct. For such degraded controllers, the driver
1833          * should not submit commands the user did not request, so skip
1834          * registering for asynchronous event notification on this condition.
1835          */
1836         if (dev->online_queues > 1)
1837                 nvme_queue_async_events(&dev->ctrl);
1838
1839         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1840
1841         /*
1842          * Keep the controller around but remove all namespaces if we don't have
1843          * any working I/O queue.
1844          */
1845         if (dev->online_queues < 2) {
1846                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1847                 nvme_kill_queues(&dev->ctrl);
1848                 nvme_remove_namespaces(&dev->ctrl);
1849         } else {
1850                 nvme_start_queues(&dev->ctrl);
1851                 nvme_wait_freeze(&dev->ctrl);
1852                 nvme_dev_add(dev);
1853                 nvme_unfreeze(&dev->ctrl);
1854         }
1855
1856         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1857                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1858                 goto out;
1859         }
1860
1861         if (dev->online_queues > 1)
1862                 nvme_queue_scan(&dev->ctrl);
1863         return;
1864
1865  out:
1866         nvme_remove_dead_ctrl(dev, result);
1867 }
1868
1869 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1870 {
1871         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1872         struct pci_dev *pdev = to_pci_dev(dev->dev);
1873
1874         nvme_kill_queues(&dev->ctrl);
1875         if (pci_get_drvdata(pdev))
1876                 device_release_driver(&pdev->dev);
1877         nvme_put_ctrl(&dev->ctrl);
1878 }
1879
1880 static int nvme_reset(struct nvme_dev *dev)
1881 {
1882         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1883                 return -ENODEV;
1884         if (work_busy(&dev->reset_work))
1885                 return -ENODEV;
1886         if (!queue_work(nvme_workq, &dev->reset_work))
1887                 return -EBUSY;
1888         return 0;
1889 }
1890
1891 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1892 {
1893         *val = readl(to_nvme_dev(ctrl)->bar + off);
1894         return 0;
1895 }
1896
1897 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1898 {
1899         writel(val, to_nvme_dev(ctrl)->bar + off);
1900         return 0;
1901 }
1902
1903 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1904 {
1905         *val = readq(to_nvme_dev(ctrl)->bar + off);
1906         return 0;
1907 }
1908
1909 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1910 {
1911         struct nvme_dev *dev = to_nvme_dev(ctrl);
1912         int ret = nvme_reset(dev);
1913
1914         if (!ret)
1915                 flush_work(&dev->reset_work);
1916         return ret;
1917 }
1918
1919 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1920         .name                   = "pcie",
1921         .module                 = THIS_MODULE,
1922         .reg_read32             = nvme_pci_reg_read32,
1923         .reg_write32            = nvme_pci_reg_write32,
1924         .reg_read64             = nvme_pci_reg_read64,
1925         .reset_ctrl             = nvme_pci_reset_ctrl,
1926         .free_ctrl              = nvme_pci_free_ctrl,
1927         .submit_async_event     = nvme_pci_submit_async_event,
1928 };
1929
1930 static int nvme_dev_map(struct nvme_dev *dev)
1931 {
1932         struct pci_dev *pdev = to_pci_dev(dev->dev);
1933
1934         if (pci_request_mem_regions(pdev, "nvme"))
1935                 return -ENODEV;
1936
1937         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1938         if (!dev->bar)
1939                 goto release;
1940
1941         return 0;
1942   release:
1943         pci_release_mem_regions(pdev);
1944         return -ENODEV;
1945 }
1946
1947 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
1948 {
1949         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
1950                 /*
1951                  * Several Samsung devices seem to drop off the PCIe bus
1952                  * randomly when APST is on and uses the deepest sleep state.
1953                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
1954                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
1955                  * 950 PRO 256GB", but it seems to be restricted to two Dell
1956                  * laptops.
1957                  */
1958                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
1959                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
1960                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
1961                         return NVME_QUIRK_NO_DEEPEST_PS;
1962         }
1963
1964         return 0;
1965 }
1966
1967 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1968 {
1969         int node, result = -ENOMEM;
1970         struct nvme_dev *dev;
1971         unsigned long quirks = id->driver_data;
1972
1973         node = dev_to_node(&pdev->dev);
1974         if (node == NUMA_NO_NODE)
1975                 set_dev_node(&pdev->dev, first_memory_node);
1976
1977         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1978         if (!dev)
1979                 return -ENOMEM;
1980         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1981                                                         GFP_KERNEL, node);
1982         if (!dev->queues)
1983                 goto free;
1984
1985         dev->dev = get_device(&pdev->dev);
1986         pci_set_drvdata(pdev, dev);
1987
1988         result = nvme_dev_map(dev);
1989         if (result)
1990                 goto free;
1991
1992         INIT_WORK(&dev->reset_work, nvme_reset_work);
1993         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1994         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1995                 (unsigned long)dev);
1996         mutex_init(&dev->shutdown_lock);
1997         init_completion(&dev->ioq_wait);
1998
1999         result = nvme_setup_prp_pools(dev);
2000         if (result)
2001                 goto put_pci;
2002
2003         quirks |= check_dell_samsung_bug(pdev);
2004
2005         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2006                         quirks);
2007         if (result)
2008                 goto release_pools;
2009
2010         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2011
2012         queue_work(nvme_workq, &dev->reset_work);
2013         return 0;
2014
2015  release_pools:
2016         nvme_release_prp_pools(dev);
2017  put_pci:
2018         put_device(dev->dev);
2019         nvme_dev_unmap(dev);
2020  free:
2021         kfree(dev->queues);
2022         kfree(dev);
2023         return result;
2024 }
2025
2026 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2027 {
2028         struct nvme_dev *dev = pci_get_drvdata(pdev);
2029
2030         if (prepare)
2031                 nvme_dev_disable(dev, false);
2032         else
2033                 nvme_reset(dev);
2034 }
2035
2036 static void nvme_shutdown(struct pci_dev *pdev)
2037 {
2038         struct nvme_dev *dev = pci_get_drvdata(pdev);
2039         nvme_dev_disable(dev, true);
2040 }
2041
2042 /*
2043  * The driver's remove may be called on a device in a partially initialized
2044  * state. This function must not have any dependencies on the device state in
2045  * order to proceed.
2046  */
2047 static void nvme_remove(struct pci_dev *pdev)
2048 {
2049         struct nvme_dev *dev = pci_get_drvdata(pdev);
2050
2051         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2052
2053         pci_set_drvdata(pdev, NULL);
2054
2055         if (!pci_device_is_present(pdev)) {
2056                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2057                 nvme_dev_disable(dev, false);
2058         }
2059
2060         flush_work(&dev->reset_work);
2061         nvme_uninit_ctrl(&dev->ctrl);
2062         nvme_dev_disable(dev, true);
2063         nvme_dev_remove_admin(dev);
2064         nvme_free_queues(dev, 0);
2065         nvme_release_cmb(dev);
2066         nvme_release_prp_pools(dev);
2067         nvme_dev_unmap(dev);
2068         nvme_put_ctrl(&dev->ctrl);
2069 }
2070
2071 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2072 {
2073         int ret = 0;
2074
2075         if (numvfs == 0) {
2076                 if (pci_vfs_assigned(pdev)) {
2077                         dev_warn(&pdev->dev,
2078                                 "Cannot disable SR-IOV VFs while assigned\n");
2079                         return -EPERM;
2080                 }
2081                 pci_disable_sriov(pdev);
2082                 return 0;
2083         }
2084
2085         ret = pci_enable_sriov(pdev, numvfs);
2086         return ret ? ret : numvfs;
2087 }
2088
2089 #ifdef CONFIG_PM_SLEEP
2090 static int nvme_suspend(struct device *dev)
2091 {
2092         struct pci_dev *pdev = to_pci_dev(dev);
2093         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2094
2095         nvme_dev_disable(ndev, true);
2096         return 0;
2097 }
2098
2099 static int nvme_resume(struct device *dev)
2100 {
2101         struct pci_dev *pdev = to_pci_dev(dev);
2102         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2103
2104         nvme_reset(ndev);
2105         return 0;
2106 }
2107 #endif
2108
2109 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2110
2111 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2112                                                 pci_channel_state_t state)
2113 {
2114         struct nvme_dev *dev = pci_get_drvdata(pdev);
2115
2116         /*
2117          * A frozen channel requires a reset. When detected, this method will
2118          * shutdown the controller to quiesce. The controller will be restarted
2119          * after the slot reset through driver's slot_reset callback.
2120          */
2121         switch (state) {
2122         case pci_channel_io_normal:
2123                 return PCI_ERS_RESULT_CAN_RECOVER;
2124         case pci_channel_io_frozen:
2125                 dev_warn(dev->ctrl.device,
2126                         "frozen state error detected, reset controller\n");
2127                 nvme_dev_disable(dev, false);
2128                 return PCI_ERS_RESULT_NEED_RESET;
2129         case pci_channel_io_perm_failure:
2130                 dev_warn(dev->ctrl.device,
2131                         "failure state error detected, request disconnect\n");
2132                 return PCI_ERS_RESULT_DISCONNECT;
2133         }
2134         return PCI_ERS_RESULT_NEED_RESET;
2135 }
2136
2137 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2138 {
2139         struct nvme_dev *dev = pci_get_drvdata(pdev);
2140
2141         dev_info(dev->ctrl.device, "restart after slot reset\n");
2142         pci_restore_state(pdev);
2143         nvme_reset(dev);
2144         return PCI_ERS_RESULT_RECOVERED;
2145 }
2146
2147 static void nvme_error_resume(struct pci_dev *pdev)
2148 {
2149         pci_cleanup_aer_uncorrect_error_status(pdev);
2150 }
2151
2152 static const struct pci_error_handlers nvme_err_handler = {
2153         .error_detected = nvme_error_detected,
2154         .slot_reset     = nvme_slot_reset,
2155         .resume         = nvme_error_resume,
2156         .reset_notify   = nvme_reset_notify,
2157 };
2158
2159 static const struct pci_device_id nvme_id_table[] = {
2160         { PCI_VDEVICE(INTEL, 0x0953),
2161                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2162                                 NVME_QUIRK_DISCARD_ZEROES, },
2163         { PCI_VDEVICE(INTEL, 0x0a53),
2164                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2165                                 NVME_QUIRK_DISCARD_ZEROES, },
2166         { PCI_VDEVICE(INTEL, 0x0a54),
2167                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2168                                 NVME_QUIRK_DISCARD_ZEROES, },
2169         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2170                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2171         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2172                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2173         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2174                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2175         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2176         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2177         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2178         { 0, }
2179 };
2180 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2181
2182 static struct pci_driver nvme_driver = {
2183         .name           = "nvme",
2184         .id_table       = nvme_id_table,
2185         .probe          = nvme_probe,
2186         .remove         = nvme_remove,
2187         .shutdown       = nvme_shutdown,
2188         .driver         = {
2189                 .pm     = &nvme_dev_pm_ops,
2190         },
2191         .sriov_configure = nvme_pci_sriov_configure,
2192         .err_handler    = &nvme_err_handler,
2193 };
2194
2195 static int __init nvme_init(void)
2196 {
2197         int result;
2198
2199         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2200         if (!nvme_workq)
2201                 return -ENOMEM;
2202
2203         result = pci_register_driver(&nvme_driver);
2204         if (result)
2205                 destroy_workqueue(nvme_workq);
2206         return result;
2207 }
2208
2209 static void __exit nvme_exit(void)
2210 {
2211         pci_unregister_driver(&nvme_driver);
2212         destroy_workqueue(nvme_workq);
2213         _nvme_check_size();
2214 }
2215
2216 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2217 MODULE_LICENSE("GPL");
2218 MODULE_VERSION("1.0");
2219 module_init(nvme_init);
2220 module_exit(nvme_exit);