drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2500pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2500pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2500pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2500pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2500pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2500pci_read_csr,
 214                 .write          = rt2500pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2500pci_bbp_read,
 226                 .write          = rt2500pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2500pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2500PCI_RFKILL
 240 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #endif /* CONFIG_RT2400PCI_RFKILL */
 248
 249 /*
 250  * Configuration handlers.
 251  */
 252 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
 253 {
 254         __le32 reg[2];
 255
 256         memset(&reg, 0, sizeof(reg));
 257         memcpy(&reg, addr, ETH_ALEN);
 258
 259         /*
 260          * The MAC address is passed to us as an array of bytes,
 261          * that array is little endian, so no need for byte ordering.
 262          */
 263         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
 264 }
 265
 266 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
 267 {
 268         __le32 reg[2];
 269
 270         memset(&reg, 0, sizeof(reg));
 271         memcpy(&reg, bssid, ETH_ALEN);
 272
 273         /*
 274          * The BSSID is passed to us as an array of bytes,
 275          * that array is little endian, so no need for byte ordering.
 276          */
 277         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
 278 }
 279
 280 static void rt2500pci_config_packet_filter(struct rt2x00_dev *rt2x00dev,
 281                                            const unsigned int filter)
 282 {
 283         int promisc = !!(filter & IFF_PROMISC);
 284         int multicast = !!(filter & IFF_MULTICAST);
 285         int broadcast = !!(filter & IFF_BROADCAST);
 286         u32 reg;
 287
 288         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 289         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, !promisc);
 290         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST, !multicast);
 291         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, !broadcast);
 292         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 293 }
 294
 295 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type)
 296 {
 297         u32 reg;
 298
 299         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 300
 301         /*
 302          * Apply hardware packet filter.
 303          */
 304         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 305
 306         if (!is_monitor_present(&rt2x00dev->interface) &&
 307             (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
 308                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 1);
 309         else
 310                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
 311
 312         /*
 313          * If there is a non-monitor interface present
 314          * the packet should be strict (even if a monitor interface is present!).
 315          * When there is only 1 interface present which is in monitor mode
 316          * we should start accepting _all_ frames.
 317          */
 318         if (is_interface_present(&rt2x00dev->interface)) {
 319                 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
 320                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
 321                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
 322                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 323         } else if (is_monitor_present(&rt2x00dev->interface)) {
 324                 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 0);
 325                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 0);
 326                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 0);
 327                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 0);
 328         }
 329
 330         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 331
 332         /*
 333          * Enable beacon config
 334          */
 335         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 336         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 337                            PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 338         rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
 339                            rt2x00lib_get_ring(rt2x00dev,
 340                                               IEEE80211_TX_QUEUE_BEACON)
 341                            ->tx_params.cw_min);
 342         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 343
 344         /*
 345          * Enable synchronisation.
 346          */
 347         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 348         if (is_interface_present(&rt2x00dev->interface)) {
 349                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 350                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 351         }
 352
 353         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 354         if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
 355                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
 356         else if (type == IEEE80211_IF_TYPE_STA)
 357                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
 358         else if (is_monitor_present(&rt2x00dev->interface) &&
 359                  !is_interface_present(&rt2x00dev->interface))
 360                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 361
 362         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 363 }
 364
 365 static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 366 {
 367         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 368         u32 reg;
 369         u32 preamble;
 370         u16 value;
 371
 372         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
 373                 preamble = SHORT_PREAMBLE;
 374         else
 375                 preamble = PREAMBLE;
 376
 377         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
 378         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 379
 380         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 381         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 382                  SHORT_DIFS : DIFS) +
 383             PLCP + preamble + get_duration(ACK_SIZE, 10);
 384         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 385         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 386         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 387         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 388
 389         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 390
 391         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 392         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 393         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 394         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 395         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 396
 397         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 398         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 399         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 400         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 401         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 402
 403         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 404         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 405         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 406         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 407         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 408
 409         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 410         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 411         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 412         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 413         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 414 }
 415
 416 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 417                                      const int phymode)
 418 {
 419         struct ieee80211_hw_mode *mode;
 420         struct ieee80211_rate *rate;
 421
 422         if (phymode == MODE_IEEE80211A)
 423                 rt2x00dev->curr_hwmode = HWMODE_A;
 424         else if (phymode == MODE_IEEE80211B)
 425                 rt2x00dev->curr_hwmode = HWMODE_B;
 426         else
 427                 rt2x00dev->curr_hwmode = HWMODE_G;
 428
 429         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 430         rate = &mode->rates[mode->num_rates - 1];
 431
 432         rt2500pci_config_rate(rt2x00dev, rate->val2);
 433 }
 434
 435 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 436                                      const int index, const int channel,
 437                                      const int txpower)
 438 {
 439         struct rf_channel reg;
 440         u8 r70;
 441
 442         /*
 443          * Fill rf_reg structure.
 444          */
 445         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
 446
 447         /*
 448          * Set TXpower.
 449          */
 450         rt2x00_set_field32(&reg.rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 451
 452         /*
 453          * Switch on tuning bits.
 454          * For RT2523 devices we do not need to update the R1 register.
 455          */
 456         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 457                 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
 458         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 459
 460         /*
 461          * For RT2525 we should first set the channel to half band higher.
 462          */
 463         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 464                 static const u32 vals[] = {
 465                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 466                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 467                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 468                         0x00080d2e, 0x00080d3a
 469                 };
 470
 471                 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
 472                 rt2500pci_rf_write(rt2x00dev, 2, vals[channel - 1]);
 473                 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
 474                 if (reg.rf4)
 475                         rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
 476         }
 477
 478         rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
 479         rt2500pci_rf_write(rt2x00dev, 2, reg.rf2);
 480         rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
 481         if (reg.rf4)
 482                 rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
 483
 484         /*
 485          * Channel 14 requires the Japan filter bit to be set.
 486          */
 487         r70 = 0x46;
 488         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
 489         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 490
 491         msleep(1);
 492
 493         /*
 494          * Switch off tuning bits.
 495          * For RT2523 devices we do not need to update the R1 register.
 496          */
 497         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 498                 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
 499                 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
 500         }
 501
 502         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 503         rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
 504
 505         /*
 506          * Clear false CRC during channel switch.
 507          */
 508         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 509 }
 510
 511 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 512                                      const int txpower)
 513 {
 514         u32 rf3;
 515
 516         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 517         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 518         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 519 }
 520
 521 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 522                                      const int antenna_tx, const int antenna_rx)
 523 {
 524         u32 reg;
 525         u8 r14;
 526         u8 r2;
 527
 528         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 529         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 530         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 531
 532         /*
 533          * Configure the TX antenna.
 534          */
 535         switch (antenna_tx) {
 536         case ANTENNA_SW_DIVERSITY:
 537         case ANTENNA_HW_DIVERSITY:
 538                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 539                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 540                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 541                 break;
 542         case ANTENNA_A:
 543                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 544                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 545                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 546                 break;
 547         case ANTENNA_B:
 548                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 549                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 550                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 551                 break;
 552         }
 553
 554         /*
 555          * Configure the RX antenna.
 556          */
 557         switch (antenna_rx) {
 558         case ANTENNA_SW_DIVERSITY:
 559         case ANTENNA_HW_DIVERSITY:
 560                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 561                 break;
 562         case ANTENNA_A:
 563                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 564                 break;
 565         case ANTENNA_B:
 566                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 567                 break;
 568         }
 569
 570         /*
 571          * RT2525E and RT5222 need to flip TX I/Q
 572          */
 573         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 574             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 575                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 576                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 577                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 578
 579                 /*
 580                  * RT2525E does not need RX I/Q Flip.
 581                  */
 582                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 583                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 584         } else {
 585                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 586                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 587         }
 588
 589         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 590         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 591         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 592 }
 593
 594 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 595                                       const int short_slot_time,
 596                                       const int beacon_int)
 597 {
 598         u32 reg;
 599
 600         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 601         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 602                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 603         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 604
 605         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 606         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 607         rt2x00_set_field32(&reg, CSR18_PIFS,
 608                            short_slot_time ? SHORT_PIFS : PIFS);
 609         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 610
 611         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 612         rt2x00_set_field32(&reg, CSR19_DIFS,
 613                            short_slot_time ? SHORT_DIFS : DIFS);
 614         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 615         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 616
 617         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 618         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 619         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 620         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 621
 622         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 623         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 624         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 625         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 626 }
 627
 628 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 629                              const unsigned int flags,
 630                              struct ieee80211_conf *conf)
 631 {
 632         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
 633
 634         if (flags & CONFIG_UPDATE_PHYMODE)
 635                 rt2500pci_config_phymode(rt2x00dev, conf->phymode);
 636         if (flags & CONFIG_UPDATE_CHANNEL)
 637                 rt2500pci_config_channel(rt2x00dev, conf->channel_val,
 638                                          conf->channel, conf->power_level);
 639         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 640                 rt2500pci_config_txpower(rt2x00dev, conf->power_level);
 641         if (flags & CONFIG_UPDATE_ANTENNA)
 642                 rt2500pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
 643                                          conf->antenna_sel_rx);
 644         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 645                 rt2500pci_config_duration(rt2x00dev, short_slot_time,
 646                                           conf->beacon_int);
 647 }
 648
 649 /*
 650  * LED functions.
 651  */
 652 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
 653 {
 654         u32 reg;
 655
 656         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 657
 658         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 659         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 660
 661         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 662                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 663                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 664         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 665                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 666                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 667         } else {
 668                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 669                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 670         }
 671
 672         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 673 }
 674
 675 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
 676 {
 677         u32 reg;
 678
 679         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 680         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 681         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 682         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 683 }
 684
 685 /*
 686  * Link tuning
 687  */
 688 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
 689 {
 690         u32 reg;
 691
 692         /*
 693          * Update FCS error count from register.
 694          */
 695         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 696         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 697
 698         /*
 699          * Update False CCA count from register.
 700          */
 701         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 702         rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 703 }
 704
 705 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 706 {
 707         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 708         rt2x00dev->link.vgc_level = 0x48;
 709 }
 710
 711 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 712 {
 713         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 714         u8 r17;
 715
 716         /*
 717          * To prevent collisions with MAC ASIC on chipsets
 718          * up to version C the link tuning should halt after 20
 719          * seconds.
 720          */
 721         if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 722             rt2x00dev->link.count > 20)
 723                 return;
 724
 725         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 726
 727         /*
 728          * Chipset versions C and lower should directly continue
 729          * to the dynamic CCA tuning.
 730          */
 731         if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
 732                 goto dynamic_cca_tune;
 733
 734         /*
 735          * A too low RSSI will cause too much false CCA which will
 736          * then corrupt the R17 tuning. To remidy this the tuning should
 737          * be stopped (While making sure the R17 value will not exceed limits)
 738          */
 739         if (rssi < -80 && rt2x00dev->link.count > 20) {
 740                 if (r17 >= 0x41) {
 741                         r17 = rt2x00dev->link.vgc_level;
 742                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 743                 }
 744                 return;
 745         }
 746
 747         /*
 748          * Special big-R17 for short distance
 749          */
 750         if (rssi >= -58) {
 751                 if (r17 != 0x50)
 752                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 753                 return;
 754         }
 755
 756         /*
 757          * Special mid-R17 for middle distance
 758          */
 759         if (rssi >= -74) {
 760                 if (r17 != 0x41)
 761                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 762                 return;
 763         }
 764
 765         /*
 766          * Leave short or middle distance condition, restore r17
 767          * to the dynamic tuning range.
 768          */
 769         if (r17 >= 0x41) {
 770                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 771                 return;
 772         }
 773
 774 dynamic_cca_tune:
 775
 776         /*
 777          * R17 is inside the dynamic tuning range,
 778          * start tuning the link based on the false cca counter.
 779          */
 780         if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
 781                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 782                 rt2x00dev->link.vgc_level = r17;
 783         } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
 784                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 785                 rt2x00dev->link.vgc_level = r17;
 786         }
 787 }
 788
 789 /*
 790  * Initialization functions.
 791  */
 792 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 793 {
 794         struct data_ring *ring = rt2x00dev->rx;
 795         struct data_desc *rxd;
 796         unsigned int i;
 797         u32 word;
 798
 799         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 800
 801         for (i = 0; i < ring->stats.limit; i++) {
 802                 rxd = ring->entry[i].priv;
 803
 804                 rt2x00_desc_read(rxd, 1, &word);
 805                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 806                                    ring->entry[i].data_dma);
 807                 rt2x00_desc_write(rxd, 1, word);
 808
 809                 rt2x00_desc_read(rxd, 0, &word);
 810                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 811                 rt2x00_desc_write(rxd, 0, word);
 812         }
 813
 814         rt2x00_ring_index_clear(rt2x00dev->rx);
 815 }
 816
 817 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 818 {
 819         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 820         struct data_desc *txd;
 821         unsigned int i;
 822         u32 word;
 823
 824         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 825
 826         for (i = 0; i < ring->stats.limit; i++) {
 827                 txd = ring->entry[i].priv;
 828
 829                 rt2x00_desc_read(txd, 1, &word);
 830                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 831                                    ring->entry[i].data_dma);
 832                 rt2x00_desc_write(txd, 1, word);
 833
 834                 rt2x00_desc_read(txd, 0, &word);
 835                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 836                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 837                 rt2x00_desc_write(txd, 0, word);
 838         }
 839
 840         rt2x00_ring_index_clear(ring);
 841 }
 842
 843 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
 844 {
 845         u32 reg;
 846
 847         /*
 848          * Initialize rings.
 849          */
 850         rt2500pci_init_rxring(rt2x00dev);
 851         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 852         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 853         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 854         rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 855
 856         /*
 857          * Initialize registers.
 858          */
 859         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 860         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 861                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 862         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 863                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 864         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 865                            rt2x00dev->bcn[1].stats.limit);
 866         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 867                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 868         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 869
 870         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 871         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 872                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 873         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 874
 875         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 876         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 877                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 878         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 879
 880         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 881         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 882                            rt2x00dev->bcn[1].data_dma);
 883         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 884
 885         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 886         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 887                            rt2x00dev->bcn[0].data_dma);
 888         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 889
 890         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 891         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 892         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 893         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 894
 895         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 896         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 897                            rt2x00dev->rx->data_dma);
 898         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 899
 900         return 0;
 901 }
 902
 903 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 904 {
 905         u32 reg;
 906
 907         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 908         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 909         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 910         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 911
 912         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 913         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 914         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 915         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 916         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 917
 918         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 919         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 920                            rt2x00dev->rx->data_size / 128);
 921         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 922
 923         /*
 924          * Always use CWmin and CWmax set in descriptor.
 925          */
 926         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 927         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 928         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 929
 930         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 931
 932         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 933         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 934         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 935         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 936         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 937         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 938         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 939         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 940         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 941         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 942
 943         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 944         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 945         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 946         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 947         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 948         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 949
 950         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 951         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 952         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 953         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 954         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 955         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 956
 957         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 958         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 959         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 960         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 961         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 962         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 963
 964         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 965         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 966         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 967         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 968         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 969         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 970         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 971         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 972         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 973         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 974
 975         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 976         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 977         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 978         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 979         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 980         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 981         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 982         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 983         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 984
 985         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 986
 987         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 988         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 989
 990         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 991                 return -EBUSY;
 992
 993         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 994         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 995
 996         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 997         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 998         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 999
1000         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
1001         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1002         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1003         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1004         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1005         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1006         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1007         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
1008
1009         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1010
1011         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1012
1013         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1014         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1015         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1016         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1017         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1018
1019         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
1020         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1021         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1022         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1023
1024         /*
1025          * We must clear the FCS and FIFO error count.
1026          * These registers are cleared on read,
1027          * so we may pass a useless variable to store the value.
1028          */
1029         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1030         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
1031
1032         return 0;
1033 }
1034
1035 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1036 {
1037         unsigned int i;
1038         u16 eeprom;
1039         u8 reg_id;
1040         u8 value;
1041
1042         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1043                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1044                 if ((value != 0xff) && (value != 0x00))
1045                         goto continue_csr_init;
1046                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1047                 udelay(REGISTER_BUSY_DELAY);
1048         }
1049
1050         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1051         return -EACCES;
1052
1053 continue_csr_init:
1054         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1055         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1056         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1057         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1058         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1059         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1060         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1061         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1062         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1063         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1064         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1065         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1066         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1067         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1068         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1069         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1070         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1071         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1072         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1073         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1074         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1075         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1076         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1077         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1078         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1079         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1080         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1081         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1082         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1083         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1084
1085         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1086         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1087                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1088
1089                 if (eeprom != 0xffff && eeprom != 0x0000) {
1090                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1091                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1092                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1093                               reg_id, value);
1094                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1095                 }
1096         }
1097         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1098
1099         return 0;
1100 }
1101
1102 /*
1103  * Device state switch handlers.
1104  */
1105 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1106                                 enum dev_state state)
1107 {
1108         u32 reg;
1109
1110         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1111         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1112                            state == STATE_RADIO_RX_OFF);
1113         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1114 }
1115
1116 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1117                                  enum dev_state state)
1118 {
1119         int mask = (state == STATE_RADIO_IRQ_OFF);
1120         u32 reg;
1121
1122         /*
1123          * When interrupts are being enabled, the interrupt registers
1124          * should clear the register to assure a clean state.
1125          */
1126         if (state == STATE_RADIO_IRQ_ON) {
1127                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1128                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1129         }
1130
1131         /*
1132          * Only toggle the interrupts bits we are going to use.
1133          * Non-checked interrupt bits are disabled by default.
1134          */
1135         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1136         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1137         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1138         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1139         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1140         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1141         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1142 }
1143
1144 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1145 {
1146         /*
1147          * Initialize all registers.
1148          */
1149         if (rt2500pci_init_rings(rt2x00dev) ||
1150             rt2500pci_init_registers(rt2x00dev) ||
1151             rt2500pci_init_bbp(rt2x00dev)) {
1152                 ERROR(rt2x00dev, "Register initialization failed.\n");
1153                 return -EIO;
1154         }
1155
1156         /*
1157          * Enable interrupts.
1158          */
1159         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1160
1161         /*
1162          * Enable LED
1163          */
1164         rt2500pci_enable_led(rt2x00dev);
1165
1166         return 0;
1167 }
1168
1169 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1170 {
1171         u32 reg;
1172
1173         /*
1174          * Disable LED
1175          */
1176         rt2500pci_disable_led(rt2x00dev);
1177
1178         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1179
1180         /*
1181          * Disable synchronisation.
1182          */
1183         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1184
1185         /*
1186          * Cancel RX and TX.
1187          */
1188         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1189         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1190         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1191
1192         /*
1193          * Disable interrupts.
1194          */
1195         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1196 }
1197
1198 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1199                                enum dev_state state)
1200 {
1201         u32 reg;
1202         unsigned int i;
1203         char put_to_sleep;
1204         char bbp_state;
1205         char rf_state;
1206
1207         put_to_sleep = (state != STATE_AWAKE);
1208
1209         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1210         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1211         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1212         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1213         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1214         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1215
1216         /*
1217          * Device is not guaranteed to be in the requested state yet.
1218          * We must wait until the register indicates that the
1219          * device has entered the correct state.
1220          */
1221         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1222                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1223                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1224                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1225                 if (bbp_state == state && rf_state == state)
1226                         return 0;
1227                 msleep(10);
1228         }
1229
1230         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1231                "current device state: bbp %d and rf %d.\n",
1232                state, bbp_state, rf_state);
1233
1234         return -EBUSY;
1235 }
1236
1237 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1238                                       enum dev_state state)
1239 {
1240         int retval = 0;
1241
1242         switch (state) {
1243         case STATE_RADIO_ON:
1244                 retval = rt2500pci_enable_radio(rt2x00dev);
1245                 break;
1246         case STATE_RADIO_OFF:
1247                 rt2500pci_disable_radio(rt2x00dev);
1248                 break;
1249         case STATE_RADIO_RX_ON:
1250         case STATE_RADIO_RX_OFF:
1251                 rt2500pci_toggle_rx(rt2x00dev, state);
1252                 break;
1253         case STATE_DEEP_SLEEP:
1254         case STATE_SLEEP:
1255         case STATE_STANDBY:
1256         case STATE_AWAKE:
1257                 retval = rt2500pci_set_state(rt2x00dev, state);
1258                 break;
1259         default:
1260                 retval = -ENOTSUPP;
1261                 break;
1262         }
1263
1264         return retval;
1265 }
1266
1267 /*
1268  * TX descriptor initialization
1269  */
1270 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1271                                     struct data_desc *txd,
1272                                     struct data_entry_desc *desc,
1273                                     struct ieee80211_hdr *ieee80211hdr,
1274                                     unsigned int length,
1275                                     struct ieee80211_tx_control *control)
1276 {
1277         u32 word;
1278
1279         /*
1280          * Start writing the descriptor words.
1281          */
1282         rt2x00_desc_read(txd, 2, &word);
1283         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1284         rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1285         rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1286         rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1287         rt2x00_desc_write(txd, 2, word);
1288
1289         rt2x00_desc_read(txd, 3, &word);
1290         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1291         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1292         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1293         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1294         rt2x00_desc_write(txd, 3, word);
1295
1296         rt2x00_desc_read(txd, 10, &word);
1297         rt2x00_set_field32(&word, TXD_W10_RTS,
1298                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1299         rt2x00_desc_write(txd, 10, word);
1300
1301         rt2x00_desc_read(txd, 0, &word);
1302         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1303         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1304         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1305                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1306         rt2x00_set_field32(&word, TXD_W0_ACK,
1307                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1308         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1309                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1310         rt2x00_set_field32(&word, TXD_W0_OFDM,
1311                            test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1312         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1313         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1314         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1315                            !!(control->flags &
1316                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1317         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1318         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1319         rt2x00_desc_write(txd, 0, word);
1320 }
1321
1322 /*
1323  * TX data initialization
1324  */
1325 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1326                                     unsigned int queue)
1327 {
1328         u32 reg;
1329
1330         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1331                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1332                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1333                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1334                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1335                 }
1336                 return;
1337         }
1338
1339         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1340         if (queue == IEEE80211_TX_QUEUE_DATA0)
1341                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1342         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1343                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1344         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1345                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1346         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1347 }
1348
1349 /*
1350  * RX control handlers
1351  */
1352 static int rt2500pci_fill_rxdone(struct data_entry *entry,
1353                                  int *signal, int *rssi, int *ofdm, int *size)
1354 {
1355         struct data_desc *rxd = entry->priv;
1356         u32 word0;
1357         u32 word2;
1358
1359         rt2x00_desc_read(rxd, 0, &word0);
1360         rt2x00_desc_read(rxd, 2, &word2);
1361
1362         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR) ||
1363             rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR) ||
1364             rt2x00_get_field32(word0, RXD_W0_ICV_ERROR))
1365                 return -EINVAL;
1366
1367         *signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1368         *rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1369             entry->ring->rt2x00dev->rssi_offset;
1370         *ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1371         *size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1372
1373         return 0;
1374 }
1375
1376 /*
1377  * Interrupt functions.
1378  */
1379 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1380 {
1381         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1382         struct data_entry *entry;
1383         struct data_desc *txd;
1384         u32 word;
1385         int tx_status;
1386         int retry;
1387
1388         while (!rt2x00_ring_empty(ring)) {
1389                 entry = rt2x00_get_data_entry_done(ring);
1390                 txd = entry->priv;
1391                 rt2x00_desc_read(txd, 0, &word);
1392
1393                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1394                     !rt2x00_get_field32(word, TXD_W0_VALID))
1395                         break;
1396
1397                 /*
1398                  * Obtain the status about this packet.
1399                  */
1400                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1401                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1402
1403                 rt2x00lib_txdone(entry, tx_status, retry);
1404
1405                 /*
1406                  * Make this entry available for reuse.
1407                  */
1408                 entry->flags = 0;
1409                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1410                 rt2x00_desc_write(txd, 0, word);
1411                 rt2x00_ring_index_done_inc(ring);
1412         }
1413
1414         /*
1415          * If the data ring was full before the txdone handler
1416          * we must make sure the packet queue in the mac80211 stack
1417          * is reenabled when the txdone handler has finished.
1418          */
1419         entry = ring->entry;
1420         if (!rt2x00_ring_full(ring))
1421                 ieee80211_wake_queue(rt2x00dev->hw,
1422                                      entry->tx_status.control.queue);
1423 }
1424
1425 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1426 {
1427         struct rt2x00_dev *rt2x00dev = dev_instance;
1428         u32 reg;
1429
1430         /*
1431          * Get the interrupt sources & saved to local variable.
1432          * Write register value back to clear pending interrupts.
1433          */
1434         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1435         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1436
1437         if (!reg)
1438                 return IRQ_NONE;
1439
1440         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1441                 return IRQ_HANDLED;
1442
1443         /*
1444          * Handle interrupts, walk through all bits
1445          * and run the tasks, the bits are checked in order of
1446          * priority.
1447          */
1448
1449         /*
1450          * 1 - Beacon timer expired interrupt.
1451          */
1452         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1453                 rt2x00lib_beacondone(rt2x00dev);
1454
1455         /*
1456          * 2 - Rx ring done interrupt.
1457          */
1458         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1459                 rt2x00pci_rxdone(rt2x00dev);
1460
1461         /*
1462          * 3 - Atim ring transmit done interrupt.
1463          */
1464         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1465                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1466
1467         /*
1468          * 4 - Priority ring transmit done interrupt.
1469          */
1470         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1471                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1472
1473         /*
1474          * 5 - Tx ring transmit done interrupt.
1475          */
1476         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1477                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1478
1479         return IRQ_HANDLED;
1480 }
1481
1482 /*
1483  * Device probe functions.
1484  */
1485 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1486 {
1487         struct eeprom_93cx6 eeprom;
1488         u32 reg;
1489         u16 word;
1490         u8 *mac;
1491
1492         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1493
1494         eeprom.data = rt2x00dev;
1495         eeprom.register_read = rt2500pci_eepromregister_read;
1496         eeprom.register_write = rt2500pci_eepromregister_write;
1497         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1498             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1499         eeprom.reg_data_in = 0;
1500         eeprom.reg_data_out = 0;
1501         eeprom.reg_data_clock = 0;
1502         eeprom.reg_chip_select = 0;
1503
1504         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1505                                EEPROM_SIZE / sizeof(u16));
1506
1507         /*
1508          * Start validation of the data that has been read.
1509          */
1510         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1511         if (!is_valid_ether_addr(mac)) {
1512                 random_ether_addr(mac);
1513                 EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
1514         }
1515
1516         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1517         if (word == 0xffff) {
1518                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1519                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1520                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1521                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1522                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1523                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1524                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1525                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1526                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1527         }
1528
1529         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1530         if (word == 0xffff) {
1531                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1532                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1533                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1534                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1535                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1536         }
1537
1538         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1539         if (word == 0xffff) {
1540                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1541                                    DEFAULT_RSSI_OFFSET);
1542                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1543                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1544         }
1545
1546         return 0;
1547 }
1548
1549 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1550 {
1551         u32 reg;
1552         u16 value;
1553         u16 eeprom;
1554
1555         /*
1556          * Read EEPROM word for configuration.
1557          */
1558         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1559
1560         /*
1561          * Identify RF chipset.
1562          */
1563         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1564         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1565         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1566
1567         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1568             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1569             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1570             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1571             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1572             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1573                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1574                 return -ENODEV;
1575         }
1576
1577         /*
1578          * Identify default antenna configuration.
1579          */
1580         rt2x00dev->hw->conf.antenna_sel_tx =
1581             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1582         rt2x00dev->hw->conf.antenna_sel_rx =
1583             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1584
1585         /*
1586          * Store led mode, for correct led behaviour.
1587          */
1588         rt2x00dev->led_mode =
1589             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1590
1591         /*
1592          * Detect if this device has an hardware controlled radio.
1593          */
1594         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1595                 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1596
1597         /*
1598          * Check if the BBP tuning should be enabled.
1599          */
1600         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1601
1602         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1603                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1604
1605         /*
1606          * Read the RSSI <-> dBm offset information.
1607          */
1608         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1609         rt2x00dev->rssi_offset =
1610             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1611
1612         return 0;
1613 }
1614
1615 /*
1616  * RF value list for RF2522
1617  * Supports: 2.4 GHz
1618  */
1619 static const struct rf_channel rf_vals_bg_2522[] = {
1620         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1621         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1622         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1623         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1624         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1625         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1626         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1627         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1628         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1629         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1630         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1631         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1632         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1633         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1634 };
1635
1636 /*
1637  * RF value list for RF2523
1638  * Supports: 2.4 GHz
1639  */
1640 static const struct rf_channel rf_vals_bg_2523[] = {
1641         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1642         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1643         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1644         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1645         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1646         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1647         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1648         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1649         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1650         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1651         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1652         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1653         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1654         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1655 };
1656
1657 /*
1658  * RF value list for RF2524
1659  * Supports: 2.4 GHz
1660  */
1661 static const struct rf_channel rf_vals_bg_2524[] = {
1662         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1663         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1664         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1665         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1666         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1667         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1668         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1669         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1670         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1671         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1672         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1673         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1674         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1675         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1676 };
1677
1678 /*
1679  * RF value list for RF2525
1680  * Supports: 2.4 GHz
1681  */
1682 static const struct rf_channel rf_vals_bg_2525[] = {
1683         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1684         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1685         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1686         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1687         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1688         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1689         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1690         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1691         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1692         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1693         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1694         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1695         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1696         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1697 };
1698
1699 /*
1700  * RF value list for RF2525e
1701  * Supports: 2.4 GHz
1702  */
1703 static const struct rf_channel rf_vals_bg_2525e[] = {
1704         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1705         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1706         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1707         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1708         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1709         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1710         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1711         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1712         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1713         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1714         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1715         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1716         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1717         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1718 };
1719
1720 /*
1721  * RF value list for RF5222
1722  * Supports: 2.4 GHz & 5.2 GHz
1723  */
1724 static const struct rf_channel rf_vals_5222[] = {
1725         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1726         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1727         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1728         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1729         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1730         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1731         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1732         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1733         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1734         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1735         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1736         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1737         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1738         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1739
1740         /* 802.11 UNI / HyperLan 2 */
1741         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1742         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1743         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1744         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1745         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1746         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1747         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1748         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1749
1750         /* 802.11 HyperLan 2 */
1751         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1752         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1753         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1754         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1755         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1756         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1757         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1758         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1759         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1760         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1761
1762         /* 802.11 UNII */
1763         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1764         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1765         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1766         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1767         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1768 };
1769
1770 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1771 {
1772         struct hw_mode_spec *spec = &rt2x00dev->spec;
1773         u8 *txpower;
1774         unsigned int i;
1775
1776         /*
1777          * Initialize all hw fields.
1778          */
1779         rt2x00dev->hw->flags =
1780             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1781             IEEE80211_HW_MONITOR_DURING_OPER |
1782             IEEE80211_HW_NO_PROBE_FILTERING;
1783         rt2x00dev->hw->extra_tx_headroom = 0;
1784         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1785         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1786         rt2x00dev->hw->queues = 2;
1787
1788         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1789         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1790                                 rt2x00_eeprom_addr(rt2x00dev,
1791                                                    EEPROM_MAC_ADDR_0));
1792
1793         /*
1794          * Convert tx_power array in eeprom.
1795          */
1796         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1797         for (i = 0; i < 14; i++)
1798                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1799
1800         /*
1801          * Initialize hw_mode information.
1802          */
1803         spec->num_modes = 2;
1804         spec->num_rates = 12;
1805         spec->tx_power_a = NULL;
1806         spec->tx_power_bg = txpower;
1807         spec->tx_power_default = DEFAULT_TXPOWER;
1808
1809         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1810                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1811                 spec->channels = rf_vals_bg_2522;
1812         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1813                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1814                 spec->channels = rf_vals_bg_2523;
1815         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1816                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1817                 spec->channels = rf_vals_bg_2524;
1818         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1819                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1820                 spec->channels = rf_vals_bg_2525;
1821         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1822                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1823                 spec->channels = rf_vals_bg_2525e;
1824         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1825                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1826                 spec->channels = rf_vals_5222;
1827                 spec->num_modes = 3;
1828         }
1829 }
1830
1831 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1832 {
1833         int retval;
1834
1835         /*
1836          * Allocate eeprom data.
1837          */
1838         retval = rt2500pci_validate_eeprom(rt2x00dev);
1839         if (retval)
1840                 return retval;
1841
1842         retval = rt2500pci_init_eeprom(rt2x00dev);
1843         if (retval)
1844                 return retval;
1845
1846         /*
1847          * Initialize hw specifications.
1848          */
1849         rt2500pci_probe_hw_mode(rt2x00dev);
1850
1851         /*
1852          * This device requires the beacon ring
1853          */
1854         __set_bit(REQUIRE_BEACON_RING, &rt2x00dev->flags);
1855
1856         /*
1857          * Set the rssi offset.
1858          */
1859         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1860
1861         return 0;
1862 }
1863
1864 /*
1865  * IEEE80211 stack callback functions.
1866  */
1867 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1868                                      u32 short_retry, u32 long_retry)
1869 {
1870         struct rt2x00_dev *rt2x00dev = hw->priv;
1871         u32 reg;
1872
1873         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1874         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1875         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1876         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1877
1878         return 0;
1879 }
1880
1881 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1882 {
1883         struct rt2x00_dev *rt2x00dev = hw->priv;
1884         u64 tsf;
1885         u32 reg;
1886
1887         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1888         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1889         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1890         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1891
1892         return tsf;
1893 }
1894
1895 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1896 {
1897         struct rt2x00_dev *rt2x00dev = hw->priv;
1898
1899         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1900         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1901 }
1902
1903 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1904 {
1905         struct rt2x00_dev *rt2x00dev = hw->priv;
1906         u32 reg;
1907
1908         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1909         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1910 }
1911
1912 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1913         .tx                     = rt2x00mac_tx,
1914         .add_interface          = rt2x00mac_add_interface,
1915         .remove_interface       = rt2x00mac_remove_interface,
1916         .config                 = rt2x00mac_config,
1917         .config_interface       = rt2x00mac_config_interface,
1918         .set_multicast_list     = rt2x00mac_set_multicast_list,
1919         .get_stats              = rt2x00mac_get_stats,
1920         .set_retry_limit        = rt2500pci_set_retry_limit,
1921         .conf_tx                = rt2x00mac_conf_tx,
1922         .get_tx_stats           = rt2x00mac_get_tx_stats,
1923         .get_tsf                = rt2500pci_get_tsf,
1924         .reset_tsf              = rt2500pci_reset_tsf,
1925         .beacon_update          = rt2x00pci_beacon_update,
1926         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1927 };
1928
1929 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1930         .irq_handler            = rt2500pci_interrupt,
1931         .probe_hw               = rt2500pci_probe_hw,
1932         .initialize             = rt2x00pci_initialize,
1933         .uninitialize           = rt2x00pci_uninitialize,
1934         .set_device_state       = rt2500pci_set_device_state,
1935 #ifdef CONFIG_RT2500PCI_RFKILL
1936         .rfkill_poll            = rt2500pci_rfkill_poll,
1937 #endif /* CONFIG_RT2500PCI_RFKILL */
1938         .link_stats             = rt2500pci_link_stats,
1939         .reset_tuner            = rt2500pci_reset_tuner,
1940         .link_tuner             = rt2500pci_link_tuner,
1941         .write_tx_desc          = rt2500pci_write_tx_desc,
1942         .write_tx_data          = rt2x00pci_write_tx_data,
1943         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1944         .fill_rxdone            = rt2500pci_fill_rxdone,
1945         .config_mac_addr        = rt2500pci_config_mac_addr,
1946         .config_bssid           = rt2500pci_config_bssid,
1947         .config_packet_filter   = rt2500pci_config_packet_filter,
1948         .config_type            = rt2500pci_config_type,
1949         .config                 = rt2500pci_config,
1950 };
1951
1952 static const struct rt2x00_ops rt2500pci_ops = {
1953         .name           = DRV_NAME,
1954         .rxd_size       = RXD_DESC_SIZE,
1955         .txd_size       = TXD_DESC_SIZE,
1956         .eeprom_size    = EEPROM_SIZE,
1957         .rf_size        = RF_SIZE,
1958         .lib            = &rt2500pci_rt2x00_ops,
1959         .hw             = &rt2500pci_mac80211_ops,
1960 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1961         .debugfs        = &rt2500pci_rt2x00debug,
1962 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1963 };
1964
1965 /*
1966  * RT2500pci module information.
1967  */
1968 static struct pci_device_id rt2500pci_device_table[] = {
1969         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1970         { 0, }
1971 };
1972
1973 MODULE_AUTHOR(DRV_PROJECT);
1974 MODULE_VERSION(DRV_VERSION);
1975 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1976 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1977 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1978 MODULE_LICENSE("GPL");
1979
1980 static struct pci_driver rt2500pci_driver = {
1981         .name           = DRV_NAME,
1982         .id_table       = rt2500pci_device_table,
1983         .probe          = rt2x00pci_probe,
1984         .remove         = __devexit_p(rt2x00pci_remove),
1985         .suspend        = rt2x00pci_suspend,
1986         .resume         = rt2x00pci_resume,
1987 };
1988
1989 static int __init rt2500pci_init(void)
1990 {
1991         return pci_register_driver(&rt2500pci_driver);
1992 }
1993
1994 static void __exit rt2500pci_exit(void)
1995 {
1996         pci_unregister_driver(&rt2500pci_driver);
1997 }
1998
1999 module_init(rt2500pci_init);
2000 module_exit(rt2500pci_exit);