drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 /*
  20         Module: rt2500pci
  21         Abstract: rt2500pci device specific routines.
  22         Supported chipsets: RT2560.
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/eeprom_93cx6.h>
  31 #include <linux/slab.h>
  32
  33 #include "rt2x00.h"
  34 #include "rt2x00mmio.h"
  35 #include "rt2x00pci.h"
  36 #include "rt2500pci.h"
  37
  38 /*
  39  * Register access.
  40  * All access to the CSR registers will go through the methods
  41  * rt2x00mmio_register_read and rt2x00mmio_register_write.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 #define WAIT_FOR_BBP(__dev, __reg) \
  52         rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  53 #define WAIT_FOR_RF(__dev, __reg) \
  54         rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  55
  56 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  57                                 const unsigned int word, const u8 value)
  58 {
  59         u32 reg;
  60
  61         mutex_lock(&rt2x00dev->csr_mutex);
  62
  63         /*
  64          * Wait until the BBP becomes available, afterwards we
  65          * can safely write the new data into the register.
  66          */
  67         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  68                 reg = 0;
  69                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  70                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  71                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  72                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  73
  74                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
  75         }
  76
  77         mutex_unlock(&rt2x00dev->csr_mutex);
  78 }
  79
  80 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  81                                const unsigned int word, u8 *value)
  82 {
  83         u32 reg;
  84
  85         mutex_lock(&rt2x00dev->csr_mutex);
  86
  87         /*
  88          * Wait until the BBP becomes available, afterwards we
  89          * can safely write the read request into the register.
  90          * After the data has been written, we wait until hardware
  91          * returns the correct value, if at any time the register
  92          * doesn't become available in time, reg will be 0xffffffff
  93          * which means we return 0xff to the caller.
  94          */
  95         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  96                 reg = 0;
  97                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  98                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  99                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 100
 101                 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg);
 102
 103                 WAIT_FOR_BBP(rt2x00dev, &reg);
 104         }
 105
 106         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 107
 108         mutex_unlock(&rt2x00dev->csr_mutex);
 109 }
 110
 111 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 112                                const unsigned int word, const u32 value)
 113 {
 114         u32 reg;
 115
 116         mutex_lock(&rt2x00dev->csr_mutex);
 117
 118         /*
 119          * Wait until the RF becomes available, afterwards we
 120          * can safely write the new data into the register.
 121          */
 122         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 123                 reg = 0;
 124                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 125                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 126                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 127                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 128
 129                 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg);
 130                 rt2x00_rf_write(rt2x00dev, word, value);
 131         }
 132
 133         mutex_unlock(&rt2x00dev->csr_mutex);
 134 }
 135
 136 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 137 {
 138         struct rt2x00_dev *rt2x00dev = eeprom->data;
 139         u32 reg;
 140
 141         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
 142
 143         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 144         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 145         eeprom->reg_data_clock =
 146             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 147         eeprom->reg_chip_select =
 148             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 149 }
 150
 151 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 152 {
 153         struct rt2x00_dev *rt2x00dev = eeprom->data;
 154         u32 reg = 0;
 155
 156         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 159                            !!eeprom->reg_data_clock);
 160         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 161                            !!eeprom->reg_chip_select);
 162
 163         rt2x00mmio_register_write(rt2x00dev, CSR21, reg);
 164 }
 165
 166 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 167 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 168         .owner  = THIS_MODULE,
 169         .csr    = {
 170                 .read           = rt2x00mmio_register_read,
 171                 .write          = rt2x00mmio_register_write,
 172                 .flags          = RT2X00DEBUGFS_OFFSET,
 173                 .word_base      = CSR_REG_BASE,
 174                 .word_size      = sizeof(u32),
 175                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 176         },
 177         .eeprom = {
 178                 .read           = rt2x00_eeprom_read,
 179                 .write          = rt2x00_eeprom_write,
 180                 .word_base      = EEPROM_BASE,
 181                 .word_size      = sizeof(u16),
 182                 .word_count     = EEPROM_SIZE / sizeof(u16),
 183         },
 184         .bbp    = {
 185                 .read           = rt2500pci_bbp_read,
 186                 .write          = rt2500pci_bbp_write,
 187                 .word_base      = BBP_BASE,
 188                 .word_size      = sizeof(u8),
 189                 .word_count     = BBP_SIZE / sizeof(u8),
 190         },
 191         .rf     = {
 192                 .read           = rt2x00_rf_read,
 193                 .write          = rt2500pci_rf_write,
 194                 .word_base      = RF_BASE,
 195                 .word_size      = sizeof(u32),
 196                 .word_count     = RF_SIZE / sizeof(u32),
 197         },
 198 };
 199 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 200
 201 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 202 {
 203         u32 reg;
 204
 205         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
 206         return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 207 }
 208
 209 #ifdef CONFIG_RT2X00_LIB_LEDS
 210 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 211                                      enum led_brightness brightness)
 212 {
 213         struct rt2x00_led *led =
 214             container_of(led_cdev, struct rt2x00_led, led_dev);
 215         unsigned int enabled = brightness != LED_OFF;
 216         u32 reg;
 217
 218         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 219
 220         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 221                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 222         else if (led->type == LED_TYPE_ACTIVITY)
 223                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 224
 225         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 226 }
 227
 228 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 229                                unsigned long *delay_on,
 230                                unsigned long *delay_off)
 231 {
 232         struct rt2x00_led *led =
 233             container_of(led_cdev, struct rt2x00_led, led_dev);
 234         u32 reg;
 235
 236         rt2x00mmio_register_read(led->rt2x00dev, LEDCSR, &reg);
 237         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 238         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 239         rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg);
 240
 241         return 0;
 242 }
 243
 244 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
 245                                struct rt2x00_led *led,
 246                                enum led_type type)
 247 {
 248         led->rt2x00dev = rt2x00dev;
 249         led->type = type;
 250         led->led_dev.brightness_set = rt2500pci_brightness_set;
 251         led->led_dev.blink_set = rt2500pci_blink_set;
 252         led->flags = LED_INITIALIZED;
 253 }
 254 #endif /* CONFIG_RT2X00_LIB_LEDS */
 255
 256 /*
 257  * Configuration handlers.
 258  */
 259 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 260                                     const unsigned int filter_flags)
 261 {
 262         u32 reg;
 263
 264         /*
 265          * Start configuration steps.
 266          * Note that the version error will always be dropped
 267          * and broadcast frames will always be accepted since
 268          * there is no filter for it at this time.
 269          */
 270         rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 271         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 272                            !(filter_flags & FIF_FCSFAIL));
 273         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 274                            !(filter_flags & FIF_PLCPFAIL));
 275         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 276                            !(filter_flags & FIF_CONTROL));
 277         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 278                            !(filter_flags & FIF_PROMISC_IN_BSS));
 279         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 280                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 281                            !rt2x00dev->intf_ap_count);
 282         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 283         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 284                            !(filter_flags & FIF_ALLMULTI));
 285         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 286         rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 287 }
 288
 289 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 290                                   struct rt2x00_intf *intf,
 291                                   struct rt2x00intf_conf *conf,
 292                                   const unsigned int flags)
 293 {
 294         struct data_queue *queue = rt2x00dev->bcn;
 295         unsigned int bcn_preload;
 296         u32 reg;
 297
 298         if (flags & CONFIG_UPDATE_TYPE) {
 299                 /*
 300                  * Enable beacon config
 301                  */
 302                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 303                 rt2x00mmio_register_read(rt2x00dev, BCNCSR1, &reg);
 304                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 305                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 306                 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg);
 307
 308                 /*
 309                  * Enable synchronisation.
 310                  */
 311                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 312                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 313                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 314         }
 315
 316         if (flags & CONFIG_UPDATE_MAC)
 317                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3,
 318                                               conf->mac, sizeof(conf->mac));
 319
 320         if (flags & CONFIG_UPDATE_BSSID)
 321                 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5,
 322                                               conf->bssid, sizeof(conf->bssid));
 323 }
 324
 325 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 326                                  struct rt2x00lib_erp *erp,
 327                                  u32 changed)
 328 {
 329         int preamble_mask;
 330         u32 reg;
 331
 332         /*
 333          * When short preamble is enabled, we should set bit 0x08
 334          */
 335         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 336                 preamble_mask = erp->short_preamble << 3;
 337
 338                 rt2x00mmio_register_read(rt2x00dev, TXCSR1, &reg);
 339                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
 340                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
 341                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 342                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 343                 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg);
 344
 345                 rt2x00mmio_register_read(rt2x00dev, ARCSR2, &reg);
 346                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 347                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 348                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 349                                    GET_DURATION(ACK_SIZE, 10));
 350                 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg);
 351
 352                 rt2x00mmio_register_read(rt2x00dev, ARCSR3, &reg);
 353                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 354                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 355                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 356                                    GET_DURATION(ACK_SIZE, 20));
 357                 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg);
 358
 359                 rt2x00mmio_register_read(rt2x00dev, ARCSR4, &reg);
 360                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 361                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 362                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 363                                    GET_DURATION(ACK_SIZE, 55));
 364                 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg);
 365
 366                 rt2x00mmio_register_read(rt2x00dev, ARCSR5, &reg);
 367                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 368                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 369                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
 370                                    GET_DURATION(ACK_SIZE, 110));
 371                 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg);
 372         }
 373
 374         if (changed & BSS_CHANGED_BASIC_RATES)
 375                 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 376
 377         if (changed & BSS_CHANGED_ERP_SLOT) {
 378                 rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 379                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 380                 rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 381
 382                 rt2x00mmio_register_read(rt2x00dev, CSR18, &reg);
 383                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 384                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 385                 rt2x00mmio_register_write(rt2x00dev, CSR18, reg);
 386
 387                 rt2x00mmio_register_read(rt2x00dev, CSR19, &reg);
 388                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 389                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 390                 rt2x00mmio_register_write(rt2x00dev, CSR19, reg);
 391         }
 392
 393         if (changed & BSS_CHANGED_BEACON_INT) {
 394                 rt2x00mmio_register_read(rt2x00dev, CSR12, &reg);
 395                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 396                                    erp->beacon_int * 16);
 397                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 398                                    erp->beacon_int * 16);
 399                 rt2x00mmio_register_write(rt2x00dev, CSR12, reg);
 400         }
 401
 402 }
 403
 404 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
 405                                  struct antenna_setup *ant)
 406 {
 407         u32 reg;
 408         u8 r14;
 409         u8 r2;
 410
 411         /*
 412          * We should never come here because rt2x00lib is supposed
 413          * to catch this and send us the correct antenna explicitely.
 414          */
 415         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 416                ant->tx == ANTENNA_SW_DIVERSITY);
 417
 418         rt2x00mmio_register_read(rt2x00dev, BBPCSR1, &reg);
 419         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 420         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 421
 422         /*
 423          * Configure the TX antenna.
 424          */
 425         switch (ant->tx) {
 426         case ANTENNA_A:
 427                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 428                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 429                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 430                 break;
 431         case ANTENNA_B:
 432         default:
 433                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 434                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 435                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 436                 break;
 437         }
 438
 439         /*
 440          * Configure the RX antenna.
 441          */
 442         switch (ant->rx) {
 443         case ANTENNA_A:
 444                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 445                 break;
 446         case ANTENNA_B:
 447         default:
 448                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 449                 break;
 450         }
 451
 452         /*
 453          * RT2525E and RT5222 need to flip TX I/Q
 454          */
 455         if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) {
 456                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 457                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 458                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 459
 460                 /*
 461                  * RT2525E does not need RX I/Q Flip.
 462                  */
 463                 if (rt2x00_rf(rt2x00dev, RF2525E))
 464                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 465         } else {
 466                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 467                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 468         }
 469
 470         rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg);
 471         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 472         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 473 }
 474
 475 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 476                                      struct rf_channel *rf, const int txpower)
 477 {
 478         u8 r70;
 479
 480         /*
 481          * Set TXpower.
 482          */
 483         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 484
 485         /*
 486          * Switch on tuning bits.
 487          * For RT2523 devices we do not need to update the R1 register.
 488          */
 489         if (!rt2x00_rf(rt2x00dev, RF2523))
 490                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 491         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 492
 493         /*
 494          * For RT2525 we should first set the channel to half band higher.
 495          */
 496         if (rt2x00_rf(rt2x00dev, RF2525)) {
 497                 static const u32 vals[] = {
 498                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 499                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 500                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 501                         0x00080d2e, 0x00080d3a
 502                 };
 503
 504                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 505                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 506                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 507                 if (rf->rf4)
 508                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 509         }
 510
 511         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 512         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 513         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 514         if (rf->rf4)
 515                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 516
 517         /*
 518          * Channel 14 requires the Japan filter bit to be set.
 519          */
 520         r70 = 0x46;
 521         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 522         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 523
 524         msleep(1);
 525
 526         /*
 527          * Switch off tuning bits.
 528          * For RT2523 devices we do not need to update the R1 register.
 529          */
 530         if (!rt2x00_rf(rt2x00dev, RF2523)) {
 531                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 532                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 533         }
 534
 535         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 536         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 537
 538         /*
 539          * Clear false CRC during channel switch.
 540          */
 541         rt2x00mmio_register_read(rt2x00dev, CNT0, &rf->rf1);
 542 }
 543
 544 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 545                                      const int txpower)
 546 {
 547         u32 rf3;
 548
 549         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 550         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 551         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 552 }
 553
 554 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 555                                          struct rt2x00lib_conf *libconf)
 556 {
 557         u32 reg;
 558
 559         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 560         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 561                            libconf->conf->long_frame_max_tx_count);
 562         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 563                            libconf->conf->short_frame_max_tx_count);
 564         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 565 }
 566
 567 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
 568                                 struct rt2x00lib_conf *libconf)
 569 {
 570         enum dev_state state =
 571             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 572                 STATE_SLEEP : STATE_AWAKE;
 573         u32 reg;
 574
 575         if (state == STATE_SLEEP) {
 576                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 577                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 578                                    (rt2x00dev->beacon_int - 20) * 16);
 579                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 580                                    libconf->conf->listen_interval - 1);
 581
 582                 /* We must first disable autowake before it can be enabled */
 583                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 584                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 585
 586                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 587                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 588         } else {
 589                 rt2x00mmio_register_read(rt2x00dev, CSR20, &reg);
 590                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 591                 rt2x00mmio_register_write(rt2x00dev, CSR20, reg);
 592         }
 593
 594         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 595 }
 596
 597 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 598                              struct rt2x00lib_conf *libconf,
 599                              const unsigned int flags)
 600 {
 601         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 602                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 603                                          libconf->conf->power_level);
 604         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 605             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 606                 rt2500pci_config_txpower(rt2x00dev,
 607                                          libconf->conf->power_level);
 608         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 609                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
 610         if (flags & IEEE80211_CONF_CHANGE_PS)
 611                 rt2500pci_config_ps(rt2x00dev, libconf);
 612 }
 613
 614 /*
 615  * Link tuning
 616  */
 617 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 618                                  struct link_qual *qual)
 619 {
 620         u32 reg;
 621
 622         /*
 623          * Update FCS error count from register.
 624          */
 625         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
 626         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 627
 628         /*
 629          * Update False CCA count from register.
 630          */
 631         rt2x00mmio_register_read(rt2x00dev, CNT3, &reg);
 632         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 633 }
 634
 635 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 636                                      struct link_qual *qual, u8 vgc_level)
 637 {
 638         if (qual->vgc_level_reg != vgc_level) {
 639                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
 640                 qual->vgc_level = vgc_level;
 641                 qual->vgc_level_reg = vgc_level;
 642         }
 643 }
 644
 645 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 646                                   struct link_qual *qual)
 647 {
 648         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
 649 }
 650
 651 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 652                                  struct link_qual *qual, const u32 count)
 653 {
 654         /*
 655          * To prevent collisions with MAC ASIC on chipsets
 656          * up to version C the link tuning should halt after 20
 657          * seconds while being associated.
 658          */
 659         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D &&
 660             rt2x00dev->intf_associated && count > 20)
 661                 return;
 662
 663         /*
 664          * Chipset versions C and lower should directly continue
 665          * to the dynamic CCA tuning. Chipset version D and higher
 666          * should go straight to dynamic CCA tuning when they
 667          * are not associated.
 668          */
 669         if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D ||
 670             !rt2x00dev->intf_associated)
 671                 goto dynamic_cca_tune;
 672
 673         /*
 674          * A too low RSSI will cause too much false CCA which will
 675          * then corrupt the R17 tuning. To remidy this the tuning should
 676          * be stopped (While making sure the R17 value will not exceed limits)
 677          */
 678         if (qual->rssi < -80 && count > 20) {
 679                 if (qual->vgc_level_reg >= 0x41)
 680                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 681                 return;
 682         }
 683
 684         /*
 685          * Special big-R17 for short distance
 686          */
 687         if (qual->rssi >= -58) {
 688                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
 689                 return;
 690         }
 691
 692         /*
 693          * Special mid-R17 for middle distance
 694          */
 695         if (qual->rssi >= -74) {
 696                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
 697                 return;
 698         }
 699
 700         /*
 701          * Leave short or middle distance condition, restore r17
 702          * to the dynamic tuning range.
 703          */
 704         if (qual->vgc_level_reg >= 0x41) {
 705                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
 706                 return;
 707         }
 708
 709 dynamic_cca_tune:
 710
 711         /*
 712          * R17 is inside the dynamic tuning range,
 713          * start tuning the link based on the false cca counter.
 714          */
 715         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40)
 716                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
 717         else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32)
 718                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
 719 }
 720
 721 /*
 722  * Queue handlers.
 723  */
 724 static void rt2500pci_start_queue(struct data_queue *queue)
 725 {
 726         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 727         u32 reg;
 728
 729         switch (queue->qid) {
 730         case QID_RX:
 731                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 732                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
 733                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 734                 break;
 735         case QID_BEACON:
 736                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 737                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 738                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 739                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
 740                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 741                 break;
 742         default:
 743                 break;
 744         }
 745 }
 746
 747 static void rt2500pci_kick_queue(struct data_queue *queue)
 748 {
 749         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 750         u32 reg;
 751
 752         switch (queue->qid) {
 753         case QID_AC_VO:
 754                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 755                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
 756                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 757                 break;
 758         case QID_AC_VI:
 759                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 760                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
 761                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 762                 break;
 763         case QID_ATIM:
 764                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 765                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
 766                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 767                 break;
 768         default:
 769                 break;
 770         }
 771 }
 772
 773 static void rt2500pci_stop_queue(struct data_queue *queue)
 774 {
 775         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 776         u32 reg;
 777
 778         switch (queue->qid) {
 779         case QID_AC_VO:
 780         case QID_AC_VI:
 781         case QID_ATIM:
 782                 rt2x00mmio_register_read(rt2x00dev, TXCSR0, &reg);
 783                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 784                 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg);
 785                 break;
 786         case QID_RX:
 787                 rt2x00mmio_register_read(rt2x00dev, RXCSR0, &reg);
 788                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
 789                 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg);
 790                 break;
 791         case QID_BEACON:
 792                 rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 793                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 794                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 795                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 796                 rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 797
 798                 /*
 799                  * Wait for possibly running tbtt tasklets.
 800                  */
 801                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 802                 break;
 803         default:
 804                 break;
 805         }
 806 }
 807
 808 /*
 809  * Initialization functions.
 810  */
 811 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
 812 {
 813         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 814         u32 word;
 815
 816         if (entry->queue->qid == QID_RX) {
 817                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 818
 819                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 820         } else {
 821                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 822
 823                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 824                         rt2x00_get_field32(word, TXD_W0_VALID));
 825         }
 826 }
 827
 828 static void rt2500pci_clear_entry(struct queue_entry *entry)
 829 {
 830         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
 831         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 832         u32 word;
 833
 834         if (entry->queue->qid == QID_RX) {
 835                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 836                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 837                 rt2x00_desc_write(entry_priv->desc, 1, word);
 838
 839                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 840                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 841                 rt2x00_desc_write(entry_priv->desc, 0, word);
 842         } else {
 843                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 844                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 845                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 846                 rt2x00_desc_write(entry_priv->desc, 0, word);
 847         }
 848 }
 849
 850 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 851 {
 852         struct queue_entry_priv_mmio *entry_priv;
 853         u32 reg;
 854
 855         /*
 856          * Initialize registers.
 857          */
 858         rt2x00mmio_register_read(rt2x00dev, TXCSR2, &reg);
 859         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 860         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 861         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
 862         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 863         rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg);
 864
 865         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 866         rt2x00mmio_register_read(rt2x00dev, TXCSR3, &reg);
 867         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 868                            entry_priv->desc_dma);
 869         rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg);
 870
 871         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 872         rt2x00mmio_register_read(rt2x00dev, TXCSR5, &reg);
 873         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 874                            entry_priv->desc_dma);
 875         rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg);
 876
 877         entry_priv = rt2x00dev->atim->entries[0].priv_data;
 878         rt2x00mmio_register_read(rt2x00dev, TXCSR4, &reg);
 879         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 880                            entry_priv->desc_dma);
 881         rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg);
 882
 883         entry_priv = rt2x00dev->bcn->entries[0].priv_data;
 884         rt2x00mmio_register_read(rt2x00dev, TXCSR6, &reg);
 885         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 886                            entry_priv->desc_dma);
 887         rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg);
 888
 889         rt2x00mmio_register_read(rt2x00dev, RXCSR1, &reg);
 890         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 891         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 892         rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg);
 893
 894         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 895         rt2x00mmio_register_read(rt2x00dev, RXCSR2, &reg);
 896         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 897                            entry_priv->desc_dma);
 898         rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg);
 899
 900         return 0;
 901 }
 902
 903 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 904 {
 905         u32 reg;
 906
 907         rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002);
 908         rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002);
 909         rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002);
 910         rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002);
 911
 912         rt2x00mmio_register_read(rt2x00dev, TIMECSR, &reg);
 913         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 914         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 915         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 916         rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg);
 917
 918         rt2x00mmio_register_read(rt2x00dev, CSR9, &reg);
 919         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 920                            rt2x00dev->rx->data_size / 128);
 921         rt2x00mmio_register_write(rt2x00dev, CSR9, reg);
 922
 923         /*
 924          * Always use CWmin and CWmax set in descriptor.
 925          */
 926         rt2x00mmio_register_read(rt2x00dev, CSR11, &reg);
 927         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 928         rt2x00mmio_register_write(rt2x00dev, CSR11, reg);
 929
 930         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
 931         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 932         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 933         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 934         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 935         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 936         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 937         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 938         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 939         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
 940
 941         rt2x00mmio_register_write(rt2x00dev, CNT3, 0);
 942
 943         rt2x00mmio_register_read(rt2x00dev, TXCSR8, &reg);
 944         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 945         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 946         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 947         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 948         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 949         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 950         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 951         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 952         rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg);
 953
 954         rt2x00mmio_register_read(rt2x00dev, ARTCSR0, &reg);
 955         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 956         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 957         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 958         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 959         rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg);
 960
 961         rt2x00mmio_register_read(rt2x00dev, ARTCSR1, &reg);
 962         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 963         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 964         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 965         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 966         rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg);
 967
 968         rt2x00mmio_register_read(rt2x00dev, ARTCSR2, &reg);
 969         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 970         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 971         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 972         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 973         rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg);
 974
 975         rt2x00mmio_register_read(rt2x00dev, RXCSR3, &reg);
 976         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 977         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 978         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 979         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 980         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 981         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 982         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 983         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 984         rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg);
 985
 986         rt2x00mmio_register_read(rt2x00dev, PCICSR, &reg);
 987         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 988         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 989         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 990         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 991         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 992         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 993         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 994         rt2x00mmio_register_write(rt2x00dev, PCICSR, reg);
 995
 996         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 997
 998         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 999         rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0);
1000
1001         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1002                 return -EBUSY;
1003
1004         rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223);
1005         rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518);
1006
1007         rt2x00mmio_register_read(rt2x00dev, MACCSR2, &reg);
1008         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
1009         rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg);
1010
1011         rt2x00mmio_register_read(rt2x00dev, RALINKCSR, &reg);
1012         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
1013         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
1014         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
1015         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
1016         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
1017         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
1018         rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg);
1019
1020         rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200);
1021
1022         rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
1023
1024         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
1025         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
1026         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
1027         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
1028         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1029
1030         rt2x00mmio_register_read(rt2x00dev, CSR1, &reg);
1031         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1032         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1033         rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1034
1035         /*
1036          * We must clear the FCS and FIFO error count.
1037          * These registers are cleared on read,
1038          * so we may pass a useless variable to store the value.
1039          */
1040         rt2x00mmio_register_read(rt2x00dev, CNT0, &reg);
1041         rt2x00mmio_register_read(rt2x00dev, CNT4, &reg);
1042
1043         return 0;
1044 }
1045
1046 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1047 {
1048         unsigned int i;
1049         u8 value;
1050
1051         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1052                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1053                 if ((value != 0xff) && (value != 0x00))
1054                         return 0;
1055                 udelay(REGISTER_BUSY_DELAY);
1056         }
1057
1058         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1059         return -EACCES;
1060 }
1061
1062 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1063 {
1064         unsigned int i;
1065         u16 eeprom;
1066         u8 reg_id;
1067         u8 value;
1068
1069         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
1070                 return -EACCES;
1071
1072         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1073         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1074         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1075         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1076         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1077         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1078         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1079         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1080         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1081         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1082         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1083         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1084         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1085         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1086         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1087         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1088         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1089         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1090         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1091         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1092         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1093         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1094         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1095         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1096         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1097         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1098         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1099         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1100         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1101         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1102
1103         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1104                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1105
1106                 if (eeprom != 0xffff && eeprom != 0x0000) {
1107                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1108                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1109                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1110                 }
1111         }
1112
1113         return 0;
1114 }
1115
1116 /*
1117  * Device state switch handlers.
1118  */
1119 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1120                                  enum dev_state state)
1121 {
1122         int mask = (state == STATE_RADIO_IRQ_OFF);
1123         u32 reg;
1124         unsigned long flags;
1125
1126         /*
1127          * When interrupts are being enabled, the interrupt registers
1128          * should clear the register to assure a clean state.
1129          */
1130         if (state == STATE_RADIO_IRQ_ON) {
1131                 rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1132                 rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1133         }
1134
1135         /*
1136          * Only toggle the interrupts bits we are going to use.
1137          * Non-checked interrupt bits are disabled by default.
1138          */
1139         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1140
1141         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1142         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1143         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1144         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1145         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1146         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1147         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1148
1149         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1150
1151         if (state == STATE_RADIO_IRQ_OFF) {
1152                 /*
1153                  * Ensure that all tasklets are finished.
1154                  */
1155                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1156                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1157                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1158         }
1159 }
1160
1161 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1162 {
1163         /*
1164          * Initialize all registers.
1165          */
1166         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1167                      rt2500pci_init_registers(rt2x00dev) ||
1168                      rt2500pci_init_bbp(rt2x00dev)))
1169                 return -EIO;
1170
1171         return 0;
1172 }
1173
1174 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1175 {
1176         /*
1177          * Disable power
1178          */
1179         rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0);
1180 }
1181
1182 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1183                                enum dev_state state)
1184 {
1185         u32 reg, reg2;
1186         unsigned int i;
1187         char put_to_sleep;
1188         char bbp_state;
1189         char rf_state;
1190
1191         put_to_sleep = (state != STATE_AWAKE);
1192
1193         rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg);
1194         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1195         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1196         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1197         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1198         rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1199
1200         /*
1201          * Device is not guaranteed to be in the requested state yet.
1202          * We must wait until the register indicates that the
1203          * device has entered the correct state.
1204          */
1205         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1206                 rt2x00mmio_register_read(rt2x00dev, PWRCSR1, &reg2);
1207                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1208                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1209                 if (bbp_state == state && rf_state == state)
1210                         return 0;
1211                 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg);
1212                 msleep(10);
1213         }
1214
1215         return -EBUSY;
1216 }
1217
1218 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1219                                       enum dev_state state)
1220 {
1221         int retval = 0;
1222
1223         switch (state) {
1224         case STATE_RADIO_ON:
1225                 retval = rt2500pci_enable_radio(rt2x00dev);
1226                 break;
1227         case STATE_RADIO_OFF:
1228                 rt2500pci_disable_radio(rt2x00dev);
1229                 break;
1230         case STATE_RADIO_IRQ_ON:
1231         case STATE_RADIO_IRQ_OFF:
1232                 rt2500pci_toggle_irq(rt2x00dev, state);
1233                 break;
1234         case STATE_DEEP_SLEEP:
1235         case STATE_SLEEP:
1236         case STATE_STANDBY:
1237         case STATE_AWAKE:
1238                 retval = rt2500pci_set_state(rt2x00dev, state);
1239                 break;
1240         default:
1241                 retval = -ENOTSUPP;
1242                 break;
1243         }
1244
1245         if (unlikely(retval))
1246                 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1247                            state, retval);
1248
1249         return retval;
1250 }
1251
1252 /*
1253  * TX descriptor initialization
1254  */
1255 static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1256                                     struct txentry_desc *txdesc)
1257 {
1258         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1259         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1260         __le32 *txd = entry_priv->desc;
1261         u32 word;
1262
1263         /*
1264          * Start writing the descriptor words.
1265          */
1266         rt2x00_desc_read(txd, 1, &word);
1267         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1268         rt2x00_desc_write(txd, 1, word);
1269
1270         rt2x00_desc_read(txd, 2, &word);
1271         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1272         rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
1273         rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
1274         rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
1275         rt2x00_desc_write(txd, 2, word);
1276
1277         rt2x00_desc_read(txd, 3, &word);
1278         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1279         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1280         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1281                            txdesc->u.plcp.length_low);
1282         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1283                            txdesc->u.plcp.length_high);
1284         rt2x00_desc_write(txd, 3, word);
1285
1286         rt2x00_desc_read(txd, 10, &word);
1287         rt2x00_set_field32(&word, TXD_W10_RTS,
1288                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1289         rt2x00_desc_write(txd, 10, word);
1290
1291         /*
1292          * Writing TXD word 0 must the last to prevent a race condition with
1293          * the device, whereby the device may take hold of the TXD before we
1294          * finished updating it.
1295          */
1296         rt2x00_desc_read(txd, 0, &word);
1297         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1298         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1299         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1300                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1301         rt2x00_set_field32(&word, TXD_W0_ACK,
1302                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1303         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1304                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1305         rt2x00_set_field32(&word, TXD_W0_OFDM,
1306                            (txdesc->rate_mode == RATE_MODE_OFDM));
1307         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1308         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1309         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1310                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1311         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1312         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1313         rt2x00_desc_write(txd, 0, word);
1314
1315         /*
1316          * Register descriptor details in skb frame descriptor.
1317          */
1318         skbdesc->desc = txd;
1319         skbdesc->desc_len = TXD_DESC_SIZE;
1320 }
1321
1322 /*
1323  * TX data initialization
1324  */
1325 static void rt2500pci_write_beacon(struct queue_entry *entry,
1326                                    struct txentry_desc *txdesc)
1327 {
1328         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1329         u32 reg;
1330
1331         /*
1332          * Disable beaconing while we are reloading the beacon data,
1333          * otherwise we might be sending out invalid data.
1334          */
1335         rt2x00mmio_register_read(rt2x00dev, CSR14, &reg);
1336         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1337         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1338
1339         if (rt2x00queue_map_txskb(entry)) {
1340                 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n");
1341                 goto out;
1342         }
1343
1344         /*
1345          * Write the TX descriptor for the beacon.
1346          */
1347         rt2500pci_write_tx_desc(entry, txdesc);
1348
1349         /*
1350          * Dump beacon to userspace through debugfs.
1351          */
1352         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1353 out:
1354         /*
1355          * Enable beaconing again.
1356          */
1357         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1358         rt2x00mmio_register_write(rt2x00dev, CSR14, reg);
1359 }
1360
1361 /*
1362  * RX control handlers
1363  */
1364 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1365                                   struct rxdone_entry_desc *rxdesc)
1366 {
1367         struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1368         u32 word0;
1369         u32 word2;
1370
1371         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1372         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1373
1374         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1375                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1376         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1377                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1378
1379         /*
1380          * Obtain the status about this packet.
1381          * When frame was received with an OFDM bitrate,
1382          * the signal is the PLCP value. If it was received with
1383          * a CCK bitrate the signal is the rate in 100kbit/s.
1384          */
1385         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1386         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1387             entry->queue->rt2x00dev->rssi_offset;
1388         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1389
1390         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1391                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1392         else
1393                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1394         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1395                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1396 }
1397
1398 /*
1399  * Interrupt functions.
1400  */
1401 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1402                              const enum data_queue_qid queue_idx)
1403 {
1404         struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1405         struct queue_entry_priv_mmio *entry_priv;
1406         struct queue_entry *entry;
1407         struct txdone_entry_desc txdesc;
1408         u32 word;
1409
1410         while (!rt2x00queue_empty(queue)) {
1411                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1412                 entry_priv = entry->priv_data;
1413                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1414
1415                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1416                     !rt2x00_get_field32(word, TXD_W0_VALID))
1417                         break;
1418
1419                 /*
1420                  * Obtain the status about this packet.
1421                  */
1422                 txdesc.flags = 0;
1423                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1424                 case 0: /* Success */
1425                 case 1: /* Success with retry */
1426                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1427                         break;
1428                 case 2: /* Failure, excessive retries */
1429                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1430                         /* Don't break, this is a failed frame! */
1431                 default: /* Failure */
1432                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1433                 }
1434                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1435
1436                 rt2x00lib_txdone(entry, &txdesc);
1437         }
1438 }
1439
1440 static inline void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1441                                               struct rt2x00_field32 irq_field)
1442 {
1443         u32 reg;
1444
1445         /*
1446          * Enable a single interrupt. The interrupt mask register
1447          * access needs locking.
1448          */
1449         spin_lock_irq(&rt2x00dev->irqmask_lock);
1450
1451         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1452         rt2x00_set_field32(&reg, irq_field, 0);
1453         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1454
1455         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1456 }
1457
1458 static void rt2500pci_txstatus_tasklet(unsigned long data)
1459 {
1460         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1461         u32 reg;
1462
1463         /*
1464          * Handle all tx queues.
1465          */
1466         rt2500pci_txdone(rt2x00dev, QID_ATIM);
1467         rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1468         rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1469
1470         /*
1471          * Enable all TXDONE interrupts again.
1472          */
1473         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1474                 spin_lock_irq(&rt2x00dev->irqmask_lock);
1475
1476                 rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1477                 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1478                 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1479                 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1480                 rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1481
1482                 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1483         }
1484 }
1485
1486 static void rt2500pci_tbtt_tasklet(unsigned long data)
1487 {
1488         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1489         rt2x00lib_beacondone(rt2x00dev);
1490         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1491                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1492 }
1493
1494 static void rt2500pci_rxdone_tasklet(unsigned long data)
1495 {
1496         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1497         if (rt2x00mmio_rxdone(rt2x00dev))
1498                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1499         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1500                 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1501 }
1502
1503 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1504 {
1505         struct rt2x00_dev *rt2x00dev = dev_instance;
1506         u32 reg, mask;
1507
1508         /*
1509          * Get the interrupt sources & saved to local variable.
1510          * Write register value back to clear pending interrupts.
1511          */
1512         rt2x00mmio_register_read(rt2x00dev, CSR7, &reg);
1513         rt2x00mmio_register_write(rt2x00dev, CSR7, reg);
1514
1515         if (!reg)
1516                 return IRQ_NONE;
1517
1518         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1519                 return IRQ_HANDLED;
1520
1521         mask = reg;
1522
1523         /*
1524          * Schedule tasklets for interrupt handling.
1525          */
1526         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1527                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1528
1529         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1530                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1531
1532         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1533             rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1534             rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1535                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1536                 /*
1537                  * Mask out all txdone interrupts.
1538                  */
1539                 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1540                 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1541                 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1542         }
1543
1544         /*
1545          * Disable all interrupts for which a tasklet was scheduled right now,
1546          * the tasklet will reenable the appropriate interrupts.
1547          */
1548         spin_lock(&rt2x00dev->irqmask_lock);
1549
1550         rt2x00mmio_register_read(rt2x00dev, CSR8, &reg);
1551         reg |= mask;
1552         rt2x00mmio_register_write(rt2x00dev, CSR8, reg);
1553
1554         spin_unlock(&rt2x00dev->irqmask_lock);
1555
1556         return IRQ_HANDLED;
1557 }
1558
1559 /*
1560  * Device probe functions.
1561  */
1562 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1563 {
1564         struct eeprom_93cx6 eeprom;
1565         u32 reg;
1566         u16 word;
1567         u8 *mac;
1568
1569         rt2x00mmio_register_read(rt2x00dev, CSR21, &reg);
1570
1571         eeprom.data = rt2x00dev;
1572         eeprom.register_read = rt2500pci_eepromregister_read;
1573         eeprom.register_write = rt2500pci_eepromregister_write;
1574         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1575             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1576         eeprom.reg_data_in = 0;
1577         eeprom.reg_data_out = 0;
1578         eeprom.reg_data_clock = 0;
1579         eeprom.reg_chip_select = 0;
1580
1581         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1582                                EEPROM_SIZE / sizeof(u16));
1583
1584         /*
1585          * Start validation of the data that has been read.
1586          */
1587         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1588         if (!is_valid_ether_addr(mac)) {
1589                 eth_random_addr(mac);
1590                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
1591         }
1592
1593         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1594         if (word == 0xffff) {
1595                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1596                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1597                                    ANTENNA_SW_DIVERSITY);
1598                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1599                                    ANTENNA_SW_DIVERSITY);
1600                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1601                                    LED_MODE_DEFAULT);
1602                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1603                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1604                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1605                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1606                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
1607         }
1608
1609         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1610         if (word == 0xffff) {
1611                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1612                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1613                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1614                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1615                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
1616         }
1617
1618         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1619         if (word == 0xffff) {
1620                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1621                                    DEFAULT_RSSI_OFFSET);
1622                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1623                 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n",
1624                                   word);
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1631 {
1632         u32 reg;
1633         u16 value;
1634         u16 eeprom;
1635
1636         /*
1637          * Read EEPROM word for configuration.
1638          */
1639         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1640
1641         /*
1642          * Identify RF chipset.
1643          */
1644         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1645         rt2x00mmio_register_read(rt2x00dev, CSR0, &reg);
1646         rt2x00_set_chip(rt2x00dev, RT2560, value,
1647                         rt2x00_get_field32(reg, CSR0_REVISION));
1648
1649         if (!rt2x00_rf(rt2x00dev, RF2522) &&
1650             !rt2x00_rf(rt2x00dev, RF2523) &&
1651             !rt2x00_rf(rt2x00dev, RF2524) &&
1652             !rt2x00_rf(rt2x00dev, RF2525) &&
1653             !rt2x00_rf(rt2x00dev, RF2525E) &&
1654             !rt2x00_rf(rt2x00dev, RF5222)) {
1655                 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
1656                 return -ENODEV;
1657         }
1658
1659         /*
1660          * Identify default antenna configuration.
1661          */
1662         rt2x00dev->default_ant.tx =
1663             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1664         rt2x00dev->default_ant.rx =
1665             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1666
1667         /*
1668          * Store led mode, for correct led behaviour.
1669          */
1670 #ifdef CONFIG_RT2X00_LIB_LEDS
1671         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1672
1673         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1674         if (value == LED_MODE_TXRX_ACTIVITY ||
1675             value == LED_MODE_DEFAULT ||
1676             value == LED_MODE_ASUS)
1677                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1678                                    LED_TYPE_ACTIVITY);
1679 #endif /* CONFIG_RT2X00_LIB_LEDS */
1680
1681         /*
1682          * Detect if this device has an hardware controlled radio.
1683          */
1684         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) {
1685                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1686                 /*
1687                  * On this device RFKILL initialized during probe does not work.
1688                  */
1689                 __set_bit(REQUIRE_DELAYED_RFKILL, &rt2x00dev->cap_flags);
1690         }
1691
1692         /*
1693          * Check if the BBP tuning should be enabled.
1694          */
1695         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1696         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1697                 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1698
1699         /*
1700          * Read the RSSI <-> dBm offset information.
1701          */
1702         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1703         rt2x00dev->rssi_offset =
1704             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1705
1706         return 0;
1707 }
1708
1709 /*
1710  * RF value list for RF2522
1711  * Supports: 2.4 GHz
1712  */
1713 static const struct rf_channel rf_vals_bg_2522[] = {
1714         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1715         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1716         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1717         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1718         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1719         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1720         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1721         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1722         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1723         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1724         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1725         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1726         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1727         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1728 };
1729
1730 /*
1731  * RF value list for RF2523
1732  * Supports: 2.4 GHz
1733  */
1734 static const struct rf_channel rf_vals_bg_2523[] = {
1735         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1736         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1737         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1738         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1739         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1740         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1741         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1742         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1743         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1744         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1745         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1746         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1747         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1748         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1749 };
1750
1751 /*
1752  * RF value list for RF2524
1753  * Supports: 2.4 GHz
1754  */
1755 static const struct rf_channel rf_vals_bg_2524[] = {
1756         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1757         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1758         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1759         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1760         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1761         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1762         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1763         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1764         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1765         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1766         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1767         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1768         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1769         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1770 };
1771
1772 /*
1773  * RF value list for RF2525
1774  * Supports: 2.4 GHz
1775  */
1776 static const struct rf_channel rf_vals_bg_2525[] = {
1777         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1778         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1779         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1780         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1781         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1782         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1783         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1784         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1785         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1786         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1787         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1788         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1789         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1790         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1791 };
1792
1793 /*
1794  * RF value list for RF2525e
1795  * Supports: 2.4 GHz
1796  */
1797 static const struct rf_channel rf_vals_bg_2525e[] = {
1798         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1799         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1800         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1801         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1802         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1803         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1804         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1805         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1806         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1807         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1808         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1809         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1810         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1811         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1812 };
1813
1814 /*
1815  * RF value list for RF5222
1816  * Supports: 2.4 GHz & 5.2 GHz
1817  */
1818 static const struct rf_channel rf_vals_5222[] = {
1819         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1820         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1821         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1822         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1823         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1824         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1825         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1826         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1827         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1828         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1829         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1830         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1831         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1832         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1833
1834         /* 802.11 UNI / HyperLan 2 */
1835         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1836         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1837         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1838         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1839         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1840         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1841         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1842         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1843
1844         /* 802.11 HyperLan 2 */
1845         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1846         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1847         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1848         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1849         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1850         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1851         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1852         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1853         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1854         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1855
1856         /* 802.11 UNII */
1857         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1858         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1859         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1860         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1861         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1862 };
1863
1864 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1865 {
1866         struct hw_mode_spec *spec = &rt2x00dev->spec;
1867         struct channel_info *info;
1868         char *tx_power;
1869         unsigned int i;
1870
1871         /*
1872          * Initialize all hw fields.
1873          */
1874         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1875                                IEEE80211_HW_SIGNAL_DBM |
1876                                IEEE80211_HW_SUPPORTS_PS |
1877                                IEEE80211_HW_PS_NULLFUNC_STACK;
1878
1879         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1880         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1881                                 rt2x00_eeprom_addr(rt2x00dev,
1882                                                    EEPROM_MAC_ADDR_0));
1883
1884         /*
1885          * Disable powersaving as default.
1886          */
1887         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1888
1889         /*
1890          * Initialize hw_mode information.
1891          */
1892         spec->supported_bands = SUPPORT_BAND_2GHZ;
1893         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1894
1895         if (rt2x00_rf(rt2x00dev, RF2522)) {
1896                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1897                 spec->channels = rf_vals_bg_2522;
1898         } else if (rt2x00_rf(rt2x00dev, RF2523)) {
1899                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1900                 spec->channels = rf_vals_bg_2523;
1901         } else if (rt2x00_rf(rt2x00dev, RF2524)) {
1902                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1903                 spec->channels = rf_vals_bg_2524;
1904         } else if (rt2x00_rf(rt2x00dev, RF2525)) {
1905                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1906                 spec->channels = rf_vals_bg_2525;
1907         } else if (rt2x00_rf(rt2x00dev, RF2525E)) {
1908                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1909                 spec->channels = rf_vals_bg_2525e;
1910         } else if (rt2x00_rf(rt2x00dev, RF5222)) {
1911                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1912                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1913                 spec->channels = rf_vals_5222;
1914         }
1915
1916         /*
1917          * Create channel information array
1918          */
1919         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1920         if (!info)
1921                 return -ENOMEM;
1922
1923         spec->channels_info = info;
1924
1925         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1926         for (i = 0; i < 14; i++) {
1927                 info[i].max_power = MAX_TXPOWER;
1928                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1929         }
1930
1931         if (spec->num_channels > 14) {
1932                 for (i = 14; i < spec->num_channels; i++) {
1933                         info[i].max_power = MAX_TXPOWER;
1934                         info[i].default_power1 = DEFAULT_TXPOWER;
1935                 }
1936         }
1937
1938         return 0;
1939 }
1940
1941 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1942 {
1943         int retval;
1944         u32 reg;
1945
1946         /*
1947          * Allocate eeprom data.
1948          */
1949         retval = rt2500pci_validate_eeprom(rt2x00dev);
1950         if (retval)
1951                 return retval;
1952
1953         retval = rt2500pci_init_eeprom(rt2x00dev);
1954         if (retval)
1955                 return retval;
1956
1957         /*
1958          * Enable rfkill polling by setting GPIO direction of the
1959          * rfkill switch GPIO pin correctly.
1960          */
1961         rt2x00mmio_register_read(rt2x00dev, GPIOCSR, &reg);
1962         rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1963         rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg);
1964
1965         /*
1966          * Initialize hw specifications.
1967          */
1968         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1969         if (retval)
1970                 return retval;
1971
1972         /*
1973          * This device requires the atim queue and DMA-mapped skbs.
1974          */
1975         __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1976         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1977         __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1978
1979         /*
1980          * Set the rssi offset.
1981          */
1982         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1983
1984         return 0;
1985 }
1986
1987 /*
1988  * IEEE80211 stack callback functions.
1989  */
1990 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw,
1991                              struct ieee80211_vif *vif)
1992 {
1993         struct rt2x00_dev *rt2x00dev = hw->priv;
1994         u64 tsf;
1995         u32 reg;
1996
1997         rt2x00mmio_register_read(rt2x00dev, CSR17, &reg);
1998         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1999         rt2x00mmio_register_read(rt2x00dev, CSR16, &reg);
2000         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
2001
2002         return tsf;
2003 }
2004
2005 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
2006 {
2007         struct rt2x00_dev *rt2x00dev = hw->priv;
2008         u32 reg;
2009
2010         rt2x00mmio_register_read(rt2x00dev, CSR15, &reg);
2011         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
2012 }
2013
2014 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2015         .tx                     = rt2x00mac_tx,
2016         .start                  = rt2x00mac_start,
2017         .stop                   = rt2x00mac_stop,
2018         .add_interface          = rt2x00mac_add_interface,
2019         .remove_interface       = rt2x00mac_remove_interface,
2020         .config                 = rt2x00mac_config,
2021         .configure_filter       = rt2x00mac_configure_filter,
2022         .sw_scan_start          = rt2x00mac_sw_scan_start,
2023         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2024         .get_stats              = rt2x00mac_get_stats,
2025         .bss_info_changed       = rt2x00mac_bss_info_changed,
2026         .conf_tx                = rt2x00mac_conf_tx,
2027         .get_tsf                = rt2500pci_get_tsf,
2028         .tx_last_beacon         = rt2500pci_tx_last_beacon,
2029         .rfkill_poll            = rt2x00mac_rfkill_poll,
2030         .flush                  = rt2x00mac_flush,
2031         .set_antenna            = rt2x00mac_set_antenna,
2032         .get_antenna            = rt2x00mac_get_antenna,
2033         .get_ringparam          = rt2x00mac_get_ringparam,
2034         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
2035 };
2036
2037 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
2038         .irq_handler            = rt2500pci_interrupt,
2039         .txstatus_tasklet       = rt2500pci_txstatus_tasklet,
2040         .tbtt_tasklet           = rt2500pci_tbtt_tasklet,
2041         .rxdone_tasklet         = rt2500pci_rxdone_tasklet,
2042         .probe_hw               = rt2500pci_probe_hw,
2043         .initialize             = rt2x00mmio_initialize,
2044         .uninitialize           = rt2x00mmio_uninitialize,
2045         .get_entry_state        = rt2500pci_get_entry_state,
2046         .clear_entry            = rt2500pci_clear_entry,
2047         .set_device_state       = rt2500pci_set_device_state,
2048         .rfkill_poll            = rt2500pci_rfkill_poll,
2049         .link_stats             = rt2500pci_link_stats,
2050         .reset_tuner            = rt2500pci_reset_tuner,
2051         .link_tuner             = rt2500pci_link_tuner,
2052         .start_queue            = rt2500pci_start_queue,
2053         .kick_queue             = rt2500pci_kick_queue,
2054         .stop_queue             = rt2500pci_stop_queue,
2055         .flush_queue            = rt2x00mmio_flush_queue,
2056         .write_tx_desc          = rt2500pci_write_tx_desc,
2057         .write_beacon           = rt2500pci_write_beacon,
2058         .fill_rxdone            = rt2500pci_fill_rxdone,
2059         .config_filter          = rt2500pci_config_filter,
2060         .config_intf            = rt2500pci_config_intf,
2061         .config_erp             = rt2500pci_config_erp,
2062         .config_ant             = rt2500pci_config_ant,
2063         .config                 = rt2500pci_config,
2064 };
2065
2066 static void rt2500pci_queue_init(struct data_queue *queue)
2067 {
2068         switch (queue->qid) {
2069         case QID_RX:
2070                 queue->limit = 32;
2071                 queue->data_size = DATA_FRAME_SIZE;
2072                 queue->desc_size = RXD_DESC_SIZE;
2073                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2074                 break;
2075
2076         case QID_AC_VO:
2077         case QID_AC_VI:
2078         case QID_AC_BE:
2079         case QID_AC_BK:
2080                 queue->limit = 32;
2081                 queue->data_size = DATA_FRAME_SIZE;
2082                 queue->desc_size = TXD_DESC_SIZE;
2083                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2084                 break;
2085
2086         case QID_BEACON:
2087                 queue->limit = 1;
2088                 queue->data_size = MGMT_FRAME_SIZE;
2089                 queue->desc_size = TXD_DESC_SIZE;
2090                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2091                 break;
2092
2093         case QID_ATIM:
2094                 queue->limit = 8;
2095                 queue->data_size = DATA_FRAME_SIZE;
2096                 queue->desc_size = TXD_DESC_SIZE;
2097                 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
2098                 break;
2099
2100         default:
2101                 BUG();
2102                 break;
2103         }
2104 }
2105
2106 static const struct rt2x00_ops rt2500pci_ops = {
2107         .name                   = KBUILD_MODNAME,
2108         .max_ap_intf            = 1,
2109         .eeprom_size            = EEPROM_SIZE,
2110         .rf_size                = RF_SIZE,
2111         .tx_queues              = NUM_TX_QUEUES,
2112         .queue_init             = rt2500pci_queue_init,
2113         .lib                    = &rt2500pci_rt2x00_ops,
2114         .hw                     = &rt2500pci_mac80211_ops,
2115 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2116         .debugfs                = &rt2500pci_rt2x00debug,
2117 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2118 };
2119
2120 /*
2121  * RT2500pci module information.
2122  */
2123 static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = {
2124         { PCI_DEVICE(0x1814, 0x0201) },
2125         { 0, }
2126 };
2127
2128 MODULE_AUTHOR(DRV_PROJECT);
2129 MODULE_VERSION(DRV_VERSION);
2130 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
2131 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
2132 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
2133 MODULE_LICENSE("GPL");
2134
2135 static int rt2500pci_probe(struct pci_dev *pci_dev,
2136                            const struct pci_device_id *id)
2137 {
2138         return rt2x00pci_probe(pci_dev, &rt2500pci_ops);
2139 }
2140
2141 static struct pci_driver rt2500pci_driver = {
2142         .name           = KBUILD_MODNAME,
2143         .id_table       = rt2500pci_device_table,
2144         .probe          = rt2500pci_probe,
2145         .remove         = rt2x00pci_remove,
2146         .suspend        = rt2x00pci_suspend,
2147         .resume         = rt2x00pci_resume,
2148 };
2149
2150 module_pci_driver(rt2500pci_driver);