drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 /*
 247  * Configuration handlers.
 248  */
 249 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 250                                       __le32 *mac)
 251 {
 252         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 253                                       (2 * sizeof(__le32)));
 254 }
 255
 256 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 257                                    __le32 *bssid)
 258 {
 259         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 260                                       (2 * sizeof(__le32)));
 261 }
 262
 263 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
 264                                   const int tsf_sync)
 265 {
 266         u32 reg;
 267
 268         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 269
 270         /*
 271          * Enable beacon config
 272          */
 273         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 274         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 275                            PREAMBLE + get_duration(IEEE80211_HEADER, 20));
 276         rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
 277                            rt2x00lib_get_ring(rt2x00dev,
 278                                               IEEE80211_TX_QUEUE_BEACON)
 279                            ->tx_params.cw_min);
 280         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 281
 282         /*
 283          * Enable synchronisation.
 284          */
 285         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 286         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 287         rt2x00_set_field32(&reg, CSR14_TBCN, (tsf_sync == TSF_SYNC_BEACON));
 288         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 289         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
 290         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 291 }
 292
 293 static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
 294                                       const int short_preamble,
 295                                       const int ack_timeout,
 296                                       const int ack_consume_time)
 297 {
 298         int preamble_mask;
 299         u32 reg;
 300
 301         /*
 302          * When short preamble is enabled, we should set bit 0x08
 303          */
 304         preamble_mask = short_preamble << 3;
 305
 306         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 307         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
 308         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
 309         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 310
 311         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 312         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 313         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 314         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 315         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 316
 317         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 318         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 319         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 320         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 321         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 322
 323         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 324         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 325         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 326         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 327         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 328
 329         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 330         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 331         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 332         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 333         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 334 }
 335
 336 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 337                                      const int basic_rate_mask)
 338 {
 339         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 340 }
 341
 342 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 343                                      struct rf_channel *rf, const int txpower)
 344 {
 345         u8 r70;
 346
 347         /*
 348          * Set TXpower.
 349          */
 350         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 351
 352         /*
 353          * Switch on tuning bits.
 354          * For RT2523 devices we do not need to update the R1 register.
 355          */
 356         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 357                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 358         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 359
 360         /*
 361          * For RT2525 we should first set the channel to half band higher.
 362          */
 363         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 364                 static const u32 vals[] = {
 365                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 366                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 367                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 368                         0x00080d2e, 0x00080d3a
 369                 };
 370
 371                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 372                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 373                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 374                 if (rf->rf4)
 375                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 376         }
 377
 378         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 379         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 380         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 381         if (rf->rf4)
 382                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 383
 384         /*
 385          * Channel 14 requires the Japan filter bit to be set.
 386          */
 387         r70 = 0x46;
 388         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 389         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 390
 391         msleep(1);
 392
 393         /*
 394          * Switch off tuning bits.
 395          * For RT2523 devices we do not need to update the R1 register.
 396          */
 397         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 398                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 399                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 400         }
 401
 402         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 403         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 404
 405         /*
 406          * Clear false CRC during channel switch.
 407          */
 408         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 409 }
 410
 411 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 412                                      const int txpower)
 413 {
 414         u32 rf3;
 415
 416         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 417         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 418         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 419 }
 420
 421 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 422                                      struct antenna_setup *ant)
 423 {
 424         u32 reg;
 425         u8 r14;
 426         u8 r2;
 427
 428         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 429         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 430         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 431
 432         /*
 433          * Configure the TX antenna.
 434          */
 435         switch (ant->tx) {
 436         case ANTENNA_A:
 437                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 438                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 439                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 440                 break;
 441         case ANTENNA_HW_DIVERSITY:
 442         case ANTENNA_SW_DIVERSITY:
 443                 /*
 444                  * NOTE: We should never come here because rt2x00lib is
 445                  * supposed to catch this and send us the correct antenna
 446                  * explicitely. However we are nog going to bug about this.
 447                  * Instead, just default to antenna B.
 448                  */
 449         case ANTENNA_B:
 450                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 451                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 452                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 453                 break;
 454         }
 455
 456         /*
 457          * Configure the RX antenna.
 458          */
 459         switch (ant->rx) {
 460         case ANTENNA_A:
 461                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 462                 break;
 463         case ANTENNA_HW_DIVERSITY:
 464         case ANTENNA_SW_DIVERSITY:
 465                 /*
 466                  * NOTE: We should never come here because rt2x00lib is
 467                  * supposed to catch this and send us the correct antenna
 468                  * explicitely. However we are nog going to bug about this.
 469                  * Instead, just default to antenna B.
 470                  */
 471         case ANTENNA_B:
 472                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 473                 break;
 474         }
 475
 476         /*
 477          * RT2525E and RT5222 need to flip TX I/Q
 478          */
 479         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 480             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 481                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 482                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 483                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 484
 485                 /*
 486                  * RT2525E does not need RX I/Q Flip.
 487                  */
 488                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 489                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 490         } else {
 491                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 492                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 493         }
 494
 495         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 496         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 497         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 498 }
 499
 500 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 501                                       struct rt2x00lib_conf *libconf)
 502 {
 503         u32 reg;
 504
 505         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 506         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 507         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 508
 509         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 510         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 511         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 512         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 513
 514         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 515         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 516         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 517         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 518
 519         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 520         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 521         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 522         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 523
 524         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 525         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 526                            libconf->conf->beacon_int * 16);
 527         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 528                            libconf->conf->beacon_int * 16);
 529         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 530 }
 531
 532 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 533                              const unsigned int flags,
 534                              struct rt2x00lib_conf *libconf)
 535 {
 536         if (flags & CONFIG_UPDATE_PHYMODE)
 537                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 538         if (flags & CONFIG_UPDATE_CHANNEL)
 539                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 540                                          libconf->conf->power_level);
 541         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 542                 rt2500pci_config_txpower(rt2x00dev,
 543                                          libconf->conf->power_level);
 544         if (flags & CONFIG_UPDATE_ANTENNA)
 545                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 546         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 547                 rt2500pci_config_duration(rt2x00dev, libconf);
 548 }
 549
 550 /*
 551  * LED functions.
 552  */
 553 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
 554 {
 555         u32 reg;
 556
 557         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 558
 559         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 560         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 561         rt2x00_set_field32(&reg, LEDCSR_LINK,
 562                            (rt2x00dev->led_mode != LED_MODE_ASUS));
 563         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
 564                            (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
 565         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 566 }
 567
 568 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
 569 {
 570         u32 reg;
 571
 572         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 573         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 574         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 575         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 576 }
 577
 578 /*
 579  * Link tuning
 580  */
 581 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 582                                  struct link_qual *qual)
 583 {
 584         u32 reg;
 585
 586         /*
 587          * Update FCS error count from register.
 588          */
 589         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 590         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 591
 592         /*
 593          * Update False CCA count from register.
 594          */
 595         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 596         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 597 }
 598
 599 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 600 {
 601         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 602         rt2x00dev->link.vgc_level = 0x48;
 603 }
 604
 605 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 606 {
 607         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 608         u8 r17;
 609
 610         /*
 611          * To prevent collisions with MAC ASIC on chipsets
 612          * up to version C the link tuning should halt after 20
 613          * seconds.
 614          */
 615         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 616             rt2x00dev->link.count > 20)
 617                 return;
 618
 619         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 620
 621         /*
 622          * Chipset versions C and lower should directly continue
 623          * to the dynamic CCA tuning.
 624          */
 625         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
 626                 goto dynamic_cca_tune;
 627
 628         /*
 629          * A too low RSSI will cause too much false CCA which will
 630          * then corrupt the R17 tuning. To remidy this the tuning should
 631          * be stopped (While making sure the R17 value will not exceed limits)
 632          */
 633         if (rssi < -80 && rt2x00dev->link.count > 20) {
 634                 if (r17 >= 0x41) {
 635                         r17 = rt2x00dev->link.vgc_level;
 636                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 637                 }
 638                 return;
 639         }
 640
 641         /*
 642          * Special big-R17 for short distance
 643          */
 644         if (rssi >= -58) {
 645                 if (r17 != 0x50)
 646                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 647                 return;
 648         }
 649
 650         /*
 651          * Special mid-R17 for middle distance
 652          */
 653         if (rssi >= -74) {
 654                 if (r17 != 0x41)
 655                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 656                 return;
 657         }
 658
 659         /*
 660          * Leave short or middle distance condition, restore r17
 661          * to the dynamic tuning range.
 662          */
 663         if (r17 >= 0x41) {
 664                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 665                 return;
 666         }
 667
 668 dynamic_cca_tune:
 669
 670         /*
 671          * R17 is inside the dynamic tuning range,
 672          * start tuning the link based on the false cca counter.
 673          */
 674         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 675                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 676                 rt2x00dev->link.vgc_level = r17;
 677         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 678                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 679                 rt2x00dev->link.vgc_level = r17;
 680         }
 681 }
 682
 683 /*
 684  * Initialization functions.
 685  */
 686 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 687                                    struct data_entry *entry)
 688 {
 689         __le32 *rxd = entry->priv;
 690         u32 word;
 691
 692         rt2x00_desc_read(rxd, 1, &word);
 693         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry->data_dma);
 694         rt2x00_desc_write(rxd, 1, word);
 695
 696         rt2x00_desc_read(rxd, 0, &word);
 697         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 698         rt2x00_desc_write(rxd, 0, word);
 699 }
 700
 701 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 702                                    struct data_entry *entry)
 703 {
 704         __le32 *txd = entry->priv;
 705         u32 word;
 706
 707         rt2x00_desc_read(txd, 1, &word);
 708         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry->data_dma);
 709         rt2x00_desc_write(txd, 1, word);
 710
 711         rt2x00_desc_read(txd, 0, &word);
 712         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 713         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 714         rt2x00_desc_write(txd, 0, word);
 715 }
 716
 717 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
 718 {
 719         u32 reg;
 720
 721         /*
 722          * Initialize registers.
 723          */
 724         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 725         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 726                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 727         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 728                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 729         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 730                            rt2x00dev->bcn[1].stats.limit);
 731         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 732                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 733         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 734
 735         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 736         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 737                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 738         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 739
 740         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 741         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 742                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 743         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 744
 745         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 746         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 747                            rt2x00dev->bcn[1].data_dma);
 748         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 749
 750         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 751         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 752                            rt2x00dev->bcn[0].data_dma);
 753         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 754
 755         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 756         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 757         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 758         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 759
 760         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 761         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 762                            rt2x00dev->rx->data_dma);
 763         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 764
 765         return 0;
 766 }
 767
 768 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 769 {
 770         u32 reg;
 771
 772         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 773         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 774         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 775         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 776
 777         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 778         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 779         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 780         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 781         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 782
 783         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 784         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 785                            rt2x00dev->rx->data_size / 128);
 786         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 787
 788         /*
 789          * Always use CWmin and CWmax set in descriptor.
 790          */
 791         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 792         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 793         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 794
 795         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 796
 797         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 798         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 799         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 800         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 801         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 802         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 803         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 804         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 805         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 806         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 807
 808         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 809         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 810         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 811         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 812         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 813         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 814
 815         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 816         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 817         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 818         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 819         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 820         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 821
 822         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 823         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 824         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 825         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 826         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 827         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 828
 829         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 830         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 831         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 832         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 833         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 834         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 835         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 836         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 837         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 838         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 839
 840         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 841         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 842         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 843         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 844         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 845         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 846         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 847         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 848         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 849
 850         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 851
 852         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 853         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 854
 855         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 856                 return -EBUSY;
 857
 858         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 859         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 860
 861         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 862         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 863         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 864
 865         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 866         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 867         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 868         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 869         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 870         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 871         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 872         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 873
 874         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 875
 876         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 877
 878         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 879         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 880         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 881         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 882         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 883
 884         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 885         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 886         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 887         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 888
 889         /*
 890          * We must clear the FCS and FIFO error count.
 891          * These registers are cleared on read,
 892          * so we may pass a useless variable to store the value.
 893          */
 894         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 895         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 896
 897         return 0;
 898 }
 899
 900 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 901 {
 902         unsigned int i;
 903         u16 eeprom;
 904         u8 reg_id;
 905         u8 value;
 906
 907         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 908                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 909                 if ((value != 0xff) && (value != 0x00))
 910                         goto continue_csr_init;
 911                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 912                 udelay(REGISTER_BUSY_DELAY);
 913         }
 914
 915         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 916         return -EACCES;
 917
 918 continue_csr_init:
 919         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 920         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 921         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 922         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 923         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 924         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 925         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 926         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 927         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 928         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 929         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 930         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 931         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 932         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 933         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 934         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 935         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 936         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 937         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 938         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 939         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 940         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 941         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 942         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 943         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 944         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 945         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 946         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 947         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 948         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 949
 950         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 951         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 952                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 953
 954                 if (eeprom != 0xffff && eeprom != 0x0000) {
 955                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 956                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 957                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 958                               reg_id, value);
 959                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
 960                 }
 961         }
 962         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 963
 964         return 0;
 965 }
 966
 967 /*
 968  * Device state switch handlers.
 969  */
 970 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 971                                 enum dev_state state)
 972 {
 973         u32 reg;
 974
 975         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 976         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 977                            state == STATE_RADIO_RX_OFF);
 978         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 979 }
 980
 981 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 982                                  enum dev_state state)
 983 {
 984         int mask = (state == STATE_RADIO_IRQ_OFF);
 985         u32 reg;
 986
 987         /*
 988          * When interrupts are being enabled, the interrupt registers
 989          * should clear the register to assure a clean state.
 990          */
 991         if (state == STATE_RADIO_IRQ_ON) {
 992                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 993                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 994         }
 995
 996         /*
 997          * Only toggle the interrupts bits we are going to use.
 998          * Non-checked interrupt bits are disabled by default.
 999          */
1000         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1001         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1002         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1003         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1004         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1005         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1006         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1007 }
1008
1009 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1010 {
1011         /*
1012          * Initialize all registers.
1013          */
1014         if (rt2500pci_init_rings(rt2x00dev) ||
1015             rt2500pci_init_registers(rt2x00dev) ||
1016             rt2500pci_init_bbp(rt2x00dev)) {
1017                 ERROR(rt2x00dev, "Register initialization failed.\n");
1018                 return -EIO;
1019         }
1020
1021         /*
1022          * Enable interrupts.
1023          */
1024         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1025
1026         /*
1027          * Enable LED
1028          */
1029         rt2500pci_enable_led(rt2x00dev);
1030
1031         return 0;
1032 }
1033
1034 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1035 {
1036         u32 reg;
1037
1038         /*
1039          * Disable LED
1040          */
1041         rt2500pci_disable_led(rt2x00dev);
1042
1043         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1044
1045         /*
1046          * Disable synchronisation.
1047          */
1048         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1049
1050         /*
1051          * Cancel RX and TX.
1052          */
1053         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1054         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1055         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1056
1057         /*
1058          * Disable interrupts.
1059          */
1060         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1061 }
1062
1063 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1064                                enum dev_state state)
1065 {
1066         u32 reg;
1067         unsigned int i;
1068         char put_to_sleep;
1069         char bbp_state;
1070         char rf_state;
1071
1072         put_to_sleep = (state != STATE_AWAKE);
1073
1074         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1075         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1076         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1077         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1078         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1079         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1080
1081         /*
1082          * Device is not guaranteed to be in the requested state yet.
1083          * We must wait until the register indicates that the
1084          * device has entered the correct state.
1085          */
1086         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1087                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1088                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1089                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1090                 if (bbp_state == state && rf_state == state)
1091                         return 0;
1092                 msleep(10);
1093         }
1094
1095         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1096                "current device state: bbp %d and rf %d.\n",
1097                state, bbp_state, rf_state);
1098
1099         return -EBUSY;
1100 }
1101
1102 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1103                                       enum dev_state state)
1104 {
1105         int retval = 0;
1106
1107         switch (state) {
1108         case STATE_RADIO_ON:
1109                 retval = rt2500pci_enable_radio(rt2x00dev);
1110                 break;
1111         case STATE_RADIO_OFF:
1112                 rt2500pci_disable_radio(rt2x00dev);
1113                 break;
1114         case STATE_RADIO_RX_ON:
1115         case STATE_RADIO_RX_ON_LINK:
1116                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1117                 break;
1118         case STATE_RADIO_RX_OFF:
1119         case STATE_RADIO_RX_OFF_LINK:
1120                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1121                 break;
1122         case STATE_DEEP_SLEEP:
1123         case STATE_SLEEP:
1124         case STATE_STANDBY:
1125         case STATE_AWAKE:
1126                 retval = rt2500pci_set_state(rt2x00dev, state);
1127                 break;
1128         default:
1129                 retval = -ENOTSUPP;
1130                 break;
1131         }
1132
1133         return retval;
1134 }
1135
1136 /*
1137  * TX descriptor initialization
1138  */
1139 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1140                                     struct sk_buff *skb,
1141                                     struct txdata_entry_desc *desc,
1142                                     struct ieee80211_tx_control *control)
1143 {
1144         struct skb_desc *skbdesc = get_skb_desc(skb);
1145         __le32 *txd = skbdesc->desc;
1146         u32 word;
1147
1148         /*
1149          * Start writing the descriptor words.
1150          */
1151         rt2x00_desc_read(txd, 2, &word);
1152         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1153         rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1154         rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1155         rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1156         rt2x00_desc_write(txd, 2, word);
1157
1158         rt2x00_desc_read(txd, 3, &word);
1159         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1160         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1161         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1162         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1163         rt2x00_desc_write(txd, 3, word);
1164
1165         rt2x00_desc_read(txd, 10, &word);
1166         rt2x00_set_field32(&word, TXD_W10_RTS,
1167                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1168         rt2x00_desc_write(txd, 10, word);
1169
1170         rt2x00_desc_read(txd, 0, &word);
1171         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1172         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1173         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1174                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1175         rt2x00_set_field32(&word, TXD_W0_ACK,
1176                            test_bit(ENTRY_TXD_ACK, &desc->flags));
1177         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1178                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1179         rt2x00_set_field32(&word, TXD_W0_OFDM,
1180                            test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1181         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1182         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1183         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1184                            !!(control->flags &
1185                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1186         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1187         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1188         rt2x00_desc_write(txd, 0, word);
1189 }
1190
1191 /*
1192  * TX data initialization
1193  */
1194 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1195                                     unsigned int queue)
1196 {
1197         u32 reg;
1198
1199         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1200                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1201                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1202                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1203                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1204                 }
1205                 return;
1206         }
1207
1208         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1209         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1210                            (queue == IEEE80211_TX_QUEUE_DATA0));
1211         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1212                            (queue == IEEE80211_TX_QUEUE_DATA1));
1213         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1214                            (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
1215         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1216 }
1217
1218 /*
1219  * RX control handlers
1220  */
1221 static void rt2500pci_fill_rxdone(struct data_entry *entry,
1222                                   struct rxdata_entry_desc *desc)
1223 {
1224         __le32 *rxd = entry->priv;
1225         u32 word0;
1226         u32 word2;
1227
1228         rt2x00_desc_read(rxd, 0, &word0);
1229         rt2x00_desc_read(rxd, 2, &word2);
1230
1231         desc->flags = 0;
1232         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1233                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1234         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1235                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1236
1237         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1238         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1239             entry->ring->rt2x00dev->rssi_offset;
1240         desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1241         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1242         desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1243 }
1244
1245 /*
1246  * Interrupt functions.
1247  */
1248 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1249 {
1250         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1251         struct data_entry *entry;
1252         __le32 *txd;
1253         u32 word;
1254         int tx_status;
1255         int retry;
1256
1257         while (!rt2x00_ring_empty(ring)) {
1258                 entry = rt2x00_get_data_entry_done(ring);
1259                 txd = entry->priv;
1260                 rt2x00_desc_read(txd, 0, &word);
1261
1262                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1263                     !rt2x00_get_field32(word, TXD_W0_VALID))
1264                         break;
1265
1266                 /*
1267                  * Obtain the status about this packet.
1268                  */
1269                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1270                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1271
1272                 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
1273         }
1274 }
1275
1276 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1277 {
1278         struct rt2x00_dev *rt2x00dev = dev_instance;
1279         u32 reg;
1280
1281         /*
1282          * Get the interrupt sources & saved to local variable.
1283          * Write register value back to clear pending interrupts.
1284          */
1285         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1286         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1287
1288         if (!reg)
1289                 return IRQ_NONE;
1290
1291         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1292                 return IRQ_HANDLED;
1293
1294         /*
1295          * Handle interrupts, walk through all bits
1296          * and run the tasks, the bits are checked in order of
1297          * priority.
1298          */
1299
1300         /*
1301          * 1 - Beacon timer expired interrupt.
1302          */
1303         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1304                 rt2x00lib_beacondone(rt2x00dev);
1305
1306         /*
1307          * 2 - Rx ring done interrupt.
1308          */
1309         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1310                 rt2x00pci_rxdone(rt2x00dev);
1311
1312         /*
1313          * 3 - Atim ring transmit done interrupt.
1314          */
1315         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1316                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1317
1318         /*
1319          * 4 - Priority ring transmit done interrupt.
1320          */
1321         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1322                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1323
1324         /*
1325          * 5 - Tx ring transmit done interrupt.
1326          */
1327         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1328                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1329
1330         return IRQ_HANDLED;
1331 }
1332
1333 /*
1334  * Device probe functions.
1335  */
1336 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1337 {
1338         struct eeprom_93cx6 eeprom;
1339         u32 reg;
1340         u16 word;
1341         u8 *mac;
1342
1343         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1344
1345         eeprom.data = rt2x00dev;
1346         eeprom.register_read = rt2500pci_eepromregister_read;
1347         eeprom.register_write = rt2500pci_eepromregister_write;
1348         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1349             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1350         eeprom.reg_data_in = 0;
1351         eeprom.reg_data_out = 0;
1352         eeprom.reg_data_clock = 0;
1353         eeprom.reg_chip_select = 0;
1354
1355         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1356                                EEPROM_SIZE / sizeof(u16));
1357
1358         /*
1359          * Start validation of the data that has been read.
1360          */
1361         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1362         if (!is_valid_ether_addr(mac)) {
1363                 DECLARE_MAC_BUF(macbuf);
1364
1365                 random_ether_addr(mac);
1366                 EEPROM(rt2x00dev, "MAC: %s\n",
1367                        print_mac(macbuf, mac));
1368         }
1369
1370         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1371         if (word == 0xffff) {
1372                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1373                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1374                                    ANTENNA_SW_DIVERSITY);
1375                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1376                                    ANTENNA_SW_DIVERSITY);
1377                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1378                                    LED_MODE_DEFAULT);
1379                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1380                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1381                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1382                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1383                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1384         }
1385
1386         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1387         if (word == 0xffff) {
1388                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1389                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1390                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1391                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1392                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1393         }
1394
1395         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1396         if (word == 0xffff) {
1397                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1398                                    DEFAULT_RSSI_OFFSET);
1399                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1400                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1401         }
1402
1403         return 0;
1404 }
1405
1406 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1407 {
1408         u32 reg;
1409         u16 value;
1410         u16 eeprom;
1411
1412         /*
1413          * Read EEPROM word for configuration.
1414          */
1415         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1416
1417         /*
1418          * Identify RF chipset.
1419          */
1420         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1421         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1422         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1423
1424         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1425             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1426             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1427             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1428             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1429             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1430                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1431                 return -ENODEV;
1432         }
1433
1434         /*
1435          * Identify default antenna configuration.
1436          */
1437         rt2x00dev->default_ant.tx =
1438             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1439         rt2x00dev->default_ant.rx =
1440             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1441
1442         /*
1443          * Store led mode, for correct led behaviour.
1444          */
1445         rt2x00dev->led_mode =
1446             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1447
1448         /*
1449          * Detect if this device has an hardware controlled radio.
1450          */
1451 #ifdef CONFIG_RT2500PCI_RFKILL
1452         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1453                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1454 #endif /* CONFIG_RT2500PCI_RFKILL */
1455
1456         /*
1457          * Check if the BBP tuning should be enabled.
1458          */
1459         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1460
1461         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1462                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1463
1464         /*
1465          * Read the RSSI <-> dBm offset information.
1466          */
1467         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1468         rt2x00dev->rssi_offset =
1469             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1470
1471         return 0;
1472 }
1473
1474 /*
1475  * RF value list for RF2522
1476  * Supports: 2.4 GHz
1477  */
1478 static const struct rf_channel rf_vals_bg_2522[] = {
1479         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1480         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1481         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1482         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1483         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1484         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1485         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1486         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1487         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1488         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1489         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1490         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1491         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1492         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1493 };
1494
1495 /*
1496  * RF value list for RF2523
1497  * Supports: 2.4 GHz
1498  */
1499 static const struct rf_channel rf_vals_bg_2523[] = {
1500         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1501         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1502         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1503         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1504         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1505         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1506         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1507         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1508         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1509         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1510         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1511         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1512         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1513         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1514 };
1515
1516 /*
1517  * RF value list for RF2524
1518  * Supports: 2.4 GHz
1519  */
1520 static const struct rf_channel rf_vals_bg_2524[] = {
1521         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1522         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1523         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1524         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1525         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1526         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1527         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1528         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1529         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1530         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1531         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1532         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1533         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1534         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1535 };
1536
1537 /*
1538  * RF value list for RF2525
1539  * Supports: 2.4 GHz
1540  */
1541 static const struct rf_channel rf_vals_bg_2525[] = {
1542         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1543         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1544         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1545         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1546         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1547         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1548         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1549         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1550         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1551         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1552         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1553         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1554         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1555         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1556 };
1557
1558 /*
1559  * RF value list for RF2525e
1560  * Supports: 2.4 GHz
1561  */
1562 static const struct rf_channel rf_vals_bg_2525e[] = {
1563         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1564         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1565         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1566         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1567         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1568         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1569         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1570         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1571         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1572         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1573         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1574         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1575         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1576         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1577 };
1578
1579 /*
1580  * RF value list for RF5222
1581  * Supports: 2.4 GHz & 5.2 GHz
1582  */
1583 static const struct rf_channel rf_vals_5222[] = {
1584         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1585         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1586         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1587         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1588         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1589         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1590         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1591         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1592         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1593         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1594         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1595         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1596         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1597         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1598
1599         /* 802.11 UNI / HyperLan 2 */
1600         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1601         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1602         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1603         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1604         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1605         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1606         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1607         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1608
1609         /* 802.11 HyperLan 2 */
1610         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1611         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1612         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1613         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1614         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1615         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1616         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1617         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1618         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1619         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1620
1621         /* 802.11 UNII */
1622         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1623         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1624         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1625         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1626         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1627 };
1628
1629 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1630 {
1631         struct hw_mode_spec *spec = &rt2x00dev->spec;
1632         u8 *txpower;
1633         unsigned int i;
1634
1635         /*
1636          * Initialize all hw fields.
1637          */
1638         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1639         rt2x00dev->hw->extra_tx_headroom = 0;
1640         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1641         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1642         rt2x00dev->hw->queues = 2;
1643
1644         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1645         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1646                                 rt2x00_eeprom_addr(rt2x00dev,
1647                                                    EEPROM_MAC_ADDR_0));
1648
1649         /*
1650          * Convert tx_power array in eeprom.
1651          */
1652         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1653         for (i = 0; i < 14; i++)
1654                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1655
1656         /*
1657          * Initialize hw_mode information.
1658          */
1659         spec->num_modes = 2;
1660         spec->num_rates = 12;
1661         spec->tx_power_a = NULL;
1662         spec->tx_power_bg = txpower;
1663         spec->tx_power_default = DEFAULT_TXPOWER;
1664
1665         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1666                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1667                 spec->channels = rf_vals_bg_2522;
1668         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1669                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1670                 spec->channels = rf_vals_bg_2523;
1671         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1672                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1673                 spec->channels = rf_vals_bg_2524;
1674         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1675                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1676                 spec->channels = rf_vals_bg_2525;
1677         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1678                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1679                 spec->channels = rf_vals_bg_2525e;
1680         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1681                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1682                 spec->channels = rf_vals_5222;
1683                 spec->num_modes = 3;
1684         }
1685 }
1686
1687 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1688 {
1689         int retval;
1690
1691         /*
1692          * Allocate eeprom data.
1693          */
1694         retval = rt2500pci_validate_eeprom(rt2x00dev);
1695         if (retval)
1696                 return retval;
1697
1698         retval = rt2500pci_init_eeprom(rt2x00dev);
1699         if (retval)
1700                 return retval;
1701
1702         /*
1703          * Initialize hw specifications.
1704          */
1705         rt2500pci_probe_hw_mode(rt2x00dev);
1706
1707         /*
1708          * This device requires the beacon ring
1709          */
1710         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1711
1712         /*
1713          * Set the rssi offset.
1714          */
1715         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1716
1717         return 0;
1718 }
1719
1720 /*
1721  * IEEE80211 stack callback functions.
1722  */
1723 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1724                                        unsigned int changed_flags,
1725                                        unsigned int *total_flags,
1726                                        int mc_count,
1727                                        struct dev_addr_list *mc_list)
1728 {
1729         struct rt2x00_dev *rt2x00dev = hw->priv;
1730         u32 reg;
1731
1732         /*
1733          * Mask off any flags we are going to ignore from
1734          * the total_flags field.
1735          */
1736         *total_flags &=
1737             FIF_ALLMULTI |
1738             FIF_FCSFAIL |
1739             FIF_PLCPFAIL |
1740             FIF_CONTROL |
1741             FIF_OTHER_BSS |
1742             FIF_PROMISC_IN_BSS;
1743
1744         /*
1745          * Apply some rules to the filters:
1746          * - Some filters imply different filters to be set.
1747          * - Some things we can't filter out at all.
1748          */
1749         if (mc_count)
1750                 *total_flags |= FIF_ALLMULTI;
1751         if (*total_flags & FIF_OTHER_BSS ||
1752             *total_flags & FIF_PROMISC_IN_BSS)
1753                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1754
1755         /*
1756          * Check if there is any work left for us.
1757          */
1758         if (rt2x00dev->packet_filter == *total_flags)
1759                 return;
1760         rt2x00dev->packet_filter = *total_flags;
1761
1762         /*
1763          * Start configuration steps.
1764          * Note that the version error will always be dropped
1765          * and broadcast frames will always be accepted since
1766          * there is no filter for it at this time.
1767          */
1768         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1769         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1770                            !(*total_flags & FIF_FCSFAIL));
1771         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1772                            !(*total_flags & FIF_PLCPFAIL));
1773         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1774                            !(*total_flags & FIF_CONTROL));
1775         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1776                            !(*total_flags & FIF_PROMISC_IN_BSS));
1777         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1778                            !(*total_flags & FIF_PROMISC_IN_BSS));
1779         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1780         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1781                            !(*total_flags & FIF_ALLMULTI));
1782         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1783         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1784 }
1785
1786 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1787                                      u32 short_retry, u32 long_retry)
1788 {
1789         struct rt2x00_dev *rt2x00dev = hw->priv;
1790         u32 reg;
1791
1792         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1793         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1794         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1795         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1796
1797         return 0;
1798 }
1799
1800 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1801 {
1802         struct rt2x00_dev *rt2x00dev = hw->priv;
1803         u64 tsf;
1804         u32 reg;
1805
1806         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1807         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1808         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1809         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1810
1811         return tsf;
1812 }
1813
1814 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1815 {
1816         struct rt2x00_dev *rt2x00dev = hw->priv;
1817
1818         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1819         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1820 }
1821
1822 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1823 {
1824         struct rt2x00_dev *rt2x00dev = hw->priv;
1825         u32 reg;
1826
1827         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1828         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1829 }
1830
1831 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1832         .tx                     = rt2x00mac_tx,
1833         .start                  = rt2x00mac_start,
1834         .stop                   = rt2x00mac_stop,
1835         .add_interface          = rt2x00mac_add_interface,
1836         .remove_interface       = rt2x00mac_remove_interface,
1837         .config                 = rt2x00mac_config,
1838         .config_interface       = rt2x00mac_config_interface,
1839         .configure_filter       = rt2500pci_configure_filter,
1840         .get_stats              = rt2x00mac_get_stats,
1841         .set_retry_limit        = rt2500pci_set_retry_limit,
1842         .bss_info_changed       = rt2x00mac_bss_info_changed,
1843         .conf_tx                = rt2x00mac_conf_tx,
1844         .get_tx_stats           = rt2x00mac_get_tx_stats,
1845         .get_tsf                = rt2500pci_get_tsf,
1846         .reset_tsf              = rt2500pci_reset_tsf,
1847         .beacon_update          = rt2x00pci_beacon_update,
1848         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1849 };
1850
1851 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1852         .irq_handler            = rt2500pci_interrupt,
1853         .probe_hw               = rt2500pci_probe_hw,
1854         .initialize             = rt2x00pci_initialize,
1855         .uninitialize           = rt2x00pci_uninitialize,
1856         .init_rxentry           = rt2500pci_init_rxentry,
1857         .init_txentry           = rt2500pci_init_txentry,
1858         .set_device_state       = rt2500pci_set_device_state,
1859         .rfkill_poll            = rt2500pci_rfkill_poll,
1860         .link_stats             = rt2500pci_link_stats,
1861         .reset_tuner            = rt2500pci_reset_tuner,
1862         .link_tuner             = rt2500pci_link_tuner,
1863         .write_tx_desc          = rt2500pci_write_tx_desc,
1864         .write_tx_data          = rt2x00pci_write_tx_data,
1865         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1866         .fill_rxdone            = rt2500pci_fill_rxdone,
1867         .config_mac_addr        = rt2500pci_config_mac_addr,
1868         .config_bssid           = rt2500pci_config_bssid,
1869         .config_type            = rt2500pci_config_type,
1870         .config_preamble        = rt2500pci_config_preamble,
1871         .config                 = rt2500pci_config,
1872 };
1873
1874 static const struct rt2x00_ops rt2500pci_ops = {
1875         .name           = KBUILD_MODNAME,
1876         .rxd_size       = RXD_DESC_SIZE,
1877         .txd_size       = TXD_DESC_SIZE,
1878         .eeprom_size    = EEPROM_SIZE,
1879         .rf_size        = RF_SIZE,
1880         .lib            = &rt2500pci_rt2x00_ops,
1881         .hw             = &rt2500pci_mac80211_ops,
1882 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1883         .debugfs        = &rt2500pci_rt2x00debug,
1884 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1885 };
1886
1887 /*
1888  * RT2500pci module information.
1889  */
1890 static struct pci_device_id rt2500pci_device_table[] = {
1891         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1892         { 0, }
1893 };
1894
1895 MODULE_AUTHOR(DRV_PROJECT);
1896 MODULE_VERSION(DRV_VERSION);
1897 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1898 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1899 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1900 MODULE_LICENSE("GPL");
1901
1902 static struct pci_driver rt2500pci_driver = {
1903         .name           = KBUILD_MODNAME,
1904         .id_table       = rt2500pci_device_table,
1905         .probe          = rt2x00pci_probe,
1906         .remove         = __devexit_p(rt2x00pci_remove),
1907         .suspend        = rt2x00pci_suspend,
1908         .resume         = rt2x00pci_resume,
1909 };
1910
1911 static int __init rt2500pci_init(void)
1912 {
1913         return pci_register_driver(&rt2500pci_driver);
1914 }
1915
1916 static void __exit rt2500pci_exit(void)
1917 {
1918         pci_unregister_driver(&rt2500pci_driver);
1919 }
1920
1921 module_init(rt2500pci_init);
1922 module_exit(rt2500pci_exit);